1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "radeon_audio.h" 31 #include "radeon_asic.h" 32 #include "atom.h" 33 #include <linux/dmi.h> 34 35 static u8 36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 37 { 38 u8 backlight_level; 39 u32 bios_2_scratch; 40 41 if (rdev->family >= CHIP_R600) 42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 43 else 44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 45 46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 48 49 return backlight_level; 50 } 51 52 static void 53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 54 u8 backlight_level) 55 { 56 u32 bios_2_scratch; 57 58 if (rdev->family >= CHIP_R600) 59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 60 else 61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 62 63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 65 ATOM_S2_CURRENT_BL_LEVEL_MASK); 66 67 if (rdev->family >= CHIP_R600) 68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 69 else 70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 71 } 72 73 u8 74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 75 { 76 struct drm_device *dev = radeon_encoder->base.dev; 77 struct radeon_device *rdev = dev->dev_private; 78 79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 80 return 0; 81 82 return radeon_atom_get_backlight_level_from_reg(rdev); 83 } 84 85 void 86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 87 { 88 struct drm_encoder *encoder = &radeon_encoder->base; 89 struct drm_device *dev = radeon_encoder->base.dev; 90 struct radeon_device *rdev = dev->dev_private; 91 struct radeon_encoder_atom_dig *dig; 92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 93 int index; 94 95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 96 return; 97 98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 99 radeon_encoder->enc_priv) { 100 dig = radeon_encoder->enc_priv; 101 dig->backlight_level = level; 102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 103 104 switch (radeon_encoder->encoder_id) { 105 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 108 if (dig->backlight_level == 0) { 109 args.ucAction = ATOM_LCD_BLOFF; 110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 111 } else { 112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 114 args.ucAction = ATOM_LCD_BLON; 115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 116 } 117 break; 118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 123 if (dig->backlight_level == 0) 124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 125 else { 126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 128 } 129 break; 130 default: 131 break; 132 } 133 } 134 } 135 136 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 137 138 #if 0 139 static u8 radeon_atom_bl_level(struct backlight_device *bd) 140 { 141 u8 level; 142 143 /* Convert brightness to hardware level */ 144 if (bd->props.brightness < 0) 145 level = 0; 146 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 147 level = RADEON_MAX_BL_LEVEL; 148 else 149 level = bd->props.brightness; 150 151 return level; 152 } 153 154 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 155 { 156 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 157 struct radeon_encoder *radeon_encoder = pdata->encoder; 158 159 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 160 161 return 0; 162 } 163 164 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 165 { 166 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 167 struct radeon_encoder *radeon_encoder = pdata->encoder; 168 struct drm_device *dev = radeon_encoder->base.dev; 169 struct radeon_device *rdev = dev->dev_private; 170 171 return radeon_atom_get_backlight_level_from_reg(rdev); 172 } 173 174 static const struct backlight_ops radeon_atom_backlight_ops = { 175 .get_brightness = radeon_atom_backlight_get_brightness, 176 .update_status = radeon_atom_backlight_update_status, 177 }; 178 #endif 179 180 /* 181 * Read max backlight level 182 */ 183 static int 184 sysctl_backlight_max(SYSCTL_HANDLER_ARGS) 185 { 186 int err, val; 187 188 val = RADEON_MAX_BL_LEVEL; 189 err = sysctl_handle_int(oidp, &val, 0, req); 190 return(err); 191 } 192 193 /* 194 * Read/write backlight level 195 */ 196 static int 197 sysctl_backlight_handler(SYSCTL_HANDLER_ARGS) 198 { 199 struct radeon_encoder *encoder; 200 struct radeon_encoder_atom_dig *dig; 201 int err, val; 202 203 encoder = (struct radeon_encoder *)arg1; 204 dig = encoder->enc_priv; 205 val = dig->backlight_level; 206 207 err = sysctl_handle_int(oidp, &val, 0, req); 208 if (err != 0 || req->newptr == NULL) { 209 return(err); 210 } 211 if (dig->backlight_level != val && val >= 0 && 212 val <= RADEON_MAX_BL_LEVEL) { 213 atombios_set_backlight_level(encoder, val); 214 } 215 216 return(err); 217 } 218 219 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 220 struct drm_connector *drm_connector) 221 { 222 struct drm_device *dev = radeon_encoder->base.dev; 223 struct radeon_device *rdev = dev->dev_private; 224 struct radeon_encoder_atom_dig *dig; 225 226 if (!radeon_encoder->enc_priv) 227 return; 228 229 if (!rdev->is_atom_bios) 230 return; 231 232 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 233 return; 234 235 dig = radeon_encoder->enc_priv; 236 dig->backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); 237 238 DRM_INFO("radeon atom DIG backlight initialized\n"); 239 rdev->mode_info.bl_encoder = radeon_encoder; 240 241 SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children, 242 OID_AUTO, "backlight_max", 243 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_ANYBODY, 244 radeon_encoder, sizeof(int), 245 sysctl_backlight_max, 246 "I", "Max backlight level"); 247 SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children, 248 OID_AUTO, "backlight_level", 249 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_ANYBODY, 250 radeon_encoder, sizeof(int), 251 sysctl_backlight_handler, 252 "I", "Backlight level"); 253 return; 254 } 255 256 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 257 { 258 #if 0 259 struct drm_device *dev = radeon_encoder->base.dev; 260 struct radeon_device *rdev = dev->dev_private; 261 struct backlight_device *bd = NULL; 262 struct radeon_encoder_atom_dig *dig; 263 264 if (!radeon_encoder->enc_priv) 265 return; 266 267 if (!rdev->is_atom_bios) 268 return; 269 270 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 271 return; 272 273 dig = radeon_encoder->enc_priv; 274 bd = dig->bl_dev; 275 dig->bl_dev = NULL; 276 277 if (bd) { 278 struct radeon_legacy_backlight_privdata *pdata; 279 280 pdata = bl_get_data(bd); 281 backlight_device_unregister(bd); 282 kfree(pdata); 283 284 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 285 } 286 #endif 287 } 288 289 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 290 291 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 292 struct drm_connector *drm_connector) 293 { 294 } 295 296 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 297 { 298 } 299 300 #endif 301 302 303 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 304 const struct drm_display_mode *mode, 305 struct drm_display_mode *adjusted_mode) 306 { 307 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 308 struct drm_device *dev = encoder->dev; 309 struct radeon_device *rdev = dev->dev_private; 310 311 /* set the active encoder to connector routing */ 312 radeon_encoder_set_active_device(encoder); 313 drm_mode_set_crtcinfo(adjusted_mode, 0); 314 315 /* hw bug */ 316 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 317 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 318 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 319 320 /* vertical FP must be at least 1 */ 321 if (mode->crtc_vsync_start == mode->crtc_vdisplay) 322 adjusted_mode->crtc_vsync_start++; 323 324 /* get the native mode for scaling */ 325 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 326 radeon_panel_mode_fixup(encoder, adjusted_mode); 327 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 328 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 329 if (tv_dac) { 330 if (tv_dac->tv_std == TV_STD_NTSC || 331 tv_dac->tv_std == TV_STD_NTSC_J || 332 tv_dac->tv_std == TV_STD_PAL_M) 333 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 334 else 335 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 336 } 337 } else if (radeon_encoder->rmx_type != RMX_OFF) { 338 radeon_panel_mode_fixup(encoder, adjusted_mode); 339 } 340 341 if (ASIC_IS_DCE3(rdev) && 342 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 343 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 344 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 345 radeon_dp_set_link_config(connector, adjusted_mode); 346 } 347 348 return true; 349 } 350 351 static void 352 atombios_dac_setup(struct drm_encoder *encoder, int action) 353 { 354 struct drm_device *dev = encoder->dev; 355 struct radeon_device *rdev = dev->dev_private; 356 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 357 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 358 int index = 0; 359 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 360 361 memset(&args, 0, sizeof(args)); 362 363 switch (radeon_encoder->encoder_id) { 364 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 365 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 366 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 367 break; 368 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 369 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 370 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 371 break; 372 } 373 374 args.ucAction = action; 375 376 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 377 args.ucDacStandard = ATOM_DAC1_PS2; 378 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 379 args.ucDacStandard = ATOM_DAC1_CV; 380 else { 381 switch (dac_info->tv_std) { 382 case TV_STD_PAL: 383 case TV_STD_PAL_M: 384 case TV_STD_SCART_PAL: 385 case TV_STD_SECAM: 386 case TV_STD_PAL_CN: 387 args.ucDacStandard = ATOM_DAC1_PAL; 388 break; 389 case TV_STD_NTSC: 390 case TV_STD_NTSC_J: 391 case TV_STD_PAL_60: 392 default: 393 args.ucDacStandard = ATOM_DAC1_NTSC; 394 break; 395 } 396 } 397 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 398 399 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 400 401 } 402 403 static void 404 atombios_tv_setup(struct drm_encoder *encoder, int action) 405 { 406 struct drm_device *dev = encoder->dev; 407 struct radeon_device *rdev = dev->dev_private; 408 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 409 TV_ENCODER_CONTROL_PS_ALLOCATION args; 410 int index = 0; 411 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 412 413 memset(&args, 0, sizeof(args)); 414 415 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 416 417 args.sTVEncoder.ucAction = action; 418 419 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 420 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 421 else { 422 switch (dac_info->tv_std) { 423 case TV_STD_NTSC: 424 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 425 break; 426 case TV_STD_PAL: 427 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 428 break; 429 case TV_STD_PAL_M: 430 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 431 break; 432 case TV_STD_PAL_60: 433 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 434 break; 435 case TV_STD_NTSC_J: 436 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 437 break; 438 case TV_STD_SCART_PAL: 439 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 440 break; 441 case TV_STD_SECAM: 442 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 443 break; 444 case TV_STD_PAL_CN: 445 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 446 break; 447 default: 448 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 449 break; 450 } 451 } 452 453 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 454 455 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 456 457 } 458 459 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 460 { 461 int bpc = 8; 462 463 if (encoder->crtc) { 464 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 465 bpc = radeon_crtc->bpc; 466 } 467 468 switch (bpc) { 469 case 0: 470 return PANEL_BPC_UNDEFINE; 471 case 6: 472 return PANEL_6BIT_PER_COLOR; 473 case 8: 474 default: 475 return PANEL_8BIT_PER_COLOR; 476 case 10: 477 return PANEL_10BIT_PER_COLOR; 478 case 12: 479 return PANEL_12BIT_PER_COLOR; 480 case 16: 481 return PANEL_16BIT_PER_COLOR; 482 } 483 } 484 485 union dvo_encoder_control { 486 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 487 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 488 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 489 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 490 }; 491 492 void 493 atombios_dvo_setup(struct drm_encoder *encoder, int action) 494 { 495 struct drm_device *dev = encoder->dev; 496 struct radeon_device *rdev = dev->dev_private; 497 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 498 union dvo_encoder_control args; 499 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 500 uint8_t frev, crev; 501 502 memset(&args, 0, sizeof(args)); 503 504 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 505 return; 506 507 /* some R4xx chips have the wrong frev */ 508 if (rdev->family <= CHIP_RV410) 509 frev = 1; 510 511 switch (frev) { 512 case 1: 513 switch (crev) { 514 case 1: 515 /* R4xx, R5xx */ 516 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 517 518 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 519 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 520 521 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 522 break; 523 case 2: 524 /* RS600/690/740 */ 525 args.dvo.sDVOEncoder.ucAction = action; 526 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 527 /* DFP1, CRT1, TV1 depending on the type of port */ 528 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 529 530 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 531 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 532 break; 533 case 3: 534 /* R6xx */ 535 args.dvo_v3.ucAction = action; 536 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 537 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 538 break; 539 case 4: 540 /* DCE8 */ 541 args.dvo_v4.ucAction = action; 542 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 543 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 544 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 545 break; 546 default: 547 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 548 break; 549 } 550 break; 551 default: 552 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 553 break; 554 } 555 556 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 557 } 558 559 union lvds_encoder_control { 560 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 561 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 562 }; 563 564 void 565 atombios_digital_setup(struct drm_encoder *encoder, int action) 566 { 567 struct drm_device *dev = encoder->dev; 568 struct radeon_device *rdev = dev->dev_private; 569 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 570 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 571 union lvds_encoder_control args; 572 int index = 0; 573 int hdmi_detected = 0; 574 uint8_t frev, crev; 575 576 if (!dig) 577 return; 578 579 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 580 hdmi_detected = 1; 581 582 memset(&args, 0, sizeof(args)); 583 584 switch (radeon_encoder->encoder_id) { 585 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 586 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 587 break; 588 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 589 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 590 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 591 break; 592 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 593 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 594 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 595 else 596 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 597 break; 598 } 599 600 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 601 return; 602 603 switch (frev) { 604 case 1: 605 case 2: 606 switch (crev) { 607 case 1: 608 args.v1.ucMisc = 0; 609 args.v1.ucAction = action; 610 if (hdmi_detected) 611 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 612 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 613 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 614 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 615 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 616 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 617 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 618 } else { 619 if (dig->linkb) 620 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 621 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 622 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 623 /*if (pScrn->rgbBits == 8) */ 624 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 625 } 626 break; 627 case 2: 628 case 3: 629 args.v2.ucMisc = 0; 630 args.v2.ucAction = action; 631 if (crev == 3) { 632 if (dig->coherent_mode) 633 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 634 } 635 if (hdmi_detected) 636 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 637 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 638 args.v2.ucTruncate = 0; 639 args.v2.ucSpatial = 0; 640 args.v2.ucTemporal = 0; 641 args.v2.ucFRC = 0; 642 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 643 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 644 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 645 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 646 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 647 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 648 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 649 } 650 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 651 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 652 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 653 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 654 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 655 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 656 } 657 } else { 658 if (dig->linkb) 659 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 660 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 661 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 662 } 663 break; 664 default: 665 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 666 break; 667 } 668 break; 669 default: 670 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 671 break; 672 } 673 674 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 675 } 676 677 int 678 atombios_get_encoder_mode(struct drm_encoder *encoder) 679 { 680 struct drm_device *dev = encoder->dev; 681 struct radeon_device *rdev = dev->dev_private; 682 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 683 struct drm_connector *connector; 684 struct radeon_connector *radeon_connector; 685 struct radeon_connector_atom_dig *dig_connector; 686 struct radeon_encoder_atom_dig *dig_enc; 687 688 if (radeon_encoder_is_digital(encoder)) { 689 dig_enc = radeon_encoder->enc_priv; 690 if (dig_enc->active_mst_links) 691 return ATOM_ENCODER_MODE_DP_MST; 692 } 693 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset) 694 return ATOM_ENCODER_MODE_DP_MST; 695 /* dp bridges are always DP */ 696 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 697 return ATOM_ENCODER_MODE_DP; 698 699 /* DVO is always DVO */ 700 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 701 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 702 return ATOM_ENCODER_MODE_DVO; 703 704 connector = radeon_get_connector_for_encoder(encoder); 705 /* if we don't have an active device yet, just use one of 706 * the connectors tied to the encoder. 707 */ 708 if (!connector) 709 connector = radeon_get_connector_for_encoder_init(encoder); 710 radeon_connector = to_radeon_connector(connector); 711 712 switch (connector->connector_type) { 713 case DRM_MODE_CONNECTOR_DVII: 714 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 715 if (radeon_audio != 0) { 716 if (radeon_connector->use_digital && 717 (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 718 return ATOM_ENCODER_MODE_HDMI; 719 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 720 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 721 return ATOM_ENCODER_MODE_HDMI; 722 else if (radeon_connector->use_digital) 723 return ATOM_ENCODER_MODE_DVI; 724 else 725 return ATOM_ENCODER_MODE_CRT; 726 } else if (radeon_connector->use_digital) { 727 return ATOM_ENCODER_MODE_DVI; 728 } else { 729 return ATOM_ENCODER_MODE_CRT; 730 } 731 break; 732 case DRM_MODE_CONNECTOR_DVID: 733 case DRM_MODE_CONNECTOR_HDMIA: 734 default: 735 if (radeon_audio != 0) { 736 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 737 return ATOM_ENCODER_MODE_HDMI; 738 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 739 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 740 return ATOM_ENCODER_MODE_HDMI; 741 else 742 return ATOM_ENCODER_MODE_DVI; 743 } else { 744 return ATOM_ENCODER_MODE_DVI; 745 } 746 break; 747 case DRM_MODE_CONNECTOR_LVDS: 748 return ATOM_ENCODER_MODE_LVDS; 749 break; 750 case DRM_MODE_CONNECTOR_DisplayPort: 751 dig_connector = radeon_connector->con_priv; 752 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 753 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 754 if (radeon_audio != 0 && 755 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 756 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 757 return ATOM_ENCODER_MODE_DP_AUDIO; 758 return ATOM_ENCODER_MODE_DP; 759 } else if (radeon_audio != 0) { 760 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 761 return ATOM_ENCODER_MODE_HDMI; 762 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 763 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 764 return ATOM_ENCODER_MODE_HDMI; 765 else 766 return ATOM_ENCODER_MODE_DVI; 767 } else { 768 return ATOM_ENCODER_MODE_DVI; 769 } 770 break; 771 case DRM_MODE_CONNECTOR_eDP: 772 if (radeon_audio != 0 && 773 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 774 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 775 return ATOM_ENCODER_MODE_DP_AUDIO; 776 return ATOM_ENCODER_MODE_DP; 777 case DRM_MODE_CONNECTOR_DVIA: 778 case DRM_MODE_CONNECTOR_VGA: 779 return ATOM_ENCODER_MODE_CRT; 780 break; 781 case DRM_MODE_CONNECTOR_Composite: 782 case DRM_MODE_CONNECTOR_SVIDEO: 783 case DRM_MODE_CONNECTOR_9PinDIN: 784 /* fix me */ 785 return ATOM_ENCODER_MODE_TV; 786 /*return ATOM_ENCODER_MODE_CV;*/ 787 break; 788 } 789 } 790 791 /* 792 * DIG Encoder/Transmitter Setup 793 * 794 * DCE 3.0/3.1 795 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 796 * Supports up to 3 digital outputs 797 * - 2 DIG encoder blocks. 798 * DIG1 can drive UNIPHY link A or link B 799 * DIG2 can drive UNIPHY link B or LVTMA 800 * 801 * DCE 3.2 802 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 803 * Supports up to 5 digital outputs 804 * - 2 DIG encoder blocks. 805 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 806 * 807 * DCE 4.0/5.0/6.0 808 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 809 * Supports up to 6 digital outputs 810 * - 6 DIG encoder blocks. 811 * - DIG to PHY mapping is hardcoded 812 * DIG1 drives UNIPHY0 link A, A+B 813 * DIG2 drives UNIPHY0 link B 814 * DIG3 drives UNIPHY1 link A, A+B 815 * DIG4 drives UNIPHY1 link B 816 * DIG5 drives UNIPHY2 link A, A+B 817 * DIG6 drives UNIPHY2 link B 818 * 819 * DCE 4.1 820 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 821 * Supports up to 6 digital outputs 822 * - 2 DIG encoder blocks. 823 * llano 824 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 825 * ontario 826 * DIG1 drives UNIPHY0/1/2 link A 827 * DIG2 drives UNIPHY0/1/2 link B 828 * 829 * Routing 830 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 831 * Examples: 832 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 833 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 834 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 835 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 836 */ 837 838 union dig_encoder_control { 839 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 840 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 841 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 842 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 843 }; 844 845 void 846 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override) 847 { 848 struct drm_device *dev = encoder->dev; 849 struct radeon_device *rdev = dev->dev_private; 850 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 851 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 852 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 853 union dig_encoder_control args; 854 int index = 0; 855 uint8_t frev, crev; 856 int dp_clock = 0; 857 int dp_lane_count = 0; 858 int hpd_id = RADEON_HPD_NONE; 859 860 if (connector) { 861 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 862 struct radeon_connector_atom_dig *dig_connector = 863 radeon_connector->con_priv; 864 865 dp_clock = dig_connector->dp_clock; 866 dp_lane_count = dig_connector->dp_lane_count; 867 hpd_id = radeon_connector->hpd.hpd; 868 } 869 870 /* no dig encoder assigned */ 871 if (dig->dig_encoder == -1) 872 return; 873 874 memset(&args, 0, sizeof(args)); 875 876 if (ASIC_IS_DCE4(rdev)) 877 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 878 else { 879 if (dig->dig_encoder) 880 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 881 else 882 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 883 } 884 885 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 886 return; 887 888 switch (frev) { 889 case 1: 890 switch (crev) { 891 case 1: 892 args.v1.ucAction = action; 893 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 894 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 895 args.v3.ucPanelMode = panel_mode; 896 else 897 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 898 899 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 900 args.v1.ucLaneNum = dp_lane_count; 901 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 902 args.v1.ucLaneNum = 8; 903 else 904 args.v1.ucLaneNum = 4; 905 906 switch (radeon_encoder->encoder_id) { 907 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 908 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 909 break; 910 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 911 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 912 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 913 break; 914 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 915 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 916 break; 917 } 918 if (dig->linkb) 919 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 920 else 921 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 922 923 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 924 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 925 926 break; 927 case 2: 928 case 3: 929 args.v3.ucAction = action; 930 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 931 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 932 args.v3.ucPanelMode = panel_mode; 933 else 934 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 935 936 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 937 args.v3.ucLaneNum = dp_lane_count; 938 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 939 args.v3.ucLaneNum = 8; 940 else 941 args.v3.ucLaneNum = 4; 942 943 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 944 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 945 if (enc_override != -1) 946 args.v3.acConfig.ucDigSel = enc_override; 947 else 948 args.v3.acConfig.ucDigSel = dig->dig_encoder; 949 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 950 break; 951 case 4: 952 args.v4.ucAction = action; 953 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 954 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 955 args.v4.ucPanelMode = panel_mode; 956 else 957 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 958 959 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 960 args.v4.ucLaneNum = dp_lane_count; 961 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 962 args.v4.ucLaneNum = 8; 963 else 964 args.v4.ucLaneNum = 4; 965 966 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 967 if (dp_clock == 540000) 968 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 969 else if (dp_clock == 324000) 970 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 971 else if (dp_clock == 270000) 972 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 973 else 974 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 975 } 976 977 if (enc_override != -1) 978 args.v4.acConfig.ucDigSel = enc_override; 979 else 980 args.v4.acConfig.ucDigSel = dig->dig_encoder; 981 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 982 if (hpd_id == RADEON_HPD_NONE) 983 args.v4.ucHPD_ID = 0; 984 else 985 args.v4.ucHPD_ID = hpd_id + 1; 986 break; 987 default: 988 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 989 break; 990 } 991 break; 992 default: 993 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 994 break; 995 } 996 997 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 998 999 } 1000 1001 void 1002 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 1003 { 1004 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1); 1005 } 1006 1007 union dig_transmitter_control { 1008 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 1009 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 1010 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 1011 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 1012 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 1013 }; 1014 1015 void 1016 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe) 1017 { 1018 struct drm_device *dev = encoder->dev; 1019 struct radeon_device *rdev = dev->dev_private; 1020 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1021 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1022 struct drm_connector *connector; 1023 union dig_transmitter_control args; 1024 int index = 0; 1025 uint8_t frev, crev; 1026 bool is_dp = false; 1027 int pll_id = 0; 1028 int dp_clock = 0; 1029 int dp_lane_count = 0; 1030 int connector_object_id = 0; 1031 int igp_lane_info = 0; 1032 int dig_encoder = dig->dig_encoder; 1033 int hpd_id = RADEON_HPD_NONE; 1034 1035 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1036 connector = radeon_get_connector_for_encoder_init(encoder); 1037 /* just needed to avoid bailing in the encoder check. the encoder 1038 * isn't used for init 1039 */ 1040 dig_encoder = 0; 1041 } else 1042 connector = radeon_get_connector_for_encoder(encoder); 1043 1044 if (connector) { 1045 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1046 struct radeon_connector_atom_dig *dig_connector = 1047 radeon_connector->con_priv; 1048 1049 hpd_id = radeon_connector->hpd.hpd; 1050 dp_clock = dig_connector->dp_clock; 1051 dp_lane_count = dig_connector->dp_lane_count; 1052 connector_object_id = 1053 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1054 igp_lane_info = dig_connector->igp_lane_info; 1055 } 1056 1057 if (encoder->crtc) { 1058 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1059 pll_id = radeon_crtc->pll_id; 1060 } 1061 1062 /* no dig encoder assigned */ 1063 if (dig_encoder == -1) 1064 return; 1065 1066 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1067 is_dp = true; 1068 1069 memset(&args, 0, sizeof(args)); 1070 1071 switch (radeon_encoder->encoder_id) { 1072 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1073 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1074 break; 1075 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1076 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1077 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1078 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1079 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1080 break; 1081 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1082 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1083 break; 1084 } 1085 1086 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1087 return; 1088 1089 switch (frev) { 1090 case 1: 1091 switch (crev) { 1092 case 1: 1093 args.v1.ucAction = action; 1094 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1095 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1096 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1097 args.v1.asMode.ucLaneSel = lane_num; 1098 args.v1.asMode.ucLaneSet = lane_set; 1099 } else { 1100 if (is_dp) 1101 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1102 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1103 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1104 else 1105 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1106 } 1107 1108 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1109 1110 if (dig_encoder) 1111 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1112 else 1113 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1114 1115 if ((rdev->flags & RADEON_IS_IGP) && 1116 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1117 if (is_dp || 1118 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1119 if (igp_lane_info & 0x1) 1120 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1121 else if (igp_lane_info & 0x2) 1122 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1123 else if (igp_lane_info & 0x4) 1124 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1125 else if (igp_lane_info & 0x8) 1126 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1127 } else { 1128 if (igp_lane_info & 0x3) 1129 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1130 else if (igp_lane_info & 0xc) 1131 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1132 } 1133 } 1134 1135 if (dig->linkb) 1136 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1137 else 1138 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1139 1140 if (is_dp) 1141 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1142 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1143 if (dig->coherent_mode) 1144 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1145 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1146 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1147 } 1148 break; 1149 case 2: 1150 args.v2.ucAction = action; 1151 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1152 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1153 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1154 args.v2.asMode.ucLaneSel = lane_num; 1155 args.v2.asMode.ucLaneSet = lane_set; 1156 } else { 1157 if (is_dp) 1158 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1159 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1160 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1161 else 1162 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1163 } 1164 1165 args.v2.acConfig.ucEncoderSel = dig_encoder; 1166 if (dig->linkb) 1167 args.v2.acConfig.ucLinkSel = 1; 1168 1169 switch (radeon_encoder->encoder_id) { 1170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1171 args.v2.acConfig.ucTransmitterSel = 0; 1172 break; 1173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1174 args.v2.acConfig.ucTransmitterSel = 1; 1175 break; 1176 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1177 args.v2.acConfig.ucTransmitterSel = 2; 1178 break; 1179 } 1180 1181 if (is_dp) { 1182 args.v2.acConfig.fCoherentMode = 1; 1183 args.v2.acConfig.fDPConnector = 1; 1184 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1185 if (dig->coherent_mode) 1186 args.v2.acConfig.fCoherentMode = 1; 1187 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1188 args.v2.acConfig.fDualLinkConnector = 1; 1189 } 1190 break; 1191 case 3: 1192 args.v3.ucAction = action; 1193 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1194 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1195 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1196 args.v3.asMode.ucLaneSel = lane_num; 1197 args.v3.asMode.ucLaneSet = lane_set; 1198 } else { 1199 if (is_dp) 1200 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1201 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1202 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1203 else 1204 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1205 } 1206 1207 if (is_dp) 1208 args.v3.ucLaneNum = dp_lane_count; 1209 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1210 args.v3.ucLaneNum = 8; 1211 else 1212 args.v3.ucLaneNum = 4; 1213 1214 if (dig->linkb) 1215 args.v3.acConfig.ucLinkSel = 1; 1216 if (dig_encoder & 1) 1217 args.v3.acConfig.ucEncoderSel = 1; 1218 1219 /* Select the PLL for the PHY 1220 * DP PHY should be clocked from external src if there is 1221 * one. 1222 */ 1223 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1224 if (is_dp && rdev->clock.dp_extclk) 1225 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1226 else 1227 args.v3.acConfig.ucRefClkSource = pll_id; 1228 1229 switch (radeon_encoder->encoder_id) { 1230 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1231 args.v3.acConfig.ucTransmitterSel = 0; 1232 break; 1233 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1234 args.v3.acConfig.ucTransmitterSel = 1; 1235 break; 1236 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1237 args.v3.acConfig.ucTransmitterSel = 2; 1238 break; 1239 } 1240 1241 if (is_dp) 1242 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1243 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1244 if (dig->coherent_mode) 1245 args.v3.acConfig.fCoherentMode = 1; 1246 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1247 args.v3.acConfig.fDualLinkConnector = 1; 1248 } 1249 break; 1250 case 4: 1251 args.v4.ucAction = action; 1252 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1253 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1254 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1255 args.v4.asMode.ucLaneSel = lane_num; 1256 args.v4.asMode.ucLaneSet = lane_set; 1257 } else { 1258 if (is_dp) 1259 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1260 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1261 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1262 else 1263 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1264 } 1265 1266 if (is_dp) 1267 args.v4.ucLaneNum = dp_lane_count; 1268 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1269 args.v4.ucLaneNum = 8; 1270 else 1271 args.v4.ucLaneNum = 4; 1272 1273 if (dig->linkb) 1274 args.v4.acConfig.ucLinkSel = 1; 1275 if (dig_encoder & 1) 1276 args.v4.acConfig.ucEncoderSel = 1; 1277 1278 /* Select the PLL for the PHY 1279 * DP PHY should be clocked from external src if there is 1280 * one. 1281 */ 1282 /* On DCE5 DCPLL usually generates the DP ref clock */ 1283 if (is_dp) { 1284 if (rdev->clock.dp_extclk) 1285 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1286 else 1287 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1288 } else 1289 args.v4.acConfig.ucRefClkSource = pll_id; 1290 1291 switch (radeon_encoder->encoder_id) { 1292 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1293 args.v4.acConfig.ucTransmitterSel = 0; 1294 break; 1295 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1296 args.v4.acConfig.ucTransmitterSel = 1; 1297 break; 1298 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1299 args.v4.acConfig.ucTransmitterSel = 2; 1300 break; 1301 } 1302 1303 if (is_dp) 1304 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1305 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1306 if (dig->coherent_mode) 1307 args.v4.acConfig.fCoherentMode = 1; 1308 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1309 args.v4.acConfig.fDualLinkConnector = 1; 1310 } 1311 break; 1312 case 5: 1313 args.v5.ucAction = action; 1314 if (is_dp) 1315 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1316 else 1317 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1318 1319 switch (radeon_encoder->encoder_id) { 1320 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1321 if (dig->linkb) 1322 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1323 else 1324 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1325 break; 1326 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1327 if (dig->linkb) 1328 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1329 else 1330 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1331 break; 1332 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1333 if (dig->linkb) 1334 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1335 else 1336 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1337 break; 1338 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1339 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1340 break; 1341 } 1342 if (is_dp) 1343 args.v5.ucLaneNum = dp_lane_count; 1344 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1345 args.v5.ucLaneNum = 8; 1346 else 1347 args.v5.ucLaneNum = 4; 1348 args.v5.ucConnObjId = connector_object_id; 1349 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1350 1351 if (is_dp && rdev->clock.dp_extclk) 1352 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1353 else 1354 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1355 1356 if (is_dp) 1357 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1358 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1359 if (dig->coherent_mode) 1360 args.v5.asConfig.ucCoherentMode = 1; 1361 } 1362 if (hpd_id == RADEON_HPD_NONE) 1363 args.v5.asConfig.ucHPDSel = 0; 1364 else 1365 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1366 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder); 1367 args.v5.ucDPLaneSet = lane_set; 1368 break; 1369 default: 1370 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1371 break; 1372 } 1373 break; 1374 default: 1375 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1376 break; 1377 } 1378 1379 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1380 } 1381 1382 void 1383 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 1384 { 1385 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1); 1386 } 1387 1388 bool 1389 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1390 { 1391 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1392 struct drm_device *dev = radeon_connector->base.dev; 1393 struct radeon_device *rdev = dev->dev_private; 1394 union dig_transmitter_control args; 1395 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1396 uint8_t frev, crev; 1397 1398 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1399 goto done; 1400 1401 if (!ASIC_IS_DCE4(rdev)) 1402 goto done; 1403 1404 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1405 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1406 goto done; 1407 1408 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1409 goto done; 1410 1411 memset(&args, 0, sizeof(args)); 1412 1413 args.v1.ucAction = action; 1414 1415 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1416 1417 /* wait for the panel to power up */ 1418 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1419 int i; 1420 1421 for (i = 0; i < 300; i++) { 1422 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1423 return true; 1424 mdelay(1); 1425 } 1426 return false; 1427 } 1428 done: 1429 return true; 1430 } 1431 1432 union external_encoder_control { 1433 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1434 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1435 }; 1436 1437 static void 1438 atombios_external_encoder_setup(struct drm_encoder *encoder, 1439 struct drm_encoder *ext_encoder, 1440 int action) 1441 { 1442 struct drm_device *dev = encoder->dev; 1443 struct radeon_device *rdev = dev->dev_private; 1444 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1445 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1446 union external_encoder_control args; 1447 struct drm_connector *connector; 1448 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1449 u8 frev, crev; 1450 int dp_clock = 0; 1451 int dp_lane_count = 0; 1452 int connector_object_id = 0; 1453 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1454 1455 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1456 connector = radeon_get_connector_for_encoder_init(encoder); 1457 else 1458 connector = radeon_get_connector_for_encoder(encoder); 1459 1460 if (connector) { 1461 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1462 struct radeon_connector_atom_dig *dig_connector = 1463 radeon_connector->con_priv; 1464 1465 dp_clock = dig_connector->dp_clock; 1466 dp_lane_count = dig_connector->dp_lane_count; 1467 connector_object_id = 1468 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1469 } 1470 1471 memset(&args, 0, sizeof(args)); 1472 1473 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1474 return; 1475 1476 switch (frev) { 1477 case 1: 1478 /* no params on frev 1 */ 1479 break; 1480 case 2: 1481 switch (crev) { 1482 case 1: 1483 case 2: 1484 args.v1.sDigEncoder.ucAction = action; 1485 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1486 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1487 1488 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1489 if (dp_clock == 270000) 1490 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1491 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1492 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1493 args.v1.sDigEncoder.ucLaneNum = 8; 1494 else 1495 args.v1.sDigEncoder.ucLaneNum = 4; 1496 break; 1497 case 3: 1498 args.v3.sExtEncoder.ucAction = action; 1499 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1500 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1501 else 1502 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1503 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1504 1505 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1506 if (dp_clock == 270000) 1507 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1508 else if (dp_clock == 540000) 1509 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1510 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1511 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1512 args.v3.sExtEncoder.ucLaneNum = 8; 1513 else 1514 args.v3.sExtEncoder.ucLaneNum = 4; 1515 switch (ext_enum) { 1516 case GRAPH_OBJECT_ENUM_ID1: 1517 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1518 break; 1519 case GRAPH_OBJECT_ENUM_ID2: 1520 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1521 break; 1522 case GRAPH_OBJECT_ENUM_ID3: 1523 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1524 break; 1525 } 1526 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1527 break; 1528 default: 1529 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1530 return; 1531 } 1532 break; 1533 default: 1534 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1535 return; 1536 } 1537 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1538 } 1539 1540 static void 1541 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1542 { 1543 struct drm_device *dev = encoder->dev; 1544 struct radeon_device *rdev = dev->dev_private; 1545 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1546 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1547 ENABLE_YUV_PS_ALLOCATION args; 1548 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1549 uint32_t temp, reg; 1550 1551 memset(&args, 0, sizeof(args)); 1552 1553 if (rdev->family >= CHIP_R600) 1554 reg = R600_BIOS_3_SCRATCH; 1555 else 1556 reg = RADEON_BIOS_3_SCRATCH; 1557 1558 /* XXX: fix up scratch reg handling */ 1559 temp = RREG32(reg); 1560 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1561 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1562 (radeon_crtc->crtc_id << 18))); 1563 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1564 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1565 else 1566 WREG32(reg, 0); 1567 1568 if (enable) 1569 args.ucEnable = ATOM_ENABLE; 1570 args.ucCRTC = radeon_crtc->crtc_id; 1571 1572 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1573 1574 WREG32(reg, temp); 1575 } 1576 1577 static void 1578 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1579 { 1580 struct drm_device *dev = encoder->dev; 1581 struct radeon_device *rdev = dev->dev_private; 1582 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1583 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1584 int index = 0; 1585 1586 memset(&args, 0, sizeof(args)); 1587 1588 switch (radeon_encoder->encoder_id) { 1589 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1590 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1591 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1592 break; 1593 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1594 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1595 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1596 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1597 break; 1598 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1599 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1600 break; 1601 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1602 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1603 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1604 else 1605 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1606 break; 1607 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1608 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1609 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1610 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1611 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1612 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1613 else 1614 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1615 break; 1616 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1617 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1618 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1619 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1620 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1621 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1622 else 1623 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1624 break; 1625 default: 1626 return; 1627 } 1628 1629 switch (mode) { 1630 case DRM_MODE_DPMS_ON: 1631 args.ucAction = ATOM_ENABLE; 1632 /* workaround for DVOOutputControl on some RS690 systems */ 1633 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1634 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1635 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1636 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1637 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1638 } else 1639 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1640 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1641 if (rdev->mode_info.bl_encoder) { 1642 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1643 1644 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1645 } else { 1646 args.ucAction = ATOM_LCD_BLON; 1647 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1648 } 1649 } 1650 break; 1651 case DRM_MODE_DPMS_STANDBY: 1652 case DRM_MODE_DPMS_SUSPEND: 1653 case DRM_MODE_DPMS_OFF: 1654 args.ucAction = ATOM_DISABLE; 1655 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1656 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1657 args.ucAction = ATOM_LCD_BLOFF; 1658 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1659 } 1660 break; 1661 } 1662 } 1663 1664 static void 1665 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1666 { 1667 struct drm_device *dev = encoder->dev; 1668 struct radeon_device *rdev = dev->dev_private; 1669 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1670 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1671 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1672 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1673 struct radeon_connector *radeon_connector = NULL; 1674 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1675 bool travis_quirk = false; 1676 1677 if (connector) { 1678 radeon_connector = to_radeon_connector(connector); 1679 radeon_dig_connector = radeon_connector->con_priv; 1680 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 1681 ENCODER_OBJECT_ID_TRAVIS) && 1682 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 1683 !ASIC_IS_DCE5(rdev)) 1684 travis_quirk = true; 1685 } 1686 1687 switch (mode) { 1688 case DRM_MODE_DPMS_ON: 1689 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1690 if (!connector) 1691 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1692 else 1693 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1694 1695 /* setup and enable the encoder */ 1696 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1697 atombios_dig_encoder_setup(encoder, 1698 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1699 dig->panel_mode); 1700 if (ext_encoder) { 1701 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1702 atombios_external_encoder_setup(encoder, ext_encoder, 1703 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1704 } 1705 } else if (ASIC_IS_DCE4(rdev)) { 1706 /* setup and enable the encoder */ 1707 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1708 } else { 1709 /* setup and enable the encoder and transmitter */ 1710 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1711 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1712 } 1713 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1714 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1715 atombios_set_edp_panel_power(connector, 1716 ATOM_TRANSMITTER_ACTION_POWER_ON); 1717 radeon_dig_connector->edp_on = true; 1718 } 1719 } 1720 /* enable the transmitter */ 1721 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1722 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1723 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ 1724 radeon_dp_link_train(encoder, connector); 1725 if (ASIC_IS_DCE4(rdev)) 1726 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1727 } 1728 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1729 if (rdev->mode_info.bl_encoder) 1730 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1731 else 1732 atombios_dig_transmitter_setup(encoder, 1733 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1734 } 1735 if (ext_encoder) 1736 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1737 break; 1738 case DRM_MODE_DPMS_STANDBY: 1739 case DRM_MODE_DPMS_SUSPEND: 1740 case DRM_MODE_DPMS_OFF: 1741 1742 /* don't power off encoders with active MST links */ 1743 if (dig->active_mst_links) 1744 return; 1745 1746 if (ASIC_IS_DCE4(rdev)) { 1747 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) 1748 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1749 } 1750 if (ext_encoder) 1751 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1752 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1753 atombios_dig_transmitter_setup(encoder, 1754 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1755 1756 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && 1757 connector && !travis_quirk) 1758 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1759 if (ASIC_IS_DCE4(rdev)) { 1760 /* disable the transmitter */ 1761 atombios_dig_transmitter_setup(encoder, 1762 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1763 } else { 1764 /* disable the encoder and transmitter */ 1765 atombios_dig_transmitter_setup(encoder, 1766 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1767 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1768 } 1769 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1770 if (travis_quirk) 1771 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1772 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1773 atombios_set_edp_panel_power(connector, 1774 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1775 radeon_dig_connector->edp_on = false; 1776 } 1777 } 1778 break; 1779 } 1780 } 1781 1782 static void 1783 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1784 { 1785 struct drm_device *dev = encoder->dev; 1786 struct radeon_device *rdev = dev->dev_private; 1787 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1788 int encoder_mode = atombios_get_encoder_mode(encoder); 1789 1790 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1791 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1792 radeon_encoder->active_device); 1793 1794 if ((radeon_audio != 0) && 1795 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 1796 ENCODER_MODE_IS_DP(encoder_mode))) 1797 radeon_audio_dpms(encoder, mode); 1798 1799 switch (radeon_encoder->encoder_id) { 1800 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1801 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1802 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1803 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1804 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1805 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1806 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1807 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1808 radeon_atom_encoder_dpms_avivo(encoder, mode); 1809 break; 1810 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1811 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1812 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1813 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1814 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1815 radeon_atom_encoder_dpms_dig(encoder, mode); 1816 break; 1817 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1818 if (ASIC_IS_DCE5(rdev)) { 1819 switch (mode) { 1820 case DRM_MODE_DPMS_ON: 1821 atombios_dvo_setup(encoder, ATOM_ENABLE); 1822 break; 1823 case DRM_MODE_DPMS_STANDBY: 1824 case DRM_MODE_DPMS_SUSPEND: 1825 case DRM_MODE_DPMS_OFF: 1826 atombios_dvo_setup(encoder, ATOM_DISABLE); 1827 break; 1828 } 1829 } else if (ASIC_IS_DCE3(rdev)) 1830 radeon_atom_encoder_dpms_dig(encoder, mode); 1831 else 1832 radeon_atom_encoder_dpms_avivo(encoder, mode); 1833 break; 1834 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1835 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1836 if (ASIC_IS_DCE5(rdev)) { 1837 switch (mode) { 1838 case DRM_MODE_DPMS_ON: 1839 atombios_dac_setup(encoder, ATOM_ENABLE); 1840 break; 1841 case DRM_MODE_DPMS_STANDBY: 1842 case DRM_MODE_DPMS_SUSPEND: 1843 case DRM_MODE_DPMS_OFF: 1844 atombios_dac_setup(encoder, ATOM_DISABLE); 1845 break; 1846 } 1847 } else 1848 radeon_atom_encoder_dpms_avivo(encoder, mode); 1849 break; 1850 default: 1851 return; 1852 } 1853 1854 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1855 1856 } 1857 1858 union crtc_source_param { 1859 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1860 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1861 }; 1862 1863 static void 1864 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1865 { 1866 struct drm_device *dev = encoder->dev; 1867 struct radeon_device *rdev = dev->dev_private; 1868 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1869 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1870 union crtc_source_param args; 1871 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1872 uint8_t frev, crev; 1873 struct radeon_encoder_atom_dig *dig; 1874 1875 memset(&args, 0, sizeof(args)); 1876 1877 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1878 return; 1879 1880 switch (frev) { 1881 case 1: 1882 switch (crev) { 1883 case 1: 1884 default: 1885 if (ASIC_IS_AVIVO(rdev)) 1886 args.v1.ucCRTC = radeon_crtc->crtc_id; 1887 else { 1888 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1889 args.v1.ucCRTC = radeon_crtc->crtc_id; 1890 } else { 1891 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1892 } 1893 } 1894 switch (radeon_encoder->encoder_id) { 1895 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1896 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1897 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1898 break; 1899 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1900 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1901 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1902 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1903 else 1904 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1905 break; 1906 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1907 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1908 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1909 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1910 break; 1911 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1912 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1913 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1914 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1915 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1916 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1917 else 1918 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1919 break; 1920 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1921 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1922 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1923 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1924 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1925 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1926 else 1927 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1928 break; 1929 } 1930 break; 1931 case 2: 1932 args.v2.ucCRTC = radeon_crtc->crtc_id; 1933 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1934 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1935 1936 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1937 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1938 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1939 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1940 else 1941 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1942 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1943 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1944 } else { 1945 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1946 } 1947 switch (radeon_encoder->encoder_id) { 1948 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1949 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1950 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1951 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1952 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1953 dig = radeon_encoder->enc_priv; 1954 switch (dig->dig_encoder) { 1955 case 0: 1956 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1957 break; 1958 case 1: 1959 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1960 break; 1961 case 2: 1962 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1963 break; 1964 case 3: 1965 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1966 break; 1967 case 4: 1968 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1969 break; 1970 case 5: 1971 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1972 break; 1973 case 6: 1974 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 1975 break; 1976 } 1977 break; 1978 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1979 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1980 break; 1981 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1982 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1983 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1984 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1985 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1986 else 1987 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1988 break; 1989 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1990 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1991 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1992 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1993 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1994 else 1995 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1996 break; 1997 } 1998 break; 1999 } 2000 break; 2001 default: 2002 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 2003 return; 2004 } 2005 2006 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2007 2008 /* update scratch regs with new routing */ 2009 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 2010 } 2011 2012 void 2013 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe) 2014 { 2015 struct drm_device *dev = encoder->dev; 2016 struct radeon_device *rdev = dev->dev_private; 2017 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2018 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 2019 uint8_t frev, crev; 2020 union crtc_source_param args; 2021 2022 memset(&args, 0, sizeof(args)); 2023 2024 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2025 return; 2026 2027 if (frev != 1 && crev != 2) 2028 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev); 2029 2030 args.v2.ucCRTC = radeon_crtc->crtc_id; 2031 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST; 2032 2033 switch (fe) { 2034 case 0: 2035 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 2036 break; 2037 case 1: 2038 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 2039 break; 2040 case 2: 2041 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 2042 break; 2043 case 3: 2044 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 2045 break; 2046 case 4: 2047 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 2048 break; 2049 case 5: 2050 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 2051 break; 2052 case 6: 2053 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 2054 break; 2055 } 2056 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2057 } 2058 2059 static void 2060 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 2061 struct drm_display_mode *mode) 2062 { 2063 struct drm_device *dev = encoder->dev; 2064 struct radeon_device *rdev = dev->dev_private; 2065 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2066 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2067 2068 /* Funky macbooks */ 2069 if ((dev->pdev->device == 0x71C5) && 2070 (dev->pdev->subsystem_vendor == 0x106b) && 2071 (dev->pdev->subsystem_device == 0x0080)) { 2072 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 2073 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 2074 2075 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 2076 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 2077 2078 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 2079 } 2080 } 2081 2082 /* set scaler clears this on some chips */ 2083 if (ASIC_IS_AVIVO(rdev) && 2084 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 2085 if (ASIC_IS_DCE8(rdev)) { 2086 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2087 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 2088 CIK_INTERLEAVE_EN); 2089 else 2090 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2091 } else if (ASIC_IS_DCE4(rdev)) { 2092 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2093 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 2094 EVERGREEN_INTERLEAVE_EN); 2095 else 2096 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2097 } else { 2098 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2099 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 2100 AVIVO_D1MODE_INTERLEAVE_EN); 2101 else 2102 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2103 } 2104 } 2105 } 2106 2107 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx) 2108 { 2109 if (enc_idx < 0) 2110 return; 2111 rdev->mode_info.active_encoders &= ~(1 << enc_idx); 2112 } 2113 2114 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx) 2115 { 2116 struct drm_device *dev = encoder->dev; 2117 struct radeon_device *rdev = dev->dev_private; 2118 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2119 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2120 struct drm_encoder *test_encoder; 2121 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2122 uint32_t dig_enc_in_use = 0; 2123 int enc_idx = -1; 2124 2125 if (fe_idx >= 0) { 2126 enc_idx = fe_idx; 2127 goto assigned; 2128 } 2129 if (ASIC_IS_DCE6(rdev)) { 2130 /* DCE6 */ 2131 switch (radeon_encoder->encoder_id) { 2132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2133 if (dig->linkb) 2134 enc_idx = 1; 2135 else 2136 enc_idx = 0; 2137 break; 2138 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2139 if (dig->linkb) 2140 enc_idx = 3; 2141 else 2142 enc_idx = 2; 2143 break; 2144 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2145 if (dig->linkb) 2146 enc_idx = 5; 2147 else 2148 enc_idx = 4; 2149 break; 2150 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2151 enc_idx = 6; 2152 break; 2153 } 2154 goto assigned; 2155 } else if (ASIC_IS_DCE4(rdev)) { 2156 /* DCE4/5 */ 2157 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2158 /* ontario follows DCE4 */ 2159 if (rdev->family == CHIP_PALM) { 2160 if (dig->linkb) 2161 enc_idx = 1; 2162 else 2163 enc_idx = 0; 2164 } else 2165 /* llano follows DCE3.2 */ 2166 enc_idx = radeon_crtc->crtc_id; 2167 } else { 2168 switch (radeon_encoder->encoder_id) { 2169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2170 if (dig->linkb) 2171 enc_idx = 1; 2172 else 2173 enc_idx = 0; 2174 break; 2175 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2176 if (dig->linkb) 2177 enc_idx = 3; 2178 else 2179 enc_idx = 2; 2180 break; 2181 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2182 if (dig->linkb) 2183 enc_idx = 5; 2184 else 2185 enc_idx = 4; 2186 break; 2187 } 2188 } 2189 goto assigned; 2190 } 2191 2192 /* 2193 * On DCE32 any encoder can drive any block so usually just use crtc id, 2194 * but Apple thinks different at least on iMac10,1, so there use linkb, 2195 * otherwise the internal eDP panel will stay dark. 2196 */ 2197 if (ASIC_IS_DCE32(rdev)) { 2198 if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1")) 2199 enc_idx = (dig->linkb) ? 1 : 0; 2200 else 2201 enc_idx = radeon_crtc->crtc_id; 2202 2203 goto assigned; 2204 } 2205 2206 /* on DCE3 - LVTMA can only be driven by DIGB */ 2207 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2208 struct radeon_encoder *radeon_test_encoder; 2209 2210 if (encoder == test_encoder) 2211 continue; 2212 2213 if (!radeon_encoder_is_digital(test_encoder)) 2214 continue; 2215 2216 radeon_test_encoder = to_radeon_encoder(test_encoder); 2217 dig = radeon_test_encoder->enc_priv; 2218 2219 if (dig->dig_encoder >= 0) 2220 dig_enc_in_use |= (1 << dig->dig_encoder); 2221 } 2222 2223 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2224 if (dig_enc_in_use & 0x2) 2225 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2226 return 1; 2227 } 2228 if (!(dig_enc_in_use & 1)) 2229 return 0; 2230 return 1; 2231 2232 assigned: 2233 if (enc_idx == -1) { 2234 DRM_ERROR("Got encoder index incorrect - returning 0\n"); 2235 return 0; 2236 } 2237 if (rdev->mode_info.active_encoders & (1 << enc_idx)) { 2238 DRM_ERROR("chosen encoder in use %d\n", enc_idx); 2239 } 2240 rdev->mode_info.active_encoders |= (1 << enc_idx); 2241 return enc_idx; 2242 } 2243 2244 /* This only needs to be called once at startup */ 2245 void 2246 radeon_atom_encoder_init(struct radeon_device *rdev) 2247 { 2248 struct drm_device *dev = rdev->ddev; 2249 struct drm_encoder *encoder; 2250 2251 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2252 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2253 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2254 2255 switch (radeon_encoder->encoder_id) { 2256 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2257 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2258 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2259 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2260 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2261 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2262 break; 2263 default: 2264 break; 2265 } 2266 2267 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2268 atombios_external_encoder_setup(encoder, ext_encoder, 2269 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2270 } 2271 } 2272 2273 static void 2274 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2275 struct drm_display_mode *mode, 2276 struct drm_display_mode *adjusted_mode) 2277 { 2278 struct drm_device *dev = encoder->dev; 2279 struct radeon_device *rdev = dev->dev_private; 2280 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2281 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2282 int encoder_mode; 2283 2284 radeon_encoder->pixel_clock = adjusted_mode->clock; 2285 2286 /* need to call this here rather than in prepare() since we need some crtc info */ 2287 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2288 2289 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2290 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2291 atombios_yuv_setup(encoder, true); 2292 else 2293 atombios_yuv_setup(encoder, false); 2294 } 2295 2296 switch (radeon_encoder->encoder_id) { 2297 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2298 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2299 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2300 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2301 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2302 break; 2303 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2307 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2308 /* handled in dpms */ 2309 break; 2310 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2311 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2312 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2313 atombios_dvo_setup(encoder, ATOM_ENABLE); 2314 break; 2315 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2316 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2317 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2318 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2319 atombios_dac_setup(encoder, ATOM_ENABLE); 2320 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2321 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2322 atombios_tv_setup(encoder, ATOM_ENABLE); 2323 else 2324 atombios_tv_setup(encoder, ATOM_DISABLE); 2325 } 2326 break; 2327 } 2328 2329 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2330 2331 encoder_mode = atombios_get_encoder_mode(encoder); 2332 if (connector && (radeon_audio != 0) && 2333 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 2334 ENCODER_MODE_IS_DP(encoder_mode))) 2335 radeon_audio_mode_set(encoder, adjusted_mode); 2336 } 2337 2338 static bool 2339 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2340 { 2341 struct drm_device *dev = encoder->dev; 2342 struct radeon_device *rdev = dev->dev_private; 2343 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2344 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2345 2346 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2347 ATOM_DEVICE_CV_SUPPORT | 2348 ATOM_DEVICE_CRT_SUPPORT)) { 2349 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2350 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2351 uint8_t frev, crev; 2352 2353 memset(&args, 0, sizeof(args)); 2354 2355 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2356 return false; 2357 2358 args.sDacload.ucMisc = 0; 2359 2360 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2361 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2362 args.sDacload.ucDacType = ATOM_DAC_A; 2363 else 2364 args.sDacload.ucDacType = ATOM_DAC_B; 2365 2366 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2367 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2368 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2369 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2370 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2371 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2372 if (crev >= 3) 2373 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2374 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2375 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2376 if (crev >= 3) 2377 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2378 } 2379 2380 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2381 2382 return true; 2383 } else 2384 return false; 2385 } 2386 2387 static enum drm_connector_status 2388 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2389 { 2390 struct drm_device *dev = encoder->dev; 2391 struct radeon_device *rdev = dev->dev_private; 2392 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2393 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2394 uint32_t bios_0_scratch; 2395 2396 if (!atombios_dac_load_detect(encoder, connector)) { 2397 DRM_DEBUG_KMS("detect returned false \n"); 2398 return connector_status_unknown; 2399 } 2400 2401 if (rdev->family >= CHIP_R600) 2402 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2403 else 2404 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2405 2406 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2407 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2408 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2409 return connector_status_connected; 2410 } 2411 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2412 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2413 return connector_status_connected; 2414 } 2415 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2416 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2417 return connector_status_connected; 2418 } 2419 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2420 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2421 return connector_status_connected; /* CTV */ 2422 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2423 return connector_status_connected; /* STV */ 2424 } 2425 return connector_status_disconnected; 2426 } 2427 2428 static enum drm_connector_status 2429 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2430 { 2431 struct drm_device *dev = encoder->dev; 2432 struct radeon_device *rdev = dev->dev_private; 2433 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2434 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2435 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2436 u32 bios_0_scratch; 2437 2438 if (!ASIC_IS_DCE4(rdev)) 2439 return connector_status_unknown; 2440 2441 if (!ext_encoder) 2442 return connector_status_unknown; 2443 2444 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2445 return connector_status_unknown; 2446 2447 /* load detect on the dp bridge */ 2448 atombios_external_encoder_setup(encoder, ext_encoder, 2449 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2450 2451 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2452 2453 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2454 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2455 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2456 return connector_status_connected; 2457 } 2458 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2459 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2460 return connector_status_connected; 2461 } 2462 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2463 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2464 return connector_status_connected; 2465 } 2466 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2467 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2468 return connector_status_connected; /* CTV */ 2469 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2470 return connector_status_connected; /* STV */ 2471 } 2472 return connector_status_disconnected; 2473 } 2474 2475 void 2476 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2477 { 2478 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2479 2480 if (ext_encoder) 2481 /* ddc_setup on the dp bridge */ 2482 atombios_external_encoder_setup(encoder, ext_encoder, 2483 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2484 2485 } 2486 2487 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2488 { 2489 struct radeon_device *rdev = encoder->dev->dev_private; 2490 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2491 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2492 2493 if ((radeon_encoder->active_device & 2494 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2495 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2496 ENCODER_OBJECT_ID_NONE)) { 2497 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2498 if (dig) { 2499 if (dig->dig_encoder >= 0) 2500 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2501 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1); 2502 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2503 if (rdev->family >= CHIP_R600) 2504 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2505 else 2506 /* RS600/690/740 have only 1 afmt block */ 2507 dig->afmt = rdev->mode_info.afmt[0]; 2508 } 2509 } 2510 } 2511 2512 radeon_atom_output_lock(encoder, true); 2513 2514 if (connector) { 2515 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2516 2517 /* select the clock/data port if it uses a router */ 2518 if (radeon_connector->router.cd_valid) 2519 radeon_router_select_cd_port(radeon_connector); 2520 2521 /* turn eDP panel on for mode set */ 2522 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2523 atombios_set_edp_panel_power(connector, 2524 ATOM_TRANSMITTER_ACTION_POWER_ON); 2525 } 2526 2527 /* this is needed for the pll/ss setup to work correctly in some cases */ 2528 atombios_set_encoder_crtc_source(encoder); 2529 /* set up the FMT blocks */ 2530 if (ASIC_IS_DCE8(rdev)) 2531 dce8_program_fmt(encoder); 2532 else if (ASIC_IS_DCE4(rdev)) 2533 dce4_program_fmt(encoder); 2534 else if (ASIC_IS_DCE3(rdev)) 2535 dce3_program_fmt(encoder); 2536 else if (ASIC_IS_AVIVO(rdev)) 2537 avivo_program_fmt(encoder); 2538 } 2539 2540 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2541 { 2542 /* need to call this here as we need the crtc set up */ 2543 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2544 radeon_atom_output_lock(encoder, false); 2545 } 2546 2547 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2548 { 2549 struct drm_device *dev = encoder->dev; 2550 struct radeon_device *rdev = dev->dev_private; 2551 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2552 struct radeon_encoder_atom_dig *dig; 2553 2554 /* check for pre-DCE3 cards with shared encoders; 2555 * can't really use the links individually, so don't disable 2556 * the encoder if it's in use by another connector 2557 */ 2558 if (!ASIC_IS_DCE3(rdev)) { 2559 struct drm_encoder *other_encoder; 2560 struct radeon_encoder *other_radeon_encoder; 2561 2562 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2563 other_radeon_encoder = to_radeon_encoder(other_encoder); 2564 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2565 drm_helper_encoder_in_use(other_encoder)) 2566 goto disable_done; 2567 } 2568 } 2569 2570 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2571 2572 switch (radeon_encoder->encoder_id) { 2573 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2574 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2575 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2576 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2577 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2578 break; 2579 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2580 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2581 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2582 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2583 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2584 /* handled in dpms */ 2585 break; 2586 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2587 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2588 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2589 atombios_dvo_setup(encoder, ATOM_DISABLE); 2590 break; 2591 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2592 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2593 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2594 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2595 atombios_dac_setup(encoder, ATOM_DISABLE); 2596 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2597 atombios_tv_setup(encoder, ATOM_DISABLE); 2598 break; 2599 } 2600 2601 disable_done: 2602 if (radeon_encoder_is_digital(encoder)) { 2603 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2604 if (rdev->asic->display.hdmi_enable) 2605 radeon_hdmi_enable(rdev, encoder, false); 2606 } 2607 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) { 2608 dig = radeon_encoder->enc_priv; 2609 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2610 dig->dig_encoder = -1; 2611 radeon_encoder->active_device = 0; 2612 } 2613 } else 2614 radeon_encoder->active_device = 0; 2615 } 2616 2617 /* these are handled by the primary encoders */ 2618 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2619 { 2620 2621 } 2622 2623 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2624 { 2625 2626 } 2627 2628 static void 2629 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2630 struct drm_display_mode *mode, 2631 struct drm_display_mode *adjusted_mode) 2632 { 2633 2634 } 2635 2636 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2637 { 2638 2639 } 2640 2641 static void 2642 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2643 { 2644 2645 } 2646 2647 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2648 .dpms = radeon_atom_ext_dpms, 2649 .prepare = radeon_atom_ext_prepare, 2650 .mode_set = radeon_atom_ext_mode_set, 2651 .commit = radeon_atom_ext_commit, 2652 .disable = radeon_atom_ext_disable, 2653 /* no detect for TMDS/LVDS yet */ 2654 }; 2655 2656 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2657 .dpms = radeon_atom_encoder_dpms, 2658 .mode_fixup = radeon_atom_mode_fixup, 2659 .prepare = radeon_atom_encoder_prepare, 2660 .mode_set = radeon_atom_encoder_mode_set, 2661 .commit = radeon_atom_encoder_commit, 2662 .disable = radeon_atom_encoder_disable, 2663 .detect = radeon_atom_dig_detect, 2664 }; 2665 2666 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2667 .dpms = radeon_atom_encoder_dpms, 2668 .mode_fixup = radeon_atom_mode_fixup, 2669 .prepare = radeon_atom_encoder_prepare, 2670 .mode_set = radeon_atom_encoder_mode_set, 2671 .commit = radeon_atom_encoder_commit, 2672 .detect = radeon_atom_dac_detect, 2673 }; 2674 2675 void radeon_enc_destroy(struct drm_encoder *encoder) 2676 { 2677 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2678 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2679 radeon_atom_backlight_exit(radeon_encoder); 2680 kfree(radeon_encoder->enc_priv); 2681 drm_encoder_cleanup(encoder); 2682 kfree(radeon_encoder); 2683 } 2684 2685 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2686 .destroy = radeon_enc_destroy, 2687 }; 2688 2689 static struct radeon_encoder_atom_dac * 2690 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2691 { 2692 struct drm_device *dev = radeon_encoder->base.dev; 2693 struct radeon_device *rdev = dev->dev_private; 2694 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2695 2696 if (!dac) 2697 return NULL; 2698 2699 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2700 return dac; 2701 } 2702 2703 static struct radeon_encoder_atom_dig * 2704 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2705 { 2706 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2707 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2708 2709 if (!dig) 2710 return NULL; 2711 2712 /* coherent mode by default */ 2713 dig->coherent_mode = true; 2714 dig->dig_encoder = -1; 2715 2716 if (encoder_enum == 2) 2717 dig->linkb = true; 2718 else 2719 dig->linkb = false; 2720 2721 return dig; 2722 } 2723 2724 void 2725 radeon_add_atom_encoder(struct drm_device *dev, 2726 uint32_t encoder_enum, 2727 uint32_t supported_device, 2728 u16 caps) 2729 { 2730 struct radeon_device *rdev = dev->dev_private; 2731 struct drm_encoder *encoder; 2732 struct radeon_encoder *radeon_encoder; 2733 2734 /* see if we already added it */ 2735 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2736 radeon_encoder = to_radeon_encoder(encoder); 2737 if (radeon_encoder->encoder_enum == encoder_enum) { 2738 radeon_encoder->devices |= supported_device; 2739 return; 2740 } 2741 2742 } 2743 2744 /* add a new one */ 2745 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2746 if (!radeon_encoder) 2747 return; 2748 2749 encoder = &radeon_encoder->base; 2750 switch (rdev->num_crtc) { 2751 case 1: 2752 encoder->possible_crtcs = 0x1; 2753 break; 2754 case 2: 2755 default: 2756 encoder->possible_crtcs = 0x3; 2757 break; 2758 case 4: 2759 encoder->possible_crtcs = 0xf; 2760 break; 2761 case 6: 2762 encoder->possible_crtcs = 0x3f; 2763 break; 2764 } 2765 2766 radeon_encoder->enc_priv = NULL; 2767 2768 radeon_encoder->encoder_enum = encoder_enum; 2769 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2770 radeon_encoder->devices = supported_device; 2771 radeon_encoder->rmx_type = RMX_OFF; 2772 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2773 radeon_encoder->is_ext_encoder = false; 2774 radeon_encoder->caps = caps; 2775 2776 switch (radeon_encoder->encoder_id) { 2777 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2778 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2779 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2780 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2781 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2782 radeon_encoder->rmx_type = RMX_FULL; 2783 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2784 DRM_MODE_ENCODER_LVDS, NULL); 2785 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2786 } else { 2787 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2788 DRM_MODE_ENCODER_TMDS, NULL); 2789 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2790 } 2791 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2792 break; 2793 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2794 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2795 DRM_MODE_ENCODER_DAC, NULL); 2796 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2797 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2798 break; 2799 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2800 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2801 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2802 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2803 DRM_MODE_ENCODER_TVDAC, NULL); 2804 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2805 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2806 break; 2807 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2808 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2809 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2810 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2811 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2812 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2813 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2814 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2815 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2816 radeon_encoder->rmx_type = RMX_FULL; 2817 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2818 DRM_MODE_ENCODER_LVDS, NULL); 2819 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2820 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2821 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2822 DRM_MODE_ENCODER_DAC, NULL); 2823 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2824 } else { 2825 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2826 DRM_MODE_ENCODER_TMDS, NULL); 2827 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2828 } 2829 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2830 break; 2831 case ENCODER_OBJECT_ID_SI170B: 2832 case ENCODER_OBJECT_ID_CH7303: 2833 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2834 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2835 case ENCODER_OBJECT_ID_TITFP513: 2836 case ENCODER_OBJECT_ID_VT1623: 2837 case ENCODER_OBJECT_ID_HDMI_SI1930: 2838 case ENCODER_OBJECT_ID_TRAVIS: 2839 case ENCODER_OBJECT_ID_NUTMEG: 2840 /* these are handled by the primary encoders */ 2841 radeon_encoder->is_ext_encoder = true; 2842 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2843 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2844 DRM_MODE_ENCODER_LVDS, NULL); 2845 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2846 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2847 DRM_MODE_ENCODER_DAC, NULL); 2848 else 2849 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2850 DRM_MODE_ENCODER_TMDS, NULL); 2851 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2852 break; 2853 } 2854 } 2855