1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "radeon.h" 27 #include "radeon_asic.h" 28 #include "radeon_ucode.h" 29 #include "cikd.h" 30 #include "r600_dpm.h" 31 #include "ci_dpm.h" 32 #include "ni_dpm.h" 33 #include "atom.h" 34 #include <linux/seq_file.h> 35 36 #define MC_CG_ARB_FREQ_F0 0x0a 37 #define MC_CG_ARB_FREQ_F1 0x0b 38 #define MC_CG_ARB_FREQ_F2 0x0c 39 #define MC_CG_ARB_FREQ_F3 0x0d 40 41 #define SMC_RAM_END 0x40000 42 43 #define VOLTAGE_SCALE 4 44 #define VOLTAGE_VID_OFFSET_SCALE1 625 45 #define VOLTAGE_VID_OFFSET_SCALE2 100 46 47 static const struct ci_pt_defaults defaults_hawaii_xt = 48 { 49 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000, 50 { 0x84, 0x0, 0x0, 0x7F, 0x0, 0x0, 0x5A, 0x60, 0x51, 0x8E, 0x79, 0x6B, 0x5F, 0x90, 0x79 }, 51 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC } 52 }; 53 54 static const struct ci_pt_defaults defaults_hawaii_pro = 55 { 56 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062, 57 { 0x93, 0x0, 0x0, 0x97, 0x0, 0x0, 0x6B, 0x60, 0x51, 0x95, 0x79, 0x6B, 0x5F, 0x90, 0x79 }, 58 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC } 59 }; 60 61 static const struct ci_pt_defaults defaults_bonaire_xt = 62 { 63 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, 64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 }, 65 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } 66 }; 67 68 static const struct ci_pt_defaults defaults_bonaire_pro = 69 { 70 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062, 71 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F }, 72 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB } 73 }; 74 75 static const struct ci_pt_defaults defaults_saturn_xt = 76 { 77 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000, 78 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D }, 79 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 } 80 }; 81 82 static const struct ci_pt_defaults defaults_saturn_pro = 83 { 84 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000, 85 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A }, 86 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 } 87 }; 88 89 static const struct ci_pt_config_reg didt_config_ci[] = 90 { 91 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 92 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 93 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 94 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 95 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 96 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 97 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 98 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 99 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 100 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 101 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 102 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 103 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 104 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 105 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 106 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 107 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 108 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 109 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 110 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 111 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 112 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 113 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 114 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 115 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 116 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 117 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 118 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 119 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 120 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 121 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 122 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 123 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 124 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 125 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 126 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 127 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 128 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 129 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 130 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 131 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 132 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 133 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 134 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 135 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 136 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 137 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 138 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 139 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 140 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 141 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 142 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 143 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 144 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 145 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 146 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 147 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 148 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 149 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 150 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 151 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 152 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 153 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 154 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 155 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 156 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 157 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 158 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 159 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 160 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 161 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 162 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 163 { 0xFFFFFFFF } 164 }; 165 166 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 167 struct atom_voltage_table_entry *voltage_table, 168 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd); 169 static int ci_set_power_limit(struct radeon_device *rdev, u32 n); 170 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, 171 u32 target_tdp); 172 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate); 173 174 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev) 175 { 176 struct ci_power_info *pi = rdev->pm.dpm.priv; 177 178 return pi; 179 } 180 181 static struct ci_ps *ci_get_ps(struct radeon_ps *rps) 182 { 183 struct ci_ps *ps = rps->ps_priv; 184 185 return ps; 186 } 187 188 static void ci_initialize_powertune_defaults(struct radeon_device *rdev) 189 { 190 struct ci_power_info *pi = ci_get_pi(rdev); 191 192 switch (rdev->pdev->device) { 193 case 0x6649: 194 case 0x6650: 195 case 0x6651: 196 case 0x6658: 197 case 0x665C: 198 case 0x665D: 199 default: 200 pi->powertune_defaults = &defaults_bonaire_xt; 201 break; 202 case 0x6640: 203 case 0x6641: 204 case 0x6646: 205 case 0x6647: 206 pi->powertune_defaults = &defaults_saturn_xt; 207 break; 208 case 0x67B8: 209 case 0x67B0: 210 pi->powertune_defaults = &defaults_hawaii_xt; 211 break; 212 case 0x67BA: 213 case 0x67B1: 214 pi->powertune_defaults = &defaults_hawaii_pro; 215 break; 216 case 0x67A0: 217 case 0x67A1: 218 case 0x67A2: 219 case 0x67A8: 220 case 0x67A9: 221 case 0x67AA: 222 case 0x67B9: 223 case 0x67BE: 224 pi->powertune_defaults = &defaults_bonaire_xt; 225 break; 226 } 227 228 pi->dte_tj_offset = 0; 229 230 pi->caps_power_containment = true; 231 pi->caps_cac = false; 232 pi->caps_sq_ramping = false; 233 pi->caps_db_ramping = false; 234 pi->caps_td_ramping = false; 235 pi->caps_tcp_ramping = false; 236 237 if (pi->caps_power_containment) { 238 pi->caps_cac = true; 239 pi->enable_bapm_feature = true; 240 pi->enable_tdc_limit_feature = true; 241 pi->enable_pkg_pwr_tracking_feature = true; 242 } 243 } 244 245 static u8 ci_convert_to_vid(u16 vddc) 246 { 247 return (6200 - (vddc * VOLTAGE_SCALE)) / 25; 248 } 249 250 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev) 251 { 252 struct ci_power_info *pi = ci_get_pi(rdev); 253 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; 254 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; 255 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; 256 u32 i; 257 258 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) 259 return -EINVAL; 260 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) 261 return -EINVAL; 262 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != 263 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) 264 return -EINVAL; 265 266 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { 267 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { 268 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); 269 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); 270 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); 271 } else { 272 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); 273 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); 274 } 275 } 276 return 0; 277 } 278 279 static int ci_populate_vddc_vid(struct radeon_device *rdev) 280 { 281 struct ci_power_info *pi = ci_get_pi(rdev); 282 u8 *vid = pi->smc_powertune_table.VddCVid; 283 u32 i; 284 285 if (pi->vddc_voltage_table.count > 8) 286 return -EINVAL; 287 288 for (i = 0; i < pi->vddc_voltage_table.count; i++) 289 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); 290 291 return 0; 292 } 293 294 static int ci_populate_svi_load_line(struct radeon_device *rdev) 295 { 296 struct ci_power_info *pi = ci_get_pi(rdev); 297 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 298 299 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; 300 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; 301 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; 302 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; 303 304 return 0; 305 } 306 307 static int ci_populate_tdc_limit(struct radeon_device *rdev) 308 { 309 struct ci_power_info *pi = ci_get_pi(rdev); 310 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 311 u16 tdc_limit; 312 313 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; 314 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); 315 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = 316 pt_defaults->tdc_vddc_throttle_release_limit_perc; 317 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; 318 319 return 0; 320 } 321 322 static int ci_populate_dw8(struct radeon_device *rdev) 323 { 324 struct ci_power_info *pi = ci_get_pi(rdev); 325 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 326 int ret; 327 328 ret = ci_read_smc_sram_dword(rdev, 329 SMU7_FIRMWARE_HEADER_LOCATION + 330 offsetof(SMU7_Firmware_Header, PmFuseTable) + 331 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl), 332 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, 333 pi->sram_end); 334 if (ret) 335 return -EINVAL; 336 else 337 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; 338 339 return 0; 340 } 341 342 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev) 343 { 344 struct ci_power_info *pi = ci_get_pi(rdev); 345 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; 346 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; 347 int i, min, max; 348 349 min = max = hi_vid[0]; 350 for (i = 0; i < 8; i++) { 351 if (0 != hi_vid[i]) { 352 if (min > hi_vid[i]) 353 min = hi_vid[i]; 354 if (max < hi_vid[i]) 355 max = hi_vid[i]; 356 } 357 358 if (0 != lo_vid[i]) { 359 if (min > lo_vid[i]) 360 min = lo_vid[i]; 361 if (max < lo_vid[i]) 362 max = lo_vid[i]; 363 } 364 } 365 366 if ((min == 0) || (max == 0)) 367 return -EINVAL; 368 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; 369 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; 370 371 return 0; 372 } 373 374 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev) 375 { 376 struct ci_power_info *pi = ci_get_pi(rdev); 377 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; 378 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; 379 struct radeon_cac_tdp_table *cac_tdp_table = 380 rdev->pm.dpm.dyn_state.cac_tdp_table; 381 382 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256; 383 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256; 384 385 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); 386 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); 387 388 return 0; 389 } 390 391 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev) 392 { 393 struct ci_power_info *pi = ci_get_pi(rdev); 394 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 395 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; 396 struct radeon_cac_tdp_table *cac_tdp_table = 397 rdev->pm.dpm.dyn_state.cac_tdp_table; 398 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 399 int i, j, k; 400 const u16 *def1; 401 const u16 *def2; 402 403 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; 404 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; 405 406 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; 407 dpm_table->GpuTjMax = 408 (u8)(pi->thermal_temp_setting.temperature_high / 1000); 409 dpm_table->GpuTjHyst = 8; 410 411 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; 412 413 if (ppm) { 414 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); 415 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); 416 } else { 417 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); 418 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); 419 } 420 421 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient); 422 def1 = pt_defaults->bapmti_r; 423 def2 = pt_defaults->bapmti_rc; 424 425 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) { 426 for (j = 0; j < SMU7_DTE_SOURCES; j++) { 427 for (k = 0; k < SMU7_DTE_SINKS; k++) { 428 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); 429 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); 430 def1++; 431 def2++; 432 } 433 } 434 } 435 436 return 0; 437 } 438 439 static int ci_populate_pm_base(struct radeon_device *rdev) 440 { 441 struct ci_power_info *pi = ci_get_pi(rdev); 442 u32 pm_fuse_table_offset; 443 int ret; 444 445 if (pi->caps_power_containment) { 446 ret = ci_read_smc_sram_dword(rdev, 447 SMU7_FIRMWARE_HEADER_LOCATION + 448 offsetof(SMU7_Firmware_Header, PmFuseTable), 449 &pm_fuse_table_offset, pi->sram_end); 450 if (ret) 451 return ret; 452 ret = ci_populate_bapm_vddc_vid_sidd(rdev); 453 if (ret) 454 return ret; 455 ret = ci_populate_vddc_vid(rdev); 456 if (ret) 457 return ret; 458 ret = ci_populate_svi_load_line(rdev); 459 if (ret) 460 return ret; 461 ret = ci_populate_tdc_limit(rdev); 462 if (ret) 463 return ret; 464 ret = ci_populate_dw8(rdev); 465 if (ret) 466 return ret; 467 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev); 468 if (ret) 469 return ret; 470 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev); 471 if (ret) 472 return ret; 473 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset, 474 (u8 *)&pi->smc_powertune_table, 475 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); 476 if (ret) 477 return ret; 478 } 479 480 return 0; 481 } 482 483 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable) 484 { 485 struct ci_power_info *pi = ci_get_pi(rdev); 486 u32 data; 487 488 if (pi->caps_sq_ramping) { 489 data = RREG32_DIDT(DIDT_SQ_CTRL0); 490 if (enable) 491 data |= DIDT_CTRL_EN; 492 else 493 data &= ~DIDT_CTRL_EN; 494 WREG32_DIDT(DIDT_SQ_CTRL0, data); 495 } 496 497 if (pi->caps_db_ramping) { 498 data = RREG32_DIDT(DIDT_DB_CTRL0); 499 if (enable) 500 data |= DIDT_CTRL_EN; 501 else 502 data &= ~DIDT_CTRL_EN; 503 WREG32_DIDT(DIDT_DB_CTRL0, data); 504 } 505 506 if (pi->caps_td_ramping) { 507 data = RREG32_DIDT(DIDT_TD_CTRL0); 508 if (enable) 509 data |= DIDT_CTRL_EN; 510 else 511 data &= ~DIDT_CTRL_EN; 512 WREG32_DIDT(DIDT_TD_CTRL0, data); 513 } 514 515 if (pi->caps_tcp_ramping) { 516 data = RREG32_DIDT(DIDT_TCP_CTRL0); 517 if (enable) 518 data |= DIDT_CTRL_EN; 519 else 520 data &= ~DIDT_CTRL_EN; 521 WREG32_DIDT(DIDT_TCP_CTRL0, data); 522 } 523 } 524 525 static int ci_program_pt_config_registers(struct radeon_device *rdev, 526 const struct ci_pt_config_reg *cac_config_regs) 527 { 528 const struct ci_pt_config_reg *config_regs = cac_config_regs; 529 u32 data; 530 u32 cache = 0; 531 532 if (config_regs == NULL) 533 return -EINVAL; 534 535 while (config_regs->offset != 0xFFFFFFFF) { 536 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) { 537 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); 538 } else { 539 switch (config_regs->type) { 540 case CISLANDS_CONFIGREG_SMC_IND: 541 data = RREG32_SMC(config_regs->offset); 542 break; 543 case CISLANDS_CONFIGREG_DIDT_IND: 544 data = RREG32_DIDT(config_regs->offset); 545 break; 546 default: 547 data = RREG32(config_regs->offset << 2); 548 break; 549 } 550 551 data &= ~config_regs->mask; 552 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 553 data |= cache; 554 555 switch (config_regs->type) { 556 case CISLANDS_CONFIGREG_SMC_IND: 557 WREG32_SMC(config_regs->offset, data); 558 break; 559 case CISLANDS_CONFIGREG_DIDT_IND: 560 WREG32_DIDT(config_regs->offset, data); 561 break; 562 default: 563 WREG32(config_regs->offset << 2, data); 564 break; 565 } 566 cache = 0; 567 } 568 config_regs++; 569 } 570 return 0; 571 } 572 573 static int ci_enable_didt(struct radeon_device *rdev, bool enable) 574 { 575 struct ci_power_info *pi = ci_get_pi(rdev); 576 int ret; 577 578 if (pi->caps_sq_ramping || pi->caps_db_ramping || 579 pi->caps_td_ramping || pi->caps_tcp_ramping) { 580 cik_enter_rlc_safe_mode(rdev); 581 582 if (enable) { 583 ret = ci_program_pt_config_registers(rdev, didt_config_ci); 584 if (ret) { 585 cik_exit_rlc_safe_mode(rdev); 586 return ret; 587 } 588 } 589 590 ci_do_enable_didt(rdev, enable); 591 592 cik_exit_rlc_safe_mode(rdev); 593 } 594 595 return 0; 596 } 597 598 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable) 599 { 600 struct ci_power_info *pi = ci_get_pi(rdev); 601 PPSMC_Result smc_result; 602 int ret = 0; 603 604 if (enable) { 605 pi->power_containment_features = 0; 606 if (pi->caps_power_containment) { 607 if (pi->enable_bapm_feature) { 608 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 609 if (smc_result != PPSMC_Result_OK) 610 ret = -EINVAL; 611 else 612 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; 613 } 614 615 if (pi->enable_tdc_limit_feature) { 616 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable); 617 if (smc_result != PPSMC_Result_OK) 618 ret = -EINVAL; 619 else 620 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; 621 } 622 623 if (pi->enable_pkg_pwr_tracking_feature) { 624 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable); 625 if (smc_result != PPSMC_Result_OK) { 626 ret = -EINVAL; 627 } else { 628 struct radeon_cac_tdp_table *cac_tdp_table = 629 rdev->pm.dpm.dyn_state.cac_tdp_table; 630 u32 default_pwr_limit = 631 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); 632 633 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; 634 635 ci_set_power_limit(rdev, default_pwr_limit); 636 } 637 } 638 } 639 } else { 640 if (pi->caps_power_containment && pi->power_containment_features) { 641 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) 642 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable); 643 644 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) 645 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 646 647 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) 648 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable); 649 pi->power_containment_features = 0; 650 } 651 } 652 653 return ret; 654 } 655 656 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable) 657 { 658 struct ci_power_info *pi = ci_get_pi(rdev); 659 PPSMC_Result smc_result; 660 int ret = 0; 661 662 if (pi->caps_cac) { 663 if (enable) { 664 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 665 if (smc_result != PPSMC_Result_OK) { 666 ret = -EINVAL; 667 pi->cac_enabled = false; 668 } else { 669 pi->cac_enabled = true; 670 } 671 } else if (pi->cac_enabled) { 672 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 673 pi->cac_enabled = false; 674 } 675 } 676 677 return ret; 678 } 679 680 static int ci_power_control_set_level(struct radeon_device *rdev) 681 { 682 struct ci_power_info *pi = ci_get_pi(rdev); 683 struct radeon_cac_tdp_table *cac_tdp_table = 684 rdev->pm.dpm.dyn_state.cac_tdp_table; 685 s32 adjust_percent; 686 s32 target_tdp; 687 int ret = 0; 688 bool adjust_polarity = false; /* ??? */ 689 690 if (pi->caps_power_containment && 691 (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) { 692 adjust_percent = adjust_polarity ? 693 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); 694 target_tdp = ((100 + adjust_percent) * 695 (s32)cac_tdp_table->configurable_tdp) / 100; 696 target_tdp *= 256; 697 698 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp); 699 } 700 701 return ret; 702 } 703 704 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) 705 { 706 struct ci_power_info *pi = ci_get_pi(rdev); 707 708 if (pi->uvd_power_gated == gate) 709 return; 710 711 pi->uvd_power_gated = gate; 712 713 ci_update_uvd_dpm(rdev, gate); 714 } 715 716 bool ci_dpm_vblank_too_short(struct radeon_device *rdev) 717 { 718 struct ci_power_info *pi = ci_get_pi(rdev); 719 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 720 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; 721 722 if (vblank_time < switch_limit) 723 return true; 724 else 725 return false; 726 727 } 728 729 static void ci_apply_state_adjust_rules(struct radeon_device *rdev, 730 struct radeon_ps *rps) 731 { 732 struct ci_ps *ps = ci_get_ps(rps); 733 struct ci_power_info *pi = ci_get_pi(rdev); 734 struct radeon_clock_and_voltage_limits *max_limits; 735 bool disable_mclk_switching; 736 u32 sclk, mclk; 737 int i; 738 739 if (rps->vce_active) { 740 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 741 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 742 } else { 743 rps->evclk = 0; 744 rps->ecclk = 0; 745 } 746 747 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 748 ci_dpm_vblank_too_short(rdev)) 749 disable_mclk_switching = true; 750 else 751 disable_mclk_switching = false; 752 753 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) 754 pi->battery_state = true; 755 else 756 pi->battery_state = false; 757 758 if (rdev->pm.dpm.ac_power) 759 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 760 else 761 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 762 763 if (rdev->pm.dpm.ac_power == false) { 764 for (i = 0; i < ps->performance_level_count; i++) { 765 if (ps->performance_levels[i].mclk > max_limits->mclk) 766 ps->performance_levels[i].mclk = max_limits->mclk; 767 if (ps->performance_levels[i].sclk > max_limits->sclk) 768 ps->performance_levels[i].sclk = max_limits->sclk; 769 } 770 } 771 772 /* XXX validate the min clocks required for display */ 773 774 if (disable_mclk_switching) { 775 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 776 sclk = ps->performance_levels[0].sclk; 777 } else { 778 mclk = ps->performance_levels[0].mclk; 779 sclk = ps->performance_levels[0].sclk; 780 } 781 782 if (rps->vce_active) { 783 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 784 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 785 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 786 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 787 } 788 789 ps->performance_levels[0].sclk = sclk; 790 ps->performance_levels[0].mclk = mclk; 791 792 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) 793 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; 794 795 if (disable_mclk_switching) { 796 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) 797 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; 798 } else { 799 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk) 800 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk; 801 } 802 } 803 804 static int ci_set_thermal_temperature_range(struct radeon_device *rdev, 805 int min_temp, int max_temp) 806 { 807 int low_temp = 0 * 1000; 808 int high_temp = 255 * 1000; 809 u32 tmp; 810 811 if (low_temp < min_temp) 812 low_temp = min_temp; 813 if (high_temp > max_temp) 814 high_temp = max_temp; 815 if (high_temp < low_temp) { 816 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 817 return -EINVAL; 818 } 819 820 tmp = RREG32_SMC(CG_THERMAL_INT); 821 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK); 822 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) | 823 CI_DIG_THERM_INTL(low_temp / 1000); 824 WREG32_SMC(CG_THERMAL_INT, tmp); 825 826 #if 0 827 /* XXX: need to figure out how to handle this properly */ 828 tmp = RREG32_SMC(CG_THERMAL_CTRL); 829 tmp &= DIG_THERM_DPM_MASK; 830 tmp |= DIG_THERM_DPM(high_temp / 1000); 831 WREG32_SMC(CG_THERMAL_CTRL, tmp); 832 #endif 833 834 rdev->pm.dpm.thermal.min_temp = low_temp; 835 rdev->pm.dpm.thermal.max_temp = high_temp; 836 837 return 0; 838 } 839 840 #if 0 841 static int ci_read_smc_soft_register(struct radeon_device *rdev, 842 u16 reg_offset, u32 *value) 843 { 844 struct ci_power_info *pi = ci_get_pi(rdev); 845 846 return ci_read_smc_sram_dword(rdev, 847 pi->soft_regs_start + reg_offset, 848 value, pi->sram_end); 849 } 850 #endif 851 852 static int ci_write_smc_soft_register(struct radeon_device *rdev, 853 u16 reg_offset, u32 value) 854 { 855 struct ci_power_info *pi = ci_get_pi(rdev); 856 857 return ci_write_smc_sram_dword(rdev, 858 pi->soft_regs_start + reg_offset, 859 value, pi->sram_end); 860 } 861 862 static void ci_init_fps_limits(struct radeon_device *rdev) 863 { 864 struct ci_power_info *pi = ci_get_pi(rdev); 865 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; 866 867 if (pi->caps_fps) { 868 u16 tmp; 869 870 tmp = 45; 871 table->FpsHighT = cpu_to_be16(tmp); 872 873 tmp = 30; 874 table->FpsLowT = cpu_to_be16(tmp); 875 } 876 } 877 878 static int ci_update_sclk_t(struct radeon_device *rdev) 879 { 880 struct ci_power_info *pi = ci_get_pi(rdev); 881 int ret = 0; 882 u32 low_sclk_interrupt_t = 0; 883 884 if (pi->caps_sclk_throttle_low_notification) { 885 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); 886 887 ret = ci_copy_bytes_to_smc(rdev, 888 pi->dpm_table_start + 889 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT), 890 (u8 *)&low_sclk_interrupt_t, 891 sizeof(u32), pi->sram_end); 892 893 } 894 895 return ret; 896 } 897 898 static void ci_get_leakage_voltages(struct radeon_device *rdev) 899 { 900 struct ci_power_info *pi = ci_get_pi(rdev); 901 u16 leakage_id, virtual_voltage_id; 902 u16 vddc, vddci; 903 int i; 904 905 pi->vddc_leakage.count = 0; 906 pi->vddci_leakage.count = 0; 907 908 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { 909 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { 910 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 911 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0) 912 continue; 913 if (vddc != 0 && vddc != virtual_voltage_id) { 914 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; 915 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; 916 pi->vddc_leakage.count++; 917 } 918 } 919 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) { 920 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { 921 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 922 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci, 923 virtual_voltage_id, 924 leakage_id) == 0) { 925 if (vddc != 0 && vddc != virtual_voltage_id) { 926 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; 927 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; 928 pi->vddc_leakage.count++; 929 } 930 if (vddci != 0 && vddci != virtual_voltage_id) { 931 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; 932 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; 933 pi->vddci_leakage.count++; 934 } 935 } 936 } 937 } 938 } 939 940 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 941 { 942 struct ci_power_info *pi = ci_get_pi(rdev); 943 bool want_thermal_protection; 944 enum radeon_dpm_event_src dpm_event_src; 945 u32 tmp; 946 947 switch (sources) { 948 case 0: 949 default: 950 want_thermal_protection = false; 951 break; 952 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 953 want_thermal_protection = true; 954 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 955 break; 956 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 957 want_thermal_protection = true; 958 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 959 break; 960 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 961 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 962 want_thermal_protection = true; 963 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 964 break; 965 } 966 967 if (want_thermal_protection) { 968 #if 0 969 /* XXX: need to figure out how to handle this properly */ 970 tmp = RREG32_SMC(CG_THERMAL_CTRL); 971 tmp &= DPM_EVENT_SRC_MASK; 972 tmp |= DPM_EVENT_SRC(dpm_event_src); 973 WREG32_SMC(CG_THERMAL_CTRL, tmp); 974 #endif 975 976 tmp = RREG32_SMC(GENERAL_PWRMGT); 977 if (pi->thermal_protection) 978 tmp &= ~THERMAL_PROTECTION_DIS; 979 else 980 tmp |= THERMAL_PROTECTION_DIS; 981 WREG32_SMC(GENERAL_PWRMGT, tmp); 982 } else { 983 tmp = RREG32_SMC(GENERAL_PWRMGT); 984 tmp |= THERMAL_PROTECTION_DIS; 985 WREG32_SMC(GENERAL_PWRMGT, tmp); 986 } 987 } 988 989 static void ci_enable_auto_throttle_source(struct radeon_device *rdev, 990 enum radeon_dpm_auto_throttle_src source, 991 bool enable) 992 { 993 struct ci_power_info *pi = ci_get_pi(rdev); 994 995 if (enable) { 996 if (!(pi->active_auto_throttle_sources & (1 << source))) { 997 pi->active_auto_throttle_sources |= 1 << source; 998 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 999 } 1000 } else { 1001 if (pi->active_auto_throttle_sources & (1 << source)) { 1002 pi->active_auto_throttle_sources &= ~(1 << source); 1003 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 1004 } 1005 } 1006 } 1007 1008 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev) 1009 { 1010 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) 1011 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt); 1012 } 1013 1014 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev) 1015 { 1016 struct ci_power_info *pi = ci_get_pi(rdev); 1017 PPSMC_Result smc_result; 1018 1019 if (!pi->need_update_smu7_dpm_table) 1020 return 0; 1021 1022 if ((!pi->sclk_dpm_key_disabled) && 1023 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 1024 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel); 1025 if (smc_result != PPSMC_Result_OK) 1026 return -EINVAL; 1027 } 1028 1029 if ((!pi->mclk_dpm_key_disabled) && 1030 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 1031 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel); 1032 if (smc_result != PPSMC_Result_OK) 1033 return -EINVAL; 1034 } 1035 1036 pi->need_update_smu7_dpm_table = 0; 1037 return 0; 1038 } 1039 1040 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable) 1041 { 1042 struct ci_power_info *pi = ci_get_pi(rdev); 1043 PPSMC_Result smc_result; 1044 1045 if (enable) { 1046 if (!pi->sclk_dpm_key_disabled) { 1047 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable); 1048 if (smc_result != PPSMC_Result_OK) 1049 return -EINVAL; 1050 } 1051 1052 if (!pi->mclk_dpm_key_disabled) { 1053 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable); 1054 if (smc_result != PPSMC_Result_OK) 1055 return -EINVAL; 1056 1057 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN); 1058 1059 WREG32_SMC(LCAC_MC0_CNTL, 0x05); 1060 WREG32_SMC(LCAC_MC1_CNTL, 0x05); 1061 WREG32_SMC(LCAC_CPL_CNTL, 0x100005); 1062 1063 udelay(10); 1064 1065 WREG32_SMC(LCAC_MC0_CNTL, 0x400005); 1066 WREG32_SMC(LCAC_MC1_CNTL, 0x400005); 1067 WREG32_SMC(LCAC_CPL_CNTL, 0x500005); 1068 } 1069 } else { 1070 if (!pi->sclk_dpm_key_disabled) { 1071 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable); 1072 if (smc_result != PPSMC_Result_OK) 1073 return -EINVAL; 1074 } 1075 1076 if (!pi->mclk_dpm_key_disabled) { 1077 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable); 1078 if (smc_result != PPSMC_Result_OK) 1079 return -EINVAL; 1080 } 1081 } 1082 1083 return 0; 1084 } 1085 1086 static int ci_start_dpm(struct radeon_device *rdev) 1087 { 1088 struct ci_power_info *pi = ci_get_pi(rdev); 1089 PPSMC_Result smc_result; 1090 int ret; 1091 u32 tmp; 1092 1093 tmp = RREG32_SMC(GENERAL_PWRMGT); 1094 tmp |= GLOBAL_PWRMGT_EN; 1095 WREG32_SMC(GENERAL_PWRMGT, tmp); 1096 1097 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1098 tmp |= DYNAMIC_PM_EN; 1099 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1100 1101 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000); 1102 1103 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN); 1104 1105 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable); 1106 if (smc_result != PPSMC_Result_OK) 1107 return -EINVAL; 1108 1109 ret = ci_enable_sclk_mclk_dpm(rdev, true); 1110 if (ret) 1111 return ret; 1112 1113 if (!pi->pcie_dpm_key_disabled) { 1114 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable); 1115 if (smc_result != PPSMC_Result_OK) 1116 return -EINVAL; 1117 } 1118 1119 return 0; 1120 } 1121 1122 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev) 1123 { 1124 struct ci_power_info *pi = ci_get_pi(rdev); 1125 PPSMC_Result smc_result; 1126 1127 if (!pi->need_update_smu7_dpm_table) 1128 return 0; 1129 1130 if ((!pi->sclk_dpm_key_disabled) && 1131 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 1132 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel); 1133 if (smc_result != PPSMC_Result_OK) 1134 return -EINVAL; 1135 } 1136 1137 if ((!pi->mclk_dpm_key_disabled) && 1138 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 1139 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel); 1140 if (smc_result != PPSMC_Result_OK) 1141 return -EINVAL; 1142 } 1143 1144 return 0; 1145 } 1146 1147 static int ci_stop_dpm(struct radeon_device *rdev) 1148 { 1149 struct ci_power_info *pi = ci_get_pi(rdev); 1150 PPSMC_Result smc_result; 1151 int ret; 1152 u32 tmp; 1153 1154 tmp = RREG32_SMC(GENERAL_PWRMGT); 1155 tmp &= ~GLOBAL_PWRMGT_EN; 1156 WREG32_SMC(GENERAL_PWRMGT, tmp); 1157 1158 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1159 tmp &= ~DYNAMIC_PM_EN; 1160 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1161 1162 if (!pi->pcie_dpm_key_disabled) { 1163 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable); 1164 if (smc_result != PPSMC_Result_OK) 1165 return -EINVAL; 1166 } 1167 1168 ret = ci_enable_sclk_mclk_dpm(rdev, false); 1169 if (ret) 1170 return ret; 1171 1172 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable); 1173 if (smc_result != PPSMC_Result_OK) 1174 return -EINVAL; 1175 1176 return 0; 1177 } 1178 1179 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable) 1180 { 1181 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1182 1183 if (enable) 1184 tmp &= ~SCLK_PWRMGT_OFF; 1185 else 1186 tmp |= SCLK_PWRMGT_OFF; 1187 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1188 } 1189 1190 #if 0 1191 static int ci_notify_hw_of_power_source(struct radeon_device *rdev, 1192 bool ac_power) 1193 { 1194 struct ci_power_info *pi = ci_get_pi(rdev); 1195 struct radeon_cac_tdp_table *cac_tdp_table = 1196 rdev->pm.dpm.dyn_state.cac_tdp_table; 1197 u32 power_limit; 1198 1199 if (ac_power) 1200 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); 1201 else 1202 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256); 1203 1204 ci_set_power_limit(rdev, power_limit); 1205 1206 if (pi->caps_automatic_dc_transition) { 1207 if (ac_power) 1208 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC); 1209 else 1210 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp); 1211 } 1212 1213 return 0; 1214 } 1215 #endif 1216 1217 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 1218 PPSMC_Msg msg, u32 parameter) 1219 { 1220 WREG32(SMC_MSG_ARG_0, parameter); 1221 return ci_send_msg_to_smc(rdev, msg); 1222 } 1223 1224 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev, 1225 PPSMC_Msg msg, u32 *parameter) 1226 { 1227 PPSMC_Result smc_result; 1228 1229 smc_result = ci_send_msg_to_smc(rdev, msg); 1230 1231 if ((smc_result == PPSMC_Result_OK) && parameter) 1232 *parameter = RREG32(SMC_MSG_ARG_0); 1233 1234 return smc_result; 1235 } 1236 1237 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n) 1238 { 1239 struct ci_power_info *pi = ci_get_pi(rdev); 1240 1241 if (!pi->sclk_dpm_key_disabled) { 1242 PPSMC_Result smc_result = 1243 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n); 1244 if (smc_result != PPSMC_Result_OK) 1245 return -EINVAL; 1246 } 1247 1248 return 0; 1249 } 1250 1251 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n) 1252 { 1253 struct ci_power_info *pi = ci_get_pi(rdev); 1254 1255 if (!pi->mclk_dpm_key_disabled) { 1256 PPSMC_Result smc_result = 1257 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n); 1258 if (smc_result != PPSMC_Result_OK) 1259 return -EINVAL; 1260 } 1261 1262 return 0; 1263 } 1264 1265 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n) 1266 { 1267 struct ci_power_info *pi = ci_get_pi(rdev); 1268 1269 if (!pi->pcie_dpm_key_disabled) { 1270 PPSMC_Result smc_result = 1271 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n); 1272 if (smc_result != PPSMC_Result_OK) 1273 return -EINVAL; 1274 } 1275 1276 return 0; 1277 } 1278 1279 static int ci_set_power_limit(struct radeon_device *rdev, u32 n) 1280 { 1281 struct ci_power_info *pi = ci_get_pi(rdev); 1282 1283 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { 1284 PPSMC_Result smc_result = 1285 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n); 1286 if (smc_result != PPSMC_Result_OK) 1287 return -EINVAL; 1288 } 1289 1290 return 0; 1291 } 1292 1293 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, 1294 u32 target_tdp) 1295 { 1296 PPSMC_Result smc_result = 1297 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); 1298 if (smc_result != PPSMC_Result_OK) 1299 return -EINVAL; 1300 return 0; 1301 } 1302 1303 static int ci_set_boot_state(struct radeon_device *rdev) 1304 { 1305 return ci_enable_sclk_mclk_dpm(rdev, false); 1306 } 1307 1308 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev) 1309 { 1310 u32 sclk_freq; 1311 PPSMC_Result smc_result = 1312 ci_send_msg_to_smc_return_parameter(rdev, 1313 PPSMC_MSG_API_GetSclkFrequency, 1314 &sclk_freq); 1315 if (smc_result != PPSMC_Result_OK) 1316 sclk_freq = 0; 1317 1318 return sclk_freq; 1319 } 1320 1321 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev) 1322 { 1323 u32 mclk_freq; 1324 PPSMC_Result smc_result = 1325 ci_send_msg_to_smc_return_parameter(rdev, 1326 PPSMC_MSG_API_GetMclkFrequency, 1327 &mclk_freq); 1328 if (smc_result != PPSMC_Result_OK) 1329 mclk_freq = 0; 1330 1331 return mclk_freq; 1332 } 1333 1334 static void ci_dpm_start_smc(struct radeon_device *rdev) 1335 { 1336 int i; 1337 1338 ci_program_jump_on_start(rdev); 1339 ci_start_smc_clock(rdev); 1340 ci_start_smc(rdev); 1341 for (i = 0; i < rdev->usec_timeout; i++) { 1342 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED) 1343 break; 1344 } 1345 } 1346 1347 static void ci_dpm_stop_smc(struct radeon_device *rdev) 1348 { 1349 ci_reset_smc(rdev); 1350 ci_stop_smc_clock(rdev); 1351 } 1352 1353 static int ci_process_firmware_header(struct radeon_device *rdev) 1354 { 1355 struct ci_power_info *pi = ci_get_pi(rdev); 1356 u32 tmp; 1357 int ret; 1358 1359 ret = ci_read_smc_sram_dword(rdev, 1360 SMU7_FIRMWARE_HEADER_LOCATION + 1361 offsetof(SMU7_Firmware_Header, DpmTable), 1362 &tmp, pi->sram_end); 1363 if (ret) 1364 return ret; 1365 1366 pi->dpm_table_start = tmp; 1367 1368 ret = ci_read_smc_sram_dword(rdev, 1369 SMU7_FIRMWARE_HEADER_LOCATION + 1370 offsetof(SMU7_Firmware_Header, SoftRegisters), 1371 &tmp, pi->sram_end); 1372 if (ret) 1373 return ret; 1374 1375 pi->soft_regs_start = tmp; 1376 1377 ret = ci_read_smc_sram_dword(rdev, 1378 SMU7_FIRMWARE_HEADER_LOCATION + 1379 offsetof(SMU7_Firmware_Header, mcRegisterTable), 1380 &tmp, pi->sram_end); 1381 if (ret) 1382 return ret; 1383 1384 pi->mc_reg_table_start = tmp; 1385 1386 ret = ci_read_smc_sram_dword(rdev, 1387 SMU7_FIRMWARE_HEADER_LOCATION + 1388 offsetof(SMU7_Firmware_Header, FanTable), 1389 &tmp, pi->sram_end); 1390 if (ret) 1391 return ret; 1392 1393 pi->fan_table_start = tmp; 1394 1395 ret = ci_read_smc_sram_dword(rdev, 1396 SMU7_FIRMWARE_HEADER_LOCATION + 1397 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable), 1398 &tmp, pi->sram_end); 1399 if (ret) 1400 return ret; 1401 1402 pi->arb_table_start = tmp; 1403 1404 return 0; 1405 } 1406 1407 static void ci_read_clock_registers(struct radeon_device *rdev) 1408 { 1409 struct ci_power_info *pi = ci_get_pi(rdev); 1410 1411 pi->clock_registers.cg_spll_func_cntl = 1412 RREG32_SMC(CG_SPLL_FUNC_CNTL); 1413 pi->clock_registers.cg_spll_func_cntl_2 = 1414 RREG32_SMC(CG_SPLL_FUNC_CNTL_2); 1415 pi->clock_registers.cg_spll_func_cntl_3 = 1416 RREG32_SMC(CG_SPLL_FUNC_CNTL_3); 1417 pi->clock_registers.cg_spll_func_cntl_4 = 1418 RREG32_SMC(CG_SPLL_FUNC_CNTL_4); 1419 pi->clock_registers.cg_spll_spread_spectrum = 1420 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); 1421 pi->clock_registers.cg_spll_spread_spectrum_2 = 1422 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2); 1423 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 1424 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 1425 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 1426 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 1427 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 1428 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 1429 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 1430 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 1431 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 1432 } 1433 1434 static void ci_init_sclk_t(struct radeon_device *rdev) 1435 { 1436 struct ci_power_info *pi = ci_get_pi(rdev); 1437 1438 pi->low_sclk_interrupt_t = 0; 1439 } 1440 1441 static void ci_enable_thermal_protection(struct radeon_device *rdev, 1442 bool enable) 1443 { 1444 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 1445 1446 if (enable) 1447 tmp &= ~THERMAL_PROTECTION_DIS; 1448 else 1449 tmp |= THERMAL_PROTECTION_DIS; 1450 WREG32_SMC(GENERAL_PWRMGT, tmp); 1451 } 1452 1453 static void ci_enable_acpi_power_management(struct radeon_device *rdev) 1454 { 1455 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 1456 1457 tmp |= STATIC_PM_EN; 1458 1459 WREG32_SMC(GENERAL_PWRMGT, tmp); 1460 } 1461 1462 #if 0 1463 static int ci_enter_ulp_state(struct radeon_device *rdev) 1464 { 1465 1466 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 1467 1468 udelay(25000); 1469 1470 return 0; 1471 } 1472 1473 static int ci_exit_ulp_state(struct radeon_device *rdev) 1474 { 1475 int i; 1476 1477 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 1478 1479 udelay(7000); 1480 1481 for (i = 0; i < rdev->usec_timeout; i++) { 1482 if (RREG32(SMC_RESP_0) == 1) 1483 break; 1484 udelay(1000); 1485 } 1486 1487 return 0; 1488 } 1489 #endif 1490 1491 static int ci_notify_smc_display_change(struct radeon_device *rdev, 1492 bool has_display) 1493 { 1494 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 1495 1496 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL; 1497 } 1498 1499 static int ci_enable_ds_master_switch(struct radeon_device *rdev, 1500 bool enable) 1501 { 1502 struct ci_power_info *pi = ci_get_pi(rdev); 1503 1504 if (enable) { 1505 if (pi->caps_sclk_ds) { 1506 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK) 1507 return -EINVAL; 1508 } else { 1509 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) 1510 return -EINVAL; 1511 } 1512 } else { 1513 if (pi->caps_sclk_ds) { 1514 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) 1515 return -EINVAL; 1516 } 1517 } 1518 1519 return 0; 1520 } 1521 1522 static void ci_program_display_gap(struct radeon_device *rdev) 1523 { 1524 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); 1525 u32 pre_vbi_time_in_us; 1526 u32 frame_time_in_us; 1527 u32 ref_clock = rdev->clock.spll.reference_freq; 1528 u32 refresh_rate = r600_dpm_get_vrefresh(rdev); 1529 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 1530 1531 tmp &= ~DISP_GAP_MASK; 1532 if (rdev->pm.dpm.new_active_crtc_count > 0) 1533 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 1534 else 1535 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE); 1536 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); 1537 1538 if (refresh_rate == 0) 1539 refresh_rate = 60; 1540 if (vblank_time == 0xffffffff) 1541 vblank_time = 500; 1542 frame_time_in_us = 1000000 / refresh_rate; 1543 pre_vbi_time_in_us = 1544 frame_time_in_us - 200 - vblank_time; 1545 tmp = pre_vbi_time_in_us * (ref_clock / 100); 1546 1547 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp); 1548 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64); 1549 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); 1550 1551 1552 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); 1553 1554 } 1555 1556 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 1557 { 1558 struct ci_power_info *pi = ci_get_pi(rdev); 1559 u32 tmp; 1560 1561 if (enable) { 1562 if (pi->caps_sclk_ss_support) { 1563 tmp = RREG32_SMC(GENERAL_PWRMGT); 1564 tmp |= DYN_SPREAD_SPECTRUM_EN; 1565 WREG32_SMC(GENERAL_PWRMGT, tmp); 1566 } 1567 } else { 1568 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); 1569 tmp &= ~SSEN; 1570 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp); 1571 1572 tmp = RREG32_SMC(GENERAL_PWRMGT); 1573 tmp &= ~DYN_SPREAD_SPECTRUM_EN; 1574 WREG32_SMC(GENERAL_PWRMGT, tmp); 1575 } 1576 } 1577 1578 static void ci_program_sstp(struct radeon_device *rdev) 1579 { 1580 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 1581 } 1582 1583 static void ci_enable_display_gap(struct radeon_device *rdev) 1584 { 1585 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); 1586 1587 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK); 1588 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 1589 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK)); 1590 1591 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); 1592 } 1593 1594 static void ci_program_vc(struct radeon_device *rdev) 1595 { 1596 u32 tmp; 1597 1598 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1599 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT); 1600 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1601 1602 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0); 1603 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1); 1604 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2); 1605 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3); 1606 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4); 1607 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5); 1608 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6); 1609 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7); 1610 } 1611 1612 static void ci_clear_vc(struct radeon_device *rdev) 1613 { 1614 u32 tmp; 1615 1616 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1617 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT); 1618 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1619 1620 WREG32_SMC(CG_FTV_0, 0); 1621 WREG32_SMC(CG_FTV_1, 0); 1622 WREG32_SMC(CG_FTV_2, 0); 1623 WREG32_SMC(CG_FTV_3, 0); 1624 WREG32_SMC(CG_FTV_4, 0); 1625 WREG32_SMC(CG_FTV_5, 0); 1626 WREG32_SMC(CG_FTV_6, 0); 1627 WREG32_SMC(CG_FTV_7, 0); 1628 } 1629 1630 static int ci_upload_firmware(struct radeon_device *rdev) 1631 { 1632 struct ci_power_info *pi = ci_get_pi(rdev); 1633 int i, ret; 1634 1635 for (i = 0; i < rdev->usec_timeout; i++) { 1636 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE) 1637 break; 1638 } 1639 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1); 1640 1641 ci_stop_smc_clock(rdev); 1642 ci_reset_smc(rdev); 1643 1644 ret = ci_load_smc_ucode(rdev, pi->sram_end); 1645 1646 return ret; 1647 1648 } 1649 1650 static int ci_get_svi2_voltage_table(struct radeon_device *rdev, 1651 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 1652 struct atom_voltage_table *voltage_table) 1653 { 1654 u32 i; 1655 1656 if (voltage_dependency_table == NULL) 1657 return -EINVAL; 1658 1659 voltage_table->mask_low = 0; 1660 voltage_table->phase_delay = 0; 1661 1662 voltage_table->count = voltage_dependency_table->count; 1663 for (i = 0; i < voltage_table->count; i++) { 1664 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 1665 voltage_table->entries[i].smio_low = 0; 1666 } 1667 1668 return 0; 1669 } 1670 1671 static int ci_construct_voltage_tables(struct radeon_device *rdev) 1672 { 1673 struct ci_power_info *pi = ci_get_pi(rdev); 1674 int ret; 1675 1676 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 1677 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 1678 VOLTAGE_OBJ_GPIO_LUT, 1679 &pi->vddc_voltage_table); 1680 if (ret) 1681 return ret; 1682 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 1683 ret = ci_get_svi2_voltage_table(rdev, 1684 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 1685 &pi->vddc_voltage_table); 1686 if (ret) 1687 return ret; 1688 } 1689 1690 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) 1691 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC, 1692 &pi->vddc_voltage_table); 1693 1694 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 1695 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 1696 VOLTAGE_OBJ_GPIO_LUT, 1697 &pi->vddci_voltage_table); 1698 if (ret) 1699 return ret; 1700 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 1701 ret = ci_get_svi2_voltage_table(rdev, 1702 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 1703 &pi->vddci_voltage_table); 1704 if (ret) 1705 return ret; 1706 } 1707 1708 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) 1709 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI, 1710 &pi->vddci_voltage_table); 1711 1712 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 1713 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 1714 VOLTAGE_OBJ_GPIO_LUT, 1715 &pi->mvdd_voltage_table); 1716 if (ret) 1717 return ret; 1718 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 1719 ret = ci_get_svi2_voltage_table(rdev, 1720 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 1721 &pi->mvdd_voltage_table); 1722 if (ret) 1723 return ret; 1724 } 1725 1726 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) 1727 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD, 1728 &pi->mvdd_voltage_table); 1729 1730 return 0; 1731 } 1732 1733 static void ci_populate_smc_voltage_table(struct radeon_device *rdev, 1734 struct atom_voltage_table_entry *voltage_table, 1735 SMU7_Discrete_VoltageLevel *smc_voltage_table) 1736 { 1737 int ret; 1738 1739 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table, 1740 &smc_voltage_table->StdVoltageHiSidd, 1741 &smc_voltage_table->StdVoltageLoSidd); 1742 1743 if (ret) { 1744 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE; 1745 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE; 1746 } 1747 1748 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE); 1749 smc_voltage_table->StdVoltageHiSidd = 1750 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd); 1751 smc_voltage_table->StdVoltageLoSidd = 1752 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd); 1753 } 1754 1755 static int ci_populate_smc_vddc_table(struct radeon_device *rdev, 1756 SMU7_Discrete_DpmTable *table) 1757 { 1758 struct ci_power_info *pi = ci_get_pi(rdev); 1759 unsigned int count; 1760 1761 table->VddcLevelCount = pi->vddc_voltage_table.count; 1762 for (count = 0; count < table->VddcLevelCount; count++) { 1763 ci_populate_smc_voltage_table(rdev, 1764 &pi->vddc_voltage_table.entries[count], 1765 &table->VddcLevel[count]); 1766 1767 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 1768 table->VddcLevel[count].Smio |= 1769 pi->vddc_voltage_table.entries[count].smio_low; 1770 else 1771 table->VddcLevel[count].Smio = 0; 1772 } 1773 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); 1774 1775 return 0; 1776 } 1777 1778 static int ci_populate_smc_vddci_table(struct radeon_device *rdev, 1779 SMU7_Discrete_DpmTable *table) 1780 { 1781 unsigned int count; 1782 struct ci_power_info *pi = ci_get_pi(rdev); 1783 1784 table->VddciLevelCount = pi->vddci_voltage_table.count; 1785 for (count = 0; count < table->VddciLevelCount; count++) { 1786 ci_populate_smc_voltage_table(rdev, 1787 &pi->vddci_voltage_table.entries[count], 1788 &table->VddciLevel[count]); 1789 1790 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 1791 table->VddciLevel[count].Smio |= 1792 pi->vddci_voltage_table.entries[count].smio_low; 1793 else 1794 table->VddciLevel[count].Smio = 0; 1795 } 1796 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); 1797 1798 return 0; 1799 } 1800 1801 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev, 1802 SMU7_Discrete_DpmTable *table) 1803 { 1804 struct ci_power_info *pi = ci_get_pi(rdev); 1805 unsigned int count; 1806 1807 table->MvddLevelCount = pi->mvdd_voltage_table.count; 1808 for (count = 0; count < table->MvddLevelCount; count++) { 1809 ci_populate_smc_voltage_table(rdev, 1810 &pi->mvdd_voltage_table.entries[count], 1811 &table->MvddLevel[count]); 1812 1813 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 1814 table->MvddLevel[count].Smio |= 1815 pi->mvdd_voltage_table.entries[count].smio_low; 1816 else 1817 table->MvddLevel[count].Smio = 0; 1818 } 1819 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); 1820 1821 return 0; 1822 } 1823 1824 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev, 1825 SMU7_Discrete_DpmTable *table) 1826 { 1827 int ret; 1828 1829 ret = ci_populate_smc_vddc_table(rdev, table); 1830 if (ret) 1831 return ret; 1832 1833 ret = ci_populate_smc_vddci_table(rdev, table); 1834 if (ret) 1835 return ret; 1836 1837 ret = ci_populate_smc_mvdd_table(rdev, table); 1838 if (ret) 1839 return ret; 1840 1841 return 0; 1842 } 1843 1844 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 1845 SMU7_Discrete_VoltageLevel *voltage) 1846 { 1847 struct ci_power_info *pi = ci_get_pi(rdev); 1848 u32 i = 0; 1849 1850 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 1851 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { 1852 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { 1853 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; 1854 break; 1855 } 1856 } 1857 1858 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) 1859 return -EINVAL; 1860 } 1861 1862 return -EINVAL; 1863 } 1864 1865 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 1866 struct atom_voltage_table_entry *voltage_table, 1867 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd) 1868 { 1869 u16 v_index, idx; 1870 bool voltage_found = false; 1871 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE; 1872 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE; 1873 1874 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 1875 return -EINVAL; 1876 1877 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 1878 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 1879 if (voltage_table->value == 1880 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 1881 voltage_found = true; 1882 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 1883 idx = v_index; 1884 else 1885 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; 1886 *std_voltage_lo_sidd = 1887 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; 1888 *std_voltage_hi_sidd = 1889 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; 1890 break; 1891 } 1892 } 1893 1894 if (!voltage_found) { 1895 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 1896 if (voltage_table->value <= 1897 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 1898 voltage_found = true; 1899 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 1900 idx = v_index; 1901 else 1902 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; 1903 *std_voltage_lo_sidd = 1904 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; 1905 *std_voltage_hi_sidd = 1906 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; 1907 break; 1908 } 1909 } 1910 } 1911 } 1912 1913 return 0; 1914 } 1915 1916 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev, 1917 const struct radeon_phase_shedding_limits_table *limits, 1918 u32 sclk, 1919 u32 *phase_shedding) 1920 { 1921 unsigned int i; 1922 1923 *phase_shedding = 1; 1924 1925 for (i = 0; i < limits->count; i++) { 1926 if (sclk < limits->entries[i].sclk) { 1927 *phase_shedding = i; 1928 break; 1929 } 1930 } 1931 } 1932 1933 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev, 1934 const struct radeon_phase_shedding_limits_table *limits, 1935 u32 mclk, 1936 u32 *phase_shedding) 1937 { 1938 unsigned int i; 1939 1940 *phase_shedding = 1; 1941 1942 for (i = 0; i < limits->count; i++) { 1943 if (mclk < limits->entries[i].mclk) { 1944 *phase_shedding = i; 1945 break; 1946 } 1947 } 1948 } 1949 1950 static int ci_init_arb_table_index(struct radeon_device *rdev) 1951 { 1952 struct ci_power_info *pi = ci_get_pi(rdev); 1953 u32 tmp; 1954 int ret; 1955 1956 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, 1957 &tmp, pi->sram_end); 1958 if (ret) 1959 return ret; 1960 1961 tmp &= 0x00FFFFFF; 1962 tmp |= MC_CG_ARB_FREQ_F1 << 24; 1963 1964 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, 1965 tmp, pi->sram_end); 1966 } 1967 1968 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev, 1969 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table, 1970 u32 clock, u32 *voltage) 1971 { 1972 u32 i = 0; 1973 1974 if (allowed_clock_voltage_table->count == 0) 1975 return -EINVAL; 1976 1977 for (i = 0; i < allowed_clock_voltage_table->count; i++) { 1978 if (allowed_clock_voltage_table->entries[i].clk >= clock) { 1979 *voltage = allowed_clock_voltage_table->entries[i].v; 1980 return 0; 1981 } 1982 } 1983 1984 *voltage = allowed_clock_voltage_table->entries[i-1].v; 1985 1986 return 0; 1987 } 1988 1989 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev, 1990 u32 sclk, u32 min_sclk_in_sr) 1991 { 1992 u32 i; 1993 u32 tmp; 1994 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ? 1995 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK; 1996 1997 if (sclk < min) 1998 return 0; 1999 2000 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { 2001 tmp = sclk / (1 << i); 2002 if (tmp >= min || i == 0) 2003 break; 2004 } 2005 2006 return (u8)i; 2007 } 2008 2009 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 2010 { 2011 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 2012 } 2013 2014 static int ci_reset_to_default(struct radeon_device *rdev) 2015 { 2016 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 2017 0 : -EINVAL; 2018 } 2019 2020 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev) 2021 { 2022 u32 tmp; 2023 2024 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8; 2025 2026 if (tmp == MC_CG_ARB_FREQ_F0) 2027 return 0; 2028 2029 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 2030 } 2031 2032 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev, 2033 u32 sclk, 2034 u32 mclk, 2035 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs) 2036 { 2037 u32 dram_timing; 2038 u32 dram_timing2; 2039 u32 burst_time; 2040 2041 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk); 2042 2043 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 2044 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 2045 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 2046 2047 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing); 2048 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2); 2049 arb_regs->McArbBurstTime = (u8)burst_time; 2050 2051 return 0; 2052 } 2053 2054 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev) 2055 { 2056 struct ci_power_info *pi = ci_get_pi(rdev); 2057 SMU7_Discrete_MCArbDramTimingTable arb_regs; 2058 u32 i, j; 2059 int ret = 0; 2060 2061 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable)); 2062 2063 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { 2064 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { 2065 ret = ci_populate_memory_timing_parameters(rdev, 2066 pi->dpm_table.sclk_table.dpm_levels[i].value, 2067 pi->dpm_table.mclk_table.dpm_levels[j].value, 2068 &arb_regs.entries[i][j]); 2069 if (ret) 2070 break; 2071 } 2072 } 2073 2074 if (ret == 0) 2075 ret = ci_copy_bytes_to_smc(rdev, 2076 pi->arb_table_start, 2077 (u8 *)&arb_regs, 2078 sizeof(SMU7_Discrete_MCArbDramTimingTable), 2079 pi->sram_end); 2080 2081 return ret; 2082 } 2083 2084 static int ci_program_memory_timing_parameters(struct radeon_device *rdev) 2085 { 2086 struct ci_power_info *pi = ci_get_pi(rdev); 2087 2088 if (pi->need_update_smu7_dpm_table == 0) 2089 return 0; 2090 2091 return ci_do_program_memory_timing_parameters(rdev); 2092 } 2093 2094 static void ci_populate_smc_initial_state(struct radeon_device *rdev, 2095 struct radeon_ps *radeon_boot_state) 2096 { 2097 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state); 2098 struct ci_power_info *pi = ci_get_pi(rdev); 2099 u32 level = 0; 2100 2101 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { 2102 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= 2103 boot_state->performance_levels[0].sclk) { 2104 pi->smc_state_table.GraphicsBootLevel = level; 2105 break; 2106 } 2107 } 2108 2109 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { 2110 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= 2111 boot_state->performance_levels[0].mclk) { 2112 pi->smc_state_table.MemoryBootLevel = level; 2113 break; 2114 } 2115 } 2116 } 2117 2118 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) 2119 { 2120 u32 i; 2121 u32 mask_value = 0; 2122 2123 for (i = dpm_table->count; i > 0; i--) { 2124 mask_value = mask_value << 1; 2125 if (dpm_table->dpm_levels[i-1].enabled) 2126 mask_value |= 0x1; 2127 else 2128 mask_value &= 0xFFFFFFFE; 2129 } 2130 2131 return mask_value; 2132 } 2133 2134 static void ci_populate_smc_link_level(struct radeon_device *rdev, 2135 SMU7_Discrete_DpmTable *table) 2136 { 2137 struct ci_power_info *pi = ci_get_pi(rdev); 2138 struct ci_dpm_table *dpm_table = &pi->dpm_table; 2139 u32 i; 2140 2141 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { 2142 table->LinkLevel[i].PcieGenSpeed = 2143 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; 2144 table->LinkLevel[i].PcieLaneCount = 2145 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 2146 table->LinkLevel[i].EnabledForActivity = 1; 2147 table->LinkLevel[i].DownT = cpu_to_be32(5); 2148 table->LinkLevel[i].UpT = cpu_to_be32(30); 2149 } 2150 2151 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; 2152 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = 2153 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 2154 } 2155 2156 static int ci_populate_smc_uvd_level(struct radeon_device *rdev, 2157 SMU7_Discrete_DpmTable *table) 2158 { 2159 u32 count; 2160 struct atom_clock_dividers dividers; 2161 int ret = -EINVAL; 2162 2163 table->UvdLevelCount = 2164 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; 2165 2166 for (count = 0; count < table->UvdLevelCount; count++) { 2167 table->UvdLevel[count].VclkFrequency = 2168 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; 2169 table->UvdLevel[count].DclkFrequency = 2170 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; 2171 table->UvdLevel[count].MinVddc = 2172 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2173 table->UvdLevel[count].MinVddcPhases = 1; 2174 2175 ret = radeon_atom_get_clock_dividers(rdev, 2176 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2177 table->UvdLevel[count].VclkFrequency, false, ÷rs); 2178 if (ret) 2179 return ret; 2180 2181 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; 2182 2183 ret = radeon_atom_get_clock_dividers(rdev, 2184 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2185 table->UvdLevel[count].DclkFrequency, false, ÷rs); 2186 if (ret) 2187 return ret; 2188 2189 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; 2190 2191 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); 2192 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); 2193 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); 2194 } 2195 2196 return ret; 2197 } 2198 2199 static int ci_populate_smc_vce_level(struct radeon_device *rdev, 2200 SMU7_Discrete_DpmTable *table) 2201 { 2202 u32 count; 2203 struct atom_clock_dividers dividers; 2204 int ret = -EINVAL; 2205 2206 table->VceLevelCount = 2207 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; 2208 2209 for (count = 0; count < table->VceLevelCount; count++) { 2210 table->VceLevel[count].Frequency = 2211 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; 2212 table->VceLevel[count].MinVoltage = 2213 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2214 table->VceLevel[count].MinPhases = 1; 2215 2216 ret = radeon_atom_get_clock_dividers(rdev, 2217 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2218 table->VceLevel[count].Frequency, false, ÷rs); 2219 if (ret) 2220 return ret; 2221 2222 table->VceLevel[count].Divider = (u8)dividers.post_divider; 2223 2224 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); 2225 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); 2226 } 2227 2228 return ret; 2229 2230 } 2231 2232 static int ci_populate_smc_acp_level(struct radeon_device *rdev, 2233 SMU7_Discrete_DpmTable *table) 2234 { 2235 u32 count; 2236 struct atom_clock_dividers dividers; 2237 int ret = -EINVAL; 2238 2239 table->AcpLevelCount = (u8) 2240 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); 2241 2242 for (count = 0; count < table->AcpLevelCount; count++) { 2243 table->AcpLevel[count].Frequency = 2244 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; 2245 table->AcpLevel[count].MinVoltage = 2246 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; 2247 table->AcpLevel[count].MinPhases = 1; 2248 2249 ret = radeon_atom_get_clock_dividers(rdev, 2250 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2251 table->AcpLevel[count].Frequency, false, ÷rs); 2252 if (ret) 2253 return ret; 2254 2255 table->AcpLevel[count].Divider = (u8)dividers.post_divider; 2256 2257 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); 2258 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); 2259 } 2260 2261 return ret; 2262 } 2263 2264 static int ci_populate_smc_samu_level(struct radeon_device *rdev, 2265 SMU7_Discrete_DpmTable *table) 2266 { 2267 u32 count; 2268 struct atom_clock_dividers dividers; 2269 int ret = -EINVAL; 2270 2271 table->SamuLevelCount = 2272 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; 2273 2274 for (count = 0; count < table->SamuLevelCount; count++) { 2275 table->SamuLevel[count].Frequency = 2276 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; 2277 table->SamuLevel[count].MinVoltage = 2278 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2279 table->SamuLevel[count].MinPhases = 1; 2280 2281 ret = radeon_atom_get_clock_dividers(rdev, 2282 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2283 table->SamuLevel[count].Frequency, false, ÷rs); 2284 if (ret) 2285 return ret; 2286 2287 table->SamuLevel[count].Divider = (u8)dividers.post_divider; 2288 2289 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); 2290 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); 2291 } 2292 2293 return ret; 2294 } 2295 2296 static int ci_calculate_mclk_params(struct radeon_device *rdev, 2297 u32 memory_clock, 2298 SMU7_Discrete_MemoryLevel *mclk, 2299 bool strobe_mode, 2300 bool dll_state_on) 2301 { 2302 struct ci_power_info *pi = ci_get_pi(rdev); 2303 u32 dll_cntl = pi->clock_registers.dll_cntl; 2304 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; 2305 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; 2306 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; 2307 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; 2308 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; 2309 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; 2310 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; 2311 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; 2312 struct atom_mpll_param mpll_param; 2313 int ret; 2314 2315 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 2316 if (ret) 2317 return ret; 2318 2319 mpll_func_cntl &= ~BWCTRL_MASK; 2320 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 2321 2322 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 2323 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 2324 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 2325 2326 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 2327 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 2328 2329 if (pi->mem_gddr5) { 2330 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 2331 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 2332 YCLK_POST_DIV(mpll_param.post_div); 2333 } 2334 2335 if (pi->caps_mclk_ss_support) { 2336 struct radeon_atom_ss ss; 2337 u32 freq_nom; 2338 u32 tmp; 2339 u32 reference_clock = rdev->clock.mpll.reference_freq; 2340 2341 if (pi->mem_gddr5) 2342 freq_nom = memory_clock * 4; 2343 else 2344 freq_nom = memory_clock * 2; 2345 2346 tmp = (freq_nom / reference_clock); 2347 tmp = tmp * tmp; 2348 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 2349 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 2350 u32 clks = reference_clock * 5 / ss.rate; 2351 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 2352 2353 mpll_ss1 &= ~CLKV_MASK; 2354 mpll_ss1 |= CLKV(clkv); 2355 2356 mpll_ss2 &= ~CLKS_MASK; 2357 mpll_ss2 |= CLKS(clks); 2358 } 2359 } 2360 2361 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 2362 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 2363 2364 if (dll_state_on) 2365 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 2366 else 2367 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 2368 2369 mclk->MclkFrequency = memory_clock; 2370 mclk->MpllFuncCntl = mpll_func_cntl; 2371 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; 2372 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; 2373 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; 2374 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; 2375 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; 2376 mclk->DllCntl = dll_cntl; 2377 mclk->MpllSs1 = mpll_ss1; 2378 mclk->MpllSs2 = mpll_ss2; 2379 2380 return 0; 2381 } 2382 2383 static int ci_populate_single_memory_level(struct radeon_device *rdev, 2384 u32 memory_clock, 2385 SMU7_Discrete_MemoryLevel *memory_level) 2386 { 2387 struct ci_power_info *pi = ci_get_pi(rdev); 2388 int ret; 2389 bool dll_state_on; 2390 2391 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { 2392 ret = ci_get_dependency_volt_by_clk(rdev, 2393 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2394 memory_clock, &memory_level->MinVddc); 2395 if (ret) 2396 return ret; 2397 } 2398 2399 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { 2400 ret = ci_get_dependency_volt_by_clk(rdev, 2401 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2402 memory_clock, &memory_level->MinVddci); 2403 if (ret) 2404 return ret; 2405 } 2406 2407 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { 2408 ret = ci_get_dependency_volt_by_clk(rdev, 2409 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 2410 memory_clock, &memory_level->MinMvdd); 2411 if (ret) 2412 return ret; 2413 } 2414 2415 memory_level->MinVddcPhases = 1; 2416 2417 if (pi->vddc_phase_shed_control) 2418 ci_populate_phase_value_based_on_mclk(rdev, 2419 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 2420 memory_clock, 2421 &memory_level->MinVddcPhases); 2422 2423 memory_level->EnabledForThrottle = 1; 2424 memory_level->EnabledForActivity = 1; 2425 memory_level->UpH = 0; 2426 memory_level->DownH = 100; 2427 memory_level->VoltageDownH = 0; 2428 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; 2429 2430 memory_level->StutterEnable = false; 2431 memory_level->StrobeEnable = false; 2432 memory_level->EdcReadEnable = false; 2433 memory_level->EdcWriteEnable = false; 2434 memory_level->RttEnable = false; 2435 2436 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2437 2438 if (pi->mclk_stutter_mode_threshold && 2439 (memory_clock <= pi->mclk_stutter_mode_threshold) && 2440 (pi->uvd_enabled == false) && 2441 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 2442 (rdev->pm.dpm.new_active_crtc_count <= 2)) 2443 memory_level->StutterEnable = true; 2444 2445 if (pi->mclk_strobe_mode_threshold && 2446 (memory_clock <= pi->mclk_strobe_mode_threshold)) 2447 memory_level->StrobeEnable = 1; 2448 2449 if (pi->mem_gddr5) { 2450 memory_level->StrobeRatio = 2451 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); 2452 if (pi->mclk_edc_enable_threshold && 2453 (memory_clock > pi->mclk_edc_enable_threshold)) 2454 memory_level->EdcReadEnable = true; 2455 2456 if (pi->mclk_edc_wr_enable_threshold && 2457 (memory_clock > pi->mclk_edc_wr_enable_threshold)) 2458 memory_level->EdcWriteEnable = true; 2459 2460 if (memory_level->StrobeEnable) { 2461 if (si_get_mclk_frequency_ratio(memory_clock, true) >= 2462 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 2463 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2464 else 2465 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 2466 } else { 2467 dll_state_on = pi->dll_default_on; 2468 } 2469 } else { 2470 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock); 2471 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2472 } 2473 2474 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); 2475 if (ret) 2476 return ret; 2477 2478 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); 2479 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); 2480 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); 2481 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); 2482 2483 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); 2484 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); 2485 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl); 2486 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1); 2487 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2); 2488 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl); 2489 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl); 2490 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl); 2491 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl); 2492 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1); 2493 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2); 2494 2495 return 0; 2496 } 2497 2498 static int ci_populate_smc_acpi_level(struct radeon_device *rdev, 2499 SMU7_Discrete_DpmTable *table) 2500 { 2501 struct ci_power_info *pi = ci_get_pi(rdev); 2502 struct atom_clock_dividers dividers; 2503 SMU7_Discrete_VoltageLevel voltage_level; 2504 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; 2505 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; 2506 u32 dll_cntl = pi->clock_registers.dll_cntl; 2507 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; 2508 int ret; 2509 2510 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 2511 2512 if (pi->acpi_vddc) 2513 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); 2514 else 2515 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); 2516 2517 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; 2518 2519 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; 2520 2521 ret = radeon_atom_get_clock_dividers(rdev, 2522 COMPUTE_GPUCLK_INPUT_FLAG_SCLK, 2523 table->ACPILevel.SclkFrequency, false, ÷rs); 2524 if (ret) 2525 return ret; 2526 2527 table->ACPILevel.SclkDid = (u8)dividers.post_divider; 2528 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2529 table->ACPILevel.DeepSleepDivId = 0; 2530 2531 spll_func_cntl &= ~SPLL_PWRON; 2532 spll_func_cntl |= SPLL_RESET; 2533 2534 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 2535 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 2536 2537 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; 2538 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; 2539 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; 2540 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; 2541 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; 2542 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; 2543 table->ACPILevel.CcPwrDynRm = 0; 2544 table->ACPILevel.CcPwrDynRm1 = 0; 2545 2546 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); 2547 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); 2548 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); 2549 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); 2550 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); 2551 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); 2552 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); 2553 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); 2554 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); 2555 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); 2556 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); 2557 2558 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; 2559 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; 2560 2561 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 2562 if (pi->acpi_vddci) 2563 table->MemoryACPILevel.MinVddci = 2564 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); 2565 else 2566 table->MemoryACPILevel.MinVddci = 2567 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); 2568 } 2569 2570 if (ci_populate_mvdd_value(rdev, 0, &voltage_level)) 2571 table->MemoryACPILevel.MinMvdd = 0; 2572 else 2573 table->MemoryACPILevel.MinMvdd = 2574 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE); 2575 2576 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 2577 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 2578 2579 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 2580 2581 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); 2582 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); 2583 table->MemoryACPILevel.MpllAdFuncCntl = 2584 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); 2585 table->MemoryACPILevel.MpllDqFuncCntl = 2586 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); 2587 table->MemoryACPILevel.MpllFuncCntl = 2588 cpu_to_be32(pi->clock_registers.mpll_func_cntl); 2589 table->MemoryACPILevel.MpllFuncCntl_1 = 2590 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); 2591 table->MemoryACPILevel.MpllFuncCntl_2 = 2592 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); 2593 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); 2594 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); 2595 2596 table->MemoryACPILevel.EnabledForThrottle = 0; 2597 table->MemoryACPILevel.EnabledForActivity = 0; 2598 table->MemoryACPILevel.UpH = 0; 2599 table->MemoryACPILevel.DownH = 100; 2600 table->MemoryACPILevel.VoltageDownH = 0; 2601 table->MemoryACPILevel.ActivityLevel = 2602 cpu_to_be16((u16)pi->mclk_activity_target); 2603 2604 table->MemoryACPILevel.StutterEnable = false; 2605 table->MemoryACPILevel.StrobeEnable = false; 2606 table->MemoryACPILevel.EdcReadEnable = false; 2607 table->MemoryACPILevel.EdcWriteEnable = false; 2608 table->MemoryACPILevel.RttEnable = false; 2609 2610 return 0; 2611 } 2612 2613 2614 static int ci_enable_ulv(struct radeon_device *rdev, bool enable) 2615 { 2616 struct ci_power_info *pi = ci_get_pi(rdev); 2617 struct ci_ulv_parm *ulv = &pi->ulv; 2618 2619 if (ulv->supported) { 2620 if (enable) 2621 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 2622 0 : -EINVAL; 2623 else 2624 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 2625 0 : -EINVAL; 2626 } 2627 2628 return 0; 2629 } 2630 2631 static int ci_populate_ulv_level(struct radeon_device *rdev, 2632 SMU7_Discrete_Ulv *state) 2633 { 2634 struct ci_power_info *pi = ci_get_pi(rdev); 2635 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; 2636 2637 state->CcPwrDynRm = 0; 2638 state->CcPwrDynRm1 = 0; 2639 2640 if (ulv_voltage == 0) { 2641 pi->ulv.supported = false; 2642 return 0; 2643 } 2644 2645 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 2646 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) 2647 state->VddcOffset = 0; 2648 else 2649 state->VddcOffset = 2650 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; 2651 } else { 2652 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) 2653 state->VddcOffsetVid = 0; 2654 else 2655 state->VddcOffsetVid = (u8) 2656 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * 2657 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 2658 } 2659 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; 2660 2661 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm); 2662 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1); 2663 state->VddcOffset = cpu_to_be16(state->VddcOffset); 2664 2665 return 0; 2666 } 2667 2668 static int ci_calculate_sclk_params(struct radeon_device *rdev, 2669 u32 engine_clock, 2670 SMU7_Discrete_GraphicsLevel *sclk) 2671 { 2672 struct ci_power_info *pi = ci_get_pi(rdev); 2673 struct atom_clock_dividers dividers; 2674 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; 2675 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; 2676 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; 2677 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; 2678 u32 reference_clock = rdev->clock.spll.reference_freq; 2679 u32 reference_divider; 2680 u32 fbdiv; 2681 int ret; 2682 2683 ret = radeon_atom_get_clock_dividers(rdev, 2684 COMPUTE_GPUCLK_INPUT_FLAG_SCLK, 2685 engine_clock, false, ÷rs); 2686 if (ret) 2687 return ret; 2688 2689 reference_divider = 1 + dividers.ref_div; 2690 fbdiv = dividers.fb_div & 0x3FFFFFF; 2691 2692 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 2693 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 2694 spll_func_cntl_3 |= SPLL_DITHEN; 2695 2696 if (pi->caps_sclk_ss_support) { 2697 struct radeon_atom_ss ss; 2698 u32 vco_freq = engine_clock * dividers.post_div; 2699 2700 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 2701 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 2702 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 2703 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 2704 2705 cg_spll_spread_spectrum &= ~CLK_S_MASK; 2706 cg_spll_spread_spectrum |= CLK_S(clk_s); 2707 cg_spll_spread_spectrum |= SSEN; 2708 2709 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 2710 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 2711 } 2712 } 2713 2714 sclk->SclkFrequency = engine_clock; 2715 sclk->CgSpllFuncCntl3 = spll_func_cntl_3; 2716 sclk->CgSpllFuncCntl4 = spll_func_cntl_4; 2717 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; 2718 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; 2719 sclk->SclkDid = (u8)dividers.post_divider; 2720 2721 return 0; 2722 } 2723 2724 static int ci_populate_single_graphic_level(struct radeon_device *rdev, 2725 u32 engine_clock, 2726 u16 sclk_activity_level_t, 2727 SMU7_Discrete_GraphicsLevel *graphic_level) 2728 { 2729 struct ci_power_info *pi = ci_get_pi(rdev); 2730 int ret; 2731 2732 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); 2733 if (ret) 2734 return ret; 2735 2736 ret = ci_get_dependency_volt_by_clk(rdev, 2737 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2738 engine_clock, &graphic_level->MinVddc); 2739 if (ret) 2740 return ret; 2741 2742 graphic_level->SclkFrequency = engine_clock; 2743 2744 graphic_level->Flags = 0; 2745 graphic_level->MinVddcPhases = 1; 2746 2747 if (pi->vddc_phase_shed_control) 2748 ci_populate_phase_value_based_on_sclk(rdev, 2749 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 2750 engine_clock, 2751 &graphic_level->MinVddcPhases); 2752 2753 graphic_level->ActivityLevel = sclk_activity_level_t; 2754 2755 graphic_level->CcPwrDynRm = 0; 2756 graphic_level->CcPwrDynRm1 = 0; 2757 graphic_level->EnabledForActivity = 1; 2758 graphic_level->EnabledForThrottle = 1; 2759 graphic_level->UpH = 0; 2760 graphic_level->DownH = 0; 2761 graphic_level->VoltageDownH = 0; 2762 graphic_level->PowerThrottle = 0; 2763 2764 if (pi->caps_sclk_ds) 2765 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev, 2766 engine_clock, 2767 CISLAND_MINIMUM_ENGINE_CLOCK); 2768 2769 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2770 2771 graphic_level->Flags = cpu_to_be32(graphic_level->Flags); 2772 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); 2773 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); 2774 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency); 2775 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel); 2776 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3); 2777 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4); 2778 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum); 2779 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); 2780 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); 2781 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1); 2782 2783 return 0; 2784 } 2785 2786 static int ci_populate_all_graphic_levels(struct radeon_device *rdev) 2787 { 2788 struct ci_power_info *pi = ci_get_pi(rdev); 2789 struct ci_dpm_table *dpm_table = &pi->dpm_table; 2790 u32 level_array_address = pi->dpm_table_start + 2791 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); 2792 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) * 2793 SMU7_MAX_LEVELS_GRAPHICS; 2794 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; 2795 u32 i, ret; 2796 2797 memset(levels, 0, level_array_size); 2798 2799 for (i = 0; i < dpm_table->sclk_table.count; i++) { 2800 ret = ci_populate_single_graphic_level(rdev, 2801 dpm_table->sclk_table.dpm_levels[i].value, 2802 (u16)pi->activity_target[i], 2803 &pi->smc_state_table.GraphicsLevel[i]); 2804 if (ret) 2805 return ret; 2806 if (i == (dpm_table->sclk_table.count - 1)) 2807 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = 2808 PPSMC_DISPLAY_WATERMARK_HIGH; 2809 } 2810 2811 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; 2812 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = 2813 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); 2814 2815 ret = ci_copy_bytes_to_smc(rdev, level_array_address, 2816 (u8 *)levels, level_array_size, 2817 pi->sram_end); 2818 if (ret) 2819 return ret; 2820 2821 return 0; 2822 } 2823 2824 static int ci_populate_ulv_state(struct radeon_device *rdev, 2825 SMU7_Discrete_Ulv *ulv_level) 2826 { 2827 return ci_populate_ulv_level(rdev, ulv_level); 2828 } 2829 2830 static int ci_populate_all_memory_levels(struct radeon_device *rdev) 2831 { 2832 struct ci_power_info *pi = ci_get_pi(rdev); 2833 struct ci_dpm_table *dpm_table = &pi->dpm_table; 2834 u32 level_array_address = pi->dpm_table_start + 2835 offsetof(SMU7_Discrete_DpmTable, MemoryLevel); 2836 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * 2837 SMU7_MAX_LEVELS_MEMORY; 2838 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; 2839 u32 i, ret; 2840 2841 memset(levels, 0, level_array_size); 2842 2843 for (i = 0; i < dpm_table->mclk_table.count; i++) { 2844 if (dpm_table->mclk_table.dpm_levels[i].value == 0) 2845 return -EINVAL; 2846 ret = ci_populate_single_memory_level(rdev, 2847 dpm_table->mclk_table.dpm_levels[i].value, 2848 &pi->smc_state_table.MemoryLevel[i]); 2849 if (ret) 2850 return ret; 2851 } 2852 2853 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); 2854 2855 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; 2856 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = 2857 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 2858 2859 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = 2860 PPSMC_DISPLAY_WATERMARK_HIGH; 2861 2862 ret = ci_copy_bytes_to_smc(rdev, level_array_address, 2863 (u8 *)levels, level_array_size, 2864 pi->sram_end); 2865 if (ret) 2866 return ret; 2867 2868 return 0; 2869 } 2870 2871 static void ci_reset_single_dpm_table(struct radeon_device *rdev, 2872 struct ci_single_dpm_table* dpm_table, 2873 u32 count) 2874 { 2875 u32 i; 2876 2877 dpm_table->count = count; 2878 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) 2879 dpm_table->dpm_levels[i].enabled = false; 2880 } 2881 2882 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table, 2883 u32 index, u32 pcie_gen, u32 pcie_lanes) 2884 { 2885 dpm_table->dpm_levels[index].value = pcie_gen; 2886 dpm_table->dpm_levels[index].param1 = pcie_lanes; 2887 dpm_table->dpm_levels[index].enabled = true; 2888 } 2889 2890 static int ci_setup_default_pcie_tables(struct radeon_device *rdev) 2891 { 2892 struct ci_power_info *pi = ci_get_pi(rdev); 2893 2894 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) 2895 return -EINVAL; 2896 2897 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { 2898 pi->pcie_gen_powersaving = pi->pcie_gen_performance; 2899 pi->pcie_lane_powersaving = pi->pcie_lane_performance; 2900 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { 2901 pi->pcie_gen_performance = pi->pcie_gen_powersaving; 2902 pi->pcie_lane_performance = pi->pcie_lane_powersaving; 2903 } 2904 2905 ci_reset_single_dpm_table(rdev, 2906 &pi->dpm_table.pcie_speed_table, 2907 SMU7_MAX_LEVELS_LINK); 2908 2909 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, 2910 pi->pcie_gen_powersaving.min, 2911 pi->pcie_lane_powersaving.min); 2912 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, 2913 pi->pcie_gen_performance.min, 2914 pi->pcie_lane_performance.min); 2915 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, 2916 pi->pcie_gen_powersaving.min, 2917 pi->pcie_lane_powersaving.max); 2918 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, 2919 pi->pcie_gen_performance.min, 2920 pi->pcie_lane_performance.max); 2921 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, 2922 pi->pcie_gen_powersaving.max, 2923 pi->pcie_lane_powersaving.max); 2924 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, 2925 pi->pcie_gen_performance.max, 2926 pi->pcie_lane_performance.max); 2927 2928 pi->dpm_table.pcie_speed_table.count = 6; 2929 2930 return 0; 2931 } 2932 2933 static int ci_setup_default_dpm_tables(struct radeon_device *rdev) 2934 { 2935 struct ci_power_info *pi = ci_get_pi(rdev); 2936 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = 2937 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2938 struct radeon_clock_voltage_dependency_table *allowed_mclk_table = 2939 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; 2940 struct radeon_cac_leakage_table *std_voltage_table = 2941 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2942 u32 i; 2943 2944 if (allowed_sclk_vddc_table == NULL) 2945 return -EINVAL; 2946 if (allowed_sclk_vddc_table->count < 1) 2947 return -EINVAL; 2948 if (allowed_mclk_table == NULL) 2949 return -EINVAL; 2950 if (allowed_mclk_table->count < 1) 2951 return -EINVAL; 2952 2953 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); 2954 2955 ci_reset_single_dpm_table(rdev, 2956 &pi->dpm_table.sclk_table, 2957 SMU7_MAX_LEVELS_GRAPHICS); 2958 ci_reset_single_dpm_table(rdev, 2959 &pi->dpm_table.mclk_table, 2960 SMU7_MAX_LEVELS_MEMORY); 2961 ci_reset_single_dpm_table(rdev, 2962 &pi->dpm_table.vddc_table, 2963 SMU7_MAX_LEVELS_VDDC); 2964 ci_reset_single_dpm_table(rdev, 2965 &pi->dpm_table.vddci_table, 2966 SMU7_MAX_LEVELS_VDDCI); 2967 ci_reset_single_dpm_table(rdev, 2968 &pi->dpm_table.mvdd_table, 2969 SMU7_MAX_LEVELS_MVDD); 2970 2971 pi->dpm_table.sclk_table.count = 0; 2972 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { 2973 if ((i == 0) || 2974 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != 2975 allowed_sclk_vddc_table->entries[i].clk)) { 2976 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = 2977 allowed_sclk_vddc_table->entries[i].clk; 2978 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true; 2979 pi->dpm_table.sclk_table.count++; 2980 } 2981 } 2982 2983 pi->dpm_table.mclk_table.count = 0; 2984 for (i = 0; i < allowed_mclk_table->count; i++) { 2985 if ((i==0) || 2986 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != 2987 allowed_mclk_table->entries[i].clk)) { 2988 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = 2989 allowed_mclk_table->entries[i].clk; 2990 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true; 2991 pi->dpm_table.mclk_table.count++; 2992 } 2993 } 2994 2995 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { 2996 pi->dpm_table.vddc_table.dpm_levels[i].value = 2997 allowed_sclk_vddc_table->entries[i].v; 2998 pi->dpm_table.vddc_table.dpm_levels[i].param1 = 2999 std_voltage_table->entries[i].leakage; 3000 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; 3001 } 3002 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; 3003 3004 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; 3005 if (allowed_mclk_table) { 3006 for (i = 0; i < allowed_mclk_table->count; i++) { 3007 pi->dpm_table.vddci_table.dpm_levels[i].value = 3008 allowed_mclk_table->entries[i].v; 3009 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; 3010 } 3011 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; 3012 } 3013 3014 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; 3015 if (allowed_mclk_table) { 3016 for (i = 0; i < allowed_mclk_table->count; i++) { 3017 pi->dpm_table.mvdd_table.dpm_levels[i].value = 3018 allowed_mclk_table->entries[i].v; 3019 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; 3020 } 3021 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; 3022 } 3023 3024 ci_setup_default_pcie_tables(rdev); 3025 3026 return 0; 3027 } 3028 3029 static int ci_find_boot_level(struct ci_single_dpm_table *table, 3030 u32 value, u32 *boot_level) 3031 { 3032 u32 i; 3033 int ret = -EINVAL; 3034 3035 for(i = 0; i < table->count; i++) { 3036 if (value == table->dpm_levels[i].value) { 3037 *boot_level = i; 3038 ret = 0; 3039 } 3040 } 3041 3042 return ret; 3043 } 3044 3045 static int ci_init_smc_table(struct radeon_device *rdev) 3046 { 3047 struct ci_power_info *pi = ci_get_pi(rdev); 3048 struct ci_ulv_parm *ulv = &pi->ulv; 3049 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 3050 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; 3051 int ret; 3052 3053 ret = ci_setup_default_dpm_tables(rdev); 3054 if (ret) 3055 return ret; 3056 3057 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) 3058 ci_populate_smc_voltage_tables(rdev, table); 3059 3060 ci_init_fps_limits(rdev); 3061 3062 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 3063 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 3064 3065 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 3066 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 3067 3068 if (pi->mem_gddr5) 3069 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 3070 3071 if (ulv->supported) { 3072 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); 3073 if (ret) 3074 return ret; 3075 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 3076 } 3077 3078 ret = ci_populate_all_graphic_levels(rdev); 3079 if (ret) 3080 return ret; 3081 3082 ret = ci_populate_all_memory_levels(rdev); 3083 if (ret) 3084 return ret; 3085 3086 ci_populate_smc_link_level(rdev, table); 3087 3088 ret = ci_populate_smc_acpi_level(rdev, table); 3089 if (ret) 3090 return ret; 3091 3092 ret = ci_populate_smc_vce_level(rdev, table); 3093 if (ret) 3094 return ret; 3095 3096 ret = ci_populate_smc_acp_level(rdev, table); 3097 if (ret) 3098 return ret; 3099 3100 ret = ci_populate_smc_samu_level(rdev, table); 3101 if (ret) 3102 return ret; 3103 3104 ret = ci_do_program_memory_timing_parameters(rdev); 3105 if (ret) 3106 return ret; 3107 3108 ret = ci_populate_smc_uvd_level(rdev, table); 3109 if (ret) 3110 return ret; 3111 3112 table->UvdBootLevel = 0; 3113 table->VceBootLevel = 0; 3114 table->AcpBootLevel = 0; 3115 table->SamuBootLevel = 0; 3116 table->GraphicsBootLevel = 0; 3117 table->MemoryBootLevel = 0; 3118 3119 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, 3120 pi->vbios_boot_state.sclk_bootup_value, 3121 (u32 *)&pi->smc_state_table.GraphicsBootLevel); 3122 3123 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, 3124 pi->vbios_boot_state.mclk_bootup_value, 3125 (u32 *)&pi->smc_state_table.MemoryBootLevel); 3126 3127 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; 3128 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; 3129 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; 3130 3131 ci_populate_smc_initial_state(rdev, radeon_boot_state); 3132 3133 ret = ci_populate_bapm_parameters_in_dpm_table(rdev); 3134 if (ret) 3135 return ret; 3136 3137 table->UVDInterval = 1; 3138 table->VCEInterval = 1; 3139 table->ACPInterval = 1; 3140 table->SAMUInterval = 1; 3141 table->GraphicsVoltageChangeEnable = 1; 3142 table->GraphicsThermThrottleEnable = 1; 3143 table->GraphicsInterval = 1; 3144 table->VoltageInterval = 1; 3145 table->ThermalInterval = 1; 3146 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * 3147 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); 3148 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * 3149 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); 3150 table->MemoryVoltageChangeEnable = 1; 3151 table->MemoryInterval = 1; 3152 table->VoltageResponseTime = 0; 3153 table->VddcVddciDelta = 4000; 3154 table->PhaseResponseTime = 0; 3155 table->MemoryThermThrottleEnable = 1; 3156 table->PCIeBootLinkLevel = 0; 3157 table->PCIeGenInterval = 1; 3158 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) 3159 table->SVI2Enable = 1; 3160 else 3161 table->SVI2Enable = 0; 3162 3163 table->ThermGpio = 17; 3164 table->SclkStepSize = 0x4000; 3165 3166 table->SystemFlags = cpu_to_be32(table->SystemFlags); 3167 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); 3168 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); 3169 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); 3170 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); 3171 table->SclkStepSize = cpu_to_be32(table->SclkStepSize); 3172 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); 3173 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); 3174 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); 3175 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); 3176 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); 3177 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); 3178 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); 3179 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); 3180 3181 ret = ci_copy_bytes_to_smc(rdev, 3182 pi->dpm_table_start + 3183 offsetof(SMU7_Discrete_DpmTable, SystemFlags), 3184 (u8 *)&table->SystemFlags, 3185 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController), 3186 pi->sram_end); 3187 if (ret) 3188 return ret; 3189 3190 return 0; 3191 } 3192 3193 static void ci_trim_single_dpm_states(struct radeon_device *rdev, 3194 struct ci_single_dpm_table *dpm_table, 3195 u32 low_limit, u32 high_limit) 3196 { 3197 u32 i; 3198 3199 for (i = 0; i < dpm_table->count; i++) { 3200 if ((dpm_table->dpm_levels[i].value < low_limit) || 3201 (dpm_table->dpm_levels[i].value > high_limit)) 3202 dpm_table->dpm_levels[i].enabled = false; 3203 else 3204 dpm_table->dpm_levels[i].enabled = true; 3205 } 3206 } 3207 3208 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev, 3209 u32 speed_low, u32 lanes_low, 3210 u32 speed_high, u32 lanes_high) 3211 { 3212 struct ci_power_info *pi = ci_get_pi(rdev); 3213 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; 3214 u32 i, j; 3215 3216 for (i = 0; i < pcie_table->count; i++) { 3217 if ((pcie_table->dpm_levels[i].value < speed_low) || 3218 (pcie_table->dpm_levels[i].param1 < lanes_low) || 3219 (pcie_table->dpm_levels[i].value > speed_high) || 3220 (pcie_table->dpm_levels[i].param1 > lanes_high)) 3221 pcie_table->dpm_levels[i].enabled = false; 3222 else 3223 pcie_table->dpm_levels[i].enabled = true; 3224 } 3225 3226 for (i = 0; i < pcie_table->count; i++) { 3227 if (pcie_table->dpm_levels[i].enabled) { 3228 for (j = i + 1; j < pcie_table->count; j++) { 3229 if (pcie_table->dpm_levels[j].enabled) { 3230 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) && 3231 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1)) 3232 pcie_table->dpm_levels[j].enabled = false; 3233 } 3234 } 3235 } 3236 } 3237 } 3238 3239 static int ci_trim_dpm_states(struct radeon_device *rdev, 3240 struct radeon_ps *radeon_state) 3241 { 3242 struct ci_ps *state = ci_get_ps(radeon_state); 3243 struct ci_power_info *pi = ci_get_pi(rdev); 3244 u32 high_limit_count; 3245 3246 if (state->performance_level_count < 1) 3247 return -EINVAL; 3248 3249 if (state->performance_level_count == 1) 3250 high_limit_count = 0; 3251 else 3252 high_limit_count = 1; 3253 3254 ci_trim_single_dpm_states(rdev, 3255 &pi->dpm_table.sclk_table, 3256 state->performance_levels[0].sclk, 3257 state->performance_levels[high_limit_count].sclk); 3258 3259 ci_trim_single_dpm_states(rdev, 3260 &pi->dpm_table.mclk_table, 3261 state->performance_levels[0].mclk, 3262 state->performance_levels[high_limit_count].mclk); 3263 3264 ci_trim_pcie_dpm_states(rdev, 3265 state->performance_levels[0].pcie_gen, 3266 state->performance_levels[0].pcie_lane, 3267 state->performance_levels[high_limit_count].pcie_gen, 3268 state->performance_levels[high_limit_count].pcie_lane); 3269 3270 return 0; 3271 } 3272 3273 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev) 3274 { 3275 struct radeon_clock_voltage_dependency_table *disp_voltage_table = 3276 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; 3277 struct radeon_clock_voltage_dependency_table *vddc_table = 3278 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 3279 u32 requested_voltage = 0; 3280 u32 i; 3281 3282 if (disp_voltage_table == NULL) 3283 return -EINVAL; 3284 if (!disp_voltage_table->count) 3285 return -EINVAL; 3286 3287 for (i = 0; i < disp_voltage_table->count; i++) { 3288 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk) 3289 requested_voltage = disp_voltage_table->entries[i].v; 3290 } 3291 3292 for (i = 0; i < vddc_table->count; i++) { 3293 if (requested_voltage <= vddc_table->entries[i].v) { 3294 requested_voltage = vddc_table->entries[i].v; 3295 return (ci_send_msg_to_smc_with_parameter(rdev, 3296 PPSMC_MSG_VddC_Request, 3297 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ? 3298 0 : -EINVAL; 3299 } 3300 } 3301 3302 return -EINVAL; 3303 } 3304 3305 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev) 3306 { 3307 struct ci_power_info *pi = ci_get_pi(rdev); 3308 PPSMC_Result result; 3309 3310 if (!pi->sclk_dpm_key_disabled) { 3311 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3312 result = ci_send_msg_to_smc_with_parameter(rdev, 3313 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3314 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); 3315 if (result != PPSMC_Result_OK) 3316 return -EINVAL; 3317 } 3318 } 3319 3320 if (!pi->mclk_dpm_key_disabled) { 3321 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3322 result = ci_send_msg_to_smc_with_parameter(rdev, 3323 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3324 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3325 if (result != PPSMC_Result_OK) 3326 return -EINVAL; 3327 } 3328 } 3329 3330 if (!pi->pcie_dpm_key_disabled) { 3331 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3332 result = ci_send_msg_to_smc_with_parameter(rdev, 3333 PPSMC_MSG_PCIeDPM_SetEnabledMask, 3334 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); 3335 if (result != PPSMC_Result_OK) 3336 return -EINVAL; 3337 } 3338 } 3339 3340 ci_apply_disp_minimum_voltage_request(rdev); 3341 3342 return 0; 3343 } 3344 3345 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev, 3346 struct radeon_ps *radeon_state) 3347 { 3348 struct ci_power_info *pi = ci_get_pi(rdev); 3349 struct ci_ps *state = ci_get_ps(radeon_state); 3350 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; 3351 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; 3352 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; 3353 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; 3354 u32 i; 3355 3356 pi->need_update_smu7_dpm_table = 0; 3357 3358 for (i = 0; i < sclk_table->count; i++) { 3359 if (sclk == sclk_table->dpm_levels[i].value) 3360 break; 3361 } 3362 3363 if (i >= sclk_table->count) { 3364 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3365 } else { 3366 /* XXX check display min clock requirements */ 3367 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK) 3368 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; 3369 } 3370 3371 for (i = 0; i < mclk_table->count; i++) { 3372 if (mclk == mclk_table->dpm_levels[i].value) 3373 break; 3374 } 3375 3376 if (i >= mclk_table->count) 3377 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3378 3379 if (rdev->pm.dpm.current_active_crtc_count != 3380 rdev->pm.dpm.new_active_crtc_count) 3381 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; 3382 } 3383 3384 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev, 3385 struct radeon_ps *radeon_state) 3386 { 3387 struct ci_power_info *pi = ci_get_pi(rdev); 3388 struct ci_ps *state = ci_get_ps(radeon_state); 3389 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; 3390 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; 3391 struct ci_dpm_table *dpm_table = &pi->dpm_table; 3392 int ret; 3393 3394 if (!pi->need_update_smu7_dpm_table) 3395 return 0; 3396 3397 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) 3398 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; 3399 3400 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) 3401 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; 3402 3403 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { 3404 ret = ci_populate_all_graphic_levels(rdev); 3405 if (ret) 3406 return ret; 3407 } 3408 3409 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 3410 ret = ci_populate_all_memory_levels(rdev); 3411 if (ret) 3412 return ret; 3413 } 3414 3415 return 0; 3416 } 3417 3418 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable) 3419 { 3420 struct ci_power_info *pi = ci_get_pi(rdev); 3421 const struct radeon_clock_and_voltage_limits *max_limits; 3422 int i; 3423 3424 if (rdev->pm.dpm.ac_power) 3425 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3426 else 3427 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3428 3429 if (enable) { 3430 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; 3431 3432 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3433 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3434 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; 3435 3436 if (!pi->caps_uvd_dpm) 3437 break; 3438 } 3439 } 3440 3441 ci_send_msg_to_smc_with_parameter(rdev, 3442 PPSMC_MSG_UVDDPM_SetEnabledMask, 3443 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); 3444 3445 if (pi->last_mclk_dpm_enable_mask & 0x1) { 3446 pi->uvd_enabled = true; 3447 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; 3448 ci_send_msg_to_smc_with_parameter(rdev, 3449 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3450 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3451 } 3452 } else { 3453 if (pi->last_mclk_dpm_enable_mask & 0x1) { 3454 pi->uvd_enabled = false; 3455 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; 3456 ci_send_msg_to_smc_with_parameter(rdev, 3457 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3458 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3459 } 3460 } 3461 3462 return (ci_send_msg_to_smc(rdev, enable ? 3463 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ? 3464 0 : -EINVAL; 3465 } 3466 3467 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable) 3468 { 3469 struct ci_power_info *pi = ci_get_pi(rdev); 3470 const struct radeon_clock_and_voltage_limits *max_limits; 3471 int i; 3472 3473 if (rdev->pm.dpm.ac_power) 3474 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3475 else 3476 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3477 3478 if (enable) { 3479 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; 3480 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3481 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3482 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; 3483 3484 if (!pi->caps_vce_dpm) 3485 break; 3486 } 3487 } 3488 3489 ci_send_msg_to_smc_with_parameter(rdev, 3490 PPSMC_MSG_VCEDPM_SetEnabledMask, 3491 pi->dpm_level_enable_mask.vce_dpm_enable_mask); 3492 } 3493 3494 return (ci_send_msg_to_smc(rdev, enable ? 3495 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ? 3496 0 : -EINVAL; 3497 } 3498 3499 #if 0 3500 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable) 3501 { 3502 struct ci_power_info *pi = ci_get_pi(rdev); 3503 const struct radeon_clock_and_voltage_limits *max_limits; 3504 int i; 3505 3506 if (rdev->pm.dpm.ac_power) 3507 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3508 else 3509 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3510 3511 if (enable) { 3512 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0; 3513 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3514 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3515 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i; 3516 3517 if (!pi->caps_samu_dpm) 3518 break; 3519 } 3520 } 3521 3522 ci_send_msg_to_smc_with_parameter(rdev, 3523 PPSMC_MSG_SAMUDPM_SetEnabledMask, 3524 pi->dpm_level_enable_mask.samu_dpm_enable_mask); 3525 } 3526 return (ci_send_msg_to_smc(rdev, enable ? 3527 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ? 3528 0 : -EINVAL; 3529 } 3530 3531 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable) 3532 { 3533 struct ci_power_info *pi = ci_get_pi(rdev); 3534 const struct radeon_clock_and_voltage_limits *max_limits; 3535 int i; 3536 3537 if (rdev->pm.dpm.ac_power) 3538 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3539 else 3540 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3541 3542 if (enable) { 3543 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0; 3544 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3545 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3546 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i; 3547 3548 if (!pi->caps_acp_dpm) 3549 break; 3550 } 3551 } 3552 3553 ci_send_msg_to_smc_with_parameter(rdev, 3554 PPSMC_MSG_ACPDPM_SetEnabledMask, 3555 pi->dpm_level_enable_mask.acp_dpm_enable_mask); 3556 } 3557 3558 return (ci_send_msg_to_smc(rdev, enable ? 3559 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ? 3560 0 : -EINVAL; 3561 } 3562 #endif 3563 3564 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate) 3565 { 3566 struct ci_power_info *pi = ci_get_pi(rdev); 3567 u32 tmp; 3568 3569 if (!gate) { 3570 if (pi->caps_uvd_dpm || 3571 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) 3572 pi->smc_state_table.UvdBootLevel = 0; 3573 else 3574 pi->smc_state_table.UvdBootLevel = 3575 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; 3576 3577 tmp = RREG32_SMC(DPM_TABLE_475); 3578 tmp &= ~UvdBootLevel_MASK; 3579 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); 3580 WREG32_SMC(DPM_TABLE_475, tmp); 3581 } 3582 3583 return ci_enable_uvd_dpm(rdev, !gate); 3584 } 3585 3586 static u8 ci_get_vce_boot_level(struct radeon_device *rdev) 3587 { 3588 u8 i; 3589 u32 min_evclk = 30000; /* ??? */ 3590 struct radeon_vce_clock_voltage_dependency_table *table = 3591 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 3592 3593 for (i = 0; i < table->count; i++) { 3594 if (table->entries[i].evclk >= min_evclk) 3595 return i; 3596 } 3597 3598 return table->count - 1; 3599 } 3600 3601 static int ci_update_vce_dpm(struct radeon_device *rdev, 3602 struct radeon_ps *radeon_new_state, 3603 struct radeon_ps *radeon_current_state) 3604 { 3605 struct ci_power_info *pi = ci_get_pi(rdev); 3606 int ret = 0; 3607 u32 tmp; 3608 3609 if (radeon_current_state->evclk != radeon_new_state->evclk) { 3610 if (radeon_new_state->evclk) { 3611 /* turn the clocks on when encoding */ 3612 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false); 3613 3614 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); 3615 tmp = RREG32_SMC(DPM_TABLE_475); 3616 tmp &= ~VceBootLevel_MASK; 3617 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); 3618 WREG32_SMC(DPM_TABLE_475, tmp); 3619 3620 ret = ci_enable_vce_dpm(rdev, true); 3621 } else { 3622 /* turn the clocks off when not encoding */ 3623 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true); 3624 3625 ret = ci_enable_vce_dpm(rdev, false); 3626 } 3627 } 3628 return ret; 3629 } 3630 3631 #if 0 3632 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate) 3633 { 3634 return ci_enable_samu_dpm(rdev, gate); 3635 } 3636 3637 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate) 3638 { 3639 struct ci_power_info *pi = ci_get_pi(rdev); 3640 u32 tmp; 3641 3642 if (!gate) { 3643 pi->smc_state_table.AcpBootLevel = 0; 3644 3645 tmp = RREG32_SMC(DPM_TABLE_475); 3646 tmp &= ~AcpBootLevel_MASK; 3647 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel); 3648 WREG32_SMC(DPM_TABLE_475, tmp); 3649 } 3650 3651 return ci_enable_acp_dpm(rdev, !gate); 3652 } 3653 #endif 3654 3655 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev, 3656 struct radeon_ps *radeon_state) 3657 { 3658 struct ci_power_info *pi = ci_get_pi(rdev); 3659 int ret; 3660 3661 ret = ci_trim_dpm_states(rdev, radeon_state); 3662 if (ret) 3663 return ret; 3664 3665 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = 3666 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); 3667 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = 3668 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); 3669 pi->last_mclk_dpm_enable_mask = 3670 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; 3671 if (pi->uvd_enabled) { 3672 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) 3673 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; 3674 } 3675 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = 3676 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); 3677 3678 return 0; 3679 } 3680 3681 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev, 3682 u32 level_mask) 3683 { 3684 u32 level = 0; 3685 3686 while ((level_mask & (1 << level)) == 0) 3687 level++; 3688 3689 return level; 3690 } 3691 3692 3693 int ci_dpm_force_performance_level(struct radeon_device *rdev, 3694 enum radeon_dpm_forced_level level) 3695 { 3696 struct ci_power_info *pi = ci_get_pi(rdev); 3697 PPSMC_Result smc_result; 3698 u32 tmp, levels, i; 3699 int ret; 3700 3701 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3702 if ((!pi->sclk_dpm_key_disabled) && 3703 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3704 levels = 0; 3705 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; 3706 while (tmp >>= 1) 3707 levels++; 3708 if (levels) { 3709 ret = ci_dpm_force_state_sclk(rdev, levels); 3710 if (ret) 3711 return ret; 3712 for (i = 0; i < rdev->usec_timeout; i++) { 3713 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 3714 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; 3715 if (tmp == levels) 3716 break; 3717 udelay(1); 3718 } 3719 } 3720 } 3721 if ((!pi->mclk_dpm_key_disabled) && 3722 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3723 levels = 0; 3724 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; 3725 while (tmp >>= 1) 3726 levels++; 3727 if (levels) { 3728 ret = ci_dpm_force_state_mclk(rdev, levels); 3729 if (ret) 3730 return ret; 3731 for (i = 0; i < rdev->usec_timeout; i++) { 3732 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 3733 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; 3734 if (tmp == levels) 3735 break; 3736 udelay(1); 3737 } 3738 } 3739 } 3740 if ((!pi->pcie_dpm_key_disabled) && 3741 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3742 levels = 0; 3743 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; 3744 while (tmp >>= 1) 3745 levels++; 3746 if (levels) { 3747 ret = ci_dpm_force_state_pcie(rdev, level); 3748 if (ret) 3749 return ret; 3750 for (i = 0; i < rdev->usec_timeout; i++) { 3751 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & 3752 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; 3753 if (tmp == levels) 3754 break; 3755 udelay(1); 3756 } 3757 } 3758 } 3759 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3760 if ((!pi->sclk_dpm_key_disabled) && 3761 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3762 levels = ci_get_lowest_enabled_level(rdev, 3763 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); 3764 ret = ci_dpm_force_state_sclk(rdev, levels); 3765 if (ret) 3766 return ret; 3767 for (i = 0; i < rdev->usec_timeout; i++) { 3768 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 3769 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; 3770 if (tmp == levels) 3771 break; 3772 udelay(1); 3773 } 3774 } 3775 if ((!pi->mclk_dpm_key_disabled) && 3776 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3777 levels = ci_get_lowest_enabled_level(rdev, 3778 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3779 ret = ci_dpm_force_state_mclk(rdev, levels); 3780 if (ret) 3781 return ret; 3782 for (i = 0; i < rdev->usec_timeout; i++) { 3783 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 3784 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; 3785 if (tmp == levels) 3786 break; 3787 udelay(1); 3788 } 3789 } 3790 if ((!pi->pcie_dpm_key_disabled) && 3791 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3792 levels = ci_get_lowest_enabled_level(rdev, 3793 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); 3794 ret = ci_dpm_force_state_pcie(rdev, levels); 3795 if (ret) 3796 return ret; 3797 for (i = 0; i < rdev->usec_timeout; i++) { 3798 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & 3799 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; 3800 if (tmp == levels) 3801 break; 3802 udelay(1); 3803 } 3804 } 3805 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3806 if (!pi->sclk_dpm_key_disabled) { 3807 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel); 3808 if (smc_result != PPSMC_Result_OK) 3809 return -EINVAL; 3810 } 3811 if (!pi->mclk_dpm_key_disabled) { 3812 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel); 3813 if (smc_result != PPSMC_Result_OK) 3814 return -EINVAL; 3815 } 3816 if (!pi->pcie_dpm_key_disabled) { 3817 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel); 3818 if (smc_result != PPSMC_Result_OK) 3819 return -EINVAL; 3820 } 3821 } 3822 3823 rdev->pm.dpm.forced_level = level; 3824 3825 return 0; 3826 } 3827 3828 static int ci_set_mc_special_registers(struct radeon_device *rdev, 3829 struct ci_mc_reg_table *table) 3830 { 3831 struct ci_power_info *pi = ci_get_pi(rdev); 3832 u8 i, j, k; 3833 u32 temp_reg; 3834 3835 for (i = 0, j = table->last; i < table->last; i++) { 3836 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3837 return -EINVAL; 3838 switch(table->mc_reg_address[i].s1 << 2) { 3839 case MC_SEQ_MISC1: 3840 temp_reg = RREG32(MC_PMG_CMD_EMRS); 3841 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 3842 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 3843 for (k = 0; k < table->num_entries; k++) { 3844 table->mc_reg_table_entry[k].mc_data[j] = 3845 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 3846 } 3847 j++; 3848 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3849 return -EINVAL; 3850 3851 temp_reg = RREG32(MC_PMG_CMD_MRS); 3852 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 3853 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 3854 for (k = 0; k < table->num_entries; k++) { 3855 table->mc_reg_table_entry[k].mc_data[j] = 3856 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 3857 if (!pi->mem_gddr5) 3858 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 3859 } 3860 j++; 3861 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3862 return -EINVAL; 3863 3864 if (!pi->mem_gddr5) { 3865 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 3866 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 3867 for (k = 0; k < table->num_entries; k++) { 3868 table->mc_reg_table_entry[k].mc_data[j] = 3869 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 3870 } 3871 j++; 3872 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3873 return -EINVAL; 3874 } 3875 break; 3876 case MC_SEQ_RESERVE_M: 3877 temp_reg = RREG32(MC_PMG_CMD_MRS1); 3878 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 3879 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 3880 for (k = 0; k < table->num_entries; k++) { 3881 table->mc_reg_table_entry[k].mc_data[j] = 3882 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 3883 } 3884 j++; 3885 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 3886 return -EINVAL; 3887 break; 3888 default: 3889 break; 3890 } 3891 3892 } 3893 3894 table->last = j; 3895 3896 return 0; 3897 } 3898 3899 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 3900 { 3901 bool result = true; 3902 3903 switch(in_reg) { 3904 case MC_SEQ_RAS_TIMING >> 2: 3905 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 3906 break; 3907 case MC_SEQ_DLL_STBY >> 2: 3908 *out_reg = MC_SEQ_DLL_STBY_LP >> 2; 3909 break; 3910 case MC_SEQ_G5PDX_CMD0 >> 2: 3911 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2; 3912 break; 3913 case MC_SEQ_G5PDX_CMD1 >> 2: 3914 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2; 3915 break; 3916 case MC_SEQ_G5PDX_CTRL >> 2: 3917 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2; 3918 break; 3919 case MC_SEQ_CAS_TIMING >> 2: 3920 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 3921 break; 3922 case MC_SEQ_MISC_TIMING >> 2: 3923 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 3924 break; 3925 case MC_SEQ_MISC_TIMING2 >> 2: 3926 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 3927 break; 3928 case MC_SEQ_PMG_DVS_CMD >> 2: 3929 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2; 3930 break; 3931 case MC_SEQ_PMG_DVS_CTL >> 2: 3932 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2; 3933 break; 3934 case MC_SEQ_RD_CTL_D0 >> 2: 3935 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 3936 break; 3937 case MC_SEQ_RD_CTL_D1 >> 2: 3938 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 3939 break; 3940 case MC_SEQ_WR_CTL_D0 >> 2: 3941 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 3942 break; 3943 case MC_SEQ_WR_CTL_D1 >> 2: 3944 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 3945 break; 3946 case MC_PMG_CMD_EMRS >> 2: 3947 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 3948 break; 3949 case MC_PMG_CMD_MRS >> 2: 3950 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 3951 break; 3952 case MC_PMG_CMD_MRS1 >> 2: 3953 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 3954 break; 3955 case MC_SEQ_PMG_TIMING >> 2: 3956 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 3957 break; 3958 case MC_PMG_CMD_MRS2 >> 2: 3959 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 3960 break; 3961 case MC_SEQ_WR_CTL_2 >> 2: 3962 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 3963 break; 3964 default: 3965 result = false; 3966 break; 3967 } 3968 3969 return result; 3970 } 3971 3972 static void ci_set_valid_flag(struct ci_mc_reg_table *table) 3973 { 3974 u8 i, j; 3975 3976 for (i = 0; i < table->last; i++) { 3977 for (j = 1; j < table->num_entries; j++) { 3978 if (table->mc_reg_table_entry[j-1].mc_data[i] != 3979 table->mc_reg_table_entry[j].mc_data[i]) { 3980 table->valid_flag |= 1 << i; 3981 break; 3982 } 3983 } 3984 } 3985 } 3986 3987 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) 3988 { 3989 u32 i; 3990 u16 address; 3991 3992 for (i = 0; i < table->last; i++) { 3993 table->mc_reg_address[i].s0 = 3994 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 3995 address : table->mc_reg_address[i].s1; 3996 } 3997 } 3998 3999 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, 4000 struct ci_mc_reg_table *ci_table) 4001 { 4002 u8 i, j; 4003 4004 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4005 return -EINVAL; 4006 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 4007 return -EINVAL; 4008 4009 for (i = 0; i < table->last; i++) 4010 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 4011 4012 ci_table->last = table->last; 4013 4014 for (i = 0; i < table->num_entries; i++) { 4015 ci_table->mc_reg_table_entry[i].mclk_max = 4016 table->mc_reg_table_entry[i].mclk_max; 4017 for (j = 0; j < table->last; j++) 4018 ci_table->mc_reg_table_entry[i].mc_data[j] = 4019 table->mc_reg_table_entry[i].mc_data[j]; 4020 } 4021 ci_table->num_entries = table->num_entries; 4022 4023 return 0; 4024 } 4025 4026 static int ci_initialize_mc_reg_table(struct radeon_device *rdev) 4027 { 4028 struct ci_power_info *pi = ci_get_pi(rdev); 4029 struct atom_mc_reg_table *table; 4030 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; 4031 u8 module_index = rv770_get_memory_module_index(rdev); 4032 int ret; 4033 4034 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 4035 if (!table) 4036 return -ENOMEM; 4037 4038 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 4039 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 4040 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY)); 4041 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0)); 4042 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1)); 4043 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL)); 4044 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD)); 4045 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL)); 4046 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 4047 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 4048 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 4049 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 4050 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 4051 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 4052 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 4053 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 4054 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 4055 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 4056 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 4057 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 4058 4059 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 4060 if (ret) 4061 goto init_mc_done; 4062 4063 ret = ci_copy_vbios_mc_reg_table(table, ci_table); 4064 if (ret) 4065 goto init_mc_done; 4066 4067 ci_set_s0_mc_reg_index(ci_table); 4068 4069 ret = ci_set_mc_special_registers(rdev, ci_table); 4070 if (ret) 4071 goto init_mc_done; 4072 4073 ci_set_valid_flag(ci_table); 4074 4075 init_mc_done: 4076 kfree(table); 4077 4078 return ret; 4079 } 4080 4081 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev, 4082 SMU7_Discrete_MCRegisters *mc_reg_table) 4083 { 4084 struct ci_power_info *pi = ci_get_pi(rdev); 4085 u32 i, j; 4086 4087 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { 4088 if (pi->mc_reg_table.valid_flag & (1 << j)) { 4089 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4090 return -EINVAL; 4091 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); 4092 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); 4093 i++; 4094 } 4095 } 4096 4097 mc_reg_table->last = (u8)i; 4098 4099 return 0; 4100 } 4101 4102 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry, 4103 SMU7_Discrete_MCRegisterSet *data, 4104 u32 num_entries, u32 valid_flag) 4105 { 4106 u32 i, j; 4107 4108 for (i = 0, j = 0; j < num_entries; j++) { 4109 if (valid_flag & (1 << j)) { 4110 data->value[i] = cpu_to_be32(entry->mc_data[j]); 4111 i++; 4112 } 4113 } 4114 } 4115 4116 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 4117 const u32 memory_clock, 4118 SMU7_Discrete_MCRegisterSet *mc_reg_table_data) 4119 { 4120 struct ci_power_info *pi = ci_get_pi(rdev); 4121 u32 i = 0; 4122 4123 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { 4124 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 4125 break; 4126 } 4127 4128 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) 4129 --i; 4130 4131 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], 4132 mc_reg_table_data, pi->mc_reg_table.last, 4133 pi->mc_reg_table.valid_flag); 4134 } 4135 4136 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 4137 SMU7_Discrete_MCRegisters *mc_reg_table) 4138 { 4139 struct ci_power_info *pi = ci_get_pi(rdev); 4140 u32 i; 4141 4142 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) 4143 ci_convert_mc_reg_table_entry_to_smc(rdev, 4144 pi->dpm_table.mclk_table.dpm_levels[i].value, 4145 &mc_reg_table->data[i]); 4146 } 4147 4148 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev) 4149 { 4150 struct ci_power_info *pi = ci_get_pi(rdev); 4151 int ret; 4152 4153 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); 4154 4155 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); 4156 if (ret) 4157 return ret; 4158 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); 4159 4160 return ci_copy_bytes_to_smc(rdev, 4161 pi->mc_reg_table_start, 4162 (u8 *)&pi->smc_mc_reg_table, 4163 sizeof(SMU7_Discrete_MCRegisters), 4164 pi->sram_end); 4165 } 4166 4167 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev) 4168 { 4169 struct ci_power_info *pi = ci_get_pi(rdev); 4170 4171 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) 4172 return 0; 4173 4174 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); 4175 4176 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); 4177 4178 return ci_copy_bytes_to_smc(rdev, 4179 pi->mc_reg_table_start + 4180 offsetof(SMU7_Discrete_MCRegisters, data[0]), 4181 (u8 *)&pi->smc_mc_reg_table.data[0], 4182 sizeof(SMU7_Discrete_MCRegisterSet) * 4183 pi->dpm_table.mclk_table.count, 4184 pi->sram_end); 4185 } 4186 4187 static void ci_enable_voltage_control(struct radeon_device *rdev) 4188 { 4189 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 4190 4191 tmp |= VOLT_PWRMGT_EN; 4192 WREG32_SMC(GENERAL_PWRMGT, tmp); 4193 } 4194 4195 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev, 4196 struct radeon_ps *radeon_state) 4197 { 4198 struct ci_ps *state = ci_get_ps(radeon_state); 4199 int i; 4200 u16 pcie_speed, max_speed = 0; 4201 4202 for (i = 0; i < state->performance_level_count; i++) { 4203 pcie_speed = state->performance_levels[i].pcie_gen; 4204 if (max_speed < pcie_speed) 4205 max_speed = pcie_speed; 4206 } 4207 4208 return max_speed; 4209 } 4210 4211 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev) 4212 { 4213 u32 speed_cntl = 0; 4214 4215 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 4216 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 4217 4218 return (u16)speed_cntl; 4219 } 4220 4221 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev) 4222 { 4223 u32 link_width = 0; 4224 4225 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; 4226 link_width >>= LC_LINK_WIDTH_RD_SHIFT; 4227 4228 switch (link_width) { 4229 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4230 return 1; 4231 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4232 return 2; 4233 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4234 return 4; 4235 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4236 return 8; 4237 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4238 /* not actually supported */ 4239 return 12; 4240 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4241 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4242 default: 4243 return 16; 4244 } 4245 } 4246 4247 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev, 4248 struct radeon_ps *radeon_new_state, 4249 struct radeon_ps *radeon_current_state) 4250 { 4251 struct ci_power_info *pi = ci_get_pi(rdev); 4252 enum radeon_pcie_gen target_link_speed = 4253 ci_get_maximum_link_speed(rdev, radeon_new_state); 4254 enum radeon_pcie_gen current_link_speed; 4255 4256 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 4257 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state); 4258 else 4259 current_link_speed = pi->force_pcie_gen; 4260 4261 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 4262 pi->pspp_notify_required = false; 4263 if (target_link_speed > current_link_speed) { 4264 switch (target_link_speed) { 4265 #ifdef CONFIG_ACPI 4266 case RADEON_PCIE_GEN3: 4267 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 4268 break; 4269 pi->force_pcie_gen = RADEON_PCIE_GEN2; 4270 if (current_link_speed == RADEON_PCIE_GEN2) 4271 break; 4272 case RADEON_PCIE_GEN2: 4273 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 4274 break; 4275 #endif 4276 default: 4277 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); 4278 break; 4279 } 4280 } else { 4281 if (target_link_speed < current_link_speed) 4282 pi->pspp_notify_required = true; 4283 } 4284 } 4285 4286 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 4287 struct radeon_ps *radeon_new_state, 4288 struct radeon_ps *radeon_current_state) 4289 { 4290 struct ci_power_info *pi = ci_get_pi(rdev); 4291 enum radeon_pcie_gen target_link_speed = 4292 ci_get_maximum_link_speed(rdev, radeon_new_state); 4293 u8 request; 4294 4295 if (pi->pspp_notify_required) { 4296 if (target_link_speed == RADEON_PCIE_GEN3) 4297 request = PCIE_PERF_REQ_PECI_GEN3; 4298 else if (target_link_speed == RADEON_PCIE_GEN2) 4299 request = PCIE_PERF_REQ_PECI_GEN2; 4300 else 4301 request = PCIE_PERF_REQ_PECI_GEN1; 4302 4303 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 4304 (ci_get_current_pcie_speed(rdev) > 0)) 4305 return; 4306 4307 #ifdef CONFIG_ACPI 4308 radeon_acpi_pcie_performance_request(rdev, request, false); 4309 #endif 4310 } 4311 } 4312 4313 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev) 4314 { 4315 struct ci_power_info *pi = ci_get_pi(rdev); 4316 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = 4317 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 4318 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table = 4319 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; 4320 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table = 4321 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; 4322 4323 if (allowed_sclk_vddc_table == NULL) 4324 return -EINVAL; 4325 if (allowed_sclk_vddc_table->count < 1) 4326 return -EINVAL; 4327 if (allowed_mclk_vddc_table == NULL) 4328 return -EINVAL; 4329 if (allowed_mclk_vddc_table->count < 1) 4330 return -EINVAL; 4331 if (allowed_mclk_vddci_table == NULL) 4332 return -EINVAL; 4333 if (allowed_mclk_vddci_table->count < 1) 4334 return -EINVAL; 4335 4336 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; 4337 pi->max_vddc_in_pp_table = 4338 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 4339 4340 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; 4341 pi->max_vddci_in_pp_table = 4342 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 4343 4344 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = 4345 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 4346 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = 4347 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 4348 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = 4349 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 4350 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = 4351 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 4352 4353 return 0; 4354 } 4355 4356 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc) 4357 { 4358 struct ci_power_info *pi = ci_get_pi(rdev); 4359 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; 4360 u32 leakage_index; 4361 4362 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { 4363 if (leakage_table->leakage_id[leakage_index] == *vddc) { 4364 *vddc = leakage_table->actual_voltage[leakage_index]; 4365 break; 4366 } 4367 } 4368 } 4369 4370 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci) 4371 { 4372 struct ci_power_info *pi = ci_get_pi(rdev); 4373 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; 4374 u32 leakage_index; 4375 4376 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { 4377 if (leakage_table->leakage_id[leakage_index] == *vddci) { 4378 *vddci = leakage_table->actual_voltage[leakage_index]; 4379 break; 4380 } 4381 } 4382 } 4383 4384 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4385 struct radeon_clock_voltage_dependency_table *table) 4386 { 4387 u32 i; 4388 4389 if (table) { 4390 for (i = 0; i < table->count; i++) 4391 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4392 } 4393 } 4394 4395 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev, 4396 struct radeon_clock_voltage_dependency_table *table) 4397 { 4398 u32 i; 4399 4400 if (table) { 4401 for (i = 0; i < table->count; i++) 4402 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); 4403 } 4404 } 4405 4406 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4407 struct radeon_vce_clock_voltage_dependency_table *table) 4408 { 4409 u32 i; 4410 4411 if (table) { 4412 for (i = 0; i < table->count; i++) 4413 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4414 } 4415 } 4416 4417 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4418 struct radeon_uvd_clock_voltage_dependency_table *table) 4419 { 4420 u32 i; 4421 4422 if (table) { 4423 for (i = 0; i < table->count; i++) 4424 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4425 } 4426 } 4427 4428 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev, 4429 struct radeon_phase_shedding_limits_table *table) 4430 { 4431 u32 i; 4432 4433 if (table) { 4434 for (i = 0; i < table->count; i++) 4435 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); 4436 } 4437 } 4438 4439 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev, 4440 struct radeon_clock_and_voltage_limits *table) 4441 { 4442 if (table) { 4443 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); 4444 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); 4445 } 4446 } 4447 4448 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev, 4449 struct radeon_cac_leakage_table *table) 4450 { 4451 u32 i; 4452 4453 if (table) { 4454 for (i = 0; i < table->count; i++) 4455 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); 4456 } 4457 } 4458 4459 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev) 4460 { 4461 4462 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4463 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 4464 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4465 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 4466 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4467 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); 4468 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev, 4469 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 4470 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4471 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); 4472 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4473 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); 4474 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4475 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); 4476 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 4477 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); 4478 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev, 4479 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); 4480 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, 4481 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); 4482 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, 4483 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); 4484 ci_patch_cac_leakage_table_with_vddc_leakage(rdev, 4485 &rdev->pm.dpm.dyn_state.cac_leakage_table); 4486 4487 } 4488 4489 static void ci_get_memory_type(struct radeon_device *rdev) 4490 { 4491 struct ci_power_info *pi = ci_get_pi(rdev); 4492 u32 tmp; 4493 4494 tmp = RREG32(MC_SEQ_MISC0); 4495 4496 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) == 4497 MC_SEQ_MISC0_GDDR5_VALUE) 4498 pi->mem_gddr5 = true; 4499 else 4500 pi->mem_gddr5 = false; 4501 4502 } 4503 4504 static void ci_update_current_ps(struct radeon_device *rdev, 4505 struct radeon_ps *rps) 4506 { 4507 struct ci_ps *new_ps = ci_get_ps(rps); 4508 struct ci_power_info *pi = ci_get_pi(rdev); 4509 4510 pi->current_rps = *rps; 4511 pi->current_ps = *new_ps; 4512 pi->current_rps.ps_priv = &pi->current_ps; 4513 } 4514 4515 static void ci_update_requested_ps(struct radeon_device *rdev, 4516 struct radeon_ps *rps) 4517 { 4518 struct ci_ps *new_ps = ci_get_ps(rps); 4519 struct ci_power_info *pi = ci_get_pi(rdev); 4520 4521 pi->requested_rps = *rps; 4522 pi->requested_ps = *new_ps; 4523 pi->requested_rps.ps_priv = &pi->requested_ps; 4524 } 4525 4526 int ci_dpm_pre_set_power_state(struct radeon_device *rdev) 4527 { 4528 struct ci_power_info *pi = ci_get_pi(rdev); 4529 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 4530 struct radeon_ps *new_ps = &requested_ps; 4531 4532 ci_update_requested_ps(rdev, new_ps); 4533 4534 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); 4535 4536 return 0; 4537 } 4538 4539 void ci_dpm_post_set_power_state(struct radeon_device *rdev) 4540 { 4541 struct ci_power_info *pi = ci_get_pi(rdev); 4542 struct radeon_ps *new_ps = &pi->requested_rps; 4543 4544 ci_update_current_ps(rdev, new_ps); 4545 } 4546 4547 4548 void ci_dpm_setup_asic(struct radeon_device *rdev) 4549 { 4550 int r; 4551 4552 r = ci_mc_load_microcode(rdev); 4553 if (r) 4554 DRM_ERROR("Failed to load MC firmware!\n"); 4555 ci_read_clock_registers(rdev); 4556 ci_get_memory_type(rdev); 4557 ci_enable_acpi_power_management(rdev); 4558 ci_init_sclk_t(rdev); 4559 } 4560 4561 int ci_dpm_enable(struct radeon_device *rdev) 4562 { 4563 struct ci_power_info *pi = ci_get_pi(rdev); 4564 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 4565 int ret; 4566 4567 if (ci_is_smc_running(rdev)) 4568 return -EINVAL; 4569 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 4570 ci_enable_voltage_control(rdev); 4571 ret = ci_construct_voltage_tables(rdev); 4572 if (ret) { 4573 DRM_ERROR("ci_construct_voltage_tables failed\n"); 4574 return ret; 4575 } 4576 } 4577 if (pi->caps_dynamic_ac_timing) { 4578 ret = ci_initialize_mc_reg_table(rdev); 4579 if (ret) 4580 pi->caps_dynamic_ac_timing = false; 4581 } 4582 if (pi->dynamic_ss) 4583 ci_enable_spread_spectrum(rdev, true); 4584 if (pi->thermal_protection) 4585 ci_enable_thermal_protection(rdev, true); 4586 ci_program_sstp(rdev); 4587 ci_enable_display_gap(rdev); 4588 ci_program_vc(rdev); 4589 ret = ci_upload_firmware(rdev); 4590 if (ret) { 4591 DRM_ERROR("ci_upload_firmware failed\n"); 4592 return ret; 4593 } 4594 ret = ci_process_firmware_header(rdev); 4595 if (ret) { 4596 DRM_ERROR("ci_process_firmware_header failed\n"); 4597 return ret; 4598 } 4599 ret = ci_initial_switch_from_arb_f0_to_f1(rdev); 4600 if (ret) { 4601 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n"); 4602 return ret; 4603 } 4604 ret = ci_init_smc_table(rdev); 4605 if (ret) { 4606 DRM_ERROR("ci_init_smc_table failed\n"); 4607 return ret; 4608 } 4609 ret = ci_init_arb_table_index(rdev); 4610 if (ret) { 4611 DRM_ERROR("ci_init_arb_table_index failed\n"); 4612 return ret; 4613 } 4614 if (pi->caps_dynamic_ac_timing) { 4615 ret = ci_populate_initial_mc_reg_table(rdev); 4616 if (ret) { 4617 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n"); 4618 return ret; 4619 } 4620 } 4621 ret = ci_populate_pm_base(rdev); 4622 if (ret) { 4623 DRM_ERROR("ci_populate_pm_base failed\n"); 4624 return ret; 4625 } 4626 ci_dpm_start_smc(rdev); 4627 ci_enable_vr_hot_gpio_interrupt(rdev); 4628 ret = ci_notify_smc_display_change(rdev, false); 4629 if (ret) { 4630 DRM_ERROR("ci_notify_smc_display_change failed\n"); 4631 return ret; 4632 } 4633 ci_enable_sclk_control(rdev, true); 4634 ret = ci_enable_ulv(rdev, true); 4635 if (ret) { 4636 DRM_ERROR("ci_enable_ulv failed\n"); 4637 return ret; 4638 } 4639 ret = ci_enable_ds_master_switch(rdev, true); 4640 if (ret) { 4641 DRM_ERROR("ci_enable_ds_master_switch failed\n"); 4642 return ret; 4643 } 4644 ret = ci_start_dpm(rdev); 4645 if (ret) { 4646 DRM_ERROR("ci_start_dpm failed\n"); 4647 return ret; 4648 } 4649 ret = ci_enable_didt(rdev, true); 4650 if (ret) { 4651 DRM_ERROR("ci_enable_didt failed\n"); 4652 return ret; 4653 } 4654 ret = ci_enable_smc_cac(rdev, true); 4655 if (ret) { 4656 DRM_ERROR("ci_enable_smc_cac failed\n"); 4657 return ret; 4658 } 4659 ret = ci_enable_power_containment(rdev, true); 4660 if (ret) { 4661 DRM_ERROR("ci_enable_power_containment failed\n"); 4662 return ret; 4663 } 4664 4665 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 4666 4667 ci_update_current_ps(rdev, boot_ps); 4668 4669 return 0; 4670 } 4671 4672 int ci_dpm_late_enable(struct radeon_device *rdev) 4673 { 4674 int ret; 4675 4676 if (rdev->irq.installed && 4677 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 4678 #if 0 4679 PPSMC_Result result; 4680 #endif 4681 ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 4682 if (ret) { 4683 DRM_ERROR("ci_set_thermal_temperature_range failed\n"); 4684 return ret; 4685 } 4686 rdev->irq.dpm_thermal = true; 4687 radeon_irq_set(rdev); 4688 #if 0 4689 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 4690 4691 if (result != PPSMC_Result_OK) 4692 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 4693 #endif 4694 } 4695 4696 ci_dpm_powergate_uvd(rdev, true); 4697 4698 return 0; 4699 } 4700 4701 void ci_dpm_disable(struct radeon_device *rdev) 4702 { 4703 struct ci_power_info *pi = ci_get_pi(rdev); 4704 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 4705 4706 ci_dpm_powergate_uvd(rdev, false); 4707 4708 if (!ci_is_smc_running(rdev)) 4709 return; 4710 4711 if (pi->thermal_protection) 4712 ci_enable_thermal_protection(rdev, false); 4713 ci_enable_power_containment(rdev, false); 4714 ci_enable_smc_cac(rdev, false); 4715 ci_enable_didt(rdev, false); 4716 ci_enable_spread_spectrum(rdev, false); 4717 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 4718 ci_stop_dpm(rdev); 4719 ci_enable_ds_master_switch(rdev, true); 4720 ci_enable_ulv(rdev, false); 4721 ci_clear_vc(rdev); 4722 ci_reset_to_default(rdev); 4723 ci_dpm_stop_smc(rdev); 4724 ci_force_switch_to_arb_f0(rdev); 4725 4726 ci_update_current_ps(rdev, boot_ps); 4727 } 4728 4729 int ci_dpm_set_power_state(struct radeon_device *rdev) 4730 { 4731 struct ci_power_info *pi = ci_get_pi(rdev); 4732 struct radeon_ps *new_ps = &pi->requested_rps; 4733 struct radeon_ps *old_ps = &pi->current_rps; 4734 int ret; 4735 4736 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps); 4737 if (pi->pcie_performance_request) 4738 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 4739 ret = ci_freeze_sclk_mclk_dpm(rdev); 4740 if (ret) { 4741 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n"); 4742 return ret; 4743 } 4744 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps); 4745 if (ret) { 4746 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n"); 4747 return ret; 4748 } 4749 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps); 4750 if (ret) { 4751 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n"); 4752 return ret; 4753 } 4754 4755 ret = ci_update_vce_dpm(rdev, new_ps, old_ps); 4756 if (ret) { 4757 DRM_ERROR("ci_update_vce_dpm failed\n"); 4758 return ret; 4759 } 4760 4761 ret = ci_update_sclk_t(rdev); 4762 if (ret) { 4763 DRM_ERROR("ci_update_sclk_t failed\n"); 4764 return ret; 4765 } 4766 if (pi->caps_dynamic_ac_timing) { 4767 ret = ci_update_and_upload_mc_reg_table(rdev); 4768 if (ret) { 4769 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n"); 4770 return ret; 4771 } 4772 } 4773 ret = ci_program_memory_timing_parameters(rdev); 4774 if (ret) { 4775 DRM_ERROR("ci_program_memory_timing_parameters failed\n"); 4776 return ret; 4777 } 4778 ret = ci_unfreeze_sclk_mclk_dpm(rdev); 4779 if (ret) { 4780 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n"); 4781 return ret; 4782 } 4783 ret = ci_upload_dpm_level_enable_mask(rdev); 4784 if (ret) { 4785 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n"); 4786 return ret; 4787 } 4788 if (pi->pcie_performance_request) 4789 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 4790 4791 return 0; 4792 } 4793 4794 static int __unused ci_dpm_power_control_set_level(struct radeon_device *rdev) 4795 { 4796 return ci_power_control_set_level(rdev); 4797 } 4798 4799 static void __unused ci_dpm_reset_asic(struct radeon_device *rdev) 4800 { 4801 ci_set_boot_state(rdev); 4802 } 4803 4804 void ci_dpm_display_configuration_changed(struct radeon_device *rdev) 4805 { 4806 ci_program_display_gap(rdev); 4807 } 4808 4809 union power_info { 4810 struct _ATOM_POWERPLAY_INFO info; 4811 struct _ATOM_POWERPLAY_INFO_V2 info_2; 4812 struct _ATOM_POWERPLAY_INFO_V3 info_3; 4813 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 4814 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 4815 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 4816 }; 4817 4818 union pplib_clock_info { 4819 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 4820 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 4821 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 4822 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 4823 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 4824 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 4825 }; 4826 4827 union pplib_power_state { 4828 struct _ATOM_PPLIB_STATE v1; 4829 struct _ATOM_PPLIB_STATE_V2 v2; 4830 }; 4831 4832 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev, 4833 struct radeon_ps *rps, 4834 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 4835 u8 table_rev) 4836 { 4837 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 4838 rps->class = le16_to_cpu(non_clock_info->usClassification); 4839 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 4840 4841 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 4842 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 4843 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 4844 } else { 4845 rps->vclk = 0; 4846 rps->dclk = 0; 4847 } 4848 4849 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 4850 rdev->pm.dpm.boot_ps = rps; 4851 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 4852 rdev->pm.dpm.uvd_ps = rps; 4853 } 4854 4855 static void ci_parse_pplib_clock_info(struct radeon_device *rdev, 4856 struct radeon_ps *rps, int index, 4857 union pplib_clock_info *clock_info) 4858 { 4859 struct ci_power_info *pi = ci_get_pi(rdev); 4860 struct ci_ps *ps = ci_get_ps(rps); 4861 struct ci_pl *pl = &ps->performance_levels[index]; 4862 4863 ps->performance_level_count = index + 1; 4864 4865 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 4866 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16; 4867 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 4868 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16; 4869 4870 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 4871 pi->sys_pcie_mask, 4872 pi->vbios_boot_state.pcie_gen_bootup_value, 4873 clock_info->ci.ucPCIEGen); 4874 pl->pcie_lane = r600_get_pcie_lane_support(rdev, 4875 pi->vbios_boot_state.pcie_lane_bootup_value, 4876 le16_to_cpu(clock_info->ci.usPCIELane)); 4877 4878 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 4879 pi->acpi_pcie_gen = pl->pcie_gen; 4880 } 4881 4882 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { 4883 pi->ulv.supported = true; 4884 pi->ulv.pl = *pl; 4885 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; 4886 } 4887 4888 /* patch up boot state */ 4889 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 4890 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; 4891 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; 4892 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; 4893 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; 4894 } 4895 4896 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 4897 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 4898 pi->use_pcie_powersaving_levels = true; 4899 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) 4900 pi->pcie_gen_powersaving.max = pl->pcie_gen; 4901 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) 4902 pi->pcie_gen_powersaving.min = pl->pcie_gen; 4903 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) 4904 pi->pcie_lane_powersaving.max = pl->pcie_lane; 4905 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) 4906 pi->pcie_lane_powersaving.min = pl->pcie_lane; 4907 break; 4908 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 4909 pi->use_pcie_performance_levels = true; 4910 if (pi->pcie_gen_performance.max < pl->pcie_gen) 4911 pi->pcie_gen_performance.max = pl->pcie_gen; 4912 if (pi->pcie_gen_performance.min > pl->pcie_gen) 4913 pi->pcie_gen_performance.min = pl->pcie_gen; 4914 if (pi->pcie_lane_performance.max < pl->pcie_lane) 4915 pi->pcie_lane_performance.max = pl->pcie_lane; 4916 if (pi->pcie_lane_performance.min > pl->pcie_lane) 4917 pi->pcie_lane_performance.min = pl->pcie_lane; 4918 break; 4919 default: 4920 break; 4921 } 4922 } 4923 4924 static int ci_parse_power_table(struct radeon_device *rdev) 4925 { 4926 struct radeon_mode_info *mode_info = &rdev->mode_info; 4927 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 4928 union pplib_power_state *power_state; 4929 int i, j, k, non_clock_array_index, clock_array_index; 4930 union pplib_clock_info *clock_info; 4931 struct _StateArray *state_array; 4932 struct _ClockInfoArray *clock_info_array; 4933 struct _NonClockInfoArray *non_clock_info_array; 4934 union power_info *power_info; 4935 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 4936 u16 data_offset; 4937 u8 frev, crev; 4938 u8 *power_state_offset; 4939 struct ci_ps *ps; 4940 4941 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 4942 &frev, &crev, &data_offset)) 4943 return -EINVAL; 4944 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 4945 4946 state_array = (struct _StateArray *) 4947 (mode_info->atom_context->bios + data_offset + 4948 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 4949 clock_info_array = (struct _ClockInfoArray *) 4950 (mode_info->atom_context->bios + data_offset + 4951 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 4952 non_clock_info_array = (struct _NonClockInfoArray *) 4953 (mode_info->atom_context->bios + data_offset + 4954 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 4955 4956 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 4957 state_array->ucNumEntries, GFP_KERNEL); 4958 if (!rdev->pm.dpm.ps) 4959 return -ENOMEM; 4960 power_state_offset = (u8 *)state_array->states; 4961 for (i = 0; i < state_array->ucNumEntries; i++) { 4962 u8 *idx; 4963 power_state = (union pplib_power_state *)power_state_offset; 4964 non_clock_array_index = power_state->v2.nonClockInfoIndex; 4965 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 4966 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 4967 if (!rdev->pm.power_state[i].clock_info) 4968 return -EINVAL; 4969 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL); 4970 if (ps == NULL) { 4971 kfree(rdev->pm.dpm.ps); 4972 return -ENOMEM; 4973 } 4974 rdev->pm.dpm.ps[i].ps_priv = ps; 4975 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 4976 non_clock_info, 4977 non_clock_info_array->ucEntrySize); 4978 k = 0; 4979 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 4980 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 4981 clock_array_index = idx[j]; 4982 if (clock_array_index >= clock_info_array->ucNumEntries) 4983 continue; 4984 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS) 4985 break; 4986 clock_info = (union pplib_clock_info *) 4987 ((u8 *)&clock_info_array->clockInfo[0] + 4988 (clock_array_index * clock_info_array->ucEntrySize)); 4989 ci_parse_pplib_clock_info(rdev, 4990 &rdev->pm.dpm.ps[i], k, 4991 clock_info); 4992 k++; 4993 } 4994 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 4995 } 4996 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 4997 4998 /* fill in the vce power states */ 4999 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 5000 u32 sclk, mclk; 5001 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 5002 clock_info = (union pplib_clock_info *) 5003 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 5004 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 5005 sclk |= clock_info->ci.ucEngineClockHigh << 16; 5006 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 5007 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 5008 rdev->pm.dpm.vce_states[i].sclk = sclk; 5009 rdev->pm.dpm.vce_states[i].mclk = mclk; 5010 } 5011 5012 return 0; 5013 } 5014 5015 static int ci_get_vbios_boot_values(struct radeon_device *rdev, 5016 struct ci_vbios_boot_state *boot_state) 5017 { 5018 struct radeon_mode_info *mode_info = &rdev->mode_info; 5019 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 5020 ATOM_FIRMWARE_INFO_V2_2 *firmware_info; 5021 u8 frev, crev; 5022 u16 data_offset; 5023 5024 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 5025 &frev, &crev, &data_offset)) { 5026 firmware_info = 5027 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios + 5028 data_offset); 5029 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage); 5030 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage); 5031 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage); 5032 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev); 5033 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev); 5034 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock); 5035 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock); 5036 5037 return 0; 5038 } 5039 return -EINVAL; 5040 } 5041 5042 void ci_dpm_fini(struct radeon_device *rdev) 5043 { 5044 int i; 5045 5046 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 5047 kfree(rdev->pm.dpm.ps[i].ps_priv); 5048 } 5049 kfree(rdev->pm.dpm.ps); 5050 kfree(rdev->pm.dpm.priv); 5051 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 5052 r600_free_extended_power_table(rdev); 5053 } 5054 5055 int ci_dpm_init(struct radeon_device *rdev) 5056 { 5057 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 5058 u16 data_offset, size; 5059 u8 frev, crev; 5060 struct ci_power_info *pi; 5061 int ret; 5062 u32 mask; 5063 5064 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); 5065 if (pi == NULL) 5066 return -ENOMEM; 5067 rdev->pm.dpm.priv = pi; 5068 5069 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 5070 if (ret) 5071 pi->sys_pcie_mask = 0; 5072 else 5073 pi->sys_pcie_mask = mask; 5074 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5075 5076 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; 5077 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; 5078 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; 5079 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; 5080 5081 pi->pcie_lane_performance.max = 0; 5082 pi->pcie_lane_performance.min = 16; 5083 pi->pcie_lane_powersaving.max = 0; 5084 pi->pcie_lane_powersaving.min = 16; 5085 5086 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); 5087 if (ret) { 5088 ci_dpm_fini(rdev); 5089 return ret; 5090 } 5091 5092 ret = r600_get_platform_caps(rdev); 5093 if (ret) { 5094 ci_dpm_fini(rdev); 5095 return ret; 5096 } 5097 5098 ret = r600_parse_extended_power_table(rdev); 5099 if (ret) { 5100 ci_dpm_fini(rdev); 5101 return ret; 5102 } 5103 5104 ret = ci_parse_power_table(rdev); 5105 if (ret) { 5106 ci_dpm_fini(rdev); 5107 return ret; 5108 } 5109 5110 pi->dll_default_on = false; 5111 pi->sram_end = SMC_RAM_END; 5112 5113 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; 5114 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; 5115 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; 5116 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; 5117 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; 5118 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; 5119 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; 5120 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; 5121 5122 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; 5123 5124 pi->sclk_dpm_key_disabled = 0; 5125 pi->mclk_dpm_key_disabled = 0; 5126 pi->pcie_dpm_key_disabled = 0; 5127 5128 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */ 5129 if ((rdev->pdev->device == 0x6658) && 5130 (rdev->mc_fw->datasize == (BONAIRE_MC_UCODE_SIZE * 4))) { 5131 pi->mclk_dpm_key_disabled = 1; 5132 } 5133 5134 pi->caps_sclk_ds = true; 5135 5136 pi->mclk_strobe_mode_threshold = 40000; 5137 pi->mclk_stutter_mode_threshold = 40000; 5138 pi->mclk_edc_enable_threshold = 40000; 5139 pi->mclk_edc_wr_enable_threshold = 40000; 5140 5141 ci_initialize_powertune_defaults(rdev); 5142 5143 pi->caps_fps = false; 5144 5145 pi->caps_sclk_throttle_low_notification = false; 5146 5147 pi->caps_uvd_dpm = true; 5148 pi->caps_vce_dpm = true; 5149 5150 ci_get_leakage_voltages(rdev); 5151 ci_patch_dependency_tables_with_leakage(rdev); 5152 ci_set_private_data_variables_based_on_pptable(rdev); 5153 5154 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 5155 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 5156 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 5157 ci_dpm_fini(rdev); 5158 return -ENOMEM; 5159 } 5160 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 5161 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 5162 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 5163 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 5164 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 5165 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 5166 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 5167 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 5168 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 5169 5170 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 5171 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 5172 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 5173 5174 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 5175 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 5176 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 5177 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 5178 5179 if (rdev->family == CHIP_HAWAII) { 5180 pi->thermal_temp_setting.temperature_low = 94500; 5181 pi->thermal_temp_setting.temperature_high = 95000; 5182 pi->thermal_temp_setting.temperature_shutdown = 104000; 5183 } else { 5184 pi->thermal_temp_setting.temperature_low = 99500; 5185 pi->thermal_temp_setting.temperature_high = 100000; 5186 pi->thermal_temp_setting.temperature_shutdown = 104000; 5187 } 5188 5189 pi->uvd_enabled = false; 5190 5191 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5192 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5193 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5194 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) 5195 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5196 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) 5197 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5198 5199 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { 5200 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 5201 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5202 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) 5203 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5204 else 5205 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; 5206 } 5207 5208 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { 5209 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) 5210 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5211 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) 5212 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5213 else 5214 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; 5215 } 5216 5217 pi->vddc_phase_shed_control = true; 5218 5219 #if defined(CONFIG_ACPI) 5220 pi->pcie_performance_request = 5221 radeon_acpi_is_pcie_performance_request_supported(rdev); 5222 #else 5223 pi->pcie_performance_request = false; 5224 #endif 5225 5226 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 5227 &frev, &crev, &data_offset)) { 5228 pi->caps_sclk_ss_support = true; 5229 pi->caps_mclk_ss_support = true; 5230 pi->dynamic_ss = true; 5231 } else { 5232 pi->caps_sclk_ss_support = false; 5233 pi->caps_mclk_ss_support = false; 5234 pi->dynamic_ss = true; 5235 } 5236 5237 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 5238 pi->thermal_protection = true; 5239 else 5240 pi->thermal_protection = false; 5241 5242 pi->caps_dynamic_ac_timing = true; 5243 5244 pi->uvd_power_gated = false; 5245 5246 /* make sure dc limits are valid */ 5247 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 5248 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 5249 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 5250 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 5251 5252 return 0; 5253 } 5254 5255 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 5256 struct seq_file *m) 5257 { 5258 struct ci_power_info *pi = ci_get_pi(rdev); 5259 struct radeon_ps *rps = &pi->current_rps; 5260 u32 sclk = ci_get_average_sclk_freq(rdev); 5261 u32 mclk = ci_get_average_mclk_freq(rdev); 5262 5263 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); 5264 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis"); 5265 seq_printf(m, "power level avg sclk: %u mclk: %u\n", 5266 sclk, mclk); 5267 } 5268 5269 void ci_dpm_print_power_state(struct radeon_device *rdev, 5270 struct radeon_ps *rps) 5271 { 5272 struct ci_ps *ps = ci_get_ps(rps); 5273 struct ci_pl *pl; 5274 int i; 5275 5276 r600_dpm_print_class_info(rps->class, rps->class2); 5277 r600_dpm_print_cap_info(rps->caps); 5278 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 5279 for (i = 0; i < ps->performance_level_count; i++) { 5280 pl = &ps->performance_levels[i]; 5281 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n", 5282 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane); 5283 } 5284 r600_dpm_print_ps_status(rdev, rps); 5285 } 5286 5287 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low) 5288 { 5289 struct ci_power_info *pi = ci_get_pi(rdev); 5290 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 5291 5292 if (low) 5293 return requested_state->performance_levels[0].sclk; 5294 else 5295 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 5296 } 5297 5298 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low) 5299 { 5300 struct ci_power_info *pi = ci_get_pi(rdev); 5301 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 5302 5303 if (low) 5304 return requested_state->performance_levels[0].mclk; 5305 else 5306 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 5307 } 5308