1926deccbSFrançois Tigeot /*
2926deccbSFrançois Tigeot * Copyright 2008 Advanced Micro Devices, Inc.
3926deccbSFrançois Tigeot * Copyright 2008 Red Hat Inc.
4926deccbSFrançois Tigeot * Copyright 2009 Jerome Glisse.
5926deccbSFrançois Tigeot *
6926deccbSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a
7926deccbSFrançois Tigeot * copy of this software and associated documentation files (the "Software"),
8926deccbSFrançois Tigeot * to deal in the Software without restriction, including without limitation
9926deccbSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10926deccbSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the
11926deccbSFrançois Tigeot * Software is furnished to do so, subject to the following conditions:
12926deccbSFrançois Tigeot *
13926deccbSFrançois Tigeot * The above copyright notice and this permission notice shall be included in
14926deccbSFrançois Tigeot * all copies or substantial portions of the Software.
15926deccbSFrançois Tigeot *
16926deccbSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17926deccbSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18926deccbSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19926deccbSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20926deccbSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21926deccbSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22926deccbSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE.
23926deccbSFrançois Tigeot *
24926deccbSFrançois Tigeot * Authors: Dave Airlie
25926deccbSFrançois Tigeot * Alex Deucher
26926deccbSFrançois Tigeot * Jerome Glisse
27926deccbSFrançois Tigeot */
28*a85cb24fSFrançois Tigeot #include <linux/seq_file.h>
29*a85cb24fSFrançois Tigeot #include <linux/slab.h>
30926deccbSFrançois Tigeot #include <drm/drmP.h>
31926deccbSFrançois Tigeot #include "radeon_reg.h"
32926deccbSFrançois Tigeot #include "radeon.h"
33926deccbSFrançois Tigeot #include "radeon_asic.h"
34926deccbSFrançois Tigeot #include "atom.h"
35926deccbSFrançois Tigeot #include "r100d.h"
36926deccbSFrançois Tigeot #include "r420d.h"
37926deccbSFrançois Tigeot #include "r420_reg_safe.h"
38926deccbSFrançois Tigeot
r420_pm_init_profile(struct radeon_device * rdev)39926deccbSFrançois Tigeot void r420_pm_init_profile(struct radeon_device *rdev)
40926deccbSFrançois Tigeot {
41926deccbSFrançois Tigeot /* default */
42926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
43926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
44926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
45926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
46926deccbSFrançois Tigeot /* low sh */
47926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
48926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
49926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
50926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
51926deccbSFrançois Tigeot /* mid sh */
52926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
53926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
54926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
55926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
56926deccbSFrançois Tigeot /* high sh */
57926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
58926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
59926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
60926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
61926deccbSFrançois Tigeot /* low mh */
62926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
63926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
64926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
65926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
66926deccbSFrançois Tigeot /* mid mh */
67926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
68926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
69926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
70926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
71926deccbSFrançois Tigeot /* high mh */
72926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
73926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
74926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
75926deccbSFrançois Tigeot rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
76926deccbSFrançois Tigeot }
77926deccbSFrançois Tigeot
r420_set_reg_safe(struct radeon_device * rdev)78926deccbSFrançois Tigeot static void r420_set_reg_safe(struct radeon_device *rdev)
79926deccbSFrançois Tigeot {
80926deccbSFrançois Tigeot rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
81c4ef309bSzrj rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
82926deccbSFrançois Tigeot }
83926deccbSFrançois Tigeot
r420_pipes_init(struct radeon_device * rdev)84926deccbSFrançois Tigeot void r420_pipes_init(struct radeon_device *rdev)
85926deccbSFrançois Tigeot {
86926deccbSFrançois Tigeot unsigned tmp;
87926deccbSFrançois Tigeot unsigned gb_pipe_select;
88926deccbSFrançois Tigeot unsigned num_pipes;
89926deccbSFrançois Tigeot
90926deccbSFrançois Tigeot /* GA_ENHANCE workaround TCL deadlock issue */
91926deccbSFrançois Tigeot WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
92926deccbSFrançois Tigeot (1 << 2) | (1 << 3));
93926deccbSFrançois Tigeot /* add idle wait as per freedesktop.org bug 24041 */
94926deccbSFrançois Tigeot if (r100_gui_wait_for_idle(rdev)) {
95*a85cb24fSFrançois Tigeot pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
96926deccbSFrançois Tigeot }
97926deccbSFrançois Tigeot /* get max number of pipes */
98926deccbSFrançois Tigeot gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
99926deccbSFrançois Tigeot num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
100926deccbSFrançois Tigeot
101926deccbSFrançois Tigeot /* SE chips have 1 pipe */
102c6f73aabSFrançois Tigeot if ((rdev->pdev->device == 0x5e4c) ||
103c6f73aabSFrançois Tigeot (rdev->pdev->device == 0x5e4f))
104926deccbSFrançois Tigeot num_pipes = 1;
105926deccbSFrançois Tigeot
106926deccbSFrançois Tigeot rdev->num_gb_pipes = num_pipes;
107926deccbSFrançois Tigeot tmp = 0;
108926deccbSFrançois Tigeot switch (num_pipes) {
109926deccbSFrançois Tigeot default:
110926deccbSFrançois Tigeot /* force to 1 pipe */
111926deccbSFrançois Tigeot num_pipes = 1;
112926deccbSFrançois Tigeot case 1:
113926deccbSFrançois Tigeot tmp = (0 << 1);
114926deccbSFrançois Tigeot break;
115926deccbSFrançois Tigeot case 2:
116926deccbSFrançois Tigeot tmp = (3 << 1);
117926deccbSFrançois Tigeot break;
118926deccbSFrançois Tigeot case 3:
119926deccbSFrançois Tigeot tmp = (6 << 1);
120926deccbSFrançois Tigeot break;
121926deccbSFrançois Tigeot case 4:
122926deccbSFrançois Tigeot tmp = (7 << 1);
123926deccbSFrançois Tigeot break;
124926deccbSFrançois Tigeot }
125926deccbSFrançois Tigeot WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
126926deccbSFrançois Tigeot /* Sub pixel 1/12 so we can have 4K rendering according to doc */
127926deccbSFrançois Tigeot tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
128926deccbSFrançois Tigeot WREG32(R300_GB_TILE_CONFIG, tmp);
129926deccbSFrançois Tigeot if (r100_gui_wait_for_idle(rdev)) {
130*a85cb24fSFrançois Tigeot pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
131926deccbSFrançois Tigeot }
132926deccbSFrançois Tigeot
133926deccbSFrançois Tigeot tmp = RREG32(R300_DST_PIPE_CONFIG);
134926deccbSFrançois Tigeot WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
135926deccbSFrançois Tigeot
136926deccbSFrançois Tigeot WREG32(R300_RB2D_DSTCACHE_MODE,
137926deccbSFrançois Tigeot RREG32(R300_RB2D_DSTCACHE_MODE) |
138926deccbSFrançois Tigeot R300_DC_AUTOFLUSH_ENABLE |
139926deccbSFrançois Tigeot R300_DC_DC_DISABLE_IGNORE_PE);
140926deccbSFrançois Tigeot
141926deccbSFrançois Tigeot if (r100_gui_wait_for_idle(rdev)) {
142*a85cb24fSFrançois Tigeot pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
143926deccbSFrançois Tigeot }
144926deccbSFrançois Tigeot
145926deccbSFrançois Tigeot if (rdev->family == CHIP_RV530) {
146926deccbSFrançois Tigeot tmp = RREG32(RV530_GB_PIPE_SELECT2);
147926deccbSFrançois Tigeot if ((tmp & 3) == 3)
148926deccbSFrançois Tigeot rdev->num_z_pipes = 2;
149926deccbSFrançois Tigeot else
150926deccbSFrançois Tigeot rdev->num_z_pipes = 1;
151926deccbSFrançois Tigeot } else
152926deccbSFrançois Tigeot rdev->num_z_pipes = 1;
153926deccbSFrançois Tigeot
154926deccbSFrançois Tigeot DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
155926deccbSFrançois Tigeot rdev->num_gb_pipes, rdev->num_z_pipes);
156926deccbSFrançois Tigeot }
157926deccbSFrançois Tigeot
r420_mc_rreg(struct radeon_device * rdev,u32 reg)158926deccbSFrançois Tigeot u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
159926deccbSFrançois Tigeot {
160*a85cb24fSFrançois Tigeot unsigned long flags;
161926deccbSFrançois Tigeot u32 r;
162926deccbSFrançois Tigeot
163*a85cb24fSFrançois Tigeot spin_lock_irqsave(&rdev->mc_idx_lock, flags);
164926deccbSFrançois Tigeot WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
165926deccbSFrançois Tigeot r = RREG32(R_0001FC_MC_IND_DATA);
166*a85cb24fSFrançois Tigeot spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
167926deccbSFrançois Tigeot return r;
168926deccbSFrançois Tigeot }
169926deccbSFrançois Tigeot
r420_mc_wreg(struct radeon_device * rdev,u32 reg,u32 v)170926deccbSFrançois Tigeot void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
171926deccbSFrançois Tigeot {
172*a85cb24fSFrançois Tigeot unsigned long flags;
173*a85cb24fSFrançois Tigeot
174*a85cb24fSFrançois Tigeot spin_lock_irqsave(&rdev->mc_idx_lock, flags);
175926deccbSFrançois Tigeot WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
176926deccbSFrançois Tigeot S_0001F8_MC_IND_WR_EN(1));
177926deccbSFrançois Tigeot WREG32(R_0001FC_MC_IND_DATA, v);
178*a85cb24fSFrançois Tigeot spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
179926deccbSFrançois Tigeot }
180926deccbSFrançois Tigeot
r420_debugfs(struct radeon_device * rdev)181926deccbSFrançois Tigeot static void r420_debugfs(struct radeon_device *rdev)
182926deccbSFrançois Tigeot {
183926deccbSFrançois Tigeot if (r100_debugfs_rbbm_init(rdev)) {
184926deccbSFrançois Tigeot DRM_ERROR("Failed to register debugfs file for RBBM !\n");
185926deccbSFrançois Tigeot }
186926deccbSFrançois Tigeot if (r420_debugfs_pipes_info_init(rdev)) {
187926deccbSFrançois Tigeot DRM_ERROR("Failed to register debugfs file for pipes !\n");
188926deccbSFrançois Tigeot }
189926deccbSFrançois Tigeot }
190926deccbSFrançois Tigeot
r420_clock_resume(struct radeon_device * rdev)191926deccbSFrançois Tigeot static void r420_clock_resume(struct radeon_device *rdev)
192926deccbSFrançois Tigeot {
193926deccbSFrançois Tigeot u32 sclk_cntl;
194926deccbSFrançois Tigeot
195926deccbSFrançois Tigeot if (radeon_dynclks != -1 && radeon_dynclks)
196926deccbSFrançois Tigeot radeon_atom_set_clock_gating(rdev, 1);
197926deccbSFrançois Tigeot sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
198926deccbSFrançois Tigeot sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
199926deccbSFrançois Tigeot if (rdev->family == CHIP_R420)
200926deccbSFrançois Tigeot sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
201926deccbSFrançois Tigeot WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
202926deccbSFrançois Tigeot }
203926deccbSFrançois Tigeot
r420_cp_errata_init(struct radeon_device * rdev)204926deccbSFrançois Tigeot static void r420_cp_errata_init(struct radeon_device *rdev)
205926deccbSFrançois Tigeot {
206*a85cb24fSFrançois Tigeot int r;
207926deccbSFrançois Tigeot struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
208926deccbSFrançois Tigeot
209926deccbSFrançois Tigeot /* RV410 and R420 can lock up if CP DMA to host memory happens
210926deccbSFrançois Tigeot * while the 2D engine is busy.
211926deccbSFrançois Tigeot *
212926deccbSFrançois Tigeot * The proper workaround is to queue a RESYNC at the beginning
213926deccbSFrançois Tigeot * of the CP init, apparently.
214926deccbSFrançois Tigeot */
215926deccbSFrançois Tigeot radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
216*a85cb24fSFrançois Tigeot r = radeon_ring_lock(rdev, ring, 8);
217*a85cb24fSFrançois Tigeot WARN_ON(r);
218926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
219926deccbSFrançois Tigeot radeon_ring_write(ring, rdev->config.r300.resync_scratch);
220926deccbSFrançois Tigeot radeon_ring_write(ring, 0xDEADBEEF);
221c6f73aabSFrançois Tigeot radeon_ring_unlock_commit(rdev, ring, false);
222926deccbSFrançois Tigeot }
223926deccbSFrançois Tigeot
r420_cp_errata_fini(struct radeon_device * rdev)224926deccbSFrançois Tigeot static void r420_cp_errata_fini(struct radeon_device *rdev)
225926deccbSFrançois Tigeot {
226*a85cb24fSFrançois Tigeot int r;
227926deccbSFrançois Tigeot struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
228926deccbSFrançois Tigeot
229926deccbSFrançois Tigeot /* Catch the RESYNC we dispatched all the way back,
230926deccbSFrançois Tigeot * at the very beginning of the CP init.
231926deccbSFrançois Tigeot */
232*a85cb24fSFrançois Tigeot r = radeon_ring_lock(rdev, ring, 8);
233*a85cb24fSFrançois Tigeot WARN_ON(r);
234926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
235926deccbSFrançois Tigeot radeon_ring_write(ring, R300_RB3D_DC_FINISH);
236c6f73aabSFrançois Tigeot radeon_ring_unlock_commit(rdev, ring, false);
237926deccbSFrançois Tigeot radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
238926deccbSFrançois Tigeot }
239926deccbSFrançois Tigeot
r420_startup(struct radeon_device * rdev)240926deccbSFrançois Tigeot static int r420_startup(struct radeon_device *rdev)
241926deccbSFrançois Tigeot {
242926deccbSFrançois Tigeot int r;
243926deccbSFrançois Tigeot
244926deccbSFrançois Tigeot /* set common regs */
245926deccbSFrançois Tigeot r100_set_common_regs(rdev);
246926deccbSFrançois Tigeot /* program mc */
247926deccbSFrançois Tigeot r300_mc_program(rdev);
248926deccbSFrançois Tigeot /* Resume clock */
249926deccbSFrançois Tigeot r420_clock_resume(rdev);
250926deccbSFrançois Tigeot /* Initialize GART (initialize after TTM so we can allocate
251926deccbSFrançois Tigeot * memory through TTM but finalize after TTM) */
252926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCIE) {
253926deccbSFrançois Tigeot r = rv370_pcie_gart_enable(rdev);
254926deccbSFrançois Tigeot if (r)
255926deccbSFrançois Tigeot return r;
256926deccbSFrançois Tigeot }
257926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCI) {
258926deccbSFrançois Tigeot r = r100_pci_gart_enable(rdev);
259926deccbSFrançois Tigeot if (r)
260926deccbSFrançois Tigeot return r;
261926deccbSFrançois Tigeot }
262926deccbSFrançois Tigeot r420_pipes_init(rdev);
263926deccbSFrançois Tigeot
264926deccbSFrançois Tigeot /* allocate wb buffer */
265926deccbSFrançois Tigeot r = radeon_wb_init(rdev);
266926deccbSFrançois Tigeot if (r)
267926deccbSFrançois Tigeot return r;
268926deccbSFrançois Tigeot
269926deccbSFrançois Tigeot r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
270926deccbSFrançois Tigeot if (r) {
271926deccbSFrançois Tigeot dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
272926deccbSFrançois Tigeot return r;
273926deccbSFrançois Tigeot }
274926deccbSFrançois Tigeot
275926deccbSFrançois Tigeot /* Enable IRQ */
276f43cf1b1SMichael Neumann if (!rdev->irq.installed) {
277f43cf1b1SMichael Neumann r = radeon_irq_kms_init(rdev);
278f43cf1b1SMichael Neumann if (r)
279f43cf1b1SMichael Neumann return r;
280f43cf1b1SMichael Neumann }
281f43cf1b1SMichael Neumann
282926deccbSFrançois Tigeot r100_irq_set(rdev);
283926deccbSFrançois Tigeot rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
284926deccbSFrançois Tigeot /* 1M ring buffer */
285926deccbSFrançois Tigeot r = r100_cp_init(rdev, 1024 * 1024);
286926deccbSFrançois Tigeot if (r) {
287926deccbSFrançois Tigeot dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
288926deccbSFrançois Tigeot return r;
289926deccbSFrançois Tigeot }
290926deccbSFrançois Tigeot r420_cp_errata_init(rdev);
291926deccbSFrançois Tigeot
292926deccbSFrançois Tigeot r = radeon_ib_pool_init(rdev);
293926deccbSFrançois Tigeot if (r) {
294926deccbSFrançois Tigeot dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
295926deccbSFrançois Tigeot return r;
296926deccbSFrançois Tigeot }
297926deccbSFrançois Tigeot
298926deccbSFrançois Tigeot return 0;
299926deccbSFrançois Tigeot }
300926deccbSFrançois Tigeot
r420_resume(struct radeon_device * rdev)301926deccbSFrançois Tigeot int r420_resume(struct radeon_device *rdev)
302926deccbSFrançois Tigeot {
303926deccbSFrançois Tigeot int r;
304926deccbSFrançois Tigeot
305926deccbSFrançois Tigeot /* Make sur GART are not working */
306926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCIE)
307926deccbSFrançois Tigeot rv370_pcie_gart_disable(rdev);
308926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCI)
309926deccbSFrançois Tigeot r100_pci_gart_disable(rdev);
310926deccbSFrançois Tigeot /* Resume clock before doing reset */
311926deccbSFrançois Tigeot r420_clock_resume(rdev);
312926deccbSFrançois Tigeot /* Reset gpu before posting otherwise ATOM will enter infinite loop */
313926deccbSFrançois Tigeot if (radeon_asic_reset(rdev)) {
314926deccbSFrançois Tigeot dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
315926deccbSFrançois Tigeot RREG32(R_000E40_RBBM_STATUS),
316926deccbSFrançois Tigeot RREG32(R_0007C0_CP_STAT));
317926deccbSFrançois Tigeot }
318926deccbSFrançois Tigeot /* check if cards are posted or not */
319926deccbSFrançois Tigeot if (rdev->is_atom_bios) {
320926deccbSFrançois Tigeot atom_asic_init(rdev->mode_info.atom_context);
321926deccbSFrançois Tigeot } else {
322926deccbSFrançois Tigeot radeon_combios_asic_init(rdev->ddev);
323926deccbSFrançois Tigeot }
324926deccbSFrançois Tigeot /* Resume clock after posting */
325926deccbSFrançois Tigeot r420_clock_resume(rdev);
326926deccbSFrançois Tigeot /* Initialize surface registers */
327926deccbSFrançois Tigeot radeon_surface_init(rdev);
328926deccbSFrançois Tigeot
329926deccbSFrançois Tigeot rdev->accel_working = true;
330926deccbSFrançois Tigeot r = r420_startup(rdev);
331926deccbSFrançois Tigeot if (r) {
332926deccbSFrançois Tigeot rdev->accel_working = false;
333926deccbSFrançois Tigeot }
334926deccbSFrançois Tigeot return r;
335926deccbSFrançois Tigeot }
336926deccbSFrançois Tigeot
r420_suspend(struct radeon_device * rdev)337926deccbSFrançois Tigeot int r420_suspend(struct radeon_device *rdev)
338926deccbSFrançois Tigeot {
339c6f73aabSFrançois Tigeot radeon_pm_suspend(rdev);
340926deccbSFrançois Tigeot r420_cp_errata_fini(rdev);
341926deccbSFrançois Tigeot r100_cp_disable(rdev);
342926deccbSFrançois Tigeot radeon_wb_disable(rdev);
343926deccbSFrançois Tigeot r100_irq_disable(rdev);
344926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCIE)
345926deccbSFrançois Tigeot rv370_pcie_gart_disable(rdev);
346926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCI)
347926deccbSFrançois Tigeot r100_pci_gart_disable(rdev);
348926deccbSFrançois Tigeot return 0;
349926deccbSFrançois Tigeot }
350926deccbSFrançois Tigeot
r420_fini(struct radeon_device * rdev)351926deccbSFrançois Tigeot void r420_fini(struct radeon_device *rdev)
352926deccbSFrançois Tigeot {
353c6f73aabSFrançois Tigeot radeon_pm_fini(rdev);
354926deccbSFrançois Tigeot r100_cp_fini(rdev);
355926deccbSFrançois Tigeot radeon_wb_fini(rdev);
356926deccbSFrançois Tigeot radeon_ib_pool_fini(rdev);
357926deccbSFrançois Tigeot radeon_gem_fini(rdev);
358926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCIE)
359926deccbSFrançois Tigeot rv370_pcie_gart_fini(rdev);
360926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCI)
361926deccbSFrançois Tigeot r100_pci_gart_fini(rdev);
362926deccbSFrançois Tigeot radeon_agp_fini(rdev);
363926deccbSFrançois Tigeot radeon_irq_kms_fini(rdev);
364926deccbSFrançois Tigeot radeon_fence_driver_fini(rdev);
365926deccbSFrançois Tigeot radeon_bo_fini(rdev);
366926deccbSFrançois Tigeot if (rdev->is_atom_bios) {
367926deccbSFrançois Tigeot radeon_atombios_fini(rdev);
368926deccbSFrançois Tigeot } else {
369926deccbSFrançois Tigeot radeon_combios_fini(rdev);
370926deccbSFrançois Tigeot }
371c4ef309bSzrj kfree(rdev->bios);
372926deccbSFrançois Tigeot rdev->bios = NULL;
373926deccbSFrançois Tigeot }
374926deccbSFrançois Tigeot
r420_init(struct radeon_device * rdev)375926deccbSFrançois Tigeot int r420_init(struct radeon_device *rdev)
376926deccbSFrançois Tigeot {
377926deccbSFrançois Tigeot int r;
378926deccbSFrançois Tigeot
379926deccbSFrançois Tigeot /* Initialize scratch registers */
380926deccbSFrançois Tigeot radeon_scratch_init(rdev);
381926deccbSFrançois Tigeot /* Initialize surface registers */
382926deccbSFrançois Tigeot radeon_surface_init(rdev);
383926deccbSFrançois Tigeot /* TODO: disable VGA need to use VGA request */
384926deccbSFrançois Tigeot /* restore some register to sane defaults */
385926deccbSFrançois Tigeot r100_restore_sanity(rdev);
386926deccbSFrançois Tigeot /* BIOS*/
387926deccbSFrançois Tigeot if (!radeon_get_bios(rdev)) {
388926deccbSFrançois Tigeot if (ASIC_IS_AVIVO(rdev))
389926deccbSFrançois Tigeot return -EINVAL;
390926deccbSFrançois Tigeot }
391926deccbSFrançois Tigeot if (rdev->is_atom_bios) {
392926deccbSFrançois Tigeot r = radeon_atombios_init(rdev);
393926deccbSFrançois Tigeot if (r) {
394926deccbSFrançois Tigeot return r;
395926deccbSFrançois Tigeot }
396926deccbSFrançois Tigeot } else {
397926deccbSFrançois Tigeot r = radeon_combios_init(rdev);
398926deccbSFrançois Tigeot if (r) {
399926deccbSFrançois Tigeot return r;
400926deccbSFrançois Tigeot }
401926deccbSFrançois Tigeot }
402926deccbSFrançois Tigeot /* Reset gpu before posting otherwise ATOM will enter infinite loop */
403926deccbSFrançois Tigeot if (radeon_asic_reset(rdev)) {
404926deccbSFrançois Tigeot dev_warn(rdev->dev,
405926deccbSFrançois Tigeot "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
406926deccbSFrançois Tigeot RREG32(R_000E40_RBBM_STATUS),
407926deccbSFrançois Tigeot RREG32(R_0007C0_CP_STAT));
408926deccbSFrançois Tigeot }
409926deccbSFrançois Tigeot /* check if cards are posted or not */
410926deccbSFrançois Tigeot if (radeon_boot_test_post_card(rdev) == false)
411926deccbSFrançois Tigeot return -EINVAL;
412926deccbSFrançois Tigeot
413926deccbSFrançois Tigeot /* Initialize clocks */
414926deccbSFrançois Tigeot radeon_get_clock_info(rdev->ddev);
415926deccbSFrançois Tigeot /* initialize AGP */
416926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) {
417926deccbSFrançois Tigeot r = radeon_agp_init(rdev);
418926deccbSFrançois Tigeot if (r) {
419926deccbSFrançois Tigeot radeon_agp_disable(rdev);
420926deccbSFrançois Tigeot }
421926deccbSFrançois Tigeot }
422926deccbSFrançois Tigeot /* initialize memory controller */
423926deccbSFrançois Tigeot r300_mc_init(rdev);
424926deccbSFrançois Tigeot r420_debugfs(rdev);
425926deccbSFrançois Tigeot /* Fence driver */
426926deccbSFrançois Tigeot r = radeon_fence_driver_init(rdev);
427926deccbSFrançois Tigeot if (r) {
428926deccbSFrançois Tigeot return r;
429926deccbSFrançois Tigeot }
430926deccbSFrançois Tigeot /* Memory manager */
431926deccbSFrançois Tigeot r = radeon_bo_init(rdev);
432926deccbSFrançois Tigeot if (r) {
433926deccbSFrançois Tigeot return r;
434926deccbSFrançois Tigeot }
435926deccbSFrançois Tigeot if (rdev->family == CHIP_R420)
436926deccbSFrançois Tigeot r100_enable_bm(rdev);
437926deccbSFrançois Tigeot
438926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCIE) {
439926deccbSFrançois Tigeot r = rv370_pcie_gart_init(rdev);
440926deccbSFrançois Tigeot if (r)
441926deccbSFrançois Tigeot return r;
442926deccbSFrançois Tigeot }
443926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCI) {
444926deccbSFrançois Tigeot r = r100_pci_gart_init(rdev);
445926deccbSFrançois Tigeot if (r)
446926deccbSFrançois Tigeot return r;
447926deccbSFrançois Tigeot }
448926deccbSFrançois Tigeot r420_set_reg_safe(rdev);
449926deccbSFrançois Tigeot
450c6f73aabSFrançois Tigeot /* Initialize power management */
451c6f73aabSFrançois Tigeot radeon_pm_init(rdev);
452c6f73aabSFrançois Tigeot
453926deccbSFrançois Tigeot rdev->accel_working = true;
454926deccbSFrançois Tigeot r = r420_startup(rdev);
455926deccbSFrançois Tigeot if (r) {
456926deccbSFrançois Tigeot /* Somethings want wront with the accel init stop accel */
457926deccbSFrançois Tigeot dev_err(rdev->dev, "Disabling GPU acceleration\n");
458926deccbSFrançois Tigeot r100_cp_fini(rdev);
459926deccbSFrançois Tigeot radeon_wb_fini(rdev);
460926deccbSFrançois Tigeot radeon_ib_pool_fini(rdev);
461926deccbSFrançois Tigeot radeon_irq_kms_fini(rdev);
462926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCIE)
463926deccbSFrançois Tigeot rv370_pcie_gart_fini(rdev);
464926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCI)
465926deccbSFrançois Tigeot r100_pci_gart_fini(rdev);
466926deccbSFrançois Tigeot radeon_agp_fini(rdev);
467926deccbSFrançois Tigeot rdev->accel_working = false;
468926deccbSFrançois Tigeot }
469926deccbSFrançois Tigeot return 0;
470926deccbSFrançois Tigeot }
471926deccbSFrançois Tigeot
472926deccbSFrançois Tigeot /*
473926deccbSFrançois Tigeot * Debugfs info
474926deccbSFrançois Tigeot */
475926deccbSFrançois Tigeot #if defined(CONFIG_DEBUG_FS)
r420_debugfs_pipes_info(struct seq_file * m,void * data)476926deccbSFrançois Tigeot static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
477926deccbSFrançois Tigeot {
478926deccbSFrançois Tigeot struct drm_info_node *node = (struct drm_info_node *) m->private;
479926deccbSFrançois Tigeot struct drm_device *dev = node->minor->dev;
480926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
481926deccbSFrançois Tigeot uint32_t tmp;
482926deccbSFrançois Tigeot
483926deccbSFrançois Tigeot tmp = RREG32(R400_GB_PIPE_SELECT);
484926deccbSFrançois Tigeot seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
485926deccbSFrançois Tigeot tmp = RREG32(R300_GB_TILE_CONFIG);
486926deccbSFrançois Tigeot seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
487926deccbSFrançois Tigeot tmp = RREG32(R300_DST_PIPE_CONFIG);
488926deccbSFrançois Tigeot seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
489926deccbSFrançois Tigeot return 0;
490926deccbSFrançois Tigeot }
491926deccbSFrançois Tigeot
492926deccbSFrançois Tigeot static struct drm_info_list r420_pipes_info_list[] = {
493926deccbSFrançois Tigeot {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
494926deccbSFrançois Tigeot };
495926deccbSFrançois Tigeot #endif
496926deccbSFrançois Tigeot
r420_debugfs_pipes_info_init(struct radeon_device * rdev)497926deccbSFrançois Tigeot int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
498926deccbSFrançois Tigeot {
499926deccbSFrançois Tigeot #if defined(CONFIG_DEBUG_FS)
500926deccbSFrançois Tigeot return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
501926deccbSFrançois Tigeot #else
502926deccbSFrançois Tigeot return 0;
503926deccbSFrançois Tigeot #endif
504926deccbSFrançois Tigeot }
505