1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/firmware.h> 30 #include <linux/module.h> 31 #include <drm/drmP.h> 32 #include <drm/radeon_drm.h> 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "radeon_audio.h" 36 #include "radeon_mode.h" 37 #include "r600d.h" 38 #include "atom.h" 39 #include "avivod.h" 40 #include "radeon_ucode.h" 41 42 /* Firmware Names */ 43 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 44 MODULE_FIRMWARE("radeon/R600_me.bin"); 45 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 46 MODULE_FIRMWARE("radeon/RV610_me.bin"); 47 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 48 MODULE_FIRMWARE("radeon/RV630_me.bin"); 49 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 50 MODULE_FIRMWARE("radeon/RV620_me.bin"); 51 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 52 MODULE_FIRMWARE("radeon/RV635_me.bin"); 53 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 54 MODULE_FIRMWARE("radeon/RV670_me.bin"); 55 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 56 MODULE_FIRMWARE("radeon/RS780_me.bin"); 57 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 58 MODULE_FIRMWARE("radeon/RV770_me.bin"); 59 MODULE_FIRMWARE("radeon/RV770_smc.bin"); 60 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 61 MODULE_FIRMWARE("radeon/RV730_me.bin"); 62 MODULE_FIRMWARE("radeon/RV730_smc.bin"); 63 MODULE_FIRMWARE("radeon/RV740_smc.bin"); 64 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 65 MODULE_FIRMWARE("radeon/RV710_me.bin"); 66 MODULE_FIRMWARE("radeon/RV710_smc.bin"); 67 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 68 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 69 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 70 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 71 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 72 MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); 73 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 74 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 75 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 76 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); 77 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 78 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 79 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 80 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); 81 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 82 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 83 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 84 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); 85 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 86 MODULE_FIRMWARE("radeon/PALM_me.bin"); 87 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 88 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 89 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 90 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 91 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 92 93 static const u32 crtc_offsets[2] = 94 { 95 0, 96 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 97 }; 98 99 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 100 101 /* r600,rv610,rv630,rv620,rv635,rv670 */ 102 static void r600_gpu_init(struct radeon_device *rdev); 103 void r600_irq_disable(struct radeon_device *rdev); 104 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 105 106 /* 107 * Indirect registers accessor 108 */ 109 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 110 { 111 u32 r; 112 113 lockmgr(&rdev->rcu_idx_lock, LK_EXCLUSIVE); 114 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 115 r = RREG32(R600_RCU_DATA); 116 lockmgr(&rdev->rcu_idx_lock, LK_RELEASE); 117 return r; 118 } 119 120 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 121 { 122 lockmgr(&rdev->rcu_idx_lock, LK_EXCLUSIVE); 123 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 124 WREG32(R600_RCU_DATA, (v)); 125 lockmgr(&rdev->rcu_idx_lock, LK_RELEASE); 126 } 127 128 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 129 { 130 u32 r; 131 132 lockmgr(&rdev->uvd_idx_lock, LK_EXCLUSIVE); 133 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 134 r = RREG32(R600_UVD_CTX_DATA); 135 lockmgr(&rdev->uvd_idx_lock, LK_RELEASE); 136 return r; 137 } 138 139 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 140 { 141 lockmgr(&rdev->uvd_idx_lock, LK_EXCLUSIVE); 142 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 143 WREG32(R600_UVD_CTX_DATA, (v)); 144 lockmgr(&rdev->uvd_idx_lock, LK_RELEASE); 145 } 146 147 /** 148 * r600_get_allowed_info_register - fetch the register for the info ioctl 149 * 150 * @rdev: radeon_device pointer 151 * @reg: register offset in bytes 152 * @val: register value 153 * 154 * Returns 0 for success or -EINVAL for an invalid register 155 * 156 */ 157 int r600_get_allowed_info_register(struct radeon_device *rdev, 158 u32 reg, u32 *val) 159 { 160 switch (reg) { 161 case GRBM_STATUS: 162 case GRBM_STATUS2: 163 case R_000E50_SRBM_STATUS: 164 case DMA_STATUS_REG: 165 case UVD_STATUS: 166 *val = RREG32(reg); 167 return 0; 168 default: 169 return -EINVAL; 170 } 171 } 172 173 /** 174 * r600_get_xclk - get the xclk 175 * 176 * @rdev: radeon_device pointer 177 * 178 * Returns the reference clock used by the gfx engine 179 * (r6xx, IGPs, APUs). 180 */ 181 u32 r600_get_xclk(struct radeon_device *rdev) 182 { 183 return rdev->clock.spll.reference_freq; 184 } 185 186 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 187 { 188 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; 189 int r; 190 191 /* bypass vclk and dclk with bclk */ 192 WREG32_P(CG_UPLL_FUNC_CNTL_2, 193 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 194 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 195 196 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */ 197 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( 198 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); 199 200 if (rdev->family >= CHIP_RS780) 201 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL, 202 ~UPLL_BYPASS_CNTL); 203 204 if (!vclk || !dclk) { 205 /* keep the Bypass mode, put PLL to sleep */ 206 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 207 return 0; 208 } 209 210 if (rdev->clock.spll.reference_freq == 10000) 211 ref_div = 34; 212 else 213 ref_div = 4; 214 215 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, 216 ref_div + 1, 0xFFF, 2, 30, ~0, 217 &fb_div, &vclk_div, &dclk_div); 218 if (r) 219 return r; 220 221 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) 222 fb_div >>= 1; 223 else 224 fb_div |= 1; 225 226 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 227 if (r) 228 return r; 229 230 /* assert PLL_RESET */ 231 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 232 233 /* For RS780 we have to choose ref clk */ 234 if (rdev->family >= CHIP_RS780) 235 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, 236 ~UPLL_REFCLK_SRC_SEL_MASK); 237 238 /* set the required fb, ref and post divder values */ 239 WREG32_P(CG_UPLL_FUNC_CNTL, 240 UPLL_FB_DIV(fb_div) | 241 UPLL_REF_DIV(ref_div), 242 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK)); 243 WREG32_P(CG_UPLL_FUNC_CNTL_2, 244 UPLL_SW_HILEN(vclk_div >> 1) | 245 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | 246 UPLL_SW_HILEN2(dclk_div >> 1) | 247 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) | 248 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK, 249 ~UPLL_SW_MASK); 250 251 /* give the PLL some time to settle */ 252 mdelay(15); 253 254 /* deassert PLL_RESET */ 255 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 256 257 mdelay(15); 258 259 /* deassert BYPASS EN */ 260 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 261 262 if (rdev->family >= CHIP_RS780) 263 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL); 264 265 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 266 if (r) 267 return r; 268 269 /* switch VCLK and DCLK selection */ 270 WREG32_P(CG_UPLL_FUNC_CNTL_2, 271 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 272 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 273 274 mdelay(100); 275 276 return 0; 277 } 278 279 void dce3_program_fmt(struct drm_encoder *encoder) 280 { 281 struct drm_device *dev = encoder->dev; 282 struct radeon_device *rdev = dev->dev_private; 283 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 284 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 285 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 286 int bpc = 0; 287 u32 tmp = 0; 288 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 289 290 if (connector) { 291 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 292 bpc = radeon_get_monitor_bpc(connector); 293 dither = radeon_connector->dither; 294 } 295 296 /* LVDS FMT is set up by atom */ 297 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 298 return; 299 300 /* not needed for analog */ 301 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 302 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 303 return; 304 305 if (bpc == 0) 306 return; 307 308 switch (bpc) { 309 case 6: 310 if (dither == RADEON_FMT_DITHER_ENABLE) 311 /* XXX sort out optimal dither settings */ 312 tmp |= FMT_SPATIAL_DITHER_EN; 313 else 314 tmp |= FMT_TRUNCATE_EN; 315 break; 316 case 8: 317 if (dither == RADEON_FMT_DITHER_ENABLE) 318 /* XXX sort out optimal dither settings */ 319 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); 320 else 321 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); 322 break; 323 case 10: 324 default: 325 /* not needed */ 326 break; 327 } 328 329 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); 330 } 331 332 /* get temperature in millidegrees */ 333 int rv6xx_get_temp(struct radeon_device *rdev) 334 { 335 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 336 ASIC_T_SHIFT; 337 int actual_temp = temp & 0xff; 338 339 if (temp & 0x100) 340 actual_temp -= 256; 341 342 return actual_temp * 1000; 343 } 344 345 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 346 { 347 int i; 348 349 rdev->pm.dynpm_can_upclock = true; 350 rdev->pm.dynpm_can_downclock = true; 351 352 /* power state array is low to high, default is first */ 353 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 354 int min_power_state_index = 0; 355 356 if (rdev->pm.num_power_states > 2) 357 min_power_state_index = 1; 358 359 switch (rdev->pm.dynpm_planned_action) { 360 case DYNPM_ACTION_MINIMUM: 361 rdev->pm.requested_power_state_index = min_power_state_index; 362 rdev->pm.requested_clock_mode_index = 0; 363 rdev->pm.dynpm_can_downclock = false; 364 break; 365 case DYNPM_ACTION_DOWNCLOCK: 366 if (rdev->pm.current_power_state_index == min_power_state_index) { 367 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 368 rdev->pm.dynpm_can_downclock = false; 369 } else { 370 if (rdev->pm.active_crtc_count > 1) { 371 for (i = 0; i < rdev->pm.num_power_states; i++) { 372 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 373 continue; 374 else if (i >= rdev->pm.current_power_state_index) { 375 rdev->pm.requested_power_state_index = 376 rdev->pm.current_power_state_index; 377 break; 378 } else { 379 rdev->pm.requested_power_state_index = i; 380 break; 381 } 382 } 383 } else { 384 if (rdev->pm.current_power_state_index == 0) 385 rdev->pm.requested_power_state_index = 386 rdev->pm.num_power_states - 1; 387 else 388 rdev->pm.requested_power_state_index = 389 rdev->pm.current_power_state_index - 1; 390 } 391 } 392 rdev->pm.requested_clock_mode_index = 0; 393 /* don't use the power state if crtcs are active and no display flag is set */ 394 if ((rdev->pm.active_crtc_count > 0) && 395 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 396 clock_info[rdev->pm.requested_clock_mode_index].flags & 397 RADEON_PM_MODE_NO_DISPLAY)) { 398 rdev->pm.requested_power_state_index++; 399 } 400 break; 401 case DYNPM_ACTION_UPCLOCK: 402 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 403 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 404 rdev->pm.dynpm_can_upclock = false; 405 } else { 406 if (rdev->pm.active_crtc_count > 1) { 407 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 408 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 409 continue; 410 else if (i <= rdev->pm.current_power_state_index) { 411 rdev->pm.requested_power_state_index = 412 rdev->pm.current_power_state_index; 413 break; 414 } else { 415 rdev->pm.requested_power_state_index = i; 416 break; 417 } 418 } 419 } else 420 rdev->pm.requested_power_state_index = 421 rdev->pm.current_power_state_index + 1; 422 } 423 rdev->pm.requested_clock_mode_index = 0; 424 break; 425 case DYNPM_ACTION_DEFAULT: 426 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 427 rdev->pm.requested_clock_mode_index = 0; 428 rdev->pm.dynpm_can_upclock = false; 429 break; 430 case DYNPM_ACTION_NONE: 431 default: 432 DRM_ERROR("Requested mode for not defined action\n"); 433 return; 434 } 435 } else { 436 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 437 /* for now just select the first power state and switch between clock modes */ 438 /* power state array is low to high, default is first (0) */ 439 if (rdev->pm.active_crtc_count > 1) { 440 rdev->pm.requested_power_state_index = -1; 441 /* start at 1 as we don't want the default mode */ 442 for (i = 1; i < rdev->pm.num_power_states; i++) { 443 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 444 continue; 445 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 446 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 447 rdev->pm.requested_power_state_index = i; 448 break; 449 } 450 } 451 /* if nothing selected, grab the default state. */ 452 if (rdev->pm.requested_power_state_index == -1) 453 rdev->pm.requested_power_state_index = 0; 454 } else 455 rdev->pm.requested_power_state_index = 1; 456 457 switch (rdev->pm.dynpm_planned_action) { 458 case DYNPM_ACTION_MINIMUM: 459 rdev->pm.requested_clock_mode_index = 0; 460 rdev->pm.dynpm_can_downclock = false; 461 break; 462 case DYNPM_ACTION_DOWNCLOCK: 463 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 464 if (rdev->pm.current_clock_mode_index == 0) { 465 rdev->pm.requested_clock_mode_index = 0; 466 rdev->pm.dynpm_can_downclock = false; 467 } else 468 rdev->pm.requested_clock_mode_index = 469 rdev->pm.current_clock_mode_index - 1; 470 } else { 471 rdev->pm.requested_clock_mode_index = 0; 472 rdev->pm.dynpm_can_downclock = false; 473 } 474 /* don't use the power state if crtcs are active and no display flag is set */ 475 if ((rdev->pm.active_crtc_count > 0) && 476 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 477 clock_info[rdev->pm.requested_clock_mode_index].flags & 478 RADEON_PM_MODE_NO_DISPLAY)) { 479 rdev->pm.requested_clock_mode_index++; 480 } 481 break; 482 case DYNPM_ACTION_UPCLOCK: 483 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 484 if (rdev->pm.current_clock_mode_index == 485 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 486 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 487 rdev->pm.dynpm_can_upclock = false; 488 } else 489 rdev->pm.requested_clock_mode_index = 490 rdev->pm.current_clock_mode_index + 1; 491 } else { 492 rdev->pm.requested_clock_mode_index = 493 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 494 rdev->pm.dynpm_can_upclock = false; 495 } 496 break; 497 case DYNPM_ACTION_DEFAULT: 498 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 499 rdev->pm.requested_clock_mode_index = 0; 500 rdev->pm.dynpm_can_upclock = false; 501 break; 502 case DYNPM_ACTION_NONE: 503 default: 504 DRM_ERROR("Requested mode for not defined action\n"); 505 return; 506 } 507 } 508 509 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 510 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 511 clock_info[rdev->pm.requested_clock_mode_index].sclk, 512 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 513 clock_info[rdev->pm.requested_clock_mode_index].mclk, 514 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 515 pcie_lanes); 516 } 517 518 void rs780_pm_init_profile(struct radeon_device *rdev) 519 { 520 if (rdev->pm.num_power_states == 2) { 521 /* default */ 522 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 523 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 524 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 525 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 526 /* low sh */ 527 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 528 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 529 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 530 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 531 /* mid sh */ 532 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 533 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 534 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 535 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 536 /* high sh */ 537 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 538 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 539 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 540 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 541 /* low mh */ 542 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 543 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 545 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 546 /* mid mh */ 547 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 548 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 549 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 550 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 551 /* high mh */ 552 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 553 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 554 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 555 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 556 } else if (rdev->pm.num_power_states == 3) { 557 /* default */ 558 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 559 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 560 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 561 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 562 /* low sh */ 563 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 564 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 565 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 566 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 567 /* mid sh */ 568 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 569 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 570 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 571 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 572 /* high sh */ 573 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 574 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 575 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 576 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 577 /* low mh */ 578 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 579 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 580 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 581 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 582 /* mid mh */ 583 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 584 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 585 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 586 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 587 /* high mh */ 588 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 589 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 590 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 591 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 592 } else { 593 /* default */ 594 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 595 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 596 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 597 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 598 /* low sh */ 599 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 600 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 601 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 602 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 603 /* mid sh */ 604 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 605 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 606 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 607 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 608 /* high sh */ 609 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 610 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 611 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 612 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 613 /* low mh */ 614 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 615 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 616 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 617 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 618 /* mid mh */ 619 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 620 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 621 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 622 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 623 /* high mh */ 624 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 625 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 626 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 627 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 628 } 629 } 630 631 void r600_pm_init_profile(struct radeon_device *rdev) 632 { 633 int idx; 634 635 if (rdev->family == CHIP_R600) { 636 /* XXX */ 637 /* default */ 638 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 639 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 640 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 641 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 642 /* low sh */ 643 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 644 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 645 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 646 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 647 /* mid sh */ 648 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 649 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 650 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 651 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 652 /* high sh */ 653 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 654 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 655 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 656 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 657 /* low mh */ 658 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 659 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 660 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 661 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 662 /* mid mh */ 663 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 664 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 665 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 666 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 667 /* high mh */ 668 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 669 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 670 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 671 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 672 } else { 673 if (rdev->pm.num_power_states < 4) { 674 /* default */ 675 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 676 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 677 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 678 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 679 /* low sh */ 680 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 681 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 682 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 683 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 684 /* mid sh */ 685 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 686 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 687 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 688 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 689 /* high sh */ 690 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 691 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 692 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 693 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 694 /* low mh */ 695 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 696 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 697 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 698 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 699 /* low mh */ 700 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 701 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 702 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 703 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 704 /* high mh */ 705 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 706 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 707 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 708 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 709 } else { 710 /* default */ 711 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 712 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 713 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 714 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 715 /* low sh */ 716 if (rdev->flags & RADEON_IS_MOBILITY) 717 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 718 else 719 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 720 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 721 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 722 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 723 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 724 /* mid sh */ 725 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 726 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 727 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 728 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 729 /* high sh */ 730 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 731 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 732 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 733 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 734 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 735 /* low mh */ 736 if (rdev->flags & RADEON_IS_MOBILITY) 737 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 738 else 739 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 740 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 741 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 742 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 743 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 744 /* mid mh */ 745 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 746 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 747 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 748 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 749 /* high mh */ 750 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 751 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 752 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 753 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 754 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 755 } 756 } 757 } 758 759 void r600_pm_misc(struct radeon_device *rdev) 760 { 761 int req_ps_idx = rdev->pm.requested_power_state_index; 762 int req_cm_idx = rdev->pm.requested_clock_mode_index; 763 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 764 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 765 766 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 767 /* 0xff01 is a flag rather then an actual voltage */ 768 if (voltage->voltage == 0xff01) 769 return; 770 if (voltage->voltage != rdev->pm.current_vddc) { 771 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 772 rdev->pm.current_vddc = voltage->voltage; 773 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 774 } 775 } 776 } 777 778 bool r600_gui_idle(struct radeon_device *rdev) 779 { 780 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 781 return false; 782 else 783 return true; 784 } 785 786 /* hpd for digital panel detect/disconnect */ 787 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 788 { 789 bool connected = false; 790 791 if (ASIC_IS_DCE3(rdev)) { 792 switch (hpd) { 793 case RADEON_HPD_1: 794 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 795 connected = true; 796 break; 797 case RADEON_HPD_2: 798 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 799 connected = true; 800 break; 801 case RADEON_HPD_3: 802 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 803 connected = true; 804 break; 805 case RADEON_HPD_4: 806 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 807 connected = true; 808 break; 809 /* DCE 3.2 */ 810 case RADEON_HPD_5: 811 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 812 connected = true; 813 break; 814 case RADEON_HPD_6: 815 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 816 connected = true; 817 break; 818 default: 819 break; 820 } 821 } else { 822 switch (hpd) { 823 case RADEON_HPD_1: 824 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 825 connected = true; 826 break; 827 case RADEON_HPD_2: 828 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 829 connected = true; 830 break; 831 case RADEON_HPD_3: 832 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 833 connected = true; 834 break; 835 default: 836 break; 837 } 838 } 839 return connected; 840 } 841 842 void r600_hpd_set_polarity(struct radeon_device *rdev, 843 enum radeon_hpd_id hpd) 844 { 845 u32 tmp; 846 bool connected = r600_hpd_sense(rdev, hpd); 847 848 if (ASIC_IS_DCE3(rdev)) { 849 switch (hpd) { 850 case RADEON_HPD_1: 851 tmp = RREG32(DC_HPD1_INT_CONTROL); 852 if (connected) 853 tmp &= ~DC_HPDx_INT_POLARITY; 854 else 855 tmp |= DC_HPDx_INT_POLARITY; 856 WREG32(DC_HPD1_INT_CONTROL, tmp); 857 break; 858 case RADEON_HPD_2: 859 tmp = RREG32(DC_HPD2_INT_CONTROL); 860 if (connected) 861 tmp &= ~DC_HPDx_INT_POLARITY; 862 else 863 tmp |= DC_HPDx_INT_POLARITY; 864 WREG32(DC_HPD2_INT_CONTROL, tmp); 865 break; 866 case RADEON_HPD_3: 867 tmp = RREG32(DC_HPD3_INT_CONTROL); 868 if (connected) 869 tmp &= ~DC_HPDx_INT_POLARITY; 870 else 871 tmp |= DC_HPDx_INT_POLARITY; 872 WREG32(DC_HPD3_INT_CONTROL, tmp); 873 break; 874 case RADEON_HPD_4: 875 tmp = RREG32(DC_HPD4_INT_CONTROL); 876 if (connected) 877 tmp &= ~DC_HPDx_INT_POLARITY; 878 else 879 tmp |= DC_HPDx_INT_POLARITY; 880 WREG32(DC_HPD4_INT_CONTROL, tmp); 881 break; 882 case RADEON_HPD_5: 883 tmp = RREG32(DC_HPD5_INT_CONTROL); 884 if (connected) 885 tmp &= ~DC_HPDx_INT_POLARITY; 886 else 887 tmp |= DC_HPDx_INT_POLARITY; 888 WREG32(DC_HPD5_INT_CONTROL, tmp); 889 break; 890 /* DCE 3.2 */ 891 case RADEON_HPD_6: 892 tmp = RREG32(DC_HPD6_INT_CONTROL); 893 if (connected) 894 tmp &= ~DC_HPDx_INT_POLARITY; 895 else 896 tmp |= DC_HPDx_INT_POLARITY; 897 WREG32(DC_HPD6_INT_CONTROL, tmp); 898 break; 899 default: 900 break; 901 } 902 } else { 903 switch (hpd) { 904 case RADEON_HPD_1: 905 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 906 if (connected) 907 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 908 else 909 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 910 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 911 break; 912 case RADEON_HPD_2: 913 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 914 if (connected) 915 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 916 else 917 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 918 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 919 break; 920 case RADEON_HPD_3: 921 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 922 if (connected) 923 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 924 else 925 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 926 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 927 break; 928 default: 929 break; 930 } 931 } 932 } 933 934 void r600_hpd_init(struct radeon_device *rdev) 935 { 936 struct drm_device *dev = rdev->ddev; 937 struct drm_connector *connector; 938 unsigned enable = 0; 939 940 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 941 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 942 943 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 944 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 945 /* don't try to enable hpd on eDP or LVDS avoid breaking the 946 * aux dp channel on imac and help (but not completely fix) 947 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 948 */ 949 continue; 950 } 951 if (ASIC_IS_DCE3(rdev)) { 952 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 953 if (ASIC_IS_DCE32(rdev)) 954 tmp |= DC_HPDx_EN; 955 956 switch (radeon_connector->hpd.hpd) { 957 case RADEON_HPD_1: 958 WREG32(DC_HPD1_CONTROL, tmp); 959 break; 960 case RADEON_HPD_2: 961 WREG32(DC_HPD2_CONTROL, tmp); 962 break; 963 case RADEON_HPD_3: 964 WREG32(DC_HPD3_CONTROL, tmp); 965 break; 966 case RADEON_HPD_4: 967 WREG32(DC_HPD4_CONTROL, tmp); 968 break; 969 /* DCE 3.2 */ 970 case RADEON_HPD_5: 971 WREG32(DC_HPD5_CONTROL, tmp); 972 break; 973 case RADEON_HPD_6: 974 WREG32(DC_HPD6_CONTROL, tmp); 975 break; 976 default: 977 break; 978 } 979 } else { 980 switch (radeon_connector->hpd.hpd) { 981 case RADEON_HPD_1: 982 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 983 break; 984 case RADEON_HPD_2: 985 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 986 break; 987 case RADEON_HPD_3: 988 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 989 break; 990 default: 991 break; 992 } 993 } 994 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 995 enable |= 1 << radeon_connector->hpd.hpd; 996 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 997 } 998 radeon_irq_kms_enable_hpd(rdev, enable); 999 } 1000 1001 void r600_hpd_fini(struct radeon_device *rdev) 1002 { 1003 struct drm_device *dev = rdev->ddev; 1004 struct drm_connector *connector; 1005 unsigned disable = 0; 1006 1007 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1008 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1009 if (ASIC_IS_DCE3(rdev)) { 1010 switch (radeon_connector->hpd.hpd) { 1011 case RADEON_HPD_1: 1012 WREG32(DC_HPD1_CONTROL, 0); 1013 break; 1014 case RADEON_HPD_2: 1015 WREG32(DC_HPD2_CONTROL, 0); 1016 break; 1017 case RADEON_HPD_3: 1018 WREG32(DC_HPD3_CONTROL, 0); 1019 break; 1020 case RADEON_HPD_4: 1021 WREG32(DC_HPD4_CONTROL, 0); 1022 break; 1023 /* DCE 3.2 */ 1024 case RADEON_HPD_5: 1025 WREG32(DC_HPD5_CONTROL, 0); 1026 break; 1027 case RADEON_HPD_6: 1028 WREG32(DC_HPD6_CONTROL, 0); 1029 break; 1030 default: 1031 break; 1032 } 1033 } else { 1034 switch (radeon_connector->hpd.hpd) { 1035 case RADEON_HPD_1: 1036 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 1037 break; 1038 case RADEON_HPD_2: 1039 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 1040 break; 1041 case RADEON_HPD_3: 1042 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 1043 break; 1044 default: 1045 break; 1046 } 1047 } 1048 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 1049 disable |= 1 << radeon_connector->hpd.hpd; 1050 } 1051 radeon_irq_kms_disable_hpd(rdev, disable); 1052 } 1053 1054 /* 1055 * R600 PCIE GART 1056 */ 1057 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 1058 { 1059 unsigned i; 1060 u32 tmp; 1061 1062 /* flush hdp cache so updates hit vram */ 1063 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 1064 !(rdev->flags & RADEON_IS_AGP)) { 1065 void __iomem *ptr = (void *)rdev->gart.ptr; 1066 u32 tmp; 1067 1068 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 1069 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 1070 * This seems to cause problems on some AGP cards. Just use the old 1071 * method for them. 1072 */ 1073 WREG32(HDP_DEBUG1, 0); 1074 tmp = readl((void __iomem *)ptr); 1075 } else 1076 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1077 1078 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 1079 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 1080 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 1081 for (i = 0; i < rdev->usec_timeout; i++) { 1082 /* read MC_STATUS */ 1083 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 1084 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 1085 if (tmp == 2) { 1086 pr_warn("[drm] r600 flush TLB failed\n"); 1087 return; 1088 } 1089 if (tmp) { 1090 return; 1091 } 1092 udelay(1); 1093 } 1094 } 1095 1096 int r600_pcie_gart_init(struct radeon_device *rdev) 1097 { 1098 int r; 1099 1100 if (rdev->gart.robj) { 1101 WARN(1, "R600 PCIE GART already initialized\n"); 1102 return 0; 1103 } 1104 /* Initialize common gart structure */ 1105 r = radeon_gart_init(rdev); 1106 if (r) 1107 return r; 1108 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 1109 return radeon_gart_table_vram_alloc(rdev); 1110 } 1111 1112 static int r600_pcie_gart_enable(struct radeon_device *rdev) 1113 { 1114 u32 tmp; 1115 int r, i; 1116 1117 if (rdev->gart.robj == NULL) { 1118 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1119 return -EINVAL; 1120 } 1121 r = radeon_gart_table_vram_pin(rdev); 1122 if (r) 1123 return r; 1124 1125 /* Setup L2 cache */ 1126 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1127 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1128 EFFECTIVE_L2_QUEUE_SIZE(7)); 1129 WREG32(VM_L2_CNTL2, 0); 1130 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1131 /* Setup TLB control */ 1132 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1133 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1134 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1135 ENABLE_WAIT_L2_QUERY; 1136 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1137 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1138 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1139 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1140 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1141 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1142 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1143 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1144 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1145 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1146 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1147 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1148 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1149 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1150 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1151 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1152 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1153 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1154 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1155 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1156 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1157 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1158 (u32)(rdev->dummy_page.addr >> 12)); 1159 for (i = 1; i < 7; i++) 1160 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1161 1162 r600_pcie_gart_tlb_flush(rdev); 1163 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1164 (unsigned)(rdev->mc.gtt_size >> 20), 1165 (unsigned long long)rdev->gart.table_addr); 1166 rdev->gart.ready = true; 1167 return 0; 1168 } 1169 1170 static void r600_pcie_gart_disable(struct radeon_device *rdev) 1171 { 1172 u32 tmp; 1173 int i; 1174 1175 /* Disable all tables */ 1176 for (i = 0; i < 7; i++) 1177 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1178 1179 /* Disable L2 cache */ 1180 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1181 EFFECTIVE_L2_QUEUE_SIZE(7)); 1182 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1183 /* Setup L1 TLB control */ 1184 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1185 ENABLE_WAIT_L2_QUERY; 1186 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1187 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1188 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1189 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1190 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1191 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1192 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1193 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1194 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 1195 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 1196 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1197 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1198 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 1199 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1200 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1201 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1202 radeon_gart_table_vram_unpin(rdev); 1203 } 1204 1205 static void r600_pcie_gart_fini(struct radeon_device *rdev) 1206 { 1207 radeon_gart_fini(rdev); 1208 r600_pcie_gart_disable(rdev); 1209 radeon_gart_table_vram_free(rdev); 1210 } 1211 1212 static void r600_agp_enable(struct radeon_device *rdev) 1213 { 1214 u32 tmp; 1215 int i; 1216 1217 /* Setup L2 cache */ 1218 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1219 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1220 EFFECTIVE_L2_QUEUE_SIZE(7)); 1221 WREG32(VM_L2_CNTL2, 0); 1222 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1223 /* Setup TLB control */ 1224 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1225 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1226 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1227 ENABLE_WAIT_L2_QUERY; 1228 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1229 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1230 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1231 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1232 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1233 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1234 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1235 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1236 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1237 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1238 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1239 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1240 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1241 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1242 for (i = 0; i < 7; i++) 1243 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1244 } 1245 1246 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1247 { 1248 unsigned i; 1249 u32 tmp; 1250 1251 for (i = 0; i < rdev->usec_timeout; i++) { 1252 /* read MC_STATUS */ 1253 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1254 if (!tmp) 1255 return 0; 1256 udelay(1); 1257 } 1258 return -1; 1259 } 1260 1261 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1262 { 1263 uint32_t r; 1264 1265 lockmgr(&rdev->mc_idx_lock, LK_EXCLUSIVE); 1266 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1267 r = RREG32(R_0028FC_MC_DATA); 1268 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1269 lockmgr(&rdev->mc_idx_lock, LK_RELEASE); 1270 return r; 1271 } 1272 1273 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1274 { 1275 lockmgr(&rdev->mc_idx_lock, LK_EXCLUSIVE); 1276 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1277 S_0028F8_MC_IND_WR_EN(1)); 1278 WREG32(R_0028FC_MC_DATA, v); 1279 WREG32(R_0028F8_MC_INDEX, 0x7F); 1280 lockmgr(&rdev->mc_idx_lock, LK_RELEASE); 1281 } 1282 1283 static void r600_mc_program(struct radeon_device *rdev) 1284 { 1285 struct rv515_mc_save save; 1286 u32 tmp; 1287 int i, j; 1288 1289 /* Initialize HDP */ 1290 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1291 WREG32((0x2c14 + j), 0x00000000); 1292 WREG32((0x2c18 + j), 0x00000000); 1293 WREG32((0x2c1c + j), 0x00000000); 1294 WREG32((0x2c20 + j), 0x00000000); 1295 WREG32((0x2c24 + j), 0x00000000); 1296 } 1297 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1298 1299 rv515_mc_stop(rdev, &save); 1300 if (r600_mc_wait_for_idle(rdev)) { 1301 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1302 } 1303 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1304 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1305 /* Update configuration */ 1306 if (rdev->flags & RADEON_IS_AGP) { 1307 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1308 /* VRAM before AGP */ 1309 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1310 rdev->mc.vram_start >> 12); 1311 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1312 rdev->mc.gtt_end >> 12); 1313 } else { 1314 /* VRAM after AGP */ 1315 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1316 rdev->mc.gtt_start >> 12); 1317 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1318 rdev->mc.vram_end >> 12); 1319 } 1320 } else { 1321 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1322 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1323 } 1324 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1325 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1326 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1327 WREG32(MC_VM_FB_LOCATION, tmp); 1328 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1329 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1330 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1331 if (rdev->flags & RADEON_IS_AGP) { 1332 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1333 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1334 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1335 } else { 1336 WREG32(MC_VM_AGP_BASE, 0); 1337 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1338 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1339 } 1340 if (r600_mc_wait_for_idle(rdev)) { 1341 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1342 } 1343 rv515_mc_resume(rdev, &save); 1344 /* we need to own VRAM, so turn off the VGA renderer here 1345 * to stop it overwriting our objects */ 1346 rv515_vga_render_disable(rdev); 1347 } 1348 1349 /** 1350 * r600_vram_gtt_location - try to find VRAM & GTT location 1351 * @rdev: radeon device structure holding all necessary informations 1352 * @mc: memory controller structure holding memory informations 1353 * 1354 * Function will place try to place VRAM at same place as in CPU (PCI) 1355 * address space as some GPU seems to have issue when we reprogram at 1356 * different address space. 1357 * 1358 * If there is not enough space to fit the unvisible VRAM after the 1359 * aperture then we limit the VRAM size to the aperture. 1360 * 1361 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1362 * them to be in one from GPU point of view so that we can program GPU to 1363 * catch access outside them (weird GPU policy see ??). 1364 * 1365 * This function will never fails, worst case are limiting VRAM or GTT. 1366 * 1367 * Note: GTT start, end, size should be initialized before calling this 1368 * function on AGP platform. 1369 */ 1370 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1371 { 1372 u64 size_bf, size_af; 1373 1374 if (mc->mc_vram_size > 0xE0000000) { 1375 /* leave room for at least 512M GTT */ 1376 dev_warn(rdev->dev, "limiting VRAM\n"); 1377 mc->real_vram_size = 0xE0000000; 1378 mc->mc_vram_size = 0xE0000000; 1379 } 1380 if (rdev->flags & RADEON_IS_AGP) { 1381 size_bf = mc->gtt_start; 1382 size_af = mc->mc_mask - mc->gtt_end; 1383 if (size_bf > size_af) { 1384 if (mc->mc_vram_size > size_bf) { 1385 dev_warn(rdev->dev, "limiting VRAM\n"); 1386 mc->real_vram_size = size_bf; 1387 mc->mc_vram_size = size_bf; 1388 } 1389 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1390 } else { 1391 if (mc->mc_vram_size > size_af) { 1392 dev_warn(rdev->dev, "limiting VRAM\n"); 1393 mc->real_vram_size = size_af; 1394 mc->mc_vram_size = size_af; 1395 } 1396 mc->vram_start = mc->gtt_end + 1; 1397 } 1398 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1399 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 1400 mc->mc_vram_size >> 20, mc->vram_start, 1401 mc->vram_end, mc->real_vram_size >> 20); 1402 } else { 1403 u64 base = 0; 1404 if (rdev->flags & RADEON_IS_IGP) { 1405 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1406 base <<= 24; 1407 } 1408 radeon_vram_location(rdev, &rdev->mc, base); 1409 rdev->mc.gtt_base_align = 0; 1410 radeon_gtt_location(rdev, mc); 1411 } 1412 } 1413 1414 static int r600_mc_init(struct radeon_device *rdev) 1415 { 1416 u32 tmp; 1417 int chansize, numchan; 1418 uint32_t h_addr, l_addr; 1419 unsigned long long k8_addr; 1420 1421 /* Get VRAM informations */ 1422 rdev->mc.vram_is_ddr = true; 1423 tmp = RREG32(RAMCFG); 1424 if (tmp & CHANSIZE_OVERRIDE) { 1425 chansize = 16; 1426 } else if (tmp & CHANSIZE_MASK) { 1427 chansize = 64; 1428 } else { 1429 chansize = 32; 1430 } 1431 tmp = RREG32(CHMAP); 1432 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1433 case 0: 1434 default: 1435 numchan = 1; 1436 break; 1437 case 1: 1438 numchan = 2; 1439 break; 1440 case 2: 1441 numchan = 4; 1442 break; 1443 case 3: 1444 numchan = 8; 1445 break; 1446 } 1447 rdev->mc.vram_width = numchan * chansize; 1448 /* Could aper size report 0 ? */ 1449 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1450 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1451 /* Setup GPU memory space */ 1452 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1453 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1454 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1455 r600_vram_gtt_location(rdev, &rdev->mc); 1456 1457 if (rdev->flags & RADEON_IS_IGP) { 1458 rs690_pm_info(rdev); 1459 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1460 1461 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 1462 /* Use K8 direct mapping for fast fb access. */ 1463 rdev->fastfb_working = false; 1464 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); 1465 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); 1466 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 1467 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 1468 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 1469 #endif 1470 { 1471 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 1472 * memory is present. 1473 */ 1474 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 1475 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 1476 (unsigned long long)rdev->mc.aper_base, k8_addr); 1477 rdev->mc.aper_base = (resource_size_t)k8_addr; 1478 rdev->fastfb_working = true; 1479 } 1480 } 1481 } 1482 } 1483 1484 radeon_update_bandwidth_info(rdev); 1485 return 0; 1486 } 1487 1488 int r600_vram_scratch_init(struct radeon_device *rdev) 1489 { 1490 int r; 1491 void *vram_scratch_ptr_ptr = &rdev->vram_scratch.ptr; 1492 1493 if (rdev->vram_scratch.robj == NULL) { 1494 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1495 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1496 0, NULL, NULL, &rdev->vram_scratch.robj); 1497 if (r) { 1498 return r; 1499 } 1500 } 1501 1502 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1503 if (unlikely(r != 0)) 1504 return r; 1505 r = radeon_bo_pin(rdev->vram_scratch.robj, 1506 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1507 if (r) { 1508 radeon_bo_unreserve(rdev->vram_scratch.robj); 1509 return r; 1510 } 1511 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1512 vram_scratch_ptr_ptr); 1513 if (r) 1514 radeon_bo_unpin(rdev->vram_scratch.robj); 1515 radeon_bo_unreserve(rdev->vram_scratch.robj); 1516 1517 return r; 1518 } 1519 1520 void r600_vram_scratch_fini(struct radeon_device *rdev) 1521 { 1522 int r; 1523 1524 if (rdev->vram_scratch.robj == NULL) { 1525 return; 1526 } 1527 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1528 if (likely(r == 0)) { 1529 radeon_bo_kunmap(rdev->vram_scratch.robj); 1530 radeon_bo_unpin(rdev->vram_scratch.robj); 1531 radeon_bo_unreserve(rdev->vram_scratch.robj); 1532 } 1533 radeon_bo_unref(&rdev->vram_scratch.robj); 1534 } 1535 1536 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1537 { 1538 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1539 1540 if (hung) 1541 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1542 else 1543 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1544 1545 WREG32(R600_BIOS_3_SCRATCH, tmp); 1546 } 1547 1548 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1549 { 1550 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1551 RREG32(R_008010_GRBM_STATUS)); 1552 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1553 RREG32(R_008014_GRBM_STATUS2)); 1554 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1555 RREG32(R_000E50_SRBM_STATUS)); 1556 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1557 RREG32(CP_STALLED_STAT1)); 1558 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1559 RREG32(CP_STALLED_STAT2)); 1560 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1561 RREG32(CP_BUSY_STAT)); 1562 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1563 RREG32(CP_STAT)); 1564 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1565 RREG32(DMA_STATUS_REG)); 1566 } 1567 1568 static bool r600_is_display_hung(struct radeon_device *rdev) 1569 { 1570 u32 crtc_hung = 0; 1571 u32 crtc_status[2]; 1572 u32 i, j, tmp; 1573 1574 for (i = 0; i < rdev->num_crtc; i++) { 1575 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1576 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1577 crtc_hung |= (1 << i); 1578 } 1579 } 1580 1581 for (j = 0; j < 10; j++) { 1582 for (i = 0; i < rdev->num_crtc; i++) { 1583 if (crtc_hung & (1 << i)) { 1584 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1585 if (tmp != crtc_status[i]) 1586 crtc_hung &= ~(1 << i); 1587 } 1588 } 1589 if (crtc_hung == 0) 1590 return false; 1591 udelay(100); 1592 } 1593 1594 return true; 1595 } 1596 1597 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1598 { 1599 u32 reset_mask = 0; 1600 u32 tmp; 1601 1602 /* GRBM_STATUS */ 1603 tmp = RREG32(R_008010_GRBM_STATUS); 1604 if (rdev->family >= CHIP_RV770) { 1605 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1606 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1607 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1608 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1609 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1610 reset_mask |= RADEON_RESET_GFX; 1611 } else { 1612 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1613 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1614 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1615 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1616 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1617 reset_mask |= RADEON_RESET_GFX; 1618 } 1619 1620 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1621 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1622 reset_mask |= RADEON_RESET_CP; 1623 1624 if (G_008010_GRBM_EE_BUSY(tmp)) 1625 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1626 1627 /* DMA_STATUS_REG */ 1628 tmp = RREG32(DMA_STATUS_REG); 1629 if (!(tmp & DMA_IDLE)) 1630 reset_mask |= RADEON_RESET_DMA; 1631 1632 /* SRBM_STATUS */ 1633 tmp = RREG32(R_000E50_SRBM_STATUS); 1634 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1635 reset_mask |= RADEON_RESET_RLC; 1636 1637 if (G_000E50_IH_BUSY(tmp)) 1638 reset_mask |= RADEON_RESET_IH; 1639 1640 if (G_000E50_SEM_BUSY(tmp)) 1641 reset_mask |= RADEON_RESET_SEM; 1642 1643 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1644 reset_mask |= RADEON_RESET_GRBM; 1645 1646 if (G_000E50_VMC_BUSY(tmp)) 1647 reset_mask |= RADEON_RESET_VMC; 1648 1649 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1650 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1651 G_000E50_MCDW_BUSY(tmp)) 1652 reset_mask |= RADEON_RESET_MC; 1653 1654 if (r600_is_display_hung(rdev)) 1655 reset_mask |= RADEON_RESET_DISPLAY; 1656 1657 /* Skip MC reset as it's mostly likely not hung, just busy */ 1658 if (reset_mask & RADEON_RESET_MC) { 1659 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1660 reset_mask &= ~RADEON_RESET_MC; 1661 } 1662 1663 return reset_mask; 1664 } 1665 1666 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1667 { 1668 struct rv515_mc_save save; 1669 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1670 u32 tmp; 1671 1672 if (reset_mask == 0) 1673 return; 1674 1675 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1676 1677 r600_print_gpu_status_regs(rdev); 1678 1679 /* Disable CP parsing/prefetching */ 1680 if (rdev->family >= CHIP_RV770) 1681 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1682 else 1683 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1684 1685 /* disable the RLC */ 1686 WREG32(RLC_CNTL, 0); 1687 1688 if (reset_mask & RADEON_RESET_DMA) { 1689 /* Disable DMA */ 1690 tmp = RREG32(DMA_RB_CNTL); 1691 tmp &= ~DMA_RB_ENABLE; 1692 WREG32(DMA_RB_CNTL, tmp); 1693 } 1694 1695 mdelay(50); 1696 1697 rv515_mc_stop(rdev, &save); 1698 if (r600_mc_wait_for_idle(rdev)) { 1699 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1700 } 1701 1702 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1703 if (rdev->family >= CHIP_RV770) 1704 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1705 S_008020_SOFT_RESET_CB(1) | 1706 S_008020_SOFT_RESET_PA(1) | 1707 S_008020_SOFT_RESET_SC(1) | 1708 S_008020_SOFT_RESET_SPI(1) | 1709 S_008020_SOFT_RESET_SX(1) | 1710 S_008020_SOFT_RESET_SH(1) | 1711 S_008020_SOFT_RESET_TC(1) | 1712 S_008020_SOFT_RESET_TA(1) | 1713 S_008020_SOFT_RESET_VC(1) | 1714 S_008020_SOFT_RESET_VGT(1); 1715 else 1716 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1717 S_008020_SOFT_RESET_DB(1) | 1718 S_008020_SOFT_RESET_CB(1) | 1719 S_008020_SOFT_RESET_PA(1) | 1720 S_008020_SOFT_RESET_SC(1) | 1721 S_008020_SOFT_RESET_SMX(1) | 1722 S_008020_SOFT_RESET_SPI(1) | 1723 S_008020_SOFT_RESET_SX(1) | 1724 S_008020_SOFT_RESET_SH(1) | 1725 S_008020_SOFT_RESET_TC(1) | 1726 S_008020_SOFT_RESET_TA(1) | 1727 S_008020_SOFT_RESET_VC(1) | 1728 S_008020_SOFT_RESET_VGT(1); 1729 } 1730 1731 if (reset_mask & RADEON_RESET_CP) { 1732 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1733 S_008020_SOFT_RESET_VGT(1); 1734 1735 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1736 } 1737 1738 if (reset_mask & RADEON_RESET_DMA) { 1739 if (rdev->family >= CHIP_RV770) 1740 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1741 else 1742 srbm_soft_reset |= SOFT_RESET_DMA; 1743 } 1744 1745 if (reset_mask & RADEON_RESET_RLC) 1746 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1747 1748 if (reset_mask & RADEON_RESET_SEM) 1749 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1750 1751 if (reset_mask & RADEON_RESET_IH) 1752 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1753 1754 if (reset_mask & RADEON_RESET_GRBM) 1755 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1756 1757 if (!(rdev->flags & RADEON_IS_IGP)) { 1758 if (reset_mask & RADEON_RESET_MC) 1759 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1760 } 1761 1762 if (reset_mask & RADEON_RESET_VMC) 1763 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1764 1765 if (grbm_soft_reset) { 1766 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1767 tmp |= grbm_soft_reset; 1768 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1769 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1770 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1771 1772 udelay(50); 1773 1774 tmp &= ~grbm_soft_reset; 1775 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1776 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1777 } 1778 1779 if (srbm_soft_reset) { 1780 tmp = RREG32(SRBM_SOFT_RESET); 1781 tmp |= srbm_soft_reset; 1782 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1783 WREG32(SRBM_SOFT_RESET, tmp); 1784 tmp = RREG32(SRBM_SOFT_RESET); 1785 1786 udelay(50); 1787 1788 tmp &= ~srbm_soft_reset; 1789 WREG32(SRBM_SOFT_RESET, tmp); 1790 tmp = RREG32(SRBM_SOFT_RESET); 1791 } 1792 1793 /* Wait a little for things to settle down */ 1794 mdelay(1); 1795 1796 rv515_mc_resume(rdev, &save); 1797 udelay(50); 1798 1799 r600_print_gpu_status_regs(rdev); 1800 } 1801 1802 static void r600_gpu_pci_config_reset(struct radeon_device *rdev) 1803 { 1804 struct rv515_mc_save save; 1805 u32 tmp, i; 1806 1807 dev_info(rdev->dev, "GPU pci config reset\n"); 1808 1809 /* disable dpm? */ 1810 1811 /* Disable CP parsing/prefetching */ 1812 if (rdev->family >= CHIP_RV770) 1813 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1814 else 1815 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1816 1817 /* disable the RLC */ 1818 WREG32(RLC_CNTL, 0); 1819 1820 /* Disable DMA */ 1821 tmp = RREG32(DMA_RB_CNTL); 1822 tmp &= ~DMA_RB_ENABLE; 1823 WREG32(DMA_RB_CNTL, tmp); 1824 1825 mdelay(50); 1826 1827 /* set mclk/sclk to bypass */ 1828 if (rdev->family >= CHIP_RV770) 1829 rv770_set_clk_bypass_mode(rdev); 1830 /* disable BM */ 1831 pci_clear_master(rdev->pdev); 1832 /* disable mem access */ 1833 rv515_mc_stop(rdev, &save); 1834 if (r600_mc_wait_for_idle(rdev)) { 1835 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1836 } 1837 1838 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1839 tmp = RREG32(BUS_CNTL); 1840 tmp |= VGA_COHE_SPEC_TIMER_DIS; 1841 WREG32(BUS_CNTL, tmp); 1842 1843 tmp = RREG32(BIF_SCRATCH0); 1844 1845 /* reset */ 1846 radeon_pci_config_reset(rdev); 1847 mdelay(1); 1848 1849 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1850 tmp = SOFT_RESET_BIF; 1851 WREG32(SRBM_SOFT_RESET, tmp); 1852 mdelay(1); 1853 WREG32(SRBM_SOFT_RESET, 0); 1854 1855 /* wait for asic to come out of reset */ 1856 for (i = 0; i < rdev->usec_timeout; i++) { 1857 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) 1858 break; 1859 udelay(1); 1860 } 1861 } 1862 1863 int r600_asic_reset(struct radeon_device *rdev, bool hard) 1864 { 1865 u32 reset_mask; 1866 1867 if (hard) { 1868 r600_gpu_pci_config_reset(rdev); 1869 return 0; 1870 } 1871 1872 reset_mask = r600_gpu_check_soft_reset(rdev); 1873 1874 if (reset_mask) 1875 r600_set_bios_scratch_engine_hung(rdev, true); 1876 1877 /* try soft reset */ 1878 r600_gpu_soft_reset(rdev, reset_mask); 1879 1880 reset_mask = r600_gpu_check_soft_reset(rdev); 1881 1882 /* try pci config reset */ 1883 if (reset_mask && radeon_hard_reset) 1884 r600_gpu_pci_config_reset(rdev); 1885 1886 reset_mask = r600_gpu_check_soft_reset(rdev); 1887 1888 if (!reset_mask) 1889 r600_set_bios_scratch_engine_hung(rdev, false); 1890 1891 return 0; 1892 } 1893 1894 /** 1895 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1896 * 1897 * @rdev: radeon_device pointer 1898 * @ring: radeon_ring structure holding ring information 1899 * 1900 * Check if the GFX engine is locked up. 1901 * Returns true if the engine appears to be locked up, false if not. 1902 */ 1903 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1904 { 1905 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1906 1907 if (!(reset_mask & (RADEON_RESET_GFX | 1908 RADEON_RESET_COMPUTE | 1909 RADEON_RESET_CP))) { 1910 radeon_ring_lockup_update(rdev, ring); 1911 return false; 1912 } 1913 return radeon_ring_test_lockup(rdev, ring); 1914 } 1915 1916 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1917 u32 tiling_pipe_num, 1918 u32 max_rb_num, 1919 u32 total_max_rb_num, 1920 u32 disabled_rb_mask) 1921 { 1922 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1923 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1924 u32 data = 0, mask = 1 << (max_rb_num - 1); 1925 unsigned i, j; 1926 1927 /* mask out the RBs that don't exist on that asic */ 1928 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1929 /* make sure at least one RB is available */ 1930 if ((tmp & 0xff) != 0xff) 1931 disabled_rb_mask = tmp; 1932 1933 rendering_pipe_num = 1 << tiling_pipe_num; 1934 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1935 BUG_ON(rendering_pipe_num < req_rb_num); 1936 1937 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1938 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1939 1940 if (rdev->family <= CHIP_RV740) { 1941 /* r6xx/r7xx */ 1942 rb_num_width = 2; 1943 } else { 1944 /* eg+ */ 1945 rb_num_width = 4; 1946 } 1947 1948 for (i = 0; i < max_rb_num; i++) { 1949 if (!(mask & disabled_rb_mask)) { 1950 for (j = 0; j < pipe_rb_ratio; j++) { 1951 data <<= rb_num_width; 1952 data |= max_rb_num - i - 1; 1953 } 1954 if (pipe_rb_remain) { 1955 data <<= rb_num_width; 1956 data |= max_rb_num - i - 1; 1957 pipe_rb_remain--; 1958 } 1959 } 1960 mask >>= 1; 1961 } 1962 1963 return data; 1964 } 1965 1966 int r600_count_pipe_bits(uint32_t val) 1967 { 1968 return hweight32(val); 1969 } 1970 1971 static void r600_gpu_init(struct radeon_device *rdev) 1972 { 1973 u32 tiling_config; 1974 u32 ramcfg; 1975 u32 cc_gc_shader_pipe_config; 1976 u32 tmp; 1977 int i, j; 1978 u32 sq_config; 1979 u32 sq_gpr_resource_mgmt_1 = 0; 1980 u32 sq_gpr_resource_mgmt_2 = 0; 1981 u32 sq_thread_resource_mgmt = 0; 1982 u32 sq_stack_resource_mgmt_1 = 0; 1983 u32 sq_stack_resource_mgmt_2 = 0; 1984 u32 disabled_rb_mask; 1985 1986 rdev->config.r600.tiling_group_size = 256; 1987 switch (rdev->family) { 1988 case CHIP_R600: 1989 rdev->config.r600.max_pipes = 4; 1990 rdev->config.r600.max_tile_pipes = 8; 1991 rdev->config.r600.max_simds = 4; 1992 rdev->config.r600.max_backends = 4; 1993 rdev->config.r600.max_gprs = 256; 1994 rdev->config.r600.max_threads = 192; 1995 rdev->config.r600.max_stack_entries = 256; 1996 rdev->config.r600.max_hw_contexts = 8; 1997 rdev->config.r600.max_gs_threads = 16; 1998 rdev->config.r600.sx_max_export_size = 128; 1999 rdev->config.r600.sx_max_export_pos_size = 16; 2000 rdev->config.r600.sx_max_export_smx_size = 128; 2001 rdev->config.r600.sq_num_cf_insts = 2; 2002 break; 2003 case CHIP_RV630: 2004 case CHIP_RV635: 2005 rdev->config.r600.max_pipes = 2; 2006 rdev->config.r600.max_tile_pipes = 2; 2007 rdev->config.r600.max_simds = 3; 2008 rdev->config.r600.max_backends = 1; 2009 rdev->config.r600.max_gprs = 128; 2010 rdev->config.r600.max_threads = 192; 2011 rdev->config.r600.max_stack_entries = 128; 2012 rdev->config.r600.max_hw_contexts = 8; 2013 rdev->config.r600.max_gs_threads = 4; 2014 rdev->config.r600.sx_max_export_size = 128; 2015 rdev->config.r600.sx_max_export_pos_size = 16; 2016 rdev->config.r600.sx_max_export_smx_size = 128; 2017 rdev->config.r600.sq_num_cf_insts = 2; 2018 break; 2019 case CHIP_RV610: 2020 case CHIP_RV620: 2021 case CHIP_RS780: 2022 case CHIP_RS880: 2023 rdev->config.r600.max_pipes = 1; 2024 rdev->config.r600.max_tile_pipes = 1; 2025 rdev->config.r600.max_simds = 2; 2026 rdev->config.r600.max_backends = 1; 2027 rdev->config.r600.max_gprs = 128; 2028 rdev->config.r600.max_threads = 192; 2029 rdev->config.r600.max_stack_entries = 128; 2030 rdev->config.r600.max_hw_contexts = 4; 2031 rdev->config.r600.max_gs_threads = 4; 2032 rdev->config.r600.sx_max_export_size = 128; 2033 rdev->config.r600.sx_max_export_pos_size = 16; 2034 rdev->config.r600.sx_max_export_smx_size = 128; 2035 rdev->config.r600.sq_num_cf_insts = 1; 2036 break; 2037 case CHIP_RV670: 2038 rdev->config.r600.max_pipes = 4; 2039 rdev->config.r600.max_tile_pipes = 4; 2040 rdev->config.r600.max_simds = 4; 2041 rdev->config.r600.max_backends = 4; 2042 rdev->config.r600.max_gprs = 192; 2043 rdev->config.r600.max_threads = 192; 2044 rdev->config.r600.max_stack_entries = 256; 2045 rdev->config.r600.max_hw_contexts = 8; 2046 rdev->config.r600.max_gs_threads = 16; 2047 rdev->config.r600.sx_max_export_size = 128; 2048 rdev->config.r600.sx_max_export_pos_size = 16; 2049 rdev->config.r600.sx_max_export_smx_size = 128; 2050 rdev->config.r600.sq_num_cf_insts = 2; 2051 break; 2052 default: 2053 break; 2054 } 2055 2056 /* Initialize HDP */ 2057 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 2058 WREG32((0x2c14 + j), 0x00000000); 2059 WREG32((0x2c18 + j), 0x00000000); 2060 WREG32((0x2c1c + j), 0x00000000); 2061 WREG32((0x2c20 + j), 0x00000000); 2062 WREG32((0x2c24 + j), 0x00000000); 2063 } 2064 2065 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 2066 2067 /* Setup tiling */ 2068 tiling_config = 0; 2069 ramcfg = RREG32(RAMCFG); 2070 switch (rdev->config.r600.max_tile_pipes) { 2071 case 1: 2072 tiling_config |= PIPE_TILING(0); 2073 break; 2074 case 2: 2075 tiling_config |= PIPE_TILING(1); 2076 break; 2077 case 4: 2078 tiling_config |= PIPE_TILING(2); 2079 break; 2080 case 8: 2081 tiling_config |= PIPE_TILING(3); 2082 break; 2083 default: 2084 break; 2085 } 2086 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 2087 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2088 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2089 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 2090 2091 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 2092 if (tmp > 3) { 2093 tiling_config |= ROW_TILING(3); 2094 tiling_config |= SAMPLE_SPLIT(3); 2095 } else { 2096 tiling_config |= ROW_TILING(tmp); 2097 tiling_config |= SAMPLE_SPLIT(tmp); 2098 } 2099 tiling_config |= BANK_SWAPS(1); 2100 2101 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 2102 tmp = rdev->config.r600.max_simds - 2103 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 2104 rdev->config.r600.active_simds = tmp; 2105 2106 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 2107 tmp = 0; 2108 for (i = 0; i < rdev->config.r600.max_backends; i++) 2109 tmp |= (1 << i); 2110 /* if all the backends are disabled, fix it up here */ 2111 if ((disabled_rb_mask & tmp) == tmp) { 2112 for (i = 0; i < rdev->config.r600.max_backends; i++) 2113 disabled_rb_mask &= ~(1 << i); 2114 } 2115 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 2116 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 2117 R6XX_MAX_BACKENDS, disabled_rb_mask); 2118 tiling_config |= tmp << 16; 2119 rdev->config.r600.backend_map = tmp; 2120 2121 rdev->config.r600.tile_config = tiling_config; 2122 WREG32(GB_TILING_CONFIG, tiling_config); 2123 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 2124 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 2125 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 2126 2127 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 2128 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 2129 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 2130 2131 /* Setup some CP states */ 2132 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 2133 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 2134 2135 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 2136 SYNC_WALKER | SYNC_ALIGNER)); 2137 /* Setup various GPU states */ 2138 if (rdev->family == CHIP_RV670) 2139 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 2140 2141 tmp = RREG32(SX_DEBUG_1); 2142 tmp |= SMX_EVENT_RELEASE; 2143 if ((rdev->family > CHIP_R600)) 2144 tmp |= ENABLE_NEW_SMX_ADDRESS; 2145 WREG32(SX_DEBUG_1, tmp); 2146 2147 if (((rdev->family) == CHIP_R600) || 2148 ((rdev->family) == CHIP_RV630) || 2149 ((rdev->family) == CHIP_RV610) || 2150 ((rdev->family) == CHIP_RV620) || 2151 ((rdev->family) == CHIP_RS780) || 2152 ((rdev->family) == CHIP_RS880)) { 2153 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 2154 } else { 2155 WREG32(DB_DEBUG, 0); 2156 } 2157 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 2158 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 2159 2160 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2161 WREG32(VGT_NUM_INSTANCES, 0); 2162 2163 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 2164 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 2165 2166 tmp = RREG32(SQ_MS_FIFO_SIZES); 2167 if (((rdev->family) == CHIP_RV610) || 2168 ((rdev->family) == CHIP_RV620) || 2169 ((rdev->family) == CHIP_RS780) || 2170 ((rdev->family) == CHIP_RS880)) { 2171 tmp = (CACHE_FIFO_SIZE(0xa) | 2172 FETCH_FIFO_HIWATER(0xa) | 2173 DONE_FIFO_HIWATER(0xe0) | 2174 ALU_UPDATE_FIFO_HIWATER(0x8)); 2175 } else if (((rdev->family) == CHIP_R600) || 2176 ((rdev->family) == CHIP_RV630)) { 2177 tmp &= ~DONE_FIFO_HIWATER(0xff); 2178 tmp |= DONE_FIFO_HIWATER(0x4); 2179 } 2180 WREG32(SQ_MS_FIFO_SIZES, tmp); 2181 2182 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 2183 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 2184 */ 2185 sq_config = RREG32(SQ_CONFIG); 2186 sq_config &= ~(PS_PRIO(3) | 2187 VS_PRIO(3) | 2188 GS_PRIO(3) | 2189 ES_PRIO(3)); 2190 sq_config |= (DX9_CONSTS | 2191 VC_ENABLE | 2192 PS_PRIO(0) | 2193 VS_PRIO(1) | 2194 GS_PRIO(2) | 2195 ES_PRIO(3)); 2196 2197 if ((rdev->family) == CHIP_R600) { 2198 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 2199 NUM_VS_GPRS(124) | 2200 NUM_CLAUSE_TEMP_GPRS(4)); 2201 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 2202 NUM_ES_GPRS(0)); 2203 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 2204 NUM_VS_THREADS(48) | 2205 NUM_GS_THREADS(4) | 2206 NUM_ES_THREADS(4)); 2207 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 2208 NUM_VS_STACK_ENTRIES(128)); 2209 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 2210 NUM_ES_STACK_ENTRIES(0)); 2211 } else if (((rdev->family) == CHIP_RV610) || 2212 ((rdev->family) == CHIP_RV620) || 2213 ((rdev->family) == CHIP_RS780) || 2214 ((rdev->family) == CHIP_RS880)) { 2215 /* no vertex cache */ 2216 sq_config &= ~VC_ENABLE; 2217 2218 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2219 NUM_VS_GPRS(44) | 2220 NUM_CLAUSE_TEMP_GPRS(2)); 2221 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2222 NUM_ES_GPRS(17)); 2223 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2224 NUM_VS_THREADS(78) | 2225 NUM_GS_THREADS(4) | 2226 NUM_ES_THREADS(31)); 2227 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2228 NUM_VS_STACK_ENTRIES(40)); 2229 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2230 NUM_ES_STACK_ENTRIES(16)); 2231 } else if (((rdev->family) == CHIP_RV630) || 2232 ((rdev->family) == CHIP_RV635)) { 2233 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2234 NUM_VS_GPRS(44) | 2235 NUM_CLAUSE_TEMP_GPRS(2)); 2236 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 2237 NUM_ES_GPRS(18)); 2238 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2239 NUM_VS_THREADS(78) | 2240 NUM_GS_THREADS(4) | 2241 NUM_ES_THREADS(31)); 2242 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2243 NUM_VS_STACK_ENTRIES(40)); 2244 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2245 NUM_ES_STACK_ENTRIES(16)); 2246 } else if ((rdev->family) == CHIP_RV670) { 2247 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2248 NUM_VS_GPRS(44) | 2249 NUM_CLAUSE_TEMP_GPRS(2)); 2250 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2251 NUM_ES_GPRS(17)); 2252 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2253 NUM_VS_THREADS(78) | 2254 NUM_GS_THREADS(4) | 2255 NUM_ES_THREADS(31)); 2256 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 2257 NUM_VS_STACK_ENTRIES(64)); 2258 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 2259 NUM_ES_STACK_ENTRIES(64)); 2260 } 2261 2262 WREG32(SQ_CONFIG, sq_config); 2263 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2264 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2265 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2266 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2267 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2268 2269 if (((rdev->family) == CHIP_RV610) || 2270 ((rdev->family) == CHIP_RV620) || 2271 ((rdev->family) == CHIP_RS780) || 2272 ((rdev->family) == CHIP_RS880)) { 2273 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 2274 } else { 2275 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 2276 } 2277 2278 /* More default values. 2D/3D driver should adjust as needed */ 2279 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 2280 S1_X(0x4) | S1_Y(0xc))); 2281 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 2282 S1_X(0x2) | S1_Y(0x2) | 2283 S2_X(0xa) | S2_Y(0x6) | 2284 S3_X(0x6) | S3_Y(0xa))); 2285 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 2286 S1_X(0x4) | S1_Y(0xc) | 2287 S2_X(0x1) | S2_Y(0x6) | 2288 S3_X(0xa) | S3_Y(0xe))); 2289 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 2290 S5_X(0x0) | S5_Y(0x0) | 2291 S6_X(0xb) | S6_Y(0x4) | 2292 S7_X(0x7) | S7_Y(0x8))); 2293 2294 WREG32(VGT_STRMOUT_EN, 0); 2295 tmp = rdev->config.r600.max_pipes * 16; 2296 switch (rdev->family) { 2297 case CHIP_RV610: 2298 case CHIP_RV620: 2299 case CHIP_RS780: 2300 case CHIP_RS880: 2301 tmp += 32; 2302 break; 2303 case CHIP_RV670: 2304 tmp += 128; 2305 break; 2306 default: 2307 break; 2308 } 2309 if (tmp > 256) { 2310 tmp = 256; 2311 } 2312 WREG32(VGT_ES_PER_GS, 128); 2313 WREG32(VGT_GS_PER_ES, tmp); 2314 WREG32(VGT_GS_PER_VS, 2); 2315 WREG32(VGT_GS_VERTEX_REUSE, 16); 2316 2317 /* more default values. 2D/3D driver should adjust as needed */ 2318 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2319 WREG32(VGT_STRMOUT_EN, 0); 2320 WREG32(SX_MISC, 0); 2321 WREG32(PA_SC_MODE_CNTL, 0); 2322 WREG32(PA_SC_AA_CONFIG, 0); 2323 WREG32(PA_SC_LINE_STIPPLE, 0); 2324 WREG32(SPI_INPUT_Z, 0); 2325 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2326 WREG32(CB_COLOR7_FRAG, 0); 2327 2328 /* Clear render buffer base addresses */ 2329 WREG32(CB_COLOR0_BASE, 0); 2330 WREG32(CB_COLOR1_BASE, 0); 2331 WREG32(CB_COLOR2_BASE, 0); 2332 WREG32(CB_COLOR3_BASE, 0); 2333 WREG32(CB_COLOR4_BASE, 0); 2334 WREG32(CB_COLOR5_BASE, 0); 2335 WREG32(CB_COLOR6_BASE, 0); 2336 WREG32(CB_COLOR7_BASE, 0); 2337 WREG32(CB_COLOR7_FRAG, 0); 2338 2339 switch (rdev->family) { 2340 case CHIP_RV610: 2341 case CHIP_RV620: 2342 case CHIP_RS780: 2343 case CHIP_RS880: 2344 tmp = TC_L2_SIZE(8); 2345 break; 2346 case CHIP_RV630: 2347 case CHIP_RV635: 2348 tmp = TC_L2_SIZE(4); 2349 break; 2350 case CHIP_R600: 2351 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2352 break; 2353 default: 2354 tmp = TC_L2_SIZE(0); 2355 break; 2356 } 2357 WREG32(TC_CNTL, tmp); 2358 2359 tmp = RREG32(HDP_HOST_PATH_CNTL); 2360 WREG32(HDP_HOST_PATH_CNTL, tmp); 2361 2362 tmp = RREG32(ARB_POP); 2363 tmp |= ENABLE_TC128; 2364 WREG32(ARB_POP, tmp); 2365 2366 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2367 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2368 NUM_CLIP_SEQ(3))); 2369 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2370 WREG32(VC_ENHANCE, 0); 2371 } 2372 2373 2374 /* 2375 * Indirect registers accessor 2376 */ 2377 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2378 { 2379 u32 r; 2380 2381 lockmgr(&rdev->pciep_idx_lock, LK_EXCLUSIVE); 2382 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2383 (void)RREG32(PCIE_PORT_INDEX); 2384 r = RREG32(PCIE_PORT_DATA); 2385 lockmgr(&rdev->pciep_idx_lock, LK_RELEASE); 2386 return r; 2387 } 2388 2389 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2390 { 2391 lockmgr(&rdev->pciep_idx_lock, LK_EXCLUSIVE); 2392 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2393 (void)RREG32(PCIE_PORT_INDEX); 2394 WREG32(PCIE_PORT_DATA, (v)); 2395 (void)RREG32(PCIE_PORT_DATA); 2396 lockmgr(&rdev->pciep_idx_lock, LK_RELEASE); 2397 } 2398 2399 /* 2400 * CP & Ring 2401 */ 2402 void r600_cp_stop(struct radeon_device *rdev) 2403 { 2404 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2405 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2406 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2407 WREG32(SCRATCH_UMSK, 0); 2408 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2409 } 2410 2411 int r600_init_microcode(struct radeon_device *rdev) 2412 { 2413 const char *chip_name; 2414 const char *rlc_chip_name; 2415 const char *smc_chip_name = "RV770"; 2416 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; 2417 char fw_name[30]; 2418 int err; 2419 2420 DRM_DEBUG("\n"); 2421 2422 switch (rdev->family) { 2423 case CHIP_R600: 2424 chip_name = "R600"; 2425 rlc_chip_name = "R600"; 2426 break; 2427 case CHIP_RV610: 2428 chip_name = "RV610"; 2429 rlc_chip_name = "R600"; 2430 break; 2431 case CHIP_RV630: 2432 chip_name = "RV630"; 2433 rlc_chip_name = "R600"; 2434 break; 2435 case CHIP_RV620: 2436 chip_name = "RV620"; 2437 rlc_chip_name = "R600"; 2438 break; 2439 case CHIP_RV635: 2440 chip_name = "RV635"; 2441 rlc_chip_name = "R600"; 2442 break; 2443 case CHIP_RV670: 2444 chip_name = "RV670"; 2445 rlc_chip_name = "R600"; 2446 break; 2447 case CHIP_RS780: 2448 case CHIP_RS880: 2449 chip_name = "RS780"; 2450 rlc_chip_name = "R600"; 2451 break; 2452 case CHIP_RV770: 2453 chip_name = "RV770"; 2454 rlc_chip_name = "R700"; 2455 smc_chip_name = "RV770"; 2456 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); 2457 break; 2458 case CHIP_RV730: 2459 chip_name = "RV730"; 2460 rlc_chip_name = "R700"; 2461 smc_chip_name = "RV730"; 2462 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); 2463 break; 2464 case CHIP_RV710: 2465 chip_name = "RV710"; 2466 rlc_chip_name = "R700"; 2467 smc_chip_name = "RV710"; 2468 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); 2469 break; 2470 case CHIP_RV740: 2471 chip_name = "RV730"; 2472 rlc_chip_name = "R700"; 2473 smc_chip_name = "RV740"; 2474 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); 2475 break; 2476 case CHIP_CEDAR: 2477 chip_name = "CEDAR"; 2478 rlc_chip_name = "CEDAR"; 2479 smc_chip_name = "CEDAR"; 2480 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); 2481 break; 2482 case CHIP_REDWOOD: 2483 chip_name = "REDWOOD"; 2484 rlc_chip_name = "REDWOOD"; 2485 smc_chip_name = "REDWOOD"; 2486 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); 2487 break; 2488 case CHIP_JUNIPER: 2489 chip_name = "JUNIPER"; 2490 rlc_chip_name = "JUNIPER"; 2491 smc_chip_name = "JUNIPER"; 2492 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); 2493 break; 2494 case CHIP_CYPRESS: 2495 case CHIP_HEMLOCK: 2496 chip_name = "CYPRESS"; 2497 rlc_chip_name = "CYPRESS"; 2498 smc_chip_name = "CYPRESS"; 2499 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); 2500 break; 2501 case CHIP_PALM: 2502 chip_name = "PALM"; 2503 rlc_chip_name = "SUMO"; 2504 break; 2505 case CHIP_SUMO: 2506 chip_name = "SUMO"; 2507 rlc_chip_name = "SUMO"; 2508 break; 2509 case CHIP_SUMO2: 2510 chip_name = "SUMO2"; 2511 rlc_chip_name = "SUMO"; 2512 break; 2513 default: BUG(); 2514 } 2515 2516 if (rdev->family >= CHIP_CEDAR) { 2517 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2518 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2519 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2520 } else if (rdev->family >= CHIP_RV770) { 2521 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2522 me_req_size = R700_PM4_UCODE_SIZE * 4; 2523 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2524 } else { 2525 pfp_req_size = R600_PFP_UCODE_SIZE * 4; 2526 me_req_size = R600_PM4_UCODE_SIZE * 12; 2527 rlc_req_size = R600_RLC_UCODE_SIZE * 4; 2528 } 2529 2530 DRM_INFO("Loading %s Microcode\n", chip_name); 2531 2532 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name); 2533 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 2534 if (err) 2535 goto out; 2536 if (rdev->pfp_fw->datasize != pfp_req_size) { 2537 printk(KERN_ERR 2538 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2539 rdev->pfp_fw->datasize, fw_name); 2540 err = -EINVAL; 2541 goto out; 2542 } 2543 2544 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name); 2545 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 2546 if (err) 2547 goto out; 2548 if (rdev->me_fw->datasize != me_req_size) { 2549 printk(KERN_ERR 2550 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2551 rdev->me_fw->datasize, fw_name); 2552 err = -EINVAL; 2553 } 2554 2555 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", rlc_chip_name); 2556 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 2557 if (err) 2558 goto out; 2559 if (rdev->rlc_fw->datasize != rlc_req_size) { 2560 printk(KERN_ERR 2561 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2562 rdev->rlc_fw->datasize, fw_name); 2563 err = -EINVAL; 2564 } 2565 2566 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2567 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", smc_chip_name); 2568 2569 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2570 if (err) { 2571 printk(KERN_ERR 2572 "smc: error loading firmware \"%s\"\n", 2573 fw_name); 2574 release_firmware(rdev->smc_fw); 2575 rdev->smc_fw = NULL; 2576 err = 0; 2577 } else if (rdev->smc_fw->datasize != smc_req_size) { 2578 printk(KERN_ERR 2579 "smc: Bogus length %zu in firmware \"%s\"\n", 2580 rdev->smc_fw->datasize, fw_name); 2581 err = -EINVAL; 2582 } 2583 } 2584 2585 out: 2586 if (err) { 2587 if (err != -EINVAL) 2588 pr_err("r600_cp: Failed to load firmware \"%s\"\n", 2589 fw_name); 2590 release_firmware(rdev->pfp_fw); 2591 rdev->pfp_fw = NULL; 2592 release_firmware(rdev->me_fw); 2593 rdev->me_fw = NULL; 2594 release_firmware(rdev->rlc_fw); 2595 rdev->rlc_fw = NULL; 2596 release_firmware(rdev->smc_fw); 2597 rdev->smc_fw = NULL; 2598 } 2599 return err; 2600 } 2601 2602 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 2603 struct radeon_ring *ring) 2604 { 2605 u32 rptr; 2606 2607 if (rdev->wb.enabled) 2608 rptr = rdev->wb.wb[ring->rptr_offs/4]; 2609 else 2610 rptr = RREG32(R600_CP_RB_RPTR); 2611 2612 return rptr; 2613 } 2614 2615 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 2616 struct radeon_ring *ring) 2617 { 2618 return RREG32(R600_CP_RB_WPTR); 2619 } 2620 2621 void r600_gfx_set_wptr(struct radeon_device *rdev, 2622 struct radeon_ring *ring) 2623 { 2624 WREG32(R600_CP_RB_WPTR, ring->wptr); 2625 (void)RREG32(R600_CP_RB_WPTR); 2626 } 2627 2628 /** 2629 * r600_fini_microcode - drop the firmwares image references 2630 * 2631 * @rdev: radeon_device pointer 2632 * 2633 * Drop the pfp, me and rlc firmwares image references. 2634 * Called at driver shutdown. 2635 */ 2636 void r600_fini_microcode(struct radeon_device *rdev) 2637 { 2638 release_firmware(rdev->pfp_fw); 2639 rdev->pfp_fw = NULL; 2640 release_firmware(rdev->me_fw); 2641 rdev->me_fw = NULL; 2642 release_firmware(rdev->rlc_fw); 2643 rdev->rlc_fw = NULL; 2644 release_firmware(rdev->smc_fw); 2645 rdev->smc_fw = NULL; 2646 } 2647 2648 static int r600_cp_load_microcode(struct radeon_device *rdev) 2649 { 2650 const __be32 *fw_data; 2651 int i; 2652 2653 if (!rdev->me_fw || !rdev->pfp_fw) 2654 return -EINVAL; 2655 2656 r600_cp_stop(rdev); 2657 2658 WREG32(CP_RB_CNTL, 2659 #ifdef __BIG_ENDIAN 2660 BUF_SWAP_32BIT | 2661 #endif 2662 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2663 2664 /* Reset cp */ 2665 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2666 RREG32(GRBM_SOFT_RESET); 2667 mdelay(15); 2668 WREG32(GRBM_SOFT_RESET, 0); 2669 2670 WREG32(CP_ME_RAM_WADDR, 0); 2671 2672 fw_data = (const __be32 *)rdev->me_fw->data; 2673 WREG32(CP_ME_RAM_WADDR, 0); 2674 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) 2675 WREG32(CP_ME_RAM_DATA, 2676 be32_to_cpup(fw_data++)); 2677 2678 fw_data = (const __be32 *)rdev->pfp_fw->data; 2679 WREG32(CP_PFP_UCODE_ADDR, 0); 2680 for (i = 0; i < R600_PFP_UCODE_SIZE; i++) 2681 WREG32(CP_PFP_UCODE_DATA, 2682 be32_to_cpup(fw_data++)); 2683 2684 WREG32(CP_PFP_UCODE_ADDR, 0); 2685 WREG32(CP_ME_RAM_WADDR, 0); 2686 WREG32(CP_ME_RAM_RADDR, 0); 2687 return 0; 2688 } 2689 2690 int r600_cp_start(struct radeon_device *rdev) 2691 { 2692 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2693 int r; 2694 uint32_t cp_me; 2695 2696 r = radeon_ring_lock(rdev, ring, 7); 2697 if (r) { 2698 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2699 return r; 2700 } 2701 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2702 radeon_ring_write(ring, 0x1); 2703 if (rdev->family >= CHIP_RV770) { 2704 radeon_ring_write(ring, 0x0); 2705 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2706 } else { 2707 radeon_ring_write(ring, 0x3); 2708 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2709 } 2710 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2711 radeon_ring_write(ring, 0); 2712 radeon_ring_write(ring, 0); 2713 radeon_ring_unlock_commit(rdev, ring, false); 2714 2715 cp_me = 0xff; 2716 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2717 return 0; 2718 } 2719 2720 int r600_cp_resume(struct radeon_device *rdev) 2721 { 2722 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2723 u32 tmp; 2724 u32 rb_bufsz; 2725 int r; 2726 2727 /* Reset cp */ 2728 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2729 RREG32(GRBM_SOFT_RESET); 2730 mdelay(15); 2731 WREG32(GRBM_SOFT_RESET, 0); 2732 2733 /* Set ring buffer size */ 2734 rb_bufsz = order_base_2(ring->ring_size / 8); 2735 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2736 #ifdef __BIG_ENDIAN 2737 tmp |= BUF_SWAP_32BIT; 2738 #endif 2739 WREG32(CP_RB_CNTL, tmp); 2740 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2741 2742 /* Set the write pointer delay */ 2743 WREG32(CP_RB_WPTR_DELAY, 0); 2744 2745 /* Initialize the ring buffer's read and write pointers */ 2746 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2747 WREG32(CP_RB_RPTR_WR, 0); 2748 ring->wptr = 0; 2749 WREG32(CP_RB_WPTR, ring->wptr); 2750 2751 /* set the wb address whether it's enabled or not */ 2752 WREG32(CP_RB_RPTR_ADDR, 2753 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2754 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2755 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2756 2757 if (rdev->wb.enabled) 2758 WREG32(SCRATCH_UMSK, 0xff); 2759 else { 2760 tmp |= RB_NO_UPDATE; 2761 WREG32(SCRATCH_UMSK, 0); 2762 } 2763 2764 mdelay(1); 2765 WREG32(CP_RB_CNTL, tmp); 2766 2767 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2768 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2769 2770 r600_cp_start(rdev); 2771 ring->ready = true; 2772 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2773 if (r) { 2774 ring->ready = false; 2775 return r; 2776 } 2777 2778 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2779 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2780 2781 return 0; 2782 } 2783 2784 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2785 { 2786 u32 rb_bufsz; 2787 int r; 2788 2789 /* Align ring size */ 2790 rb_bufsz = order_base_2(ring_size / 8); 2791 ring_size = (1 << (rb_bufsz + 1)) * 4; 2792 ring->ring_size = ring_size; 2793 ring->align_mask = 16 - 1; 2794 2795 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2796 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2797 if (r) { 2798 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2799 ring->rptr_save_reg = 0; 2800 } 2801 } 2802 } 2803 2804 void r600_cp_fini(struct radeon_device *rdev) 2805 { 2806 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2807 r600_cp_stop(rdev); 2808 radeon_ring_fini(rdev, ring); 2809 radeon_scratch_free(rdev, ring->rptr_save_reg); 2810 } 2811 2812 /* 2813 * GPU scratch registers helpers function. 2814 */ 2815 void r600_scratch_init(struct radeon_device *rdev) 2816 { 2817 int i; 2818 2819 rdev->scratch.num_reg = 7; 2820 rdev->scratch.reg_base = SCRATCH_REG0; 2821 for (i = 0; i < rdev->scratch.num_reg; i++) { 2822 rdev->scratch.free[i] = true; 2823 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2824 } 2825 } 2826 2827 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2828 { 2829 uint32_t scratch; 2830 uint32_t tmp = 0; 2831 unsigned i; 2832 int r; 2833 2834 r = radeon_scratch_get(rdev, &scratch); 2835 if (r) { 2836 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2837 return r; 2838 } 2839 WREG32(scratch, 0xCAFEDEAD); 2840 r = radeon_ring_lock(rdev, ring, 3); 2841 if (r) { 2842 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2843 radeon_scratch_free(rdev, scratch); 2844 return r; 2845 } 2846 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2847 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2848 radeon_ring_write(ring, 0xDEADBEEF); 2849 radeon_ring_unlock_commit(rdev, ring, false); 2850 for (i = 0; i < rdev->usec_timeout; i++) { 2851 tmp = RREG32(scratch); 2852 if (tmp == 0xDEADBEEF) 2853 break; 2854 DRM_UDELAY(1); 2855 } 2856 if (i < rdev->usec_timeout) { 2857 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2858 } else { 2859 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2860 ring->idx, scratch, tmp); 2861 r = -EINVAL; 2862 } 2863 radeon_scratch_free(rdev, scratch); 2864 return r; 2865 } 2866 2867 /* 2868 * CP fences/semaphores 2869 */ 2870 2871 void r600_fence_ring_emit(struct radeon_device *rdev, 2872 struct radeon_fence *fence) 2873 { 2874 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2875 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | 2876 PACKET3_SH_ACTION_ENA; 2877 2878 if (rdev->family >= CHIP_RV770) 2879 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; 2880 2881 if (rdev->wb.use_event) { 2882 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2883 /* flush read cache over gart */ 2884 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2885 radeon_ring_write(ring, cp_coher_cntl); 2886 radeon_ring_write(ring, 0xFFFFFFFF); 2887 radeon_ring_write(ring, 0); 2888 radeon_ring_write(ring, 10); /* poll interval */ 2889 /* EVENT_WRITE_EOP - flush caches, send int */ 2890 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2891 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2892 radeon_ring_write(ring, lower_32_bits(addr)); 2893 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2894 radeon_ring_write(ring, fence->seq); 2895 radeon_ring_write(ring, 0); 2896 } else { 2897 /* flush read cache over gart */ 2898 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2899 radeon_ring_write(ring, cp_coher_cntl); 2900 radeon_ring_write(ring, 0xFFFFFFFF); 2901 radeon_ring_write(ring, 0); 2902 radeon_ring_write(ring, 10); /* poll interval */ 2903 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2904 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2905 /* wait for 3D idle clean */ 2906 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2907 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2908 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2909 /* Emit fence sequence & fire IRQ */ 2910 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2911 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2912 radeon_ring_write(ring, fence->seq); 2913 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2914 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2915 radeon_ring_write(ring, RB_INT_STAT); 2916 } 2917 } 2918 2919 /** 2920 * r600_semaphore_ring_emit - emit a semaphore on the CP ring 2921 * 2922 * @rdev: radeon_device pointer 2923 * @ring: radeon ring buffer object 2924 * @semaphore: radeon semaphore object 2925 * @emit_wait: Is this a sempahore wait? 2926 * 2927 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP 2928 * from running ahead of semaphore waits. 2929 */ 2930 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 2931 struct radeon_ring *ring, 2932 struct radeon_semaphore *semaphore, 2933 bool emit_wait) 2934 { 2935 uint64_t addr = semaphore->gpu_addr; 2936 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2937 2938 if (rdev->family < CHIP_CAYMAN) 2939 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2940 2941 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2942 radeon_ring_write(ring, lower_32_bits(addr)); 2943 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2944 2945 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */ 2946 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { 2947 /* Prevent the PFP from running ahead of the semaphore wait */ 2948 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2949 radeon_ring_write(ring, 0x0); 2950 } 2951 2952 return true; 2953 } 2954 2955 /** 2956 * r600_copy_cpdma - copy pages using the CP DMA engine 2957 * 2958 * @rdev: radeon_device pointer 2959 * @src_offset: src GPU address 2960 * @dst_offset: dst GPU address 2961 * @num_gpu_pages: number of GPU pages to xfer 2962 * @fence: radeon fence object 2963 * 2964 * Copy GPU paging using the CP DMA engine (r6xx+). 2965 * Used by the radeon ttm implementation to move pages if 2966 * registered as the asic copy callback. 2967 */ 2968 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, 2969 uint64_t src_offset, uint64_t dst_offset, 2970 unsigned num_gpu_pages, 2971 struct reservation_object *resv) 2972 { 2973 struct radeon_fence *fence; 2974 struct radeon_sync sync; 2975 int ring_index = rdev->asic->copy.blit_ring_index; 2976 struct radeon_ring *ring = &rdev->ring[ring_index]; 2977 u32 size_in_bytes, cur_size_in_bytes, tmp; 2978 int i, num_loops; 2979 int r = 0; 2980 2981 radeon_sync_create(&sync); 2982 2983 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 2984 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 2985 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); 2986 if (r) { 2987 DRM_ERROR("radeon: moving bo (%d).\n", r); 2988 radeon_sync_free(rdev, &sync, NULL); 2989 return ERR_PTR(r); 2990 } 2991 2992 radeon_sync_resv(rdev, &sync, resv, false); 2993 radeon_sync_rings(rdev, &sync, ring->idx); 2994 2995 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2996 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2997 radeon_ring_write(ring, WAIT_3D_IDLE_bit); 2998 for (i = 0; i < num_loops; i++) { 2999 cur_size_in_bytes = size_in_bytes; 3000 if (cur_size_in_bytes > 0x1fffff) 3001 cur_size_in_bytes = 0x1fffff; 3002 size_in_bytes -= cur_size_in_bytes; 3003 tmp = upper_32_bits(src_offset) & 0xff; 3004 if (size_in_bytes == 0) 3005 tmp |= PACKET3_CP_DMA_CP_SYNC; 3006 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); 3007 radeon_ring_write(ring, lower_32_bits(src_offset)); 3008 radeon_ring_write(ring, tmp); 3009 radeon_ring_write(ring, lower_32_bits(dst_offset)); 3010 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 3011 radeon_ring_write(ring, cur_size_in_bytes); 3012 src_offset += cur_size_in_bytes; 3013 dst_offset += cur_size_in_bytes; 3014 } 3015 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3016 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3017 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); 3018 3019 r = radeon_fence_emit(rdev, &fence, ring->idx); 3020 if (r) { 3021 radeon_ring_unlock_undo(rdev, ring); 3022 radeon_sync_free(rdev, &sync, NULL); 3023 return ERR_PTR(r); 3024 } 3025 3026 radeon_ring_unlock_commit(rdev, ring, false); 3027 radeon_sync_free(rdev, &sync, fence); 3028 3029 return fence; 3030 } 3031 3032 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 3033 uint32_t tiling_flags, uint32_t pitch, 3034 uint32_t offset, uint32_t obj_size) 3035 { 3036 /* FIXME: implement */ 3037 return 0; 3038 } 3039 3040 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 3041 { 3042 /* FIXME: implement */ 3043 } 3044 3045 static void r600_uvd_init(struct radeon_device *rdev) 3046 { 3047 int r; 3048 3049 if (!rdev->has_uvd) 3050 return; 3051 3052 r = radeon_uvd_init(rdev); 3053 if (r) { 3054 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); 3055 /* 3056 * At this point rdev->uvd.vcpu_bo is NULL which trickles down 3057 * to early fails uvd_v1_0_resume() and thus nothing happens 3058 * there. So it is pointless to try to go through that code 3059 * hence why we disable uvd here. 3060 */ 3061 rdev->has_uvd = 0; 3062 return; 3063 } 3064 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 3065 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); 3066 } 3067 3068 static void r600_uvd_start(struct radeon_device *rdev) 3069 { 3070 int r; 3071 3072 if (!rdev->has_uvd) 3073 return; 3074 3075 r = uvd_v1_0_resume(rdev); 3076 if (r) { 3077 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); 3078 goto error; 3079 } 3080 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); 3081 if (r) { 3082 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); 3083 goto error; 3084 } 3085 return; 3086 3087 error: 3088 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 3089 } 3090 3091 static void r600_uvd_resume(struct radeon_device *rdev) 3092 { 3093 struct radeon_ring *ring; 3094 int r; 3095 3096 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) 3097 return; 3098 3099 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 3100 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); 3101 if (r) { 3102 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); 3103 return; 3104 } 3105 r = uvd_v1_0_init(rdev); 3106 if (r) { 3107 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); 3108 return; 3109 } 3110 } 3111 3112 static int r600_startup(struct radeon_device *rdev) 3113 { 3114 struct radeon_ring *ring; 3115 int r; 3116 3117 /* enable pcie gen2 link */ 3118 r600_pcie_gen2_enable(rdev); 3119 3120 /* scratch needs to be initialized before MC */ 3121 r = r600_vram_scratch_init(rdev); 3122 if (r) 3123 return r; 3124 3125 r600_mc_program(rdev); 3126 3127 if (rdev->flags & RADEON_IS_AGP) { 3128 r600_agp_enable(rdev); 3129 } else { 3130 r = r600_pcie_gart_enable(rdev); 3131 if (r) 3132 return r; 3133 } 3134 r600_gpu_init(rdev); 3135 3136 /* allocate wb buffer */ 3137 r = radeon_wb_init(rdev); 3138 if (r) 3139 return r; 3140 3141 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3142 if (r) { 3143 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3144 return r; 3145 } 3146 3147 r600_uvd_start(rdev); 3148 3149 /* Enable IRQ */ 3150 if (!rdev->irq.installed) { 3151 r = radeon_irq_kms_init(rdev); 3152 if (r) 3153 return r; 3154 } 3155 3156 r = r600_irq_init(rdev); 3157 if (r) { 3158 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3159 radeon_irq_kms_fini(rdev); 3160 return r; 3161 } 3162 r600_irq_set(rdev); 3163 3164 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3165 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3166 RADEON_CP_PACKET2); 3167 if (r) 3168 return r; 3169 3170 r = r600_cp_load_microcode(rdev); 3171 if (r) 3172 return r; 3173 r = r600_cp_resume(rdev); 3174 if (r) 3175 return r; 3176 3177 r600_uvd_resume(rdev); 3178 3179 r = radeon_ib_pool_init(rdev); 3180 if (r) { 3181 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3182 return r; 3183 } 3184 3185 r = radeon_audio_init(rdev); 3186 if (r) { 3187 DRM_ERROR("radeon: audio init failed\n"); 3188 return r; 3189 } 3190 3191 return 0; 3192 } 3193 3194 void r600_vga_set_state(struct radeon_device *rdev, bool state) 3195 { 3196 uint32_t temp; 3197 3198 temp = RREG32(CONFIG_CNTL); 3199 if (state == false) { 3200 temp &= ~(1<<0); 3201 temp |= (1<<1); 3202 } else { 3203 temp &= ~(1<<1); 3204 } 3205 WREG32(CONFIG_CNTL, temp); 3206 } 3207 3208 int r600_resume(struct radeon_device *rdev) 3209 { 3210 int r; 3211 3212 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 3213 * posting will perform necessary task to bring back GPU into good 3214 * shape. 3215 */ 3216 /* post card */ 3217 atom_asic_init(rdev->mode_info.atom_context); 3218 3219 if (rdev->pm.pm_method == PM_METHOD_DPM) 3220 radeon_pm_resume(rdev); 3221 3222 rdev->accel_working = true; 3223 r = r600_startup(rdev); 3224 if (r) { 3225 DRM_ERROR("r600 startup failed on resume\n"); 3226 rdev->accel_working = false; 3227 return r; 3228 } 3229 3230 return r; 3231 } 3232 3233 int r600_suspend(struct radeon_device *rdev) 3234 { 3235 radeon_pm_suspend(rdev); 3236 radeon_audio_fini(rdev); 3237 r600_cp_stop(rdev); 3238 if (rdev->has_uvd) { 3239 uvd_v1_0_fini(rdev); 3240 radeon_uvd_suspend(rdev); 3241 } 3242 r600_irq_suspend(rdev); 3243 radeon_wb_disable(rdev); 3244 r600_pcie_gart_disable(rdev); 3245 3246 return 0; 3247 } 3248 3249 /* Plan is to move initialization in that function and use 3250 * helper function so that radeon_device_init pretty much 3251 * do nothing more than calling asic specific function. This 3252 * should also allow to remove a bunch of callback function 3253 * like vram_info. 3254 */ 3255 int r600_init(struct radeon_device *rdev) 3256 { 3257 int r; 3258 3259 if (r600_debugfs_mc_info_init(rdev)) { 3260 DRM_ERROR("Failed to register debugfs file for mc !\n"); 3261 } 3262 /* Read BIOS */ 3263 if (!radeon_get_bios(rdev)) { 3264 if (ASIC_IS_AVIVO(rdev)) 3265 return -EINVAL; 3266 } 3267 /* Must be an ATOMBIOS */ 3268 if (!rdev->is_atom_bios) { 3269 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3270 return -EINVAL; 3271 } 3272 r = radeon_atombios_init(rdev); 3273 if (r) 3274 return r; 3275 /* Post card if necessary */ 3276 if (!radeon_card_posted(rdev)) { 3277 if (!rdev->bios) { 3278 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3279 return -EINVAL; 3280 } 3281 DRM_INFO("GPU not posted. posting now...\n"); 3282 atom_asic_init(rdev->mode_info.atom_context); 3283 } 3284 /* Initialize scratch registers */ 3285 r600_scratch_init(rdev); 3286 /* Initialize surface registers */ 3287 radeon_surface_init(rdev); 3288 /* Initialize clocks */ 3289 radeon_get_clock_info(rdev->ddev); 3290 /* Fence driver */ 3291 r = radeon_fence_driver_init(rdev); 3292 if (r) 3293 return r; 3294 if (rdev->flags & RADEON_IS_AGP) { 3295 r = radeon_agp_init(rdev); 3296 if (r) 3297 radeon_agp_disable(rdev); 3298 } 3299 r = r600_mc_init(rdev); 3300 if (r) 3301 return r; 3302 /* Memory manager */ 3303 r = radeon_bo_init(rdev); 3304 if (r) 3305 return r; 3306 3307 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3308 r = r600_init_microcode(rdev); 3309 if (r) { 3310 DRM_ERROR("Failed to load firmware!\n"); 3311 return r; 3312 } 3313 } 3314 3315 /* Initialize power management */ 3316 radeon_pm_init(rdev); 3317 3318 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3319 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3320 3321 r600_uvd_init(rdev); 3322 3323 rdev->ih.ring_obj = NULL; 3324 r600_ih_ring_init(rdev, 64 * 1024); 3325 3326 r = r600_pcie_gart_init(rdev); 3327 if (r) 3328 return r; 3329 3330 rdev->accel_working = true; 3331 r = r600_startup(rdev); 3332 if (r) { 3333 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3334 r600_cp_fini(rdev); 3335 r600_irq_fini(rdev); 3336 radeon_wb_fini(rdev); 3337 radeon_ib_pool_fini(rdev); 3338 radeon_irq_kms_fini(rdev); 3339 r600_pcie_gart_fini(rdev); 3340 rdev->accel_working = false; 3341 } 3342 3343 return 0; 3344 } 3345 3346 void r600_fini(struct radeon_device *rdev) 3347 { 3348 radeon_pm_fini(rdev); 3349 radeon_audio_fini(rdev); 3350 r600_cp_fini(rdev); 3351 r600_irq_fini(rdev); 3352 if (rdev->has_uvd) { 3353 uvd_v1_0_fini(rdev); 3354 radeon_uvd_fini(rdev); 3355 } 3356 radeon_wb_fini(rdev); 3357 radeon_ib_pool_fini(rdev); 3358 radeon_irq_kms_fini(rdev); 3359 r600_pcie_gart_fini(rdev); 3360 r600_vram_scratch_fini(rdev); 3361 radeon_agp_fini(rdev); 3362 radeon_gem_fini(rdev); 3363 radeon_fence_driver_fini(rdev); 3364 radeon_bo_fini(rdev); 3365 radeon_atombios_fini(rdev); 3366 r600_fini_microcode(rdev); 3367 kfree(rdev->bios); 3368 rdev->bios = NULL; 3369 } 3370 3371 3372 /* 3373 * CS stuff 3374 */ 3375 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3376 { 3377 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3378 u32 next_rptr; 3379 3380 if (ring->rptr_save_reg) { 3381 next_rptr = ring->wptr + 3 + 4; 3382 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3383 radeon_ring_write(ring, ((ring->rptr_save_reg - 3384 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3385 radeon_ring_write(ring, next_rptr); 3386 } else if (rdev->wb.enabled) { 3387 next_rptr = ring->wptr + 5 + 4; 3388 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3389 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3390 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3391 radeon_ring_write(ring, next_rptr); 3392 radeon_ring_write(ring, 0); 3393 } 3394 3395 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3396 radeon_ring_write(ring, 3397 #ifdef __BIG_ENDIAN 3398 (2 << 0) | 3399 #endif 3400 (ib->gpu_addr & 0xFFFFFFFC)); 3401 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3402 radeon_ring_write(ring, ib->length_dw); 3403 } 3404 3405 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3406 { 3407 struct radeon_ib ib; 3408 uint32_t scratch; 3409 uint32_t tmp = 0; 3410 unsigned i; 3411 int r; 3412 3413 r = radeon_scratch_get(rdev, &scratch); 3414 if (r) { 3415 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3416 return r; 3417 } 3418 WREG32(scratch, 0xCAFEDEAD); 3419 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3420 if (r) { 3421 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3422 goto free_scratch; 3423 } 3424 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3425 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3426 ib.ptr[2] = 0xDEADBEEF; 3427 ib.length_dw = 3; 3428 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3429 if (r) { 3430 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3431 goto free_ib; 3432 } 3433 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies( 3434 RADEON_USEC_IB_TEST_TIMEOUT)); 3435 if (r < 0) { 3436 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3437 goto free_ib; 3438 } else if (r == 0) { 3439 DRM_ERROR("radeon: fence wait timed out.\n"); 3440 r = -ETIMEDOUT; 3441 goto free_ib; 3442 } 3443 r = 0; 3444 for (i = 0; i < rdev->usec_timeout; i++) { 3445 tmp = RREG32(scratch); 3446 if (tmp == 0xDEADBEEF) 3447 break; 3448 DRM_UDELAY(1); 3449 } 3450 if (i < rdev->usec_timeout) { 3451 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3452 } else { 3453 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3454 scratch, tmp); 3455 r = -EINVAL; 3456 } 3457 free_ib: 3458 radeon_ib_free(rdev, &ib); 3459 free_scratch: 3460 radeon_scratch_free(rdev, scratch); 3461 return r; 3462 } 3463 3464 /* 3465 * Interrupts 3466 * 3467 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3468 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3469 * writing to the ring and the GPU consuming, the GPU writes to the ring 3470 * and host consumes. As the host irq handler processes interrupts, it 3471 * increments the rptr. When the rptr catches up with the wptr, all the 3472 * current interrupts have been processed. 3473 */ 3474 3475 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3476 { 3477 u32 rb_bufsz; 3478 3479 /* Align ring size */ 3480 rb_bufsz = order_base_2(ring_size / 4); 3481 ring_size = (1 << rb_bufsz) * 4; 3482 rdev->ih.ring_size = ring_size; 3483 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3484 rdev->ih.rptr = 0; 3485 } 3486 3487 int r600_ih_ring_alloc(struct radeon_device *rdev) 3488 { 3489 int r; 3490 void *ring_ptr = &rdev->ih.ring; 3491 3492 /* Allocate ring buffer */ 3493 if (rdev->ih.ring_obj == NULL) { 3494 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3495 PAGE_SIZE, true, 3496 RADEON_GEM_DOMAIN_GTT, 0, 3497 NULL, NULL, &rdev->ih.ring_obj); 3498 if (r) { 3499 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3500 return r; 3501 } 3502 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3503 if (unlikely(r != 0)) 3504 return r; 3505 r = radeon_bo_pin(rdev->ih.ring_obj, 3506 RADEON_GEM_DOMAIN_GTT, 3507 (u64 *)&rdev->ih.gpu_addr); 3508 if (r) { 3509 radeon_bo_unreserve(rdev->ih.ring_obj); 3510 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3511 return r; 3512 } 3513 r = radeon_bo_kmap(rdev->ih.ring_obj, 3514 ring_ptr); 3515 radeon_bo_unreserve(rdev->ih.ring_obj); 3516 if (r) { 3517 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3518 return r; 3519 } 3520 } 3521 return 0; 3522 } 3523 3524 void r600_ih_ring_fini(struct radeon_device *rdev) 3525 { 3526 int r; 3527 if (rdev->ih.ring_obj) { 3528 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3529 if (likely(r == 0)) { 3530 radeon_bo_kunmap(rdev->ih.ring_obj); 3531 radeon_bo_unpin(rdev->ih.ring_obj); 3532 radeon_bo_unreserve(rdev->ih.ring_obj); 3533 } 3534 radeon_bo_unref(&rdev->ih.ring_obj); 3535 rdev->ih.ring = NULL; 3536 rdev->ih.ring_obj = NULL; 3537 } 3538 } 3539 3540 void r600_rlc_stop(struct radeon_device *rdev) 3541 { 3542 3543 if ((rdev->family >= CHIP_RV770) && 3544 (rdev->family <= CHIP_RV740)) { 3545 /* r7xx asics need to soft reset RLC before halting */ 3546 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3547 RREG32(SRBM_SOFT_RESET); 3548 mdelay(15); 3549 WREG32(SRBM_SOFT_RESET, 0); 3550 RREG32(SRBM_SOFT_RESET); 3551 } 3552 3553 WREG32(RLC_CNTL, 0); 3554 } 3555 3556 static void r600_rlc_start(struct radeon_device *rdev) 3557 { 3558 WREG32(RLC_CNTL, RLC_ENABLE); 3559 } 3560 3561 static int r600_rlc_resume(struct radeon_device *rdev) 3562 { 3563 u32 i; 3564 const __be32 *fw_data; 3565 3566 if (!rdev->rlc_fw) 3567 return -EINVAL; 3568 3569 r600_rlc_stop(rdev); 3570 3571 WREG32(RLC_HB_CNTL, 0); 3572 3573 WREG32(RLC_HB_BASE, 0); 3574 WREG32(RLC_HB_RPTR, 0); 3575 WREG32(RLC_HB_WPTR, 0); 3576 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3577 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3578 WREG32(RLC_MC_CNTL, 0); 3579 WREG32(RLC_UCODE_CNTL, 0); 3580 3581 fw_data = (const __be32 *)rdev->rlc_fw->data; 3582 if (rdev->family >= CHIP_RV770) { 3583 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3584 WREG32(RLC_UCODE_ADDR, i); 3585 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3586 } 3587 } else { 3588 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { 3589 WREG32(RLC_UCODE_ADDR, i); 3590 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3591 } 3592 } 3593 WREG32(RLC_UCODE_ADDR, 0); 3594 3595 r600_rlc_start(rdev); 3596 3597 return 0; 3598 } 3599 3600 static void r600_enable_interrupts(struct radeon_device *rdev) 3601 { 3602 u32 ih_cntl = RREG32(IH_CNTL); 3603 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3604 3605 ih_cntl |= ENABLE_INTR; 3606 ih_rb_cntl |= IH_RB_ENABLE; 3607 WREG32(IH_CNTL, ih_cntl); 3608 WREG32(IH_RB_CNTL, ih_rb_cntl); 3609 rdev->ih.enabled = true; 3610 } 3611 3612 void r600_disable_interrupts(struct radeon_device *rdev) 3613 { 3614 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3615 u32 ih_cntl = RREG32(IH_CNTL); 3616 3617 ih_rb_cntl &= ~IH_RB_ENABLE; 3618 ih_cntl &= ~ENABLE_INTR; 3619 WREG32(IH_RB_CNTL, ih_rb_cntl); 3620 WREG32(IH_CNTL, ih_cntl); 3621 /* set rptr, wptr to 0 */ 3622 WREG32(IH_RB_RPTR, 0); 3623 WREG32(IH_RB_WPTR, 0); 3624 rdev->ih.enabled = false; 3625 rdev->ih.rptr = 0; 3626 } 3627 3628 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3629 { 3630 u32 tmp; 3631 3632 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3633 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3634 WREG32(DMA_CNTL, tmp); 3635 WREG32(GRBM_INT_CNTL, 0); 3636 WREG32(DxMODE_INT_MASK, 0); 3637 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3638 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3639 if (ASIC_IS_DCE3(rdev)) { 3640 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3641 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3642 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3643 WREG32(DC_HPD1_INT_CONTROL, tmp); 3644 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3645 WREG32(DC_HPD2_INT_CONTROL, tmp); 3646 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3647 WREG32(DC_HPD3_INT_CONTROL, tmp); 3648 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3649 WREG32(DC_HPD4_INT_CONTROL, tmp); 3650 if (ASIC_IS_DCE32(rdev)) { 3651 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3652 WREG32(DC_HPD5_INT_CONTROL, tmp); 3653 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3654 WREG32(DC_HPD6_INT_CONTROL, tmp); 3655 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3656 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3657 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3658 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3659 } else { 3660 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3661 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3662 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3663 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3664 } 3665 } else { 3666 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3667 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3668 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3669 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3670 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3671 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3672 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3673 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3674 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3675 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3676 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3677 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3678 } 3679 } 3680 3681 int r600_irq_init(struct radeon_device *rdev) 3682 { 3683 int ret = 0; 3684 int rb_bufsz; 3685 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3686 3687 /* allocate ring */ 3688 ret = r600_ih_ring_alloc(rdev); 3689 if (ret) 3690 return ret; 3691 3692 /* disable irqs */ 3693 r600_disable_interrupts(rdev); 3694 3695 /* init rlc */ 3696 if (rdev->family >= CHIP_CEDAR) 3697 ret = evergreen_rlc_resume(rdev); 3698 else 3699 ret = r600_rlc_resume(rdev); 3700 if (ret) { 3701 r600_ih_ring_fini(rdev); 3702 return ret; 3703 } 3704 3705 /* setup interrupt control */ 3706 /* set dummy read address to ring address */ 3707 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3708 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3709 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3710 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3711 */ 3712 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3713 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3714 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3715 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3716 3717 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3718 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); 3719 3720 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3721 IH_WPTR_OVERFLOW_CLEAR | 3722 (rb_bufsz << 1)); 3723 3724 if (rdev->wb.enabled) 3725 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3726 3727 /* set the writeback address whether it's enabled or not */ 3728 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3729 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3730 3731 WREG32(IH_RB_CNTL, ih_rb_cntl); 3732 3733 /* set rptr, wptr to 0 */ 3734 WREG32(IH_RB_RPTR, 0); 3735 WREG32(IH_RB_WPTR, 0); 3736 3737 /* Default settings for IH_CNTL (disabled at first) */ 3738 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3739 /* RPTR_REARM only works if msi's are enabled */ 3740 if (rdev->msi_enabled) 3741 ih_cntl |= RPTR_REARM; 3742 WREG32(IH_CNTL, ih_cntl); 3743 3744 /* force the active interrupt state to all disabled */ 3745 if (rdev->family >= CHIP_CEDAR) 3746 evergreen_disable_interrupt_state(rdev); 3747 else 3748 r600_disable_interrupt_state(rdev); 3749 3750 /* at this point everything should be setup correctly to enable master */ 3751 pci_set_master(rdev->pdev); 3752 3753 /* enable irqs */ 3754 r600_enable_interrupts(rdev); 3755 3756 return ret; 3757 } 3758 3759 void r600_irq_suspend(struct radeon_device *rdev) 3760 { 3761 r600_irq_disable(rdev); 3762 r600_rlc_stop(rdev); 3763 } 3764 3765 void r600_irq_fini(struct radeon_device *rdev) 3766 { 3767 r600_irq_suspend(rdev); 3768 r600_ih_ring_fini(rdev); 3769 } 3770 3771 int r600_irq_set(struct radeon_device *rdev) 3772 { 3773 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3774 u32 mode_int = 0; 3775 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3776 u32 grbm_int_cntl = 0; 3777 u32 hdmi0, hdmi1; 3778 u32 dma_cntl; 3779 u32 thermal_int = 0; 3780 3781 if (!rdev->irq.installed) { 3782 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3783 return -EINVAL; 3784 } 3785 /* don't enable anything if the ih is disabled */ 3786 if (!rdev->ih.enabled) { 3787 r600_disable_interrupts(rdev); 3788 /* force the active interrupt state to all disabled */ 3789 r600_disable_interrupt_state(rdev); 3790 return 0; 3791 } 3792 3793 if (ASIC_IS_DCE3(rdev)) { 3794 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3795 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3796 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3797 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3798 if (ASIC_IS_DCE32(rdev)) { 3799 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3800 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3801 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3802 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3803 } else { 3804 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3805 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3806 } 3807 } else { 3808 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3809 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3810 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3811 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3812 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3813 } 3814 3815 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3816 3817 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3818 thermal_int = RREG32(CG_THERMAL_INT) & 3819 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3820 } else if (rdev->family >= CHIP_RV770) { 3821 thermal_int = RREG32(RV770_CG_THERMAL_INT) & 3822 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3823 } 3824 if (rdev->irq.dpm_thermal) { 3825 DRM_DEBUG("dpm thermal\n"); 3826 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 3827 } 3828 3829 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3830 DRM_DEBUG("r600_irq_set: sw int\n"); 3831 cp_int_cntl |= RB_INT_ENABLE; 3832 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3833 } 3834 3835 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3836 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3837 dma_cntl |= TRAP_ENABLE; 3838 } 3839 3840 if (rdev->irq.crtc_vblank_int[0] || 3841 atomic_read(&rdev->irq.pflip[0])) { 3842 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3843 mode_int |= D1MODE_VBLANK_INT_MASK; 3844 } 3845 if (rdev->irq.crtc_vblank_int[1] || 3846 atomic_read(&rdev->irq.pflip[1])) { 3847 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3848 mode_int |= D2MODE_VBLANK_INT_MASK; 3849 } 3850 if (rdev->irq.hpd[0]) { 3851 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3852 hpd1 |= DC_HPDx_INT_EN; 3853 } 3854 if (rdev->irq.hpd[1]) { 3855 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3856 hpd2 |= DC_HPDx_INT_EN; 3857 } 3858 if (rdev->irq.hpd[2]) { 3859 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3860 hpd3 |= DC_HPDx_INT_EN; 3861 } 3862 if (rdev->irq.hpd[3]) { 3863 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3864 hpd4 |= DC_HPDx_INT_EN; 3865 } 3866 if (rdev->irq.hpd[4]) { 3867 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3868 hpd5 |= DC_HPDx_INT_EN; 3869 } 3870 if (rdev->irq.hpd[5]) { 3871 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3872 hpd6 |= DC_HPDx_INT_EN; 3873 } 3874 if (rdev->irq.afmt[0]) { 3875 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3876 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3877 } 3878 if (rdev->irq.afmt[1]) { 3879 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3880 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3881 } 3882 3883 WREG32(CP_INT_CNTL, cp_int_cntl); 3884 WREG32(DMA_CNTL, dma_cntl); 3885 WREG32(DxMODE_INT_MASK, mode_int); 3886 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3887 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3888 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3889 if (ASIC_IS_DCE3(rdev)) { 3890 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3891 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3892 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3893 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3894 if (ASIC_IS_DCE32(rdev)) { 3895 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3896 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3897 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3898 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3899 } else { 3900 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3901 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3902 } 3903 } else { 3904 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3905 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3906 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3907 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3908 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3909 } 3910 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3911 WREG32(CG_THERMAL_INT, thermal_int); 3912 } else if (rdev->family >= CHIP_RV770) { 3913 WREG32(RV770_CG_THERMAL_INT, thermal_int); 3914 } 3915 3916 /* posting read */ 3917 RREG32(R_000E50_SRBM_STATUS); 3918 3919 return 0; 3920 } 3921 3922 static void r600_irq_ack(struct radeon_device *rdev) 3923 { 3924 u32 tmp; 3925 3926 if (ASIC_IS_DCE3(rdev)) { 3927 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3928 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3929 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3930 if (ASIC_IS_DCE32(rdev)) { 3931 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3932 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3933 } else { 3934 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3935 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3936 } 3937 } else { 3938 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3939 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3940 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3941 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3942 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3943 } 3944 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3945 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3946 3947 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3948 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3949 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3950 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3951 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3952 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3953 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3954 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3955 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3956 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3957 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3958 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3959 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3960 if (ASIC_IS_DCE3(rdev)) { 3961 tmp = RREG32(DC_HPD1_INT_CONTROL); 3962 tmp |= DC_HPDx_INT_ACK; 3963 WREG32(DC_HPD1_INT_CONTROL, tmp); 3964 } else { 3965 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3966 tmp |= DC_HPDx_INT_ACK; 3967 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3968 } 3969 } 3970 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3971 if (ASIC_IS_DCE3(rdev)) { 3972 tmp = RREG32(DC_HPD2_INT_CONTROL); 3973 tmp |= DC_HPDx_INT_ACK; 3974 WREG32(DC_HPD2_INT_CONTROL, tmp); 3975 } else { 3976 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3977 tmp |= DC_HPDx_INT_ACK; 3978 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3979 } 3980 } 3981 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3982 if (ASIC_IS_DCE3(rdev)) { 3983 tmp = RREG32(DC_HPD3_INT_CONTROL); 3984 tmp |= DC_HPDx_INT_ACK; 3985 WREG32(DC_HPD3_INT_CONTROL, tmp); 3986 } else { 3987 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3988 tmp |= DC_HPDx_INT_ACK; 3989 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3990 } 3991 } 3992 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3993 tmp = RREG32(DC_HPD4_INT_CONTROL); 3994 tmp |= DC_HPDx_INT_ACK; 3995 WREG32(DC_HPD4_INT_CONTROL, tmp); 3996 } 3997 if (ASIC_IS_DCE32(rdev)) { 3998 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3999 tmp = RREG32(DC_HPD5_INT_CONTROL); 4000 tmp |= DC_HPDx_INT_ACK; 4001 WREG32(DC_HPD5_INT_CONTROL, tmp); 4002 } 4003 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4004 tmp = RREG32(DC_HPD6_INT_CONTROL); 4005 tmp |= DC_HPDx_INT_ACK; 4006 WREG32(DC_HPD6_INT_CONTROL, tmp); 4007 } 4008 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 4009 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 4010 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 4011 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 4012 } 4013 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 4014 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 4015 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 4016 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 4017 } 4018 } else { 4019 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4020 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 4021 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4022 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 4023 } 4024 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4025 if (ASIC_IS_DCE3(rdev)) { 4026 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 4027 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4028 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 4029 } else { 4030 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 4031 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4032 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 4033 } 4034 } 4035 } 4036 } 4037 4038 void r600_irq_disable(struct radeon_device *rdev) 4039 { 4040 r600_disable_interrupts(rdev); 4041 /* Wait and acknowledge irq */ 4042 mdelay(1); 4043 r600_irq_ack(rdev); 4044 r600_disable_interrupt_state(rdev); 4045 } 4046 4047 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 4048 { 4049 u32 wptr, tmp; 4050 4051 if (rdev->wb.enabled) 4052 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 4053 else 4054 wptr = RREG32(IH_RB_WPTR); 4055 4056 if (wptr & RB_OVERFLOW) { 4057 wptr &= ~RB_OVERFLOW; 4058 /* When a ring buffer overflow happen start parsing interrupt 4059 * from the last not overwritten vector (wptr + 16). Hopefully 4060 * this should allow us to catchup. 4061 */ 4062 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 4063 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); 4064 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 4065 tmp = RREG32(IH_RB_CNTL); 4066 tmp |= IH_WPTR_OVERFLOW_CLEAR; 4067 WREG32(IH_RB_CNTL, tmp); 4068 } 4069 return (wptr & rdev->ih.ptr_mask); 4070 } 4071 4072 /* r600 IV Ring 4073 * Each IV ring entry is 128 bits: 4074 * [7:0] - interrupt source id 4075 * [31:8] - reserved 4076 * [59:32] - interrupt source data 4077 * [127:60] - reserved 4078 * 4079 * The basic interrupt vector entries 4080 * are decoded as follows: 4081 * src_id src_data description 4082 * 1 0 D1 Vblank 4083 * 1 1 D1 Vline 4084 * 5 0 D2 Vblank 4085 * 5 1 D2 Vline 4086 * 19 0 FP Hot plug detection A 4087 * 19 1 FP Hot plug detection B 4088 * 19 2 DAC A auto-detection 4089 * 19 3 DAC B auto-detection 4090 * 21 4 HDMI block A 4091 * 21 5 HDMI block B 4092 * 176 - CP_INT RB 4093 * 177 - CP_INT IB1 4094 * 178 - CP_INT IB2 4095 * 181 - EOP Interrupt 4096 * 233 - GUI Idle 4097 * 4098 * Note, these are based on r600 and may need to be 4099 * adjusted or added to on newer asics 4100 */ 4101 4102 irqreturn_t r600_irq_process(struct radeon_device *rdev) 4103 { 4104 u32 wptr; 4105 u32 rptr; 4106 u32 src_id, src_data; 4107 u32 ring_index; 4108 bool queue_hotplug = false; 4109 bool queue_hdmi = false; 4110 bool queue_thermal = false; 4111 4112 if (!rdev->ih.enabled || rdev->shutdown) 4113 return IRQ_NONE; 4114 4115 /* No MSIs, need a dummy read to flush PCI DMAs */ 4116 if (!rdev->msi_enabled) 4117 RREG32(IH_RB_WPTR); 4118 4119 wptr = r600_get_ih_wptr(rdev); 4120 4121 restart_ih: 4122 /* is somebody else already processing irqs? */ 4123 if (atomic_xchg(&rdev->ih.lock, 1)) 4124 return IRQ_NONE; 4125 4126 rptr = rdev->ih.rptr; 4127 DRM_DEBUG_VBLANK("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4128 4129 /* Order reading of wptr vs. reading of IH ring data */ 4130 rmb(); 4131 4132 /* display interrupts */ 4133 r600_irq_ack(rdev); 4134 4135 while (rptr != wptr) { 4136 /* wptr/rptr are in bytes! */ 4137 ring_index = rptr / 4; 4138 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 4139 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 4140 4141 switch (src_id) { 4142 case 1: /* D1 vblank/vline */ 4143 switch (src_data) { 4144 case 0: /* D1 vblank */ 4145 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) 4146 DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n"); 4147 4148 if (rdev->irq.crtc_vblank_int[0]) { 4149 drm_handle_vblank(rdev->ddev, 0); 4150 rdev->pm.vblank_sync = true; 4151 wake_up(&rdev->irq.vblank_queue); 4152 } 4153 if (atomic_read(&rdev->irq.pflip[0])) 4154 radeon_crtc_handle_vblank(rdev, 0); 4155 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4156 DRM_DEBUG_VBLANK("IH: D1 vblank\n"); 4157 4158 break; 4159 case 1: /* D1 vline */ 4160 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) 4161 DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n"); 4162 4163 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4164 DRM_DEBUG_VBLANK("IH: D1 vline\n"); 4165 4166 break; 4167 default: 4168 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4169 break; 4170 } 4171 break; 4172 case 5: /* D2 vblank/vline */ 4173 switch (src_data) { 4174 case 0: /* D2 vblank */ 4175 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) 4176 DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n"); 4177 4178 if (rdev->irq.crtc_vblank_int[1]) { 4179 drm_handle_vblank(rdev->ddev, 1); 4180 rdev->pm.vblank_sync = true; 4181 wake_up(&rdev->irq.vblank_queue); 4182 } 4183 if (atomic_read(&rdev->irq.pflip[1])) 4184 radeon_crtc_handle_vblank(rdev, 1); 4185 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4186 DRM_DEBUG_VBLANK("IH: D2 vblank\n"); 4187 4188 break; 4189 case 1: /* D1 vline */ 4190 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) 4191 DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n"); 4192 4193 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4194 DRM_DEBUG_VBLANK("IH: D2 vline\n"); 4195 4196 break; 4197 default: 4198 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4199 break; 4200 } 4201 break; 4202 case 9: /* D1 pflip */ 4203 DRM_DEBUG_VBLANK("IH: D1 flip\n"); 4204 if (radeon_use_pflipirq > 0) 4205 radeon_crtc_handle_flip(rdev, 0); 4206 break; 4207 case 11: /* D2 pflip */ 4208 DRM_DEBUG_VBLANK("IH: D2 flip\n"); 4209 if (radeon_use_pflipirq > 0) 4210 radeon_crtc_handle_flip(rdev, 1); 4211 break; 4212 case 19: /* HPD/DAC hotplug */ 4213 switch (src_data) { 4214 case 0: 4215 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) 4216 DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n"); 4217 4218 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4219 queue_hotplug = true; 4220 DRM_DEBUG("IH: HPD1\n"); 4221 break; 4222 case 1: 4223 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) 4224 DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n"); 4225 4226 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4227 queue_hotplug = true; 4228 DRM_DEBUG("IH: HPD2\n"); 4229 break; 4230 case 4: 4231 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) 4232 DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n"); 4233 4234 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4235 queue_hotplug = true; 4236 DRM_DEBUG("IH: HPD3\n"); 4237 break; 4238 case 5: 4239 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) 4240 DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n"); 4241 4242 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4243 queue_hotplug = true; 4244 DRM_DEBUG("IH: HPD4\n"); 4245 break; 4246 case 10: 4247 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) 4248 DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n"); 4249 4250 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4251 queue_hotplug = true; 4252 DRM_DEBUG("IH: HPD5\n"); 4253 break; 4254 case 12: 4255 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) 4256 DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n"); 4257 4258 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4259 queue_hotplug = true; 4260 DRM_DEBUG("IH: HPD6\n"); 4261 4262 break; 4263 default: 4264 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4265 break; 4266 } 4267 break; 4268 case 21: /* hdmi */ 4269 switch (src_data) { 4270 case 4: 4271 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) 4272 DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n"); 4273 4274 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4275 queue_hdmi = true; 4276 DRM_DEBUG("IH: HDMI0\n"); 4277 4278 break; 4279 case 5: 4280 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) 4281 DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n"); 4282 4283 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4284 queue_hdmi = true; 4285 DRM_DEBUG("IH: HDMI1\n"); 4286 4287 break; 4288 default: 4289 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4290 break; 4291 } 4292 break; 4293 case 124: /* UVD */ 4294 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 4295 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); 4296 break; 4297 case 176: /* CP_INT in ring buffer */ 4298 case 177: /* CP_INT in IB1 */ 4299 case 178: /* CP_INT in IB2 */ 4300 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4301 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4302 break; 4303 case 181: /* CP EOP event */ 4304 DRM_DEBUG("IH: CP EOP\n"); 4305 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4306 break; 4307 case 224: /* DMA trap event */ 4308 DRM_DEBUG("IH: DMA trap\n"); 4309 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4310 break; 4311 case 230: /* thermal low to high */ 4312 DRM_DEBUG("IH: thermal low to high\n"); 4313 rdev->pm.dpm.thermal.high_to_low = false; 4314 queue_thermal = true; 4315 break; 4316 case 231: /* thermal high to low */ 4317 DRM_DEBUG("IH: thermal high to low\n"); 4318 rdev->pm.dpm.thermal.high_to_low = true; 4319 queue_thermal = true; 4320 break; 4321 case 233: /* GUI IDLE */ 4322 DRM_DEBUG("IH: GUI idle\n"); 4323 break; 4324 default: 4325 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4326 break; 4327 } 4328 4329 /* wptr/rptr are in bytes! */ 4330 rptr += 16; 4331 rptr &= rdev->ih.ptr_mask; 4332 WREG32(IH_RB_RPTR, rptr); 4333 } 4334 if (queue_hotplug) 4335 schedule_delayed_work(&rdev->hotplug_work, 0); 4336 if (queue_hdmi) 4337 schedule_work(&rdev->audio_work); 4338 if (queue_thermal && rdev->pm.dpm_enabled) 4339 schedule_work(&rdev->pm.dpm.thermal.work); 4340 rdev->ih.rptr = rptr; 4341 atomic_set(&rdev->ih.lock, 0); 4342 4343 /* make sure wptr hasn't changed while processing */ 4344 wptr = r600_get_ih_wptr(rdev); 4345 if (wptr != rptr) 4346 goto restart_ih; 4347 4348 return IRQ_HANDLED; 4349 } 4350 4351 /* 4352 * Debugfs info 4353 */ 4354 #if defined(CONFIG_DEBUG_FS) 4355 4356 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4357 { 4358 struct drm_info_node *node = (struct drm_info_node *) m->private; 4359 struct drm_device *dev = node->minor->dev; 4360 struct radeon_device *rdev = dev->dev_private; 4361 4362 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4363 DREG32_SYS(m, rdev, VM_L2_STATUS); 4364 return 0; 4365 } 4366 4367 static struct drm_info_list r600_mc_info_list[] = { 4368 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4369 }; 4370 #endif 4371 4372 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4373 { 4374 #if defined(CONFIG_DEBUG_FS) 4375 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4376 #else 4377 return 0; 4378 #endif 4379 } 4380 4381 /** 4382 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO 4383 * rdev: radeon device structure 4384 * 4385 * Some R6XX/R7XX don't seem to take into account HDP flushes performed 4386 * through the ring buffer. This leads to corruption in rendering, see 4387 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we 4388 * directly perform the HDP flush by writing the register through MMIO. 4389 */ 4390 void r600_mmio_hdp_flush(struct radeon_device *rdev) 4391 { 4392 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4393 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4394 * This seems to cause problems on some AGP cards. Just use the old 4395 * method for them. 4396 */ 4397 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4398 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4399 volatile void __iomem *ptr = (volatile void *)rdev->vram_scratch.ptr; 4400 u32 tmp; 4401 4402 WREG32(HDP_DEBUG1, 0); 4403 tmp = readl((volatile void __iomem *)ptr); 4404 } else 4405 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4406 } 4407 4408 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4409 { 4410 u32 link_width_cntl, mask; 4411 4412 if (rdev->flags & RADEON_IS_IGP) 4413 return; 4414 4415 if (!(rdev->flags & RADEON_IS_PCIE)) 4416 return; 4417 4418 /* x2 cards have a special sequence */ 4419 if (ASIC_IS_X2(rdev)) 4420 return; 4421 4422 radeon_gui_idle(rdev); 4423 4424 switch (lanes) { 4425 case 0: 4426 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4427 break; 4428 case 1: 4429 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4430 break; 4431 case 2: 4432 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4433 break; 4434 case 4: 4435 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4436 break; 4437 case 8: 4438 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4439 break; 4440 case 12: 4441 /* not actually supported */ 4442 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4443 break; 4444 case 16: 4445 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4446 break; 4447 default: 4448 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4449 return; 4450 } 4451 4452 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4453 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; 4454 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; 4455 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | 4456 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4457 4458 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4459 } 4460 4461 int r600_get_pcie_lanes(struct radeon_device *rdev) 4462 { 4463 u32 link_width_cntl; 4464 4465 if (rdev->flags & RADEON_IS_IGP) 4466 return 0; 4467 4468 if (!(rdev->flags & RADEON_IS_PCIE)) 4469 return 0; 4470 4471 /* x2 cards have a special sequence */ 4472 if (ASIC_IS_X2(rdev)) 4473 return 0; 4474 4475 radeon_gui_idle(rdev); 4476 4477 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4478 4479 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4480 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4481 return 1; 4482 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4483 return 2; 4484 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4485 return 4; 4486 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4487 return 8; 4488 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4489 /* not actually supported */ 4490 return 12; 4491 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4492 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4493 default: 4494 return 16; 4495 } 4496 } 4497 4498 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4499 { 4500 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4501 u16 link_cntl2; 4502 u32 mask; 4503 4504 if (radeon_pcie_gen2 == 0) 4505 return; 4506 4507 if (rdev->flags & RADEON_IS_IGP) 4508 return; 4509 4510 if (!(rdev->flags & RADEON_IS_PCIE)) 4511 return; 4512 4513 /* x2 cards have a special sequence */ 4514 if (ASIC_IS_X2(rdev)) 4515 return; 4516 4517 /* only RV6xx+ chips are supported */ 4518 if (rdev->family <= CHIP_R600) 4519 return; 4520 4521 #ifdef __DragonFly__ 4522 if (drm_pcie_get_speed_cap_mask(rdev->ddev, &mask) != 0) 4523 return; 4524 #endif 4525 4526 if (!(mask & DRM_PCIE_SPEED_50)) 4527 return; 4528 4529 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4530 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4531 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4532 return; 4533 } 4534 4535 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4536 4537 /* 55 nm r6xx asics */ 4538 if ((rdev->family == CHIP_RV670) || 4539 (rdev->family == CHIP_RV620) || 4540 (rdev->family == CHIP_RV635)) { 4541 /* advertise upconfig capability */ 4542 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4543 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4544 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4545 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4546 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4547 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4548 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4549 LC_RECONFIG_ARC_MISSING_ESCAPE); 4550 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4551 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4552 } else { 4553 link_width_cntl |= LC_UPCONFIGURE_DIS; 4554 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4555 } 4556 } 4557 4558 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4559 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4560 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4561 4562 /* 55 nm r6xx asics */ 4563 if ((rdev->family == CHIP_RV670) || 4564 (rdev->family == CHIP_RV620) || 4565 (rdev->family == CHIP_RV635)) { 4566 WREG32(MM_CFGREGS_CNTL, 0x8); 4567 link_cntl2 = RREG32(0x4088); 4568 WREG32(MM_CFGREGS_CNTL, 0); 4569 /* not supported yet */ 4570 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4571 return; 4572 } 4573 4574 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4575 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4576 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4577 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4578 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4579 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4580 4581 tmp = RREG32(0x541c); 4582 WREG32(0x541c, tmp | 0x8); 4583 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4584 link_cntl2 = RREG16(0x4088); 4585 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4586 link_cntl2 |= 0x2; 4587 WREG16(0x4088, link_cntl2); 4588 WREG32(MM_CFGREGS_CNTL, 0); 4589 4590 if ((rdev->family == CHIP_RV670) || 4591 (rdev->family == CHIP_RV620) || 4592 (rdev->family == CHIP_RV635)) { 4593 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); 4594 training_cntl &= ~LC_POINT_7_PLUS_EN; 4595 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); 4596 } else { 4597 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4598 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4599 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4600 } 4601 4602 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4603 speed_cntl |= LC_GEN2_EN_STRAP; 4604 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4605 4606 } else { 4607 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4608 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4609 if (1) 4610 link_width_cntl |= LC_UPCONFIGURE_DIS; 4611 else 4612 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4613 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4614 } 4615 } 4616 4617 /** 4618 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4619 * 4620 * @rdev: radeon_device pointer 4621 * 4622 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4623 * Returns the 64 bit clock counter snapshot. 4624 */ 4625 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4626 { 4627 uint64_t clock; 4628 4629 mutex_lock(&rdev->gpu_clock_mutex); 4630 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4631 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4632 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4633 mutex_unlock(&rdev->gpu_clock_mutex); 4634 return clock; 4635 } 4636