1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 * 27 * $FreeBSD: head/sys/dev/drm2/radeon/r600d.h 254885 2013-08-25 19:37:15Z dumbbell $ 28 */ 29 #ifndef R600D_H 30 #define R600D_H 31 32 #define CP_PACKET2 0x80000000 33 #define PACKET2_PAD_SHIFT 0 34 #define PACKET2_PAD_MASK (0x3fffffff << 0) 35 36 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 37 38 #define R6XX_MAX_SH_GPRS 256 39 #define R6XX_MAX_TEMP_GPRS 16 40 #define R6XX_MAX_SH_THREADS 256 41 #define R6XX_MAX_SH_STACK_ENTRIES 4096 42 #define R6XX_MAX_BACKENDS 8 43 #define R6XX_MAX_BACKENDS_MASK 0xff 44 #define R6XX_MAX_SIMDS 8 45 #define R6XX_MAX_SIMDS_MASK 0xff 46 #define R6XX_MAX_PIPES 8 47 #define R6XX_MAX_PIPES_MASK 0xff 48 49 /* PTE flags */ 50 #define PTE_VALID (1 << 0) 51 #define PTE_SYSTEM (1 << 1) 52 #define PTE_SNOOPED (1 << 2) 53 #define PTE_READABLE (1 << 5) 54 #define PTE_WRITEABLE (1 << 6) 55 56 /* tiling bits */ 57 #define ARRAY_LINEAR_GENERAL 0x00000000 58 #define ARRAY_LINEAR_ALIGNED 0x00000001 59 #define ARRAY_1D_TILED_THIN1 0x00000002 60 #define ARRAY_2D_TILED_THIN1 0x00000004 61 62 /* Registers */ 63 #define ARB_POP 0x2418 64 #define ENABLE_TC128 (1 << 30) 65 #define ARB_GDEC_RD_CNTL 0x246C 66 67 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 68 #define CC_RB_BACKEND_DISABLE 0x98F4 69 #define BACKEND_DISABLE(x) ((x) << 16) 70 71 #define R_028808_CB_COLOR_CONTROL 0x28808 72 #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) 73 #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) 74 #define C_028808_SPECIAL_OP 0xFFFFFF8F 75 #define V_028808_SPECIAL_NORMAL 0x00 76 #define V_028808_SPECIAL_DISABLE 0x01 77 #define V_028808_SPECIAL_RESOLVE_BOX 0x07 78 79 #define CB_COLOR0_BASE 0x28040 80 #define CB_COLOR1_BASE 0x28044 81 #define CB_COLOR2_BASE 0x28048 82 #define CB_COLOR3_BASE 0x2804C 83 #define CB_COLOR4_BASE 0x28050 84 #define CB_COLOR5_BASE 0x28054 85 #define CB_COLOR6_BASE 0x28058 86 #define CB_COLOR7_BASE 0x2805C 87 #define CB_COLOR7_FRAG 0x280FC 88 89 #define CB_COLOR0_SIZE 0x28060 90 #define CB_COLOR0_VIEW 0x28080 91 #define R_028080_CB_COLOR0_VIEW 0x028080 92 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) 93 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) 94 #define C_028080_SLICE_START 0xFFFFF800 95 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) 96 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 97 #define C_028080_SLICE_MAX 0xFF001FFF 98 #define R_028084_CB_COLOR1_VIEW 0x028084 99 #define R_028088_CB_COLOR2_VIEW 0x028088 100 #define R_02808C_CB_COLOR3_VIEW 0x02808C 101 #define R_028090_CB_COLOR4_VIEW 0x028090 102 #define R_028094_CB_COLOR5_VIEW 0x028094 103 #define R_028098_CB_COLOR6_VIEW 0x028098 104 #define R_02809C_CB_COLOR7_VIEW 0x02809C 105 #define R_028100_CB_COLOR0_MASK 0x028100 106 #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) 107 #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) 108 #define C_028100_CMASK_BLOCK_MAX 0xFFFFF000 109 #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) 110 #define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF) 111 #define C_028100_FMASK_TILE_MAX 0x00000FFF 112 #define R_028104_CB_COLOR1_MASK 0x028104 113 #define R_028108_CB_COLOR2_MASK 0x028108 114 #define R_02810C_CB_COLOR3_MASK 0x02810C 115 #define R_028110_CB_COLOR4_MASK 0x028110 116 #define R_028114_CB_COLOR5_MASK 0x028114 117 #define R_028118_CB_COLOR6_MASK 0x028118 118 #define R_02811C_CB_COLOR7_MASK 0x02811C 119 #define CB_COLOR0_INFO 0x280a0 120 # define CB_FORMAT(x) ((x) << 2) 121 # define CB_ARRAY_MODE(x) ((x) << 8) 122 # define CB_SOURCE_FORMAT(x) ((x) << 27) 123 # define CB_SF_EXPORT_FULL 0 124 # define CB_SF_EXPORT_NORM 1 125 #define CB_COLOR0_TILE 0x280c0 126 #define CB_COLOR0_FRAG 0x280e0 127 #define CB_COLOR0_MASK 0x28100 128 129 #define SQ_ALU_CONST_CACHE_PS_0 0x28940 130 #define SQ_ALU_CONST_CACHE_PS_1 0x28944 131 #define SQ_ALU_CONST_CACHE_PS_2 0x28948 132 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c 133 #define SQ_ALU_CONST_CACHE_PS_4 0x28950 134 #define SQ_ALU_CONST_CACHE_PS_5 0x28954 135 #define SQ_ALU_CONST_CACHE_PS_6 0x28958 136 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c 137 #define SQ_ALU_CONST_CACHE_PS_8 0x28960 138 #define SQ_ALU_CONST_CACHE_PS_9 0x28964 139 #define SQ_ALU_CONST_CACHE_PS_10 0x28968 140 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c 141 #define SQ_ALU_CONST_CACHE_PS_12 0x28970 142 #define SQ_ALU_CONST_CACHE_PS_13 0x28974 143 #define SQ_ALU_CONST_CACHE_PS_14 0x28978 144 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c 145 #define SQ_ALU_CONST_CACHE_VS_0 0x28980 146 #define SQ_ALU_CONST_CACHE_VS_1 0x28984 147 #define SQ_ALU_CONST_CACHE_VS_2 0x28988 148 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c 149 #define SQ_ALU_CONST_CACHE_VS_4 0x28990 150 #define SQ_ALU_CONST_CACHE_VS_5 0x28994 151 #define SQ_ALU_CONST_CACHE_VS_6 0x28998 152 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c 153 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 154 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 155 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 156 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac 157 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 158 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 159 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 160 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc 161 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 162 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 163 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 164 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc 165 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 166 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 167 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 168 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc 169 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 170 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 171 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 172 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec 173 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 174 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 175 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 176 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc 177 178 #define CONFIG_MEMSIZE 0x5428 179 #define CONFIG_CNTL 0x5424 180 #define CP_STALLED_STAT1 0x8674 181 #define CP_STALLED_STAT2 0x8678 182 #define CP_BUSY_STAT 0x867C 183 #define CP_STAT 0x8680 184 #define CP_COHER_BASE 0x85F8 185 #define CP_DEBUG 0xC1FC 186 #define R_0086D8_CP_ME_CNTL 0x86D8 187 #define S_0086D8_CP_PFP_HALT(x) (((x) & 1)<<26) 188 #define C_0086D8_CP_PFP_HALT(x) ((x) & 0xFBFFFFFF) 189 #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 190 #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 191 #define CP_ME_RAM_DATA 0xC160 192 #define CP_ME_RAM_RADDR 0xC158 193 #define CP_ME_RAM_WADDR 0xC15C 194 #define CP_MEQ_THRESHOLDS 0x8764 195 #define MEQ_END(x) ((x) << 16) 196 #define ROQ_END(x) ((x) << 24) 197 #define CP_PERFMON_CNTL 0x87FC 198 #define CP_PFP_UCODE_ADDR 0xC150 199 #define CP_PFP_UCODE_DATA 0xC154 200 #define CP_QUEUE_THRESHOLDS 0x8760 201 #define ROQ_IB1_START(x) ((x) << 0) 202 #define ROQ_IB2_START(x) ((x) << 8) 203 #define CP_RB_BASE 0xC100 204 #define CP_RB_CNTL 0xC104 205 #define RB_BUFSZ(x) ((x) << 0) 206 #define RB_BLKSZ(x) ((x) << 8) 207 #define RB_NO_UPDATE (1 << 27) 208 #define RB_RPTR_WR_ENA (1 << 31) 209 #define BUF_SWAP_32BIT (2 << 16) 210 #define CP_RB_RPTR 0x8700 211 #define CP_RB_RPTR_ADDR 0xC10C 212 #define RB_RPTR_SWAP(x) ((x) << 0) 213 #define CP_RB_RPTR_ADDR_HI 0xC110 214 #define CP_RB_RPTR_WR 0xC108 215 #define CP_RB_WPTR 0xC114 216 #define CP_RB_WPTR_ADDR 0xC118 217 #define CP_RB_WPTR_ADDR_HI 0xC11C 218 #define CP_RB_WPTR_DELAY 0x8704 219 #define CP_ROQ_IB1_STAT 0x8784 220 #define CP_ROQ_IB2_STAT 0x8788 221 #define CP_SEM_WAIT_TIMER 0x85BC 222 223 #define DB_DEBUG 0x9830 224 #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 225 #define DB_DEPTH_BASE 0x2800C 226 #define DB_HTILE_DATA_BASE 0x28014 227 #define DB_HTILE_SURFACE 0x28D24 228 #define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) 229 #define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 230 #define C_028D24_HTILE_WIDTH 0xFFFFFFFE 231 #define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 232 #define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 233 #define C_028D24_HTILE_HEIGHT 0xFFFFFFFD 234 #define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) 235 #define DB_WATERMARKS 0x9838 236 #define DEPTH_FREE(x) ((x) << 0) 237 #define DEPTH_FLUSH(x) ((x) << 5) 238 #define DEPTH_PENDING_FREE(x) ((x) << 15) 239 #define DEPTH_CACHELINE_FREE(x) ((x) << 20) 240 241 #define DCP_TILING_CONFIG 0x6CA0 242 #define PIPE_TILING(x) ((x) << 1) 243 #define BANK_TILING(x) ((x) << 4) 244 #define GROUP_SIZE(x) ((x) << 6) 245 #define ROW_TILING(x) ((x) << 8) 246 #define BANK_SWAPS(x) ((x) << 11) 247 #define SAMPLE_SPLIT(x) ((x) << 14) 248 #define BACKEND_MAP(x) ((x) << 16) 249 250 #define GB_TILING_CONFIG 0x98F0 251 #define PIPE_TILING__SHIFT 1 252 #define PIPE_TILING__MASK 0x0000000e 253 254 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 255 #define INACTIVE_QD_PIPES(x) ((x) << 8) 256 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 257 #define INACTIVE_SIMDS(x) ((x) << 16) 258 #define INACTIVE_SIMDS_MASK 0x00FF0000 259 260 #define SQ_CONFIG 0x8c00 261 # define VC_ENABLE (1 << 0) 262 # define EXPORT_SRC_C (1 << 1) 263 # define DX9_CONSTS (1 << 2) 264 # define ALU_INST_PREFER_VECTOR (1 << 3) 265 # define DX10_CLAMP (1 << 4) 266 # define CLAUSE_SEQ_PRIO(x) ((x) << 8) 267 # define PS_PRIO(x) ((x) << 24) 268 # define VS_PRIO(x) ((x) << 26) 269 # define GS_PRIO(x) ((x) << 28) 270 # define ES_PRIO(x) ((x) << 30) 271 #define SQ_GPR_RESOURCE_MGMT_1 0x8c04 272 # define NUM_PS_GPRS(x) ((x) << 0) 273 # define NUM_VS_GPRS(x) ((x) << 16) 274 # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 275 #define SQ_GPR_RESOURCE_MGMT_2 0x8c08 276 # define NUM_GS_GPRS(x) ((x) << 0) 277 # define NUM_ES_GPRS(x) ((x) << 16) 278 #define SQ_THREAD_RESOURCE_MGMT 0x8c0c 279 # define NUM_PS_THREADS(x) ((x) << 0) 280 # define NUM_VS_THREADS(x) ((x) << 8) 281 # define NUM_GS_THREADS(x) ((x) << 16) 282 # define NUM_ES_THREADS(x) ((x) << 24) 283 #define SQ_STACK_RESOURCE_MGMT_1 0x8c10 284 # define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 285 # define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 286 #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 287 # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 288 # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 289 #define SQ_ESGS_RING_BASE 0x8c40 290 #define SQ_GSVS_RING_BASE 0x8c48 291 #define SQ_ESTMP_RING_BASE 0x8c50 292 #define SQ_GSTMP_RING_BASE 0x8c58 293 #define SQ_VSTMP_RING_BASE 0x8c60 294 #define SQ_PSTMP_RING_BASE 0x8c68 295 #define SQ_FBUF_RING_BASE 0x8c70 296 #define SQ_REDUC_RING_BASE 0x8c78 297 298 #define GRBM_CNTL 0x8000 299 # define GRBM_READ_TIMEOUT(x) ((x) << 0) 300 #define GRBM_STATUS 0x8010 301 #define CMDFIFO_AVAIL_MASK 0x0000001F 302 #define GUI_ACTIVE (1<<31) 303 #define GRBM_STATUS2 0x8014 304 #define GRBM_SOFT_RESET 0x8020 305 #define SOFT_RESET_CP (1<<0) 306 307 #define CG_THERMAL_STATUS 0x7F4 308 #define ASIC_T(x) ((x) << 0) 309 #define ASIC_T_MASK 0x1FF 310 #define ASIC_T_SHIFT 0 311 312 #define HDP_HOST_PATH_CNTL 0x2C00 313 #define HDP_NONSURFACE_BASE 0x2C04 314 #define HDP_NONSURFACE_INFO 0x2C08 315 #define HDP_NONSURFACE_SIZE 0x2C0C 316 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 317 #define HDP_TILING_CONFIG 0x2F3C 318 #define HDP_DEBUG1 0x2F34 319 320 #define MC_VM_AGP_TOP 0x2184 321 #define MC_VM_AGP_BOT 0x2188 322 #define MC_VM_AGP_BASE 0x218C 323 #define MC_VM_FB_LOCATION 0x2180 324 #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C 325 #define ENABLE_L1_TLB (1 << 0) 326 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 327 #define ENABLE_L1_STRICT_ORDERING (1 << 2) 328 #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 329 #define SYSTEM_ACCESS_MODE_SHIFT 6 330 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 331 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 332 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 333 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 334 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 335 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 336 #define ENABLE_SEMAPHORE_MODE (1 << 10) 337 #define ENABLE_WAIT_L2_QUERY (1 << 11) 338 #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) 339 #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 340 #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 341 #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) 342 #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 343 #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 344 #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 345 #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC 346 #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 347 #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 348 #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C 349 #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 350 #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 351 #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 352 #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 353 #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 354 #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C 355 #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 356 #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 357 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 358 #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 359 #define LOGICAL_PAGE_NUMBER_SHIFT 0 360 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 361 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 362 363 #define PA_CL_ENHANCE 0x8A14 364 #define CLIP_VTX_REORDER_ENA (1 << 0) 365 #define NUM_CLIP_SEQ(x) ((x) << 1) 366 #define PA_SC_AA_CONFIG 0x28C04 367 #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 368 #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 369 #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 370 #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C 371 #define S0_X(x) ((x) << 0) 372 #define S0_Y(x) ((x) << 4) 373 #define S1_X(x) ((x) << 8) 374 #define S1_Y(x) ((x) << 12) 375 #define S2_X(x) ((x) << 16) 376 #define S2_Y(x) ((x) << 20) 377 #define S3_X(x) ((x) << 24) 378 #define S3_Y(x) ((x) << 28) 379 #define S4_X(x) ((x) << 0) 380 #define S4_Y(x) ((x) << 4) 381 #define S5_X(x) ((x) << 8) 382 #define S5_Y(x) ((x) << 12) 383 #define S6_X(x) ((x) << 16) 384 #define S6_Y(x) ((x) << 20) 385 #define S7_X(x) ((x) << 24) 386 #define S7_Y(x) ((x) << 28) 387 #define PA_SC_CLIPRECT_RULE 0x2820c 388 #define PA_SC_ENHANCE 0x8BF0 389 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 390 #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 391 #define PA_SC_LINE_STIPPLE 0x28A0C 392 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 393 #define PA_SC_MODE_CNTL 0x28A4C 394 #define PA_SC_MULTI_CHIP_CNTL 0x8B20 395 396 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 397 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 398 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 399 400 #define PCIE_PORT_INDEX 0x0038 401 #define PCIE_PORT_DATA 0x003C 402 403 #define CHMAP 0x2004 404 #define NOOFCHAN_SHIFT 12 405 #define NOOFCHAN_MASK 0x00003000 406 407 #define RAMCFG 0x2408 408 #define NOOFBANK_SHIFT 0 409 #define NOOFBANK_MASK 0x00000001 410 #define NOOFRANK_SHIFT 1 411 #define NOOFRANK_MASK 0x00000002 412 #define NOOFROWS_SHIFT 2 413 #define NOOFROWS_MASK 0x0000001C 414 #define NOOFCOLS_SHIFT 5 415 #define NOOFCOLS_MASK 0x00000060 416 #define CHANSIZE_SHIFT 7 417 #define CHANSIZE_MASK 0x00000080 418 #define BURSTLENGTH_SHIFT 8 419 #define BURSTLENGTH_MASK 0x00000100 420 #define CHANSIZE_OVERRIDE (1 << 10) 421 422 #define SCRATCH_REG0 0x8500 423 #define SCRATCH_REG1 0x8504 424 #define SCRATCH_REG2 0x8508 425 #define SCRATCH_REG3 0x850C 426 #define SCRATCH_REG4 0x8510 427 #define SCRATCH_REG5 0x8514 428 #define SCRATCH_REG6 0x8518 429 #define SCRATCH_REG7 0x851C 430 #define SCRATCH_UMSK 0x8540 431 #define SCRATCH_ADDR 0x8544 432 433 #define SPI_CONFIG_CNTL 0x9100 434 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 435 #define DISABLE_INTERP_1 (1 << 5) 436 #define SPI_CONFIG_CNTL_1 0x913C 437 #define VTX_DONE_DELAY(x) ((x) << 0) 438 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 439 #define SPI_INPUT_Z 0x286D8 440 #define SPI_PS_IN_CONTROL_0 0x286CC 441 #define NUM_INTERP(x) ((x)<<0) 442 #define POSITION_ENA (1<<8) 443 #define POSITION_CENTROID (1<<9) 444 #define POSITION_ADDR(x) ((x)<<10) 445 #define PARAM_GEN(x) ((x)<<15) 446 #define PARAM_GEN_ADDR(x) ((x)<<19) 447 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 448 #define PERSP_GRADIENT_ENA (1<<28) 449 #define LINEAR_GRADIENT_ENA (1<<29) 450 #define POSITION_SAMPLE (1<<30) 451 #define BARYC_AT_SAMPLE_ENA (1<<31) 452 #define SPI_PS_IN_CONTROL_1 0x286D0 453 #define GEN_INDEX_PIX (1<<0) 454 #define GEN_INDEX_PIX_ADDR(x) ((x)<<1) 455 #define FRONT_FACE_ENA (1<<8) 456 #define FRONT_FACE_CHAN(x) ((x)<<9) 457 #define FRONT_FACE_ALL_BITS (1<<11) 458 #define FRONT_FACE_ADDR(x) ((x)<<12) 459 #define FOG_ADDR(x) ((x)<<17) 460 #define FIXED_PT_POSITION_ENA (1<<24) 461 #define FIXED_PT_POSITION_ADDR(x) ((x)<<25) 462 463 #define SQ_MS_FIFO_SIZES 0x8CF0 464 #define CACHE_FIFO_SIZE(x) ((x) << 0) 465 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 466 #define DONE_FIFO_HIWATER(x) ((x) << 16) 467 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 468 #define SQ_PGM_START_ES 0x28880 469 #define SQ_PGM_START_FS 0x28894 470 #define SQ_PGM_START_GS 0x2886C 471 #define SQ_PGM_START_PS 0x28840 472 #define SQ_PGM_RESOURCES_PS 0x28850 473 #define SQ_PGM_EXPORTS_PS 0x28854 474 #define SQ_PGM_CF_OFFSET_PS 0x288cc 475 #define SQ_PGM_START_VS 0x28858 476 #define SQ_PGM_RESOURCES_VS 0x28868 477 #define SQ_PGM_CF_OFFSET_VS 0x288d0 478 479 #define SQ_VTX_CONSTANT_WORD0_0 0x30000 480 #define SQ_VTX_CONSTANT_WORD1_0 0x30004 481 #define SQ_VTX_CONSTANT_WORD2_0 0x30008 482 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 483 # define SQ_VTXC_STRIDE(x) ((x) << 8) 484 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 485 # define SQ_ENDIAN_NONE 0 486 # define SQ_ENDIAN_8IN16 1 487 # define SQ_ENDIAN_8IN32 2 488 #define SQ_VTX_CONSTANT_WORD3_0 0x3000c 489 #define SQ_VTX_CONSTANT_WORD6_0 0x38018 490 #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) 491 #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) 492 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 493 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 494 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 495 #define SQ_TEX_VTX_VALID_BUFFER 0x3 496 497 498 #define SX_MISC 0x28350 499 #define SX_MEMORY_EXPORT_BASE 0x9010 500 #define SX_DEBUG_1 0x9054 501 #define SMX_EVENT_RELEASE (1 << 0) 502 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 503 504 #define TA_CNTL_AUX 0x9508 505 #define DISABLE_CUBE_WRAP (1 << 0) 506 #define DISABLE_CUBE_ANISO (1 << 1) 507 #define SYNC_GRADIENT (1 << 24) 508 #define SYNC_WALKER (1 << 25) 509 #define SYNC_ALIGNER (1 << 26) 510 #define BILINEAR_PRECISION_6_BIT (0 << 31) 511 #define BILINEAR_PRECISION_8_BIT (1 << 31) 512 513 #define TC_CNTL 0x9608 514 #define TC_L2_SIZE(x) ((x)<<5) 515 #define L2_DISABLE_LATE_HIT (1<<9) 516 517 #define VC_ENHANCE 0x9714 518 519 #define VGT_CACHE_INVALIDATION 0x88C4 520 #define CACHE_INVALIDATION(x) ((x)<<0) 521 #define VC_ONLY 0 522 #define TC_ONLY 1 523 #define VC_AND_TC 2 524 #define VGT_DMA_BASE 0x287E8 525 #define VGT_DMA_BASE_HI 0x287E4 526 #define VGT_ES_PER_GS 0x88CC 527 #define VGT_GS_PER_ES 0x88C8 528 #define VGT_GS_PER_VS 0x88E8 529 #define VGT_GS_VERTEX_REUSE 0x88D4 530 #define VGT_PRIMITIVE_TYPE 0x8958 531 #define VGT_NUM_INSTANCES 0x8974 532 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 533 #define DEALLOC_DIST_MASK 0x0000007F 534 #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 535 #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 536 #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 537 #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c 538 #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 539 #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 540 #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c 541 #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 542 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 543 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 544 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 545 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 546 #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC 547 #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC 548 #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC 549 #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C 550 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 551 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 552 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 553 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 554 555 #define VGT_STRMOUT_EN 0x28AB0 556 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 557 #define VTX_REUSE_DEPTH_MASK 0x000000FF 558 #define VGT_EVENT_INITIATOR 0x28a90 559 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 560 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 561 562 #define VM_CONTEXT0_CNTL 0x1410 563 #define ENABLE_CONTEXT (1 << 0) 564 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 565 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 566 #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 567 #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 568 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 569 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 570 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 571 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 572 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 573 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 574 #define RESPONSE_TYPE_MASK 0x000000F0 575 #define RESPONSE_TYPE_SHIFT 4 576 #define VM_L2_CNTL 0x1400 577 #define ENABLE_L2_CACHE (1 << 0) 578 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 579 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 580 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) 581 #define VM_L2_CNTL2 0x1404 582 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 583 #define INVALIDATE_L2_CACHE (1 << 1) 584 #define VM_L2_CNTL3 0x1408 585 #define BANK_SELECT_0(x) (((x) & 0x1f) << 0) 586 #define BANK_SELECT_1(x) (((x) & 0x1f) << 5) 587 #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) 588 #define VM_L2_STATUS 0x140C 589 #define L2_BUSY (1 << 0) 590 591 #define WAIT_UNTIL 0x8040 592 #define WAIT_2D_IDLE_bit (1 << 14) 593 #define WAIT_3D_IDLE_bit (1 << 15) 594 #define WAIT_2D_IDLECLEAN_bit (1 << 16) 595 #define WAIT_3D_IDLECLEAN_bit (1 << 17) 596 597 /* async DMA */ 598 #define DMA_TILING_CONFIG 0x3ec4 599 #define DMA_CONFIG 0x3e4c 600 601 #define DMA_RB_CNTL 0xd000 602 # define DMA_RB_ENABLE (1 << 0) 603 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 604 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 605 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 606 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 607 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 608 #define DMA_RB_BASE 0xd004 609 #define DMA_RB_RPTR 0xd008 610 #define DMA_RB_WPTR 0xd00c 611 612 #define DMA_RB_RPTR_ADDR_HI 0xd01c 613 #define DMA_RB_RPTR_ADDR_LO 0xd020 614 615 #define DMA_IB_CNTL 0xd024 616 # define DMA_IB_ENABLE (1 << 0) 617 # define DMA_IB_SWAP_ENABLE (1 << 4) 618 #define DMA_IB_RPTR 0xd028 619 #define DMA_CNTL 0xd02c 620 # define TRAP_ENABLE (1 << 0) 621 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 622 # define SEM_WAIT_INT_ENABLE (1 << 2) 623 # define DATA_SWAP_ENABLE (1 << 3) 624 # define FENCE_SWAP_ENABLE (1 << 4) 625 # define CTXEMPTY_INT_ENABLE (1 << 28) 626 #define DMA_STATUS_REG 0xd034 627 # define DMA_IDLE (1 << 0) 628 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 629 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 630 #define DMA_MODE 0xd0bc 631 632 /* async DMA packets */ 633 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 634 (((t) & 0x1) << 23) | \ 635 (((s) & 0x1) << 22) | \ 636 (((n) & 0xFFFF) << 0)) 637 /* async DMA Packet types */ 638 #define DMA_PACKET_WRITE 0x2 639 #define DMA_PACKET_COPY 0x3 640 #define DMA_PACKET_INDIRECT_BUFFER 0x4 641 #define DMA_PACKET_SEMAPHORE 0x5 642 #define DMA_PACKET_FENCE 0x6 643 #define DMA_PACKET_TRAP 0x7 644 #define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */ 645 #define DMA_PACKET_NOP 0xf 646 647 #define IH_RB_CNTL 0x3e00 648 # define IH_RB_ENABLE (1 << 0) 649 # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 650 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 651 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 652 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 653 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 654 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 655 #define IH_RB_BASE 0x3e04 656 #define IH_RB_RPTR 0x3e08 657 #define IH_RB_WPTR 0x3e0c 658 # define RB_OVERFLOW (1 << 0) 659 # define WPTR_OFFSET_MASK 0x3fffc 660 #define IH_RB_WPTR_ADDR_HI 0x3e10 661 #define IH_RB_WPTR_ADDR_LO 0x3e14 662 #define IH_CNTL 0x3e18 663 # define ENABLE_INTR (1 << 0) 664 # define IH_MC_SWAP(x) ((x) << 1) 665 # define IH_MC_SWAP_NONE 0 666 # define IH_MC_SWAP_16BIT 1 667 # define IH_MC_SWAP_32BIT 2 668 # define IH_MC_SWAP_64BIT 3 669 # define RPTR_REARM (1 << 4) 670 # define MC_WRREQ_CREDIT(x) ((x) << 15) 671 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 672 673 #define RLC_CNTL 0x3f00 674 # define RLC_ENABLE (1 << 0) 675 #define RLC_HB_BASE 0x3f10 676 #define RLC_HB_CNTL 0x3f0c 677 #define RLC_HB_RPTR 0x3f20 678 #define RLC_HB_WPTR 0x3f1c 679 #define RLC_HB_WPTR_LSB_ADDR 0x3f14 680 #define RLC_HB_WPTR_MSB_ADDR 0x3f18 681 #define RLC_GPU_CLOCK_COUNT_LSB 0x3f38 682 #define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c 683 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40 684 #define RLC_MC_CNTL 0x3f44 685 #define RLC_UCODE_CNTL 0x3f48 686 #define RLC_UCODE_ADDR 0x3f2c 687 #define RLC_UCODE_DATA 0x3f30 688 689 /* new for TN */ 690 #define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 691 #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 692 693 #define SRBM_SOFT_RESET 0xe60 694 # define SOFT_RESET_DMA (1 << 12) 695 # define SOFT_RESET_RLC (1 << 13) 696 # define RV770_SOFT_RESET_DMA (1 << 20) 697 698 #define CP_INT_CNTL 0xc124 699 # define CNTX_BUSY_INT_ENABLE (1 << 19) 700 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 701 # define SCRATCH_INT_ENABLE (1 << 25) 702 # define TIME_STAMP_INT_ENABLE (1 << 26) 703 # define IB2_INT_ENABLE (1 << 29) 704 # define IB1_INT_ENABLE (1 << 30) 705 # define RB_INT_ENABLE (1 << 31) 706 #define CP_INT_STATUS 0xc128 707 # define SCRATCH_INT_STAT (1 << 25) 708 # define TIME_STAMP_INT_STAT (1 << 26) 709 # define IB2_INT_STAT (1 << 29) 710 # define IB1_INT_STAT (1 << 30) 711 # define RB_INT_STAT (1 << 31) 712 713 #define GRBM_INT_CNTL 0x8060 714 # define RDERR_INT_ENABLE (1 << 0) 715 # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) 716 # define GUI_IDLE_INT_ENABLE (1 << 19) 717 718 #define INTERRUPT_CNTL 0x5468 719 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 720 # define IH_DUMMY_RD_EN (1 << 1) 721 # define IH_REQ_NONSNOOP_EN (1 << 3) 722 # define GEN_IH_INT_EN (1 << 8) 723 #define INTERRUPT_CNTL2 0x546c 724 725 #define D1MODE_VBLANK_STATUS 0x6534 726 #define D2MODE_VBLANK_STATUS 0x6d34 727 # define DxMODE_VBLANK_OCCURRED (1 << 0) 728 # define DxMODE_VBLANK_ACK (1 << 4) 729 # define DxMODE_VBLANK_STAT (1 << 12) 730 # define DxMODE_VBLANK_INTERRUPT (1 << 16) 731 # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) 732 #define D1MODE_VLINE_STATUS 0x653c 733 #define D2MODE_VLINE_STATUS 0x6d3c 734 # define DxMODE_VLINE_OCCURRED (1 << 0) 735 # define DxMODE_VLINE_ACK (1 << 4) 736 # define DxMODE_VLINE_STAT (1 << 12) 737 # define DxMODE_VLINE_INTERRUPT (1 << 16) 738 # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) 739 #define DxMODE_INT_MASK 0x6540 740 # define D1MODE_VBLANK_INT_MASK (1 << 0) 741 # define D1MODE_VLINE_INT_MASK (1 << 4) 742 # define D2MODE_VBLANK_INT_MASK (1 << 8) 743 # define D2MODE_VLINE_INT_MASK (1 << 12) 744 #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc 745 # define DC_HPD1_INTERRUPT (1 << 18) 746 # define DC_HPD2_INTERRUPT (1 << 19) 747 #define DISP_INTERRUPT_STATUS 0x7edc 748 # define LB_D1_VLINE_INTERRUPT (1 << 2) 749 # define LB_D2_VLINE_INTERRUPT (1 << 3) 750 # define LB_D1_VBLANK_INTERRUPT (1 << 4) 751 # define LB_D2_VBLANK_INTERRUPT (1 << 5) 752 # define DACA_AUTODETECT_INTERRUPT (1 << 16) 753 # define DACB_AUTODETECT_INTERRUPT (1 << 17) 754 # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) 755 # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) 756 # define DC_I2C_SW_DONE_INTERRUPT (1 << 20) 757 # define DC_I2C_HW_DONE_INTERRUPT (1 << 21) 758 #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 759 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 760 # define DC_HPD4_INTERRUPT (1 << 14) 761 # define DC_HPD4_RX_INTERRUPT (1 << 15) 762 # define DC_HPD3_INTERRUPT (1 << 28) 763 # define DC_HPD1_RX_INTERRUPT (1 << 29) 764 # define DC_HPD2_RX_INTERRUPT (1 << 30) 765 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec 766 # define DC_HPD3_RX_INTERRUPT (1 << 0) 767 # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) 768 # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) 769 # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) 770 # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) 771 # define AUX1_SW_DONE_INTERRUPT (1 << 5) 772 # define AUX1_LS_DONE_INTERRUPT (1 << 6) 773 # define AUX2_SW_DONE_INTERRUPT (1 << 7) 774 # define AUX2_LS_DONE_INTERRUPT (1 << 8) 775 # define AUX3_SW_DONE_INTERRUPT (1 << 9) 776 # define AUX3_LS_DONE_INTERRUPT (1 << 10) 777 # define AUX4_SW_DONE_INTERRUPT (1 << 11) 778 # define AUX4_LS_DONE_INTERRUPT (1 << 12) 779 # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) 780 # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) 781 /* DCE 3.2 */ 782 # define AUX5_SW_DONE_INTERRUPT (1 << 15) 783 # define AUX5_LS_DONE_INTERRUPT (1 << 16) 784 # define AUX6_SW_DONE_INTERRUPT (1 << 17) 785 # define AUX6_LS_DONE_INTERRUPT (1 << 18) 786 # define DC_HPD5_INTERRUPT (1 << 19) 787 # define DC_HPD5_RX_INTERRUPT (1 << 20) 788 # define DC_HPD6_INTERRUPT (1 << 21) 789 # define DC_HPD6_RX_INTERRUPT (1 << 22) 790 791 #define DACA_AUTO_DETECT_CONTROL 0x7828 792 #define DACB_AUTO_DETECT_CONTROL 0x7a28 793 #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 794 #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 795 # define DACx_AUTODETECT_MODE(x) ((x) << 0) 796 # define DACx_AUTODETECT_MODE_NONE 0 797 # define DACx_AUTODETECT_MODE_CONNECT 1 798 # define DACx_AUTODETECT_MODE_DISCONNECT 2 799 # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) 800 /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ 801 # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) 802 803 #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 804 #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 805 #define DACA_AUTODETECT_INT_CONTROL 0x7838 806 #define DACB_AUTODETECT_INT_CONTROL 0x7a38 807 # define DACx_AUTODETECT_ACK (1 << 0) 808 # define DACx_AUTODETECT_INT_ENABLE (1 << 16) 809 810 #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 811 #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 812 #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 813 # define DC_HOT_PLUG_DETECTx_EN (1 << 0) 814 815 #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 816 #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 817 #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 818 # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) 819 # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) 820 821 /* DCE 3.0 */ 822 #define DC_HPD1_INT_STATUS 0x7d00 823 #define DC_HPD2_INT_STATUS 0x7d0c 824 #define DC_HPD3_INT_STATUS 0x7d18 825 #define DC_HPD4_INT_STATUS 0x7d24 826 /* DCE 3.2 */ 827 #define DC_HPD5_INT_STATUS 0x7dc0 828 #define DC_HPD6_INT_STATUS 0x7df4 829 # define DC_HPDx_INT_STATUS (1 << 0) 830 # define DC_HPDx_SENSE (1 << 1) 831 # define DC_HPDx_RX_INT_STATUS (1 << 8) 832 833 #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 834 #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 835 #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c 836 # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) 837 # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) 838 # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) 839 /* DCE 3.0 */ 840 #define DC_HPD1_INT_CONTROL 0x7d04 841 #define DC_HPD2_INT_CONTROL 0x7d10 842 #define DC_HPD3_INT_CONTROL 0x7d1c 843 #define DC_HPD4_INT_CONTROL 0x7d28 844 /* DCE 3.2 */ 845 #define DC_HPD5_INT_CONTROL 0x7dc4 846 #define DC_HPD6_INT_CONTROL 0x7df8 847 # define DC_HPDx_INT_ACK (1 << 0) 848 # define DC_HPDx_INT_POLARITY (1 << 8) 849 # define DC_HPDx_INT_EN (1 << 16) 850 # define DC_HPDx_RX_INT_ACK (1 << 20) 851 # define DC_HPDx_RX_INT_EN (1 << 24) 852 853 /* DCE 3.0 */ 854 #define DC_HPD1_CONTROL 0x7d08 855 #define DC_HPD2_CONTROL 0x7d14 856 #define DC_HPD3_CONTROL 0x7d20 857 #define DC_HPD4_CONTROL 0x7d2c 858 /* DCE 3.2 */ 859 #define DC_HPD5_CONTROL 0x7dc8 860 #define DC_HPD6_CONTROL 0x7dfc 861 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 862 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 863 /* DCE 3.2 */ 864 # define DC_HPDx_EN (1 << 28) 865 866 #define D1GRPH_INTERRUPT_STATUS 0x6158 867 #define D2GRPH_INTERRUPT_STATUS 0x6958 868 # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) 869 # define DxGRPH_PFLIP_INT_CLEAR (1 << 8) 870 #define D1GRPH_INTERRUPT_CONTROL 0x615c 871 #define D2GRPH_INTERRUPT_CONTROL 0x695c 872 # define DxGRPH_PFLIP_INT_MASK (1 << 0) 873 # define DxGRPH_PFLIP_INT_TYPE (1 << 8) 874 875 /* PCIE link stuff */ 876 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 877 # define LC_POINT_7_PLUS_EN (1 << 6) 878 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 879 # define LC_LINK_WIDTH_SHIFT 0 880 # define LC_LINK_WIDTH_MASK 0x7 881 # define LC_LINK_WIDTH_X0 0 882 # define LC_LINK_WIDTH_X1 1 883 # define LC_LINK_WIDTH_X2 2 884 # define LC_LINK_WIDTH_X4 3 885 # define LC_LINK_WIDTH_X8 4 886 # define LC_LINK_WIDTH_X16 6 887 # define LC_LINK_WIDTH_RD_SHIFT 4 888 # define LC_LINK_WIDTH_RD_MASK 0x70 889 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 890 # define LC_RECONFIG_NOW (1 << 8) 891 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 892 # define LC_RENEGOTIATE_EN (1 << 10) 893 # define LC_SHORT_RECONFIG_EN (1 << 11) 894 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 895 # define LC_UPCONFIGURE_DIS (1 << 13) 896 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 897 # define LC_GEN2_EN_STRAP (1 << 0) 898 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 899 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 900 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 901 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 902 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 903 # define LC_CURRENT_DATA_RATE (1 << 11) 904 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 905 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 906 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 907 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 908 #define MM_CFGREGS_CNTL 0x544c 909 # define MM_WR_TO_CFG_EN (1 << 3) 910 #define LINK_CNTL2 0x88 /* F0 */ 911 # define TARGET_LINK_SPEED_MASK (0xf << 0) 912 # define SELECTABLE_DEEMPHASIS (1 << 6) 913 914 /* Audio clocks */ 915 #define DCCG_AUDIO_DTO0_PHASE 0x0514 916 #define DCCG_AUDIO_DTO0_MODULE 0x0518 917 #define DCCG_AUDIO_DTO0_LOAD 0x051c 918 # define DTO_LOAD (1 << 31) 919 #define DCCG_AUDIO_DTO0_CNTL 0x0520 920 921 #define DCCG_AUDIO_DTO1_PHASE 0x0524 922 #define DCCG_AUDIO_DTO1_MODULE 0x0528 923 #define DCCG_AUDIO_DTO1_LOAD 0x052c 924 #define DCCG_AUDIO_DTO1_CNTL 0x0530 925 926 #define DCCG_AUDIO_DTO_SELECT 0x0534 927 928 /* digital blocks */ 929 #define TMDSA_CNTL 0x7880 930 # define TMDSA_HDMI_EN (1 << 2) 931 #define LVTMA_CNTL 0x7a80 932 # define LVTMA_HDMI_EN (1 << 2) 933 #define DDIA_CNTL 0x7200 934 # define DDIA_HDMI_EN (1 << 2) 935 #define DIG0_CNTL 0x75a0 936 # define DIG_MODE(x) (((x) & 7) << 8) 937 # define DIG_MODE_DP 0 938 # define DIG_MODE_LVDS 1 939 # define DIG_MODE_TMDS_DVI 2 940 # define DIG_MODE_TMDS_HDMI 3 941 # define DIG_MODE_SDVO 4 942 #define DIG1_CNTL 0x79a0 943 944 /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one 945 * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly 946 * different due to the new DIG blocks, but also have 2 instances. 947 * DCE 3.0 HDMI blocks are part of each DIG encoder. 948 */ 949 950 /* rs6xx/rs740/r6xx/dce3 */ 951 #define HDMI0_CONTROL 0x7400 952 /* rs6xx/rs740/r6xx */ 953 # define HDMI0_ENABLE (1 << 0) 954 # define HDMI0_STREAM(x) (((x) & 3) << 2) 955 # define HDMI0_STREAM_TMDSA 0 956 # define HDMI0_STREAM_LVTMA 1 957 # define HDMI0_STREAM_DVOA 2 958 # define HDMI0_STREAM_DDIA 3 959 /* rs6xx/r6xx/dce3 */ 960 # define HDMI0_ERROR_ACK (1 << 8) 961 # define HDMI0_ERROR_MASK (1 << 9) 962 #define HDMI0_STATUS 0x7404 963 # define HDMI0_ACTIVE_AVMUTE (1 << 0) 964 # define HDMI0_AUDIO_ENABLE (1 << 4) 965 # define HDMI0_AZ_FORMAT_WTRIG (1 << 28) 966 # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) 967 #define HDMI0_AUDIO_PACKET_CONTROL 0x7408 968 # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) 969 # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 970 # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) 971 # define HDMI0_AUDIO_TEST_EN (1 << 12) 972 # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 973 # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) 974 # define HDMI0_60958_CS_UPDATE (1 << 26) 975 # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) 976 # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) 977 #define HDMI0_AUDIO_CRC_CONTROL 0x740c 978 # define HDMI0_AUDIO_CRC_EN (1 << 0) 979 #define HDMI0_VBI_PACKET_CONTROL 0x7410 980 # define HDMI0_NULL_SEND (1 << 0) 981 # define HDMI0_GC_SEND (1 << 4) 982 # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 983 #define HDMI0_INFOFRAME_CONTROL0 0x7414 984 # define HDMI0_AVI_INFO_SEND (1 << 0) 985 # define HDMI0_AVI_INFO_CONT (1 << 1) 986 # define HDMI0_AUDIO_INFO_SEND (1 << 4) 987 # define HDMI0_AUDIO_INFO_CONT (1 << 5) 988 # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ 989 # define HDMI0_AUDIO_INFO_UPDATE (1 << 7) 990 # define HDMI0_MPEG_INFO_SEND (1 << 8) 991 # define HDMI0_MPEG_INFO_CONT (1 << 9) 992 # define HDMI0_MPEG_INFO_UPDATE (1 << 10) 993 #define HDMI0_INFOFRAME_CONTROL1 0x7418 994 # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 995 # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 996 # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 997 #define HDMI0_GENERIC_PACKET_CONTROL 0x741c 998 # define HDMI0_GENERIC0_SEND (1 << 0) 999 # define HDMI0_GENERIC0_CONT (1 << 1) 1000 # define HDMI0_GENERIC0_UPDATE (1 << 2) 1001 # define HDMI0_GENERIC1_SEND (1 << 4) 1002 # define HDMI0_GENERIC1_CONT (1 << 5) 1003 # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 1004 # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 1005 #define HDMI0_GC 0x7428 1006 # define HDMI0_GC_AVMUTE (1 << 0) 1007 #define HDMI0_AVI_INFO0 0x7454 1008 # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1009 # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) 1010 # define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10) 1011 # define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12) 1012 # define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13) 1013 # define HDMI0_AVI_INFO_Y_RGB 0 1014 # define HDMI0_AVI_INFO_Y_YCBCR422 1 1015 # define HDMI0_AVI_INFO_Y_YCBCR444 2 1016 # define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 1017 # define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16) 1018 # define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20) 1019 # define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22) 1020 # define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 1021 # define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24) 1022 # define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 1023 #define HDMI0_AVI_INFO1 0x7458 1024 # define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 1025 # define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 1026 # define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 1027 #define HDMI0_AVI_INFO2 0x745c 1028 # define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 1029 # define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 1030 #define HDMI0_AVI_INFO3 0x7460 1031 # define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 1032 # define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24) 1033 #define HDMI0_MPEG_INFO0 0x7464 1034 # define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1035 # define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 1036 # define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 1037 # define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 1038 #define HDMI0_MPEG_INFO1 0x7468 1039 # define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 1040 # define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8) 1041 # define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12) 1042 #define HDMI0_GENERIC0_HDR 0x746c 1043 #define HDMI0_GENERIC0_0 0x7470 1044 #define HDMI0_GENERIC0_1 0x7474 1045 #define HDMI0_GENERIC0_2 0x7478 1046 #define HDMI0_GENERIC0_3 0x747c 1047 #define HDMI0_GENERIC0_4 0x7480 1048 #define HDMI0_GENERIC0_5 0x7484 1049 #define HDMI0_GENERIC0_6 0x7488 1050 #define HDMI0_GENERIC1_HDR 0x748c 1051 #define HDMI0_GENERIC1_0 0x7490 1052 #define HDMI0_GENERIC1_1 0x7494 1053 #define HDMI0_GENERIC1_2 0x7498 1054 #define HDMI0_GENERIC1_3 0x749c 1055 #define HDMI0_GENERIC1_4 0x74a0 1056 #define HDMI0_GENERIC1_5 0x74a4 1057 #define HDMI0_GENERIC1_6 0x74a8 1058 #define HDMI0_ACR_32_0 0x74ac 1059 # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 1060 #define HDMI0_ACR_32_1 0x74b0 1061 # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) 1062 #define HDMI0_ACR_44_0 0x74b4 1063 # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 1064 #define HDMI0_ACR_44_1 0x74b8 1065 # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) 1066 #define HDMI0_ACR_48_0 0x74bc 1067 # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 1068 #define HDMI0_ACR_48_1 0x74c0 1069 # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) 1070 #define HDMI0_ACR_STATUS_0 0x74c4 1071 #define HDMI0_ACR_STATUS_1 0x74c8 1072 #define HDMI0_AUDIO_INFO0 0x74cc 1073 # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1074 # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) 1075 #define HDMI0_AUDIO_INFO1 0x74d0 1076 # define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 1077 # define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 1078 # define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 1079 # define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 1080 #define HDMI0_60958_0 0x74d4 1081 # define HDMI0_60958_CS_A(x) (((x) & 1) << 0) 1082 # define HDMI0_60958_CS_B(x) (((x) & 1) << 1) 1083 # define HDMI0_60958_CS_C(x) (((x) & 1) << 2) 1084 # define HDMI0_60958_CS_D(x) (((x) & 3) << 3) 1085 # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) 1086 # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 1087 # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 1088 # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 1089 # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 1090 # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 1091 #define HDMI0_60958_1 0x74d8 1092 # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 1093 # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 1094 # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) 1095 # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) 1096 # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 1097 #define HDMI0_ACR_PACKET_CONTROL 0x74dc 1098 # define HDMI0_ACR_SEND (1 << 0) 1099 # define HDMI0_ACR_CONT (1 << 1) 1100 # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) 1101 # define HDMI0_ACR_HW 0 1102 # define HDMI0_ACR_32 1 1103 # define HDMI0_ACR_44 2 1104 # define HDMI0_ACR_48 3 1105 # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 1106 # define HDMI0_ACR_AUTO_SEND (1 << 12) 1107 #define HDMI0_RAMP_CONTROL0 0x74e0 1108 # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 1109 #define HDMI0_RAMP_CONTROL1 0x74e4 1110 # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 1111 #define HDMI0_RAMP_CONTROL2 0x74e8 1112 # define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 1113 #define HDMI0_RAMP_CONTROL3 0x74ec 1114 # define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 1115 /* HDMI0_60958_2 is r7xx only */ 1116 #define HDMI0_60958_2 0x74f0 1117 # define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 1118 # define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 1119 # define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 1120 # define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 1121 # define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 1122 # define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 1123 /* r6xx only; second instance starts at 0x7700 */ 1124 #define HDMI1_CONTROL 0x7700 1125 #define HDMI1_STATUS 0x7704 1126 #define HDMI1_AUDIO_PACKET_CONTROL 0x7708 1127 /* DCE3; second instance starts at 0x7800 NOT 0x7700 */ 1128 #define DCE3_HDMI1_CONTROL 0x7800 1129 #define DCE3_HDMI1_STATUS 0x7804 1130 #define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808 1131 /* DCE3.2 (for interrupts) */ 1132 #define AFMT_STATUS 0x7600 1133 # define AFMT_AUDIO_ENABLE (1 << 4) 1134 # define AFMT_AZ_FORMAT_WTRIG (1 << 28) 1135 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 1136 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 1137 #define AFMT_AUDIO_PACKET_CONTROL 0x7604 1138 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 1139 # define AFMT_AUDIO_TEST_EN (1 << 12) 1140 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 1141 # define AFMT_60958_CS_UPDATE (1 << 26) 1142 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 1143 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 1144 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 1145 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 1146 1147 /* 1148 * PM4 1149 */ 1150 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1151 (((reg) >> 2) & 0xFFFF) | \ 1152 ((n) & 0x3FFF) << 16) 1153 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1154 (((op) & 0xFF) << 8) | \ 1155 ((n) & 0x3FFF) << 16) 1156 1157 /* Packet 3 types */ 1158 #define PACKET3_NOP 0x10 1159 #define PACKET3_INDIRECT_BUFFER_END 0x17 1160 #define PACKET3_SET_PREDICATION 0x20 1161 #define PACKET3_REG_RMW 0x21 1162 #define PACKET3_COND_EXEC 0x22 1163 #define PACKET3_PRED_EXEC 0x23 1164 #define PACKET3_START_3D_CMDBUF 0x24 1165 #define PACKET3_DRAW_INDEX_2 0x27 1166 #define PACKET3_CONTEXT_CONTROL 0x28 1167 #define PACKET3_DRAW_INDEX_IMMD_BE 0x29 1168 #define PACKET3_INDEX_TYPE 0x2A 1169 #define PACKET3_DRAW_INDEX 0x2B 1170 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1171 #define PACKET3_DRAW_INDEX_IMMD 0x2E 1172 #define PACKET3_NUM_INSTANCES 0x2F 1173 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1174 #define PACKET3_INDIRECT_BUFFER_MP 0x38 1175 #define PACKET3_MEM_SEMAPHORE 0x39 1176 # define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 1177 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 1178 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1179 #define PACKET3_MPEG_INDEX 0x3A 1180 #define PACKET3_COPY_DW 0x3B 1181 #define PACKET3_WAIT_REG_MEM 0x3C 1182 #define PACKET3_MEM_WRITE 0x3D 1183 #define PACKET3_INDIRECT_BUFFER 0x32 1184 #define PACKET3_CP_DMA 0x41 1185 /* 1. header 1186 * 2. SRC_ADDR_LO [31:0] 1187 * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0] 1188 * 4. DST_ADDR_LO [31:0] 1189 * 5. DST_ADDR_HI [7:0] 1190 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1191 */ 1192 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1193 /* COMMAND */ 1194 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1195 /* 0 - none 1196 * 1 - 8 in 16 1197 * 2 - 8 in 32 1198 * 3 - 8 in 64 1199 */ 1200 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1201 /* 0 - none 1202 * 1 - 8 in 16 1203 * 2 - 8 in 32 1204 * 3 - 8 in 64 1205 */ 1206 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1207 /* 0 - memory 1208 * 1 - register 1209 */ 1210 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1211 /* 0 - memory 1212 * 1 - register 1213 */ 1214 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1215 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1216 #define PACKET3_SURFACE_SYNC 0x43 1217 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1218 # define PACKET3_TC_ACTION_ENA (1 << 23) 1219 # define PACKET3_VC_ACTION_ENA (1 << 24) 1220 # define PACKET3_CB_ACTION_ENA (1 << 25) 1221 # define PACKET3_DB_ACTION_ENA (1 << 26) 1222 # define PACKET3_SH_ACTION_ENA (1 << 27) 1223 # define PACKET3_SMX_ACTION_ENA (1 << 28) 1224 #define PACKET3_ME_INITIALIZE 0x44 1225 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1226 #define PACKET3_COND_WRITE 0x45 1227 #define PACKET3_EVENT_WRITE 0x46 1228 #define EVENT_TYPE(x) ((x) << 0) 1229 #define EVENT_INDEX(x) ((x) << 8) 1230 /* 0 - any non-TS event 1231 * 1 - ZPASS_DONE 1232 * 2 - SAMPLE_PIPELINESTAT 1233 * 3 - SAMPLE_STREAMOUTSTAT* 1234 * 4 - *S_PARTIAL_FLUSH 1235 * 5 - TS events 1236 */ 1237 #define PACKET3_EVENT_WRITE_EOP 0x47 1238 #define DATA_SEL(x) ((x) << 29) 1239 /* 0 - discard 1240 * 1 - send low 32bit data 1241 * 2 - send 64bit data 1242 * 3 - send 64bit counter value 1243 */ 1244 #define INT_SEL(x) ((x) << 24) 1245 /* 0 - none 1246 * 1 - interrupt only (DATA_SEL = 0) 1247 * 2 - interrupt when data write is confirmed 1248 */ 1249 #define PACKET3_ONE_REG_WRITE 0x57 1250 #define PACKET3_SET_CONFIG_REG 0x68 1251 #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 1252 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1253 #define PACKET3_SET_CONTEXT_REG 0x69 1254 #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 1255 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1256 #define PACKET3_SET_ALU_CONST 0x6A 1257 #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 1258 #define PACKET3_SET_ALU_CONST_END 0x00032000 1259 #define PACKET3_SET_BOOL_CONST 0x6B 1260 #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 1261 #define PACKET3_SET_BOOL_CONST_END 0x00040000 1262 #define PACKET3_SET_LOOP_CONST 0x6C 1263 #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 1264 #define PACKET3_SET_LOOP_CONST_END 0x0003e380 1265 #define PACKET3_SET_RESOURCE 0x6D 1266 #define PACKET3_SET_RESOURCE_OFFSET 0x00038000 1267 #define PACKET3_SET_RESOURCE_END 0x0003c000 1268 #define PACKET3_SET_SAMPLER 0x6E 1269 #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 1270 #define PACKET3_SET_SAMPLER_END 0x0003cff0 1271 #define PACKET3_SET_CTL_CONST 0x6F 1272 #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 1273 #define PACKET3_SET_CTL_CONST_END 0x0003e200 1274 #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */ 1275 #define PACKET3_SURFACE_BASE_UPDATE 0x73 1276 1277 1278 #define R_008020_GRBM_SOFT_RESET 0x8020 1279 #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) 1280 #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) 1281 #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) 1282 #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) 1283 #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) 1284 #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) 1285 #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) 1286 #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) 1287 #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) 1288 #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) 1289 #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) 1290 #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) 1291 #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) 1292 #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) 1293 #define R_008010_GRBM_STATUS 0x8010 1294 #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) 1295 #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) 1296 #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) 1297 #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) 1298 #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) 1299 #define S_008010_VC_BUSY(x) (((x) & 1) << 11) 1300 #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) 1301 #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) 1302 #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) 1303 #define S_008010_VGT_BUSY(x) (((x) & 1) << 17) 1304 #define S_008010_TA03_BUSY(x) (((x) & 1) << 18) 1305 #define S_008010_TC_BUSY(x) (((x) & 1) << 19) 1306 #define S_008010_SX_BUSY(x) (((x) & 1) << 20) 1307 #define S_008010_SH_BUSY(x) (((x) & 1) << 21) 1308 #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) 1309 #define S_008010_SMX_BUSY(x) (((x) & 1) << 23) 1310 #define S_008010_SC_BUSY(x) (((x) & 1) << 24) 1311 #define S_008010_PA_BUSY(x) (((x) & 1) << 25) 1312 #define S_008010_DB03_BUSY(x) (((x) & 1) << 26) 1313 #define S_008010_CR_BUSY(x) (((x) & 1) << 27) 1314 #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) 1315 #define S_008010_CP_BUSY(x) (((x) & 1) << 29) 1316 #define S_008010_CB03_BUSY(x) (((x) & 1) << 30) 1317 #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) 1318 #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) 1319 #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) 1320 #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) 1321 #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) 1322 #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) 1323 #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 1324 #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 1325 #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 1326 #define G_008010_TA_BUSY(x) (((x) >> 14) & 1) 1327 #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 1328 #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 1329 #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 1330 #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) 1331 #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) 1332 #define G_008010_SH_BUSY(x) (((x) >> 21) & 1) 1333 #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) 1334 #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) 1335 #define G_008010_SC_BUSY(x) (((x) >> 24) & 1) 1336 #define G_008010_PA_BUSY(x) (((x) >> 25) & 1) 1337 #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) 1338 #define G_008010_CR_BUSY(x) (((x) >> 27) & 1) 1339 #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) 1340 #define G_008010_CP_BUSY(x) (((x) >> 29) & 1) 1341 #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) 1342 #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) 1343 #define R_008014_GRBM_STATUS2 0x8014 1344 #define S_008014_CR_CLEAN(x) (((x) & 1) << 0) 1345 #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) 1346 #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) 1347 #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) 1348 #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) 1349 #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) 1350 #define S_008014_TA0_BUSY(x) (((x) & 1) << 12) 1351 #define S_008014_TA1_BUSY(x) (((x) & 1) << 13) 1352 #define S_008014_TA2_BUSY(x) (((x) & 1) << 14) 1353 #define S_008014_TA3_BUSY(x) (((x) & 1) << 15) 1354 #define S_008014_DB0_BUSY(x) (((x) & 1) << 16) 1355 #define S_008014_DB1_BUSY(x) (((x) & 1) << 17) 1356 #define S_008014_DB2_BUSY(x) (((x) & 1) << 18) 1357 #define S_008014_DB3_BUSY(x) (((x) & 1) << 19) 1358 #define S_008014_CB0_BUSY(x) (((x) & 1) << 20) 1359 #define S_008014_CB1_BUSY(x) (((x) & 1) << 21) 1360 #define S_008014_CB2_BUSY(x) (((x) & 1) << 22) 1361 #define S_008014_CB3_BUSY(x) (((x) & 1) << 23) 1362 #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) 1363 #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) 1364 #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) 1365 #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) 1366 #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) 1367 #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) 1368 #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) 1369 #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) 1370 #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) 1371 #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) 1372 #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) 1373 #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) 1374 #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) 1375 #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) 1376 #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) 1377 #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) 1378 #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) 1379 #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) 1380 #define R_000E50_SRBM_STATUS 0x0E50 1381 #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) 1382 #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) 1383 #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) 1384 #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) 1385 #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) 1386 #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) 1387 #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) 1388 #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) 1389 #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) 1390 #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) 1391 #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 1392 #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 1393 #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 1394 #define G_000E50_IH_BUSY(x) (((x) >> 17) & 1) 1395 #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 1396 #define R_000E60_SRBM_SOFT_RESET 0x0E60 1397 #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 1398 #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) 1399 #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) 1400 #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) 1401 #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) 1402 #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) 1403 #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) 1404 #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) 1405 #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) 1406 #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) 1407 #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) 1408 #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) 1409 #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) 1410 #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 1411 1412 #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 1413 1414 #define R_028C04_PA_SC_AA_CONFIG 0x028C04 1415 #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) 1416 #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) 1417 #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC 1418 #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) 1419 #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) 1420 #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF 1421 #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) 1422 #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) 1423 #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF 1424 #define R_0280E0_CB_COLOR0_FRAG 0x0280E0 1425 #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1426 #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1427 #define C_0280E0_BASE_256B 0x00000000 1428 #define R_0280E4_CB_COLOR1_FRAG 0x0280E4 1429 #define R_0280E8_CB_COLOR2_FRAG 0x0280E8 1430 #define R_0280EC_CB_COLOR3_FRAG 0x0280EC 1431 #define R_0280F0_CB_COLOR4_FRAG 0x0280F0 1432 #define R_0280F4_CB_COLOR5_FRAG 0x0280F4 1433 #define R_0280F8_CB_COLOR6_FRAG 0x0280F8 1434 #define R_0280FC_CB_COLOR7_FRAG 0x0280FC 1435 #define R_0280C0_CB_COLOR0_TILE 0x0280C0 1436 #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1437 #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1438 #define C_0280C0_BASE_256B 0x00000000 1439 #define R_0280C4_CB_COLOR1_TILE 0x0280C4 1440 #define R_0280C8_CB_COLOR2_TILE 0x0280C8 1441 #define R_0280CC_CB_COLOR3_TILE 0x0280CC 1442 #define R_0280D0_CB_COLOR4_TILE 0x0280D0 1443 #define R_0280D4_CB_COLOR5_TILE 0x0280D4 1444 #define R_0280D8_CB_COLOR6_TILE 0x0280D8 1445 #define R_0280DC_CB_COLOR7_TILE 0x0280DC 1446 #define R_0280A0_CB_COLOR0_INFO 0x0280A0 1447 #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) 1448 #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) 1449 #define C_0280A0_ENDIAN 0xFFFFFFFC 1450 #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) 1451 #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) 1452 #define C_0280A0_FORMAT 0xFFFFFF03 1453 #define V_0280A0_COLOR_INVALID 0x00000000 1454 #define V_0280A0_COLOR_8 0x00000001 1455 #define V_0280A0_COLOR_4_4 0x00000002 1456 #define V_0280A0_COLOR_3_3_2 0x00000003 1457 #define V_0280A0_COLOR_16 0x00000005 1458 #define V_0280A0_COLOR_16_FLOAT 0x00000006 1459 #define V_0280A0_COLOR_8_8 0x00000007 1460 #define V_0280A0_COLOR_5_6_5 0x00000008 1461 #define V_0280A0_COLOR_6_5_5 0x00000009 1462 #define V_0280A0_COLOR_1_5_5_5 0x0000000A 1463 #define V_0280A0_COLOR_4_4_4_4 0x0000000B 1464 #define V_0280A0_COLOR_5_5_5_1 0x0000000C 1465 #define V_0280A0_COLOR_32 0x0000000D 1466 #define V_0280A0_COLOR_32_FLOAT 0x0000000E 1467 #define V_0280A0_COLOR_16_16 0x0000000F 1468 #define V_0280A0_COLOR_16_16_FLOAT 0x00000010 1469 #define V_0280A0_COLOR_8_24 0x00000011 1470 #define V_0280A0_COLOR_8_24_FLOAT 0x00000012 1471 #define V_0280A0_COLOR_24_8 0x00000013 1472 #define V_0280A0_COLOR_24_8_FLOAT 0x00000014 1473 #define V_0280A0_COLOR_10_11_11 0x00000015 1474 #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 1475 #define V_0280A0_COLOR_11_11_10 0x00000017 1476 #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 1477 #define V_0280A0_COLOR_2_10_10_10 0x00000019 1478 #define V_0280A0_COLOR_8_8_8_8 0x0000001A 1479 #define V_0280A0_COLOR_10_10_10_2 0x0000001B 1480 #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C 1481 #define V_0280A0_COLOR_32_32 0x0000001D 1482 #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E 1483 #define V_0280A0_COLOR_16_16_16_16 0x0000001F 1484 #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 1485 #define V_0280A0_COLOR_32_32_32_32 0x00000022 1486 #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 1487 #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) 1488 #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1489 #define C_0280A0_ARRAY_MODE 0xFFFFF0FF 1490 #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 1491 #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 1492 #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 1493 #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 1494 #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1495 #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1496 #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF 1497 #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) 1498 #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) 1499 #define C_0280A0_READ_SIZE 0xFFFF7FFF 1500 #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) 1501 #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) 1502 #define C_0280A0_COMP_SWAP 0xFFFCFFFF 1503 #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1504 #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1505 #define C_0280A0_TILE_MODE 0xFFF3FFFF 1506 #define V_0280A0_TILE_DISABLE 0 1507 #define V_0280A0_CLEAR_ENABLE 1 1508 #define V_0280A0_FRAG_ENABLE 2 1509 #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1510 #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1511 #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1512 #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) 1513 #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) 1514 #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF 1515 #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) 1516 #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) 1517 #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF 1518 #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) 1519 #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) 1520 #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF 1521 #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) 1522 #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) 1523 #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF 1524 #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) 1525 #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) 1526 #define C_0280A0_ROUND_MODE 0xFDFFFFFF 1527 #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) 1528 #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1529 #define C_0280A0_TILE_COMPACT 0xFBFFFFFF 1530 #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) 1531 #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) 1532 #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF 1533 #define R_0280A4_CB_COLOR1_INFO 0x0280A4 1534 #define R_0280A8_CB_COLOR2_INFO 0x0280A8 1535 #define R_0280AC_CB_COLOR3_INFO 0x0280AC 1536 #define R_0280B0_CB_COLOR4_INFO 0x0280B0 1537 #define R_0280B4_CB_COLOR5_INFO 0x0280B4 1538 #define R_0280B8_CB_COLOR6_INFO 0x0280B8 1539 #define R_0280BC_CB_COLOR7_INFO 0x0280BC 1540 #define R_028060_CB_COLOR0_SIZE 0x028060 1541 #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1542 #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1543 #define C_028060_PITCH_TILE_MAX 0xFFFFFC00 1544 #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1545 #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1546 #define C_028060_SLICE_TILE_MAX 0xC00003FF 1547 #define R_028064_CB_COLOR1_SIZE 0x028064 1548 #define R_028068_CB_COLOR2_SIZE 0x028068 1549 #define R_02806C_CB_COLOR3_SIZE 0x02806C 1550 #define R_028070_CB_COLOR4_SIZE 0x028070 1551 #define R_028074_CB_COLOR5_SIZE 0x028074 1552 #define R_028078_CB_COLOR6_SIZE 0x028078 1553 #define R_02807C_CB_COLOR7_SIZE 0x02807C 1554 #define R_028238_CB_TARGET_MASK 0x028238 1555 #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) 1556 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) 1557 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0 1558 #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) 1559 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) 1560 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F 1561 #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) 1562 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) 1563 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF 1564 #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) 1565 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) 1566 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF 1567 #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) 1568 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) 1569 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF 1570 #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) 1571 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) 1572 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF 1573 #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) 1574 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) 1575 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF 1576 #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) 1577 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) 1578 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF 1579 #define R_02823C_CB_SHADER_MASK 0x02823C 1580 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) 1581 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) 1582 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 1583 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) 1584 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) 1585 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F 1586 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) 1587 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) 1588 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF 1589 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) 1590 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) 1591 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF 1592 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) 1593 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) 1594 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF 1595 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) 1596 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) 1597 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF 1598 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) 1599 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) 1600 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF 1601 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) 1602 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) 1603 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF 1604 #define R_028AB0_VGT_STRMOUT_EN 0x028AB0 1605 #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) 1606 #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) 1607 #define C_028AB0_STREAMOUT 0xFFFFFFFE 1608 #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 1609 #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) 1610 #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) 1611 #define C_028B20_BUFFER_0_EN 0xFFFFFFFE 1612 #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) 1613 #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) 1614 #define C_028B20_BUFFER_1_EN 0xFFFFFFFD 1615 #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) 1616 #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) 1617 #define C_028B20_BUFFER_2_EN 0xFFFFFFFB 1618 #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) 1619 #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) 1620 #define C_028B20_BUFFER_3_EN 0xFFFFFFF7 1621 #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1622 #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1623 #define C_028B20_SIZE 0x00000000 1624 #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 1625 #define S_038000_DIM(x) (((x) & 0x7) << 0) 1626 #define G_038000_DIM(x) (((x) >> 0) & 0x7) 1627 #define C_038000_DIM 0xFFFFFFF8 1628 #define V_038000_SQ_TEX_DIM_1D 0x00000000 1629 #define V_038000_SQ_TEX_DIM_2D 0x00000001 1630 #define V_038000_SQ_TEX_DIM_3D 0x00000002 1631 #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 1632 #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1633 #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1634 #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 1635 #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1636 #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) 1637 #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) 1638 #define C_038000_TILE_MODE 0xFFFFFF87 1639 #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 1640 #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 1641 #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 1642 #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 1643 #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) 1644 #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) 1645 #define C_038000_TILE_TYPE 0xFFFFFF7F 1646 #define S_038000_PITCH(x) (((x) & 0x7FF) << 8) 1647 #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) 1648 #define C_038000_PITCH 0xFFF800FF 1649 #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) 1650 #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) 1651 #define C_038000_TEX_WIDTH 0x0007FFFF 1652 #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 1653 #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) 1654 #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) 1655 #define C_038004_TEX_HEIGHT 0xFFFFE000 1656 #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) 1657 #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) 1658 #define C_038004_TEX_DEPTH 0xFC001FFF 1659 #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) 1660 #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) 1661 #define C_038004_DATA_FORMAT 0x03FFFFFF 1662 #define V_038004_COLOR_INVALID 0x00000000 1663 #define V_038004_COLOR_8 0x00000001 1664 #define V_038004_COLOR_4_4 0x00000002 1665 #define V_038004_COLOR_3_3_2 0x00000003 1666 #define V_038004_COLOR_16 0x00000005 1667 #define V_038004_COLOR_16_FLOAT 0x00000006 1668 #define V_038004_COLOR_8_8 0x00000007 1669 #define V_038004_COLOR_5_6_5 0x00000008 1670 #define V_038004_COLOR_6_5_5 0x00000009 1671 #define V_038004_COLOR_1_5_5_5 0x0000000A 1672 #define V_038004_COLOR_4_4_4_4 0x0000000B 1673 #define V_038004_COLOR_5_5_5_1 0x0000000C 1674 #define V_038004_COLOR_32 0x0000000D 1675 #define V_038004_COLOR_32_FLOAT 0x0000000E 1676 #define V_038004_COLOR_16_16 0x0000000F 1677 #define V_038004_COLOR_16_16_FLOAT 0x00000010 1678 #define V_038004_COLOR_8_24 0x00000011 1679 #define V_038004_COLOR_8_24_FLOAT 0x00000012 1680 #define V_038004_COLOR_24_8 0x00000013 1681 #define V_038004_COLOR_24_8_FLOAT 0x00000014 1682 #define V_038004_COLOR_10_11_11 0x00000015 1683 #define V_038004_COLOR_10_11_11_FLOAT 0x00000016 1684 #define V_038004_COLOR_11_11_10 0x00000017 1685 #define V_038004_COLOR_11_11_10_FLOAT 0x00000018 1686 #define V_038004_COLOR_2_10_10_10 0x00000019 1687 #define V_038004_COLOR_8_8_8_8 0x0000001A 1688 #define V_038004_COLOR_10_10_10_2 0x0000001B 1689 #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C 1690 #define V_038004_COLOR_32_32 0x0000001D 1691 #define V_038004_COLOR_32_32_FLOAT 0x0000001E 1692 #define V_038004_COLOR_16_16_16_16 0x0000001F 1693 #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 1694 #define V_038004_COLOR_32_32_32_32 0x00000022 1695 #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 1696 #define V_038004_FMT_1 0x00000025 1697 #define V_038004_FMT_GB_GR 0x00000027 1698 #define V_038004_FMT_BG_RG 0x00000028 1699 #define V_038004_FMT_32_AS_8 0x00000029 1700 #define V_038004_FMT_32_AS_8_8 0x0000002A 1701 #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B 1702 #define V_038004_FMT_8_8_8 0x0000002C 1703 #define V_038004_FMT_16_16_16 0x0000002D 1704 #define V_038004_FMT_16_16_16_FLOAT 0x0000002E 1705 #define V_038004_FMT_32_32_32 0x0000002F 1706 #define V_038004_FMT_32_32_32_FLOAT 0x00000030 1707 #define V_038004_FMT_BC1 0x00000031 1708 #define V_038004_FMT_BC2 0x00000032 1709 #define V_038004_FMT_BC3 0x00000033 1710 #define V_038004_FMT_BC4 0x00000034 1711 #define V_038004_FMT_BC5 0x00000035 1712 #define V_038004_FMT_BC6 0x00000036 1713 #define V_038004_FMT_BC7 0x00000037 1714 #define V_038004_FMT_32_AS_32_32_32_32 0x00000038 1715 #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 1716 #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1717 #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1718 #define C_038010_FORMAT_COMP_X 0xFFFFFFFC 1719 #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1720 #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1721 #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 1722 #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1723 #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1724 #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF 1725 #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1726 #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1727 #define C_038010_FORMAT_COMP_W 0xFFFFFF3F 1728 #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1729 #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1730 #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF 1731 #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1732 #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1733 #define C_038010_SRF_MODE_ALL 0xFFFFFBFF 1734 #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1735 #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1736 #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF 1737 #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1738 #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1739 #define C_038010_ENDIAN_SWAP 0xFFFFCFFF 1740 #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) 1741 #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) 1742 #define C_038010_REQUEST_SIZE 0xFFFF3FFF 1743 #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) 1744 #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1745 #define C_038010_DST_SEL_X 0xFFF8FFFF 1746 #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1747 #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1748 #define C_038010_DST_SEL_Y 0xFFC7FFFF 1749 #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1750 #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1751 #define C_038010_DST_SEL_Z 0xFE3FFFFF 1752 #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) 1753 #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1754 #define C_038010_DST_SEL_W 0xF1FFFFFF 1755 # define SQ_SEL_X 0 1756 # define SQ_SEL_Y 1 1757 # define SQ_SEL_Z 2 1758 # define SQ_SEL_W 3 1759 # define SQ_SEL_0 4 1760 # define SQ_SEL_1 5 1761 #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1762 #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1763 #define C_038010_BASE_LEVEL 0x0FFFFFFF 1764 #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 1765 #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1766 #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1767 #define C_038014_LAST_LEVEL 0xFFFFFFF0 1768 #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1769 #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1770 #define C_038014_BASE_ARRAY 0xFFFE000F 1771 #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1772 #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1773 #define C_038014_LAST_ARRAY 0xC001FFFF 1774 #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 1775 #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1776 #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1777 #define C_0288A8_ITEMSIZE 0xFFFF8000 1778 #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 1779 #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1780 #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1781 #define C_008C44_MEM_SIZE 0x00000000 1782 #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 1783 #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1784 #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1785 #define C_0288B0_ITEMSIZE 0xFFFF8000 1786 #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 1787 #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1788 #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1789 #define C_008C54_MEM_SIZE 0x00000000 1790 #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 1791 #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1792 #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1793 #define C_0288C0_ITEMSIZE 0xFFFF8000 1794 #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 1795 #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1796 #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1797 #define C_008C74_MEM_SIZE 0x00000000 1798 #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 1799 #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1800 #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1801 #define C_0288B4_ITEMSIZE 0xFFFF8000 1802 #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C 1803 #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1804 #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1805 #define C_008C5C_MEM_SIZE 0x00000000 1806 #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC 1807 #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1808 #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1809 #define C_0288AC_ITEMSIZE 0xFFFF8000 1810 #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C 1811 #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1812 #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1813 #define C_008C4C_MEM_SIZE 0x00000000 1814 #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC 1815 #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1816 #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1817 #define C_0288BC_ITEMSIZE 0xFFFF8000 1818 #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C 1819 #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1820 #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1821 #define C_008C6C_MEM_SIZE 0x00000000 1822 #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 1823 #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1824 #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1825 #define C_0288C4_ITEMSIZE 0xFFFF8000 1826 #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C 1827 #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1828 #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1829 #define C_008C7C_MEM_SIZE 0x00000000 1830 #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 1831 #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1832 #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1833 #define C_0288B8_ITEMSIZE 0xFFFF8000 1834 #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 1835 #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1836 #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1837 #define C_008C64_MEM_SIZE 0x00000000 1838 #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 1839 #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1840 #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1841 #define C_0288C8_ITEMSIZE 0xFFFF8000 1842 #define R_028010_DB_DEPTH_INFO 0x028010 1843 #define S_028010_FORMAT(x) (((x) & 0x7) << 0) 1844 #define G_028010_FORMAT(x) (((x) >> 0) & 0x7) 1845 #define C_028010_FORMAT 0xFFFFFFF8 1846 #define V_028010_DEPTH_INVALID 0x00000000 1847 #define V_028010_DEPTH_16 0x00000001 1848 #define V_028010_DEPTH_X8_24 0x00000002 1849 #define V_028010_DEPTH_8_24 0x00000003 1850 #define V_028010_DEPTH_X8_24_FLOAT 0x00000004 1851 #define V_028010_DEPTH_8_24_FLOAT 0x00000005 1852 #define V_028010_DEPTH_32_FLOAT 0x00000006 1853 #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 1854 #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) 1855 #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) 1856 #define C_028010_READ_SIZE 0xFFFFFFF7 1857 #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) 1858 #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) 1859 #define C_028010_ARRAY_MODE 0xFFF87FFF 1860 #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 1861 #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 1862 #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) 1863 #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) 1864 #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF 1865 #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) 1866 #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1867 #define C_028010_TILE_COMPACT 0xFBFFFFFF 1868 #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1869 #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1870 #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF 1871 #define R_028000_DB_DEPTH_SIZE 0x028000 1872 #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1873 #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1874 #define C_028000_PITCH_TILE_MAX 0xFFFFFC00 1875 #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1876 #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1877 #define C_028000_SLICE_TILE_MAX 0xC00003FF 1878 #define R_028004_DB_DEPTH_VIEW 0x028004 1879 #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) 1880 #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) 1881 #define C_028004_SLICE_START 0xFFFFF800 1882 #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1883 #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1884 #define C_028004_SLICE_MAX 0xFF001FFF 1885 #define R_028800_DB_DEPTH_CONTROL 0x028800 1886 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1887 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1888 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1889 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1890 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1891 #define C_028800_Z_ENABLE 0xFFFFFFFD 1892 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1893 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1894 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1895 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1896 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1897 #define C_028800_ZFUNC 0xFFFFFF8F 1898 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1899 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1900 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1901 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1902 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1903 #define C_028800_STENCILFUNC 0xFFFFF8FF 1904 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1905 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1906 #define C_028800_STENCILFAIL 0xFFFFC7FF 1907 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1908 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1909 #define C_028800_STENCILZPASS 0xFFFE3FFF 1910 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1911 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1912 #define C_028800_STENCILZFAIL 0xFFF1FFFF 1913 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1914 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1915 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1916 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1917 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1918 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1919 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1920 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1921 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1922 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1923 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1924 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1925 1926 #endif 1927