1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon.h 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #ifndef __RADEON_H__ 32 #define __RADEON_H__ 33 34 /* TODO: Here are things that needs to be done : 35 * - surface allocator & initializer : (bit like scratch reg) should 36 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 37 * related to surface 38 * - WB : write back stuff (do it bit like scratch reg things) 39 * - Vblank : look at Jesse's rework and what we should do 40 * - r600/r700: gart & cp 41 * - cs : clean cs ioctl use bitmap & things like that. 42 * - power management stuff 43 * - Barrier in gart code 44 * - Unmappabled vram ? 45 * - TESTING, TESTING, TESTING 46 */ 47 48 /* Initialization path: 49 * We expect that acceleration initialization might fail for various 50 * reasons even thought we work hard to make it works on most 51 * configurations. In order to still have a working userspace in such 52 * situation the init path must succeed up to the memory controller 53 * initialization point. Failure before this point are considered as 54 * fatal error. Here is the init callchain : 55 * radeon_device_init perform common structure, mutex initialization 56 * asic_init setup the GPU memory layout and perform all 57 * one time initialization (failure in this 58 * function are considered fatal) 59 * asic_startup setup the GPU acceleration, in order to 60 * follow guideline the first thing this 61 * function should do is setting the GPU 62 * memory controller (only MC setup failure 63 * are considered as fatal) 64 */ 65 66 #include <sys/condvar.h> 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/linker.h> 70 #include <linux/firmware.h> 71 #include <linux/seq_file.h> 72 73 #include <contrib/dev/acpica/source/include/acpi.h> 74 #include <dev/acpica/acpivar.h> 75 76 #include <drm/ttm/ttm_bo_api.h> 77 #include <drm/ttm/ttm_bo_driver.h> 78 #include <drm/ttm/ttm_placement.h> 79 #include <drm/ttm/ttm_module.h> 80 #include <drm/ttm/ttm_execbuf_util.h> 81 82 #include <drm/drm_gem.h> 83 #define CONFIG_ACPI 1 84 85 #include "radeon_family.h" 86 #include "radeon_mode.h" 87 #include "radeon_reg.h" 88 89 /* 90 * Modules parameters. 91 */ 92 extern int radeon_no_wb; 93 extern int radeon_modeset; 94 extern int radeon_dynclks; 95 extern int radeon_r4xx_atom; 96 extern int radeon_agpmode; 97 extern int radeon_vram_limit; 98 extern int radeon_gart_size; 99 extern int radeon_benchmarking; 100 extern int radeon_testing; 101 extern int radeon_connector_table; 102 extern int radeon_tv; 103 extern int radeon_audio; 104 extern int radeon_disp_priority; 105 extern int radeon_hw_i2c; 106 extern int radeon_pcie_gen2; 107 extern int radeon_msi; 108 extern int radeon_lockup_timeout; 109 extern int radeon_fastfb; 110 extern int radeon_dpm; 111 extern int radeon_aspm; 112 extern int radeon_runtime_pm; 113 extern int radeon_hard_reset; 114 extern int radeon_vm_size; 115 extern int radeon_vm_block_size; 116 extern int radeon_deep_color; 117 extern int radeon_use_pflipirq; 118 extern int radeon_bapm; 119 extern int radeon_backlight; 120 121 /* 122 * Copy from radeon_drv.h so we don't have to include both and have conflicting 123 * symbol; 124 */ 125 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 126 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 127 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 128 #define RADEON_IB_POOL_SIZE 16 129 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 130 #define RADEONFB_CONN_LIMIT 4 131 #define RADEON_BIOS_NUM_SCRATCH 8 132 133 /* internal ring indices */ 134 /* r1xx+ has gfx CP ring */ 135 #define RADEON_RING_TYPE_GFX_INDEX 0 136 137 /* cayman has 2 compute CP rings */ 138 #define CAYMAN_RING_TYPE_CP1_INDEX 1 139 #define CAYMAN_RING_TYPE_CP2_INDEX 2 140 141 /* R600+ has an async dma ring */ 142 #define R600_RING_TYPE_DMA_INDEX 3 143 /* cayman add a second async dma ring */ 144 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 145 146 /* R600+ */ 147 #define R600_RING_TYPE_UVD_INDEX 5 148 149 /* TN+ */ 150 #define TN_RING_TYPE_VCE1_INDEX 6 151 #define TN_RING_TYPE_VCE2_INDEX 7 152 153 /* max number of rings */ 154 #define RADEON_NUM_RINGS 8 155 156 /* number of hw syncs before falling back on blocking */ 157 #define RADEON_NUM_SYNCS 4 158 159 /* hardcode those limit for now */ 160 #define RADEON_VA_IB_OFFSET (1 << 20) 161 #define RADEON_VA_RESERVED_SIZE (8 << 20) 162 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 163 164 /* hard reset data */ 165 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 166 167 /* reset flags */ 168 #define RADEON_RESET_GFX (1 << 0) 169 #define RADEON_RESET_COMPUTE (1 << 1) 170 #define RADEON_RESET_DMA (1 << 2) 171 #define RADEON_RESET_CP (1 << 3) 172 #define RADEON_RESET_GRBM (1 << 4) 173 #define RADEON_RESET_DMA1 (1 << 5) 174 #define RADEON_RESET_RLC (1 << 6) 175 #define RADEON_RESET_SEM (1 << 7) 176 #define RADEON_RESET_IH (1 << 8) 177 #define RADEON_RESET_VMC (1 << 9) 178 #define RADEON_RESET_MC (1 << 10) 179 #define RADEON_RESET_DISPLAY (1 << 11) 180 181 /* CG block flags */ 182 #define RADEON_CG_BLOCK_GFX (1 << 0) 183 #define RADEON_CG_BLOCK_MC (1 << 1) 184 #define RADEON_CG_BLOCK_SDMA (1 << 2) 185 #define RADEON_CG_BLOCK_UVD (1 << 3) 186 #define RADEON_CG_BLOCK_VCE (1 << 4) 187 #define RADEON_CG_BLOCK_HDP (1 << 5) 188 #define RADEON_CG_BLOCK_BIF (1 << 6) 189 190 /* CG flags */ 191 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 192 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 193 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 194 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 195 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 196 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 197 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 198 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 199 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 200 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 201 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 202 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 203 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 204 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 205 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 206 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 207 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 208 209 /* PG flags */ 210 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 211 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 212 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 213 #define RADEON_PG_SUPPORT_UVD (1 << 3) 214 #define RADEON_PG_SUPPORT_VCE (1 << 4) 215 #define RADEON_PG_SUPPORT_CP (1 << 5) 216 #define RADEON_PG_SUPPORT_GDS (1 << 6) 217 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 218 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 219 #define RADEON_PG_SUPPORT_ACP (1 << 9) 220 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 221 222 /* max cursor sizes (in pixels) */ 223 #define CURSOR_WIDTH 64 224 #define CURSOR_HEIGHT 64 225 226 #define CIK_CURSOR_WIDTH 128 227 #define CIK_CURSOR_HEIGHT 128 228 229 /* 230 * Errata workarounds. 231 */ 232 enum radeon_pll_errata { 233 CHIP_ERRATA_R300_CG = 0x00000001, 234 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 235 CHIP_ERRATA_PLL_DELAY = 0x00000004 236 }; 237 238 239 struct radeon_device; 240 241 242 /* 243 * BIOS. 244 */ 245 bool radeon_get_bios(struct radeon_device *rdev); 246 247 /* 248 * Dummy page 249 */ 250 struct radeon_dummy_page { 251 drm_dma_handle_t *dmah; 252 dma_addr_t addr; 253 }; 254 int radeon_dummy_page_init(struct radeon_device *rdev); 255 void radeon_dummy_page_fini(struct radeon_device *rdev); 256 257 258 /* 259 * Clocks 260 */ 261 struct radeon_clock { 262 struct radeon_pll p1pll; 263 struct radeon_pll p2pll; 264 struct radeon_pll dcpll; 265 struct radeon_pll spll; 266 struct radeon_pll mpll; 267 /* 10 Khz units */ 268 uint32_t default_mclk; 269 uint32_t default_sclk; 270 uint32_t default_dispclk; 271 uint32_t current_dispclk; 272 uint32_t dp_extclk; 273 uint32_t max_pixel_clock; 274 }; 275 276 /* 277 * Power management 278 */ 279 int radeon_pm_init(struct radeon_device *rdev); 280 int radeon_pm_late_init(struct radeon_device *rdev); 281 void radeon_pm_fini(struct radeon_device *rdev); 282 void radeon_pm_compute_clocks(struct radeon_device *rdev); 283 void radeon_pm_suspend(struct radeon_device *rdev); 284 void radeon_pm_resume(struct radeon_device *rdev); 285 void radeon_combios_get_power_modes(struct radeon_device *rdev); 286 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 287 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 288 u8 clock_type, 289 u32 clock, 290 bool strobe_mode, 291 struct atom_clock_dividers *dividers); 292 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 293 u32 clock, 294 bool strobe_mode, 295 struct atom_mpll_param *mpll_param); 296 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 297 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 298 u16 voltage_level, u8 voltage_type, 299 u32 *gpio_value, u32 *gpio_mask); 300 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 301 u32 eng_clock, u32 mem_clock); 302 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 303 u8 voltage_type, u16 *voltage_step); 304 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 305 u16 voltage_id, u16 *voltage); 306 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 307 u16 *voltage, 308 u16 leakage_idx); 309 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 310 u16 *leakage_id); 311 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 312 u16 *vddc, u16 *vddci, 313 u16 virtual_voltage_id, 314 u16 vbios_voltage_id); 315 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 316 u16 virtual_voltage_id, 317 u16 *voltage); 318 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 319 u8 voltage_type, 320 u16 nominal_voltage, 321 u16 *true_voltage); 322 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 323 u8 voltage_type, u16 *min_voltage); 324 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 325 u8 voltage_type, u16 *max_voltage); 326 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 327 u8 voltage_type, u8 voltage_mode, 328 struct atom_voltage_table *voltage_table); 329 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 330 u8 voltage_type, u8 voltage_mode); 331 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 332 u8 voltage_type, 333 u8 *svd_gpio_id, u8 *svc_gpio_id); 334 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 335 u32 mem_clock); 336 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 337 u32 mem_clock); 338 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 339 u8 module_index, 340 struct atom_mc_reg_table *reg_table); 341 int radeon_atom_get_memory_info(struct radeon_device *rdev, 342 u8 module_index, struct atom_memory_info *mem_info); 343 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 344 bool gddr5, u8 module_index, 345 struct atom_memory_clock_range_table *mclk_range_table); 346 void rs690_pm_info(struct radeon_device *rdev); 347 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 348 unsigned *bankh, unsigned *mtaspect, 349 unsigned *tile_split); 350 351 /* 352 * Fences. 353 */ 354 struct radeon_fence_driver { 355 struct radeon_device *rdev; 356 uint32_t scratch_reg; 357 uint64_t gpu_addr; 358 volatile uint32_t *cpu_addr; 359 /* sync_seq is protected by ring emission lock */ 360 uint64_t sync_seq[RADEON_NUM_RINGS]; 361 atomic64_t last_seq; 362 bool initialized; 363 struct delayed_work lockup_work; 364 }; 365 366 struct radeon_fence { 367 struct radeon_device *rdev; 368 unsigned int kref; 369 /* protected by radeon_fence.lock */ 370 uint64_t seq; 371 /* RB, DMA, etc. */ 372 unsigned ring; 373 }; 374 375 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 376 int radeon_fence_driver_init(struct radeon_device *rdev); 377 void radeon_fence_driver_fini(struct radeon_device *rdev); 378 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 379 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 380 void radeon_fence_process(struct radeon_device *rdev, int ring); 381 bool radeon_fence_signaled(struct radeon_fence *fence); 382 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 383 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 384 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 385 int radeon_fence_wait_any(struct radeon_device *rdev, 386 struct radeon_fence **fences, 387 bool intr); 388 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 389 void radeon_fence_unref(struct radeon_fence **fence); 390 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 391 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 392 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 393 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 394 struct radeon_fence *b) 395 { 396 if (!a) { 397 return b; 398 } 399 400 if (!b) { 401 return a; 402 } 403 404 BUG_ON(a->ring != b->ring); 405 406 if (a->seq > b->seq) { 407 return a; 408 } else { 409 return b; 410 } 411 } 412 413 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 414 struct radeon_fence *b) 415 { 416 if (!a) { 417 return false; 418 } 419 420 if (!b) { 421 return true; 422 } 423 424 BUG_ON(a->ring != b->ring); 425 426 return a->seq < b->seq; 427 } 428 429 /* 430 * Tiling registers 431 */ 432 struct radeon_surface_reg { 433 struct radeon_bo *bo; 434 }; 435 436 #define RADEON_GEM_MAX_SURFACES 8 437 438 /* 439 * TTM. 440 */ 441 struct radeon_mman { 442 struct ttm_bo_global_ref bo_global_ref; 443 struct drm_global_reference mem_global_ref; 444 struct ttm_bo_device bdev; 445 bool mem_global_referenced; 446 bool initialized; 447 448 #if defined(CONFIG_DEBUG_FS) 449 struct dentry *vram; 450 struct dentry *gtt; 451 #endif 452 }; 453 454 /* bo virtual address in a specific vm */ 455 struct radeon_bo_va { 456 /* protected by bo being reserved */ 457 struct list_head bo_list; 458 uint64_t soffset; 459 uint64_t eoffset; 460 uint32_t flags; 461 uint64_t addr; 462 unsigned ref_count; 463 464 /* protected by vm mutex */ 465 struct list_head vm_list; 466 struct list_head vm_status; 467 468 /* constant after initialization */ 469 struct radeon_vm *vm; 470 struct radeon_bo *bo; 471 }; 472 473 struct radeon_bo { 474 /* Protected by gem.mutex */ 475 struct list_head list; 476 /* Protected by tbo.reserved */ 477 u32 initial_domain; 478 struct ttm_place placements[3]; 479 struct ttm_placement placement; 480 struct ttm_buffer_object tbo; 481 struct ttm_bo_kmap_obj kmap; 482 u32 flags; 483 unsigned pin_count; 484 void *kptr; 485 u32 tiling_flags; 486 u32 pitch; 487 int surface_reg; 488 /* list of all virtual address to which this bo 489 * is associated to 490 */ 491 struct list_head va; 492 /* Constant after initialization */ 493 struct radeon_device *rdev; 494 struct drm_gem_object gem_base; 495 496 struct ttm_bo_kmap_obj dma_buf_vmap; 497 pid_t pid; 498 }; 499 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 500 501 int radeon_gem_debugfs_init(struct radeon_device *rdev); 502 503 /* sub-allocation manager, it has to be protected by another lock. 504 * By conception this is an helper for other part of the driver 505 * like the indirect buffer or semaphore, which both have their 506 * locking. 507 * 508 * Principe is simple, we keep a list of sub allocation in offset 509 * order (first entry has offset == 0, last entry has the highest 510 * offset). 511 * 512 * When allocating new object we first check if there is room at 513 * the end total_size - (last_object_offset + last_object_size) >= 514 * alloc_size. If so we allocate new object there. 515 * 516 * When there is not enough room at the end, we start waiting for 517 * each sub object until we reach object_offset+object_size >= 518 * alloc_size, this object then become the sub object we return. 519 * 520 * Alignment can't be bigger than page size. 521 * 522 * Hole are not considered for allocation to keep things simple. 523 * Assumption is that there won't be hole (all object on same 524 * alignment). 525 */ 526 struct radeon_sa_manager { 527 struct cv wq; 528 struct lock wq_lock; 529 struct radeon_bo *bo; 530 struct list_head *hole; 531 struct list_head flist[RADEON_NUM_RINGS]; 532 struct list_head olist; 533 unsigned size; 534 uint64_t gpu_addr; 535 void *cpu_ptr; 536 uint32_t domain; 537 uint32_t align; 538 }; 539 540 struct radeon_sa_bo; 541 542 /* sub-allocation buffer */ 543 struct radeon_sa_bo { 544 struct list_head olist; 545 struct list_head flist; 546 struct radeon_sa_manager *manager; 547 unsigned soffset; 548 unsigned eoffset; 549 struct radeon_fence *fence; 550 }; 551 552 /* 553 * GEM objects. 554 */ 555 struct radeon_gem { 556 struct spinlock mutex; 557 struct list_head objects; 558 }; 559 560 int radeon_gem_init(struct radeon_device *rdev); 561 void radeon_gem_fini(struct radeon_device *rdev); 562 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 563 int alignment, int initial_domain, 564 u32 flags, bool kernel, 565 struct drm_gem_object **obj); 566 567 int radeon_mode_dumb_create(struct drm_file *file_priv, 568 struct drm_device *dev, 569 struct drm_mode_create_dumb *args); 570 int radeon_mode_dumb_mmap(struct drm_file *filp, 571 struct drm_device *dev, 572 uint32_t handle, uint64_t *offset_p); 573 574 /* 575 * Semaphores. 576 */ 577 struct radeon_semaphore { 578 struct radeon_sa_bo *sa_bo; 579 signed waiters; 580 uint64_t gpu_addr; 581 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 582 }; 583 584 int radeon_semaphore_create(struct radeon_device *rdev, 585 struct radeon_semaphore **semaphore); 586 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 587 struct radeon_semaphore *semaphore); 588 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 589 struct radeon_semaphore *semaphore); 590 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, 591 struct radeon_fence *fence); 592 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 593 struct radeon_semaphore *semaphore, 594 int waiting_ring); 595 void radeon_semaphore_free(struct radeon_device *rdev, 596 struct radeon_semaphore **semaphore, 597 struct radeon_fence *fence); 598 599 /* 600 * GART structures, functions & helpers 601 */ 602 struct radeon_mc; 603 604 #define RADEON_GPU_PAGE_SIZE 4096 605 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 606 #define RADEON_GPU_PAGE_SHIFT 12 607 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 608 609 #define RADEON_GART_PAGE_DUMMY 0 610 #define RADEON_GART_PAGE_VALID (1 << 0) 611 #define RADEON_GART_PAGE_READ (1 << 1) 612 #define RADEON_GART_PAGE_WRITE (1 << 2) 613 #define RADEON_GART_PAGE_SNOOP (1 << 3) 614 615 struct radeon_gart { 616 drm_dma_handle_t *dmah; 617 dma_addr_t table_addr; 618 struct radeon_bo *robj; 619 void *ptr; 620 unsigned num_gpu_pages; 621 unsigned num_cpu_pages; 622 unsigned table_size; 623 vm_page_t *pages; 624 dma_addr_t *pages_addr; 625 bool ready; 626 }; 627 628 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 629 void radeon_gart_table_ram_free(struct radeon_device *rdev); 630 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 631 void radeon_gart_table_vram_free(struct radeon_device *rdev); 632 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 633 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 634 int radeon_gart_init(struct radeon_device *rdev); 635 void radeon_gart_fini(struct radeon_device *rdev); 636 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 637 int pages); 638 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 639 int pages, vm_page_t *pagelist, 640 dma_addr_t *dma_addr, uint32_t flags); 641 642 643 /* 644 * GPU MC structures, functions & helpers 645 */ 646 struct radeon_mc { 647 resource_size_t aper_size; 648 resource_size_t aper_base; 649 resource_size_t agp_base; 650 /* for some chips with <= 32MB we need to lie 651 * about vram size near mc fb location */ 652 u64 mc_vram_size; 653 u64 visible_vram_size; 654 u64 gtt_size; 655 u64 gtt_start; 656 u64 gtt_end; 657 u64 vram_start; 658 u64 vram_end; 659 unsigned vram_width; 660 u64 real_vram_size; 661 int vram_mtrr; 662 bool vram_is_ddr; 663 bool igp_sideport_enabled; 664 u64 gtt_base_align; 665 u64 mc_mask; 666 }; 667 668 bool radeon_combios_sideport_present(struct radeon_device *rdev); 669 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 670 671 /* 672 * GPU scratch registers structures, functions & helpers 673 */ 674 struct radeon_scratch { 675 unsigned num_reg; 676 uint32_t reg_base; 677 bool free[32]; 678 uint32_t reg[32]; 679 }; 680 681 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 682 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 683 684 /* 685 * GPU doorbell structures, functions & helpers 686 */ 687 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 688 689 struct radeon_doorbell { 690 /* doorbell mmio */ 691 resource_size_t base; 692 resource_size_t size; 693 u32 __iomem *ptr; 694 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 695 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 696 }; 697 698 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 699 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 700 701 /* 702 * IRQS. 703 */ 704 705 struct radeon_flip_work { 706 struct work_struct flip_work; 707 struct work_struct unpin_work; 708 struct radeon_device *rdev; 709 int crtc_id; 710 uint64_t base; 711 struct drm_pending_vblank_event *event; 712 struct radeon_bo *old_rbo; 713 struct radeon_fence *fence; 714 }; 715 716 struct r500_irq_stat_regs { 717 u32 disp_int; 718 u32 hdmi0_status; 719 }; 720 721 struct r600_irq_stat_regs { 722 u32 disp_int; 723 u32 disp_int_cont; 724 u32 disp_int_cont2; 725 u32 d1grph_int; 726 u32 d2grph_int; 727 u32 hdmi0_status; 728 u32 hdmi1_status; 729 }; 730 731 struct evergreen_irq_stat_regs { 732 u32 disp_int; 733 u32 disp_int_cont; 734 u32 disp_int_cont2; 735 u32 disp_int_cont3; 736 u32 disp_int_cont4; 737 u32 disp_int_cont5; 738 u32 d1grph_int; 739 u32 d2grph_int; 740 u32 d3grph_int; 741 u32 d4grph_int; 742 u32 d5grph_int; 743 u32 d6grph_int; 744 u32 afmt_status1; 745 u32 afmt_status2; 746 u32 afmt_status3; 747 u32 afmt_status4; 748 u32 afmt_status5; 749 u32 afmt_status6; 750 }; 751 752 struct cik_irq_stat_regs { 753 u32 disp_int; 754 u32 disp_int_cont; 755 u32 disp_int_cont2; 756 u32 disp_int_cont3; 757 u32 disp_int_cont4; 758 u32 disp_int_cont5; 759 u32 disp_int_cont6; 760 u32 d1grph_int; 761 u32 d2grph_int; 762 u32 d3grph_int; 763 u32 d4grph_int; 764 u32 d5grph_int; 765 u32 d6grph_int; 766 }; 767 768 union radeon_irq_stat_regs { 769 struct r500_irq_stat_regs r500; 770 struct r600_irq_stat_regs r600; 771 struct evergreen_irq_stat_regs evergreen; 772 struct cik_irq_stat_regs cik; 773 }; 774 775 struct radeon_irq { 776 bool installed; 777 struct lock lock; 778 atomic_t ring_int[RADEON_NUM_RINGS]; 779 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 780 atomic_t pflip[RADEON_MAX_CRTCS]; 781 wait_queue_head_t vblank_queue; 782 bool hpd[RADEON_MAX_HPD_PINS]; 783 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 784 union radeon_irq_stat_regs stat_regs; 785 bool dpm_thermal; 786 }; 787 788 int radeon_irq_kms_init(struct radeon_device *rdev); 789 void radeon_irq_kms_fini(struct radeon_device *rdev); 790 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 791 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 792 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 793 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 794 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 795 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 796 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 797 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 798 799 /* 800 * CP & rings. 801 */ 802 803 struct radeon_ib { 804 struct radeon_sa_bo *sa_bo; 805 uint32_t length_dw; 806 uint64_t gpu_addr; 807 uint32_t *ptr; 808 int ring; 809 struct radeon_fence *fence; 810 struct radeon_vm *vm; 811 bool is_const_ib; 812 struct radeon_semaphore *semaphore; 813 }; 814 815 struct radeon_ring { 816 struct radeon_bo *ring_obj; 817 volatile uint32_t *ring; 818 unsigned rptr_offs; 819 unsigned rptr_save_reg; 820 u64 next_rptr_gpu_addr; 821 volatile u32 *next_rptr_cpu_addr; 822 unsigned wptr; 823 unsigned wptr_old; 824 unsigned ring_size; 825 unsigned ring_free_dw; 826 int count_dw; 827 atomic_t last_rptr; 828 atomic64_t last_activity; 829 uint64_t gpu_addr; 830 uint32_t align_mask; 831 uint32_t ptr_mask; 832 bool ready; 833 u32 nop; 834 u32 idx; 835 u64 last_semaphore_signal_addr; 836 u64 last_semaphore_wait_addr; 837 /* for CIK queues */ 838 u32 me; 839 u32 pipe; 840 u32 queue; 841 struct radeon_bo *mqd_obj; 842 u32 doorbell_index; 843 unsigned wptr_offs; 844 }; 845 846 struct radeon_mec { 847 struct radeon_bo *hpd_eop_obj; 848 u64 hpd_eop_gpu_addr; 849 u32 num_pipe; 850 u32 num_mec; 851 u32 num_queue; 852 }; 853 854 /* 855 * VM 856 */ 857 858 /* maximum number of VMIDs */ 859 #define RADEON_NUM_VM 16 860 861 /* number of entries in page table */ 862 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 863 864 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 865 #define RADEON_VM_PTB_ALIGN_SIZE 32768 866 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 867 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 868 869 #define R600_PTE_VALID (1 << 0) 870 #define R600_PTE_SYSTEM (1 << 1) 871 #define R600_PTE_SNOOPED (1 << 2) 872 #define R600_PTE_READABLE (1 << 5) 873 #define R600_PTE_WRITEABLE (1 << 6) 874 875 /* PTE (Page Table Entry) fragment field for different page sizes */ 876 #define R600_PTE_FRAG_4KB (0 << 7) 877 #define R600_PTE_FRAG_64KB (4 << 7) 878 #define R600_PTE_FRAG_256KB (6 << 7) 879 880 /* flags needed to be set so we can copy directly from the GART table */ 881 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 882 R600_PTE_SYSTEM | R600_PTE_VALID ) 883 884 struct radeon_vm_pt { 885 struct radeon_bo *bo; 886 uint64_t addr; 887 }; 888 889 struct radeon_vm { 890 struct list_head va; 891 unsigned id; 892 893 /* BOs moved, but not yet updated in the PT */ 894 struct list_head invalidated; 895 896 /* BOs freed, but not yet updated in the PT */ 897 struct list_head freed; 898 899 /* contains the page directory */ 900 struct radeon_bo *page_directory; 901 uint64_t pd_gpu_addr; 902 unsigned max_pde_used; 903 904 /* array of page tables, one for each page directory entry */ 905 struct radeon_vm_pt *page_tables; 906 907 struct radeon_bo_va *ib_bo_va; 908 909 struct lock mutex; 910 /* last fence for cs using this vm */ 911 struct radeon_fence *fence; 912 /* last flush or NULL if we still need to flush */ 913 struct radeon_fence *last_flush; 914 /* last use of vmid */ 915 struct radeon_fence *last_id_use; 916 }; 917 918 struct radeon_vm_manager { 919 struct radeon_fence *active[RADEON_NUM_VM]; 920 uint32_t max_pfn; 921 /* number of VMIDs */ 922 unsigned nvm; 923 /* vram base address for page table entry */ 924 u64 vram_base_offset; 925 /* is vm enabled? */ 926 bool enabled; 927 /* for hw to save the PD addr on suspend/resume */ 928 uint32_t saved_table_addr[RADEON_NUM_VM]; 929 }; 930 931 /* 932 * file private structure 933 */ 934 struct radeon_fpriv { 935 struct radeon_vm vm; 936 }; 937 938 /* 939 * R6xx+ IH ring 940 */ 941 struct r600_ih { 942 struct radeon_bo *ring_obj; 943 volatile uint32_t *ring; 944 unsigned rptr; 945 unsigned ring_size; 946 uint64_t gpu_addr; 947 uint32_t ptr_mask; 948 atomic_t lock; 949 bool enabled; 950 }; 951 952 /* 953 * RLC stuff 954 */ 955 #include "clearstate_defs.h" 956 957 struct radeon_rlc { 958 /* for power gating */ 959 struct radeon_bo *save_restore_obj; 960 uint64_t save_restore_gpu_addr; 961 volatile uint32_t *sr_ptr; 962 const u32 *reg_list; 963 u32 reg_list_size; 964 /* for clear state */ 965 struct radeon_bo *clear_state_obj; 966 uint64_t clear_state_gpu_addr; 967 volatile uint32_t *cs_ptr; 968 const struct cs_section_def *cs_data; 969 u32 clear_state_size; 970 /* for cp tables */ 971 struct radeon_bo *cp_table_obj; 972 uint64_t cp_table_gpu_addr; 973 volatile uint32_t *cp_table_ptr; 974 u32 cp_table_size; 975 }; 976 977 int radeon_ib_get(struct radeon_device *rdev, int ring, 978 struct radeon_ib *ib, struct radeon_vm *vm, 979 unsigned size); 980 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 981 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 982 struct radeon_ib *const_ib, bool hdp_flush); 983 int radeon_ib_pool_init(struct radeon_device *rdev); 984 void radeon_ib_pool_fini(struct radeon_device *rdev); 985 int radeon_ib_ring_tests(struct radeon_device *rdev); 986 /* Ring access between begin & end cannot sleep */ 987 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 988 struct radeon_ring *ring); 989 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 990 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 991 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 992 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 993 bool hdp_flush); 994 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 995 bool hdp_flush); 996 void radeon_ring_undo(struct radeon_ring *ring); 997 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 998 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 999 void radeon_ring_lockup_update(struct radeon_device *rdev, 1000 struct radeon_ring *ring); 1001 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1002 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1003 uint32_t **data); 1004 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1005 unsigned size, uint32_t *data); 1006 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1007 unsigned rptr_offs, u32 nop); 1008 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1009 1010 1011 /* r600 async dma */ 1012 void r600_dma_stop(struct radeon_device *rdev); 1013 int r600_dma_resume(struct radeon_device *rdev); 1014 void r600_dma_fini(struct radeon_device *rdev); 1015 1016 void cayman_dma_stop(struct radeon_device *rdev); 1017 int cayman_dma_resume(struct radeon_device *rdev); 1018 void cayman_dma_fini(struct radeon_device *rdev); 1019 1020 /* 1021 * CS. 1022 */ 1023 struct radeon_cs_reloc { 1024 struct drm_gem_object *gobj; 1025 struct radeon_bo *robj; 1026 struct ttm_validate_buffer tv; 1027 uint64_t gpu_offset; 1028 unsigned prefered_domains; 1029 unsigned allowed_domains; 1030 uint32_t tiling_flags; 1031 uint32_t handle; 1032 }; 1033 1034 struct radeon_cs_chunk { 1035 uint32_t chunk_id; 1036 uint32_t length_dw; 1037 uint32_t *kdata; 1038 void __user *user_ptr; 1039 }; 1040 1041 struct radeon_cs_parser { 1042 device_t dev; 1043 struct radeon_device *rdev; 1044 struct drm_file *filp; 1045 /* chunks */ 1046 unsigned nchunks; 1047 struct radeon_cs_chunk *chunks; 1048 uint64_t *chunks_array; 1049 /* IB */ 1050 unsigned idx; 1051 /* relocations */ 1052 unsigned nrelocs; 1053 struct radeon_cs_reloc *relocs; 1054 struct radeon_cs_reloc **relocs_ptr; 1055 struct radeon_cs_reloc *vm_bos; 1056 struct list_head validated; 1057 unsigned dma_reloc_idx; 1058 /* indices of various chunks */ 1059 int chunk_ib_idx; 1060 int chunk_relocs_idx; 1061 int chunk_flags_idx; 1062 int chunk_const_ib_idx; 1063 struct radeon_ib ib; 1064 struct radeon_ib const_ib; 1065 void *track; 1066 unsigned family; 1067 int parser_error; 1068 u32 cs_flags; 1069 u32 ring; 1070 s32 priority; 1071 struct ww_acquire_ctx ticket; 1072 }; 1073 1074 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1075 { 1076 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1077 1078 if (ibc->kdata) 1079 return ibc->kdata[idx]; 1080 return p->ib.ptr[idx]; 1081 } 1082 1083 1084 struct radeon_cs_packet { 1085 unsigned idx; 1086 unsigned type; 1087 unsigned reg; 1088 unsigned opcode; 1089 int count; 1090 unsigned one_reg_wr; 1091 }; 1092 1093 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1094 struct radeon_cs_packet *pkt, 1095 unsigned idx, unsigned reg); 1096 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1097 struct radeon_cs_packet *pkt); 1098 1099 1100 /* 1101 * AGP 1102 */ 1103 int radeon_agp_init(struct radeon_device *rdev); 1104 void radeon_agp_resume(struct radeon_device *rdev); 1105 void radeon_agp_suspend(struct radeon_device *rdev); 1106 void radeon_agp_fini(struct radeon_device *rdev); 1107 1108 1109 /* 1110 * Writeback 1111 */ 1112 struct radeon_wb { 1113 struct radeon_bo *wb_obj; 1114 volatile uint32_t *wb; 1115 uint64_t gpu_addr; 1116 bool enabled; 1117 bool use_event; 1118 }; 1119 1120 #define RADEON_WB_SCRATCH_OFFSET 0 1121 #define RADEON_WB_RING0_NEXT_RPTR 256 1122 #define RADEON_WB_CP_RPTR_OFFSET 1024 1123 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1124 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1125 #define R600_WB_DMA_RPTR_OFFSET 1792 1126 #define R600_WB_IH_WPTR_OFFSET 2048 1127 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1128 #define R600_WB_EVENT_OFFSET 3072 1129 #define CIK_WB_CP1_WPTR_OFFSET 3328 1130 #define CIK_WB_CP2_WPTR_OFFSET 3584 1131 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1132 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1133 1134 /** 1135 * struct radeon_pm - power management datas 1136 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1137 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1138 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1139 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1140 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1141 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1142 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1143 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1144 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1145 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1146 * @needed_bandwidth: current bandwidth needs 1147 * 1148 * It keeps track of various data needed to take powermanagement decision. 1149 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1150 * Equation between gpu/memory clock and available bandwidth is hw dependent 1151 * (type of memory, bus size, efficiency, ...) 1152 */ 1153 1154 enum radeon_pm_method { 1155 PM_METHOD_PROFILE, 1156 PM_METHOD_DYNPM, 1157 PM_METHOD_DPM, 1158 }; 1159 1160 enum radeon_dynpm_state { 1161 DYNPM_STATE_DISABLED, 1162 DYNPM_STATE_MINIMUM, 1163 DYNPM_STATE_PAUSED, 1164 DYNPM_STATE_ACTIVE, 1165 DYNPM_STATE_SUSPENDED, 1166 }; 1167 enum radeon_dynpm_action { 1168 DYNPM_ACTION_NONE, 1169 DYNPM_ACTION_MINIMUM, 1170 DYNPM_ACTION_DOWNCLOCK, 1171 DYNPM_ACTION_UPCLOCK, 1172 DYNPM_ACTION_DEFAULT 1173 }; 1174 1175 enum radeon_voltage_type { 1176 VOLTAGE_NONE = 0, 1177 VOLTAGE_GPIO, 1178 VOLTAGE_VDDC, 1179 VOLTAGE_SW 1180 }; 1181 1182 enum radeon_pm_state_type { 1183 /* not used for dpm */ 1184 POWER_STATE_TYPE_DEFAULT, 1185 POWER_STATE_TYPE_POWERSAVE, 1186 /* user selectable states */ 1187 POWER_STATE_TYPE_BATTERY, 1188 POWER_STATE_TYPE_BALANCED, 1189 POWER_STATE_TYPE_PERFORMANCE, 1190 /* internal states */ 1191 POWER_STATE_TYPE_INTERNAL_UVD, 1192 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1193 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1194 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1195 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1196 POWER_STATE_TYPE_INTERNAL_BOOT, 1197 POWER_STATE_TYPE_INTERNAL_THERMAL, 1198 POWER_STATE_TYPE_INTERNAL_ACPI, 1199 POWER_STATE_TYPE_INTERNAL_ULV, 1200 POWER_STATE_TYPE_INTERNAL_3DPERF, 1201 }; 1202 1203 enum radeon_pm_profile_type { 1204 PM_PROFILE_DEFAULT, 1205 PM_PROFILE_AUTO, 1206 PM_PROFILE_LOW, 1207 PM_PROFILE_MID, 1208 PM_PROFILE_HIGH, 1209 }; 1210 1211 #define PM_PROFILE_DEFAULT_IDX 0 1212 #define PM_PROFILE_LOW_SH_IDX 1 1213 #define PM_PROFILE_MID_SH_IDX 2 1214 #define PM_PROFILE_HIGH_SH_IDX 3 1215 #define PM_PROFILE_LOW_MH_IDX 4 1216 #define PM_PROFILE_MID_MH_IDX 5 1217 #define PM_PROFILE_HIGH_MH_IDX 6 1218 #define PM_PROFILE_MAX 7 1219 1220 struct radeon_pm_profile { 1221 int dpms_off_ps_idx; 1222 int dpms_on_ps_idx; 1223 int dpms_off_cm_idx; 1224 int dpms_on_cm_idx; 1225 }; 1226 1227 enum radeon_int_thermal_type { 1228 THERMAL_TYPE_NONE, 1229 THERMAL_TYPE_EXTERNAL, 1230 THERMAL_TYPE_EXTERNAL_GPIO, 1231 THERMAL_TYPE_RV6XX, 1232 THERMAL_TYPE_RV770, 1233 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1234 THERMAL_TYPE_EVERGREEN, 1235 THERMAL_TYPE_SUMO, 1236 THERMAL_TYPE_NI, 1237 THERMAL_TYPE_SI, 1238 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1239 THERMAL_TYPE_CI, 1240 THERMAL_TYPE_KV, 1241 }; 1242 1243 struct radeon_voltage { 1244 enum radeon_voltage_type type; 1245 /* gpio voltage */ 1246 struct radeon_gpio_rec gpio; 1247 u32 delay; /* delay in usec from voltage drop to sclk change */ 1248 bool active_high; /* voltage drop is active when bit is high */ 1249 /* VDDC voltage */ 1250 u8 vddc_id; /* index into vddc voltage table */ 1251 u8 vddci_id; /* index into vddci voltage table */ 1252 bool vddci_enabled; 1253 /* r6xx+ sw */ 1254 u16 voltage; 1255 /* evergreen+ vddci */ 1256 u16 vddci; 1257 }; 1258 1259 /* clock mode flags */ 1260 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1261 1262 struct radeon_pm_clock_info { 1263 /* memory clock */ 1264 u32 mclk; 1265 /* engine clock */ 1266 u32 sclk; 1267 /* voltage info */ 1268 struct radeon_voltage voltage; 1269 /* standardized clock flags */ 1270 u32 flags; 1271 }; 1272 1273 /* state flags */ 1274 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1275 1276 struct radeon_power_state { 1277 enum radeon_pm_state_type type; 1278 struct radeon_pm_clock_info *clock_info; 1279 /* number of valid clock modes in this power state */ 1280 int num_clock_modes; 1281 struct radeon_pm_clock_info *default_clock_mode; 1282 /* standardized state flags */ 1283 u32 flags; 1284 u32 misc; /* vbios specific flags */ 1285 u32 misc2; /* vbios specific flags */ 1286 int pcie_lanes; /* pcie lanes */ 1287 }; 1288 1289 /* 1290 * Some modes are overclocked by very low value, accept them 1291 */ 1292 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1293 1294 enum radeon_dpm_auto_throttle_src { 1295 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1296 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1297 }; 1298 1299 enum radeon_dpm_event_src { 1300 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1301 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1302 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1303 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1304 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1305 }; 1306 1307 #define RADEON_MAX_VCE_LEVELS 6 1308 1309 enum radeon_vce_level { 1310 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1311 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1312 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1313 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1314 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1315 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1316 }; 1317 1318 struct radeon_ps { 1319 u32 caps; /* vbios flags */ 1320 u32 class; /* vbios flags */ 1321 u32 class2; /* vbios flags */ 1322 /* UVD clocks */ 1323 u32 vclk; 1324 u32 dclk; 1325 /* VCE clocks */ 1326 u32 evclk; 1327 u32 ecclk; 1328 bool vce_active; 1329 enum radeon_vce_level vce_level; 1330 /* asic priv */ 1331 void *ps_priv; 1332 }; 1333 1334 struct radeon_dpm_thermal { 1335 /* thermal interrupt work */ 1336 struct task work; 1337 /* low temperature threshold */ 1338 int min_temp; 1339 /* high temperature threshold */ 1340 int max_temp; 1341 /* was interrupt low to high or high to low */ 1342 bool high_to_low; 1343 }; 1344 1345 enum radeon_clk_action 1346 { 1347 RADEON_SCLK_UP = 1, 1348 RADEON_SCLK_DOWN 1349 }; 1350 1351 struct radeon_blacklist_clocks 1352 { 1353 u32 sclk; 1354 u32 mclk; 1355 enum radeon_clk_action action; 1356 }; 1357 1358 struct radeon_clock_and_voltage_limits { 1359 u32 sclk; 1360 u32 mclk; 1361 u16 vddc; 1362 u16 vddci; 1363 }; 1364 1365 struct radeon_clock_array { 1366 u32 count; 1367 u32 *values; 1368 }; 1369 1370 struct radeon_clock_voltage_dependency_entry { 1371 u32 clk; 1372 u16 v; 1373 }; 1374 1375 struct radeon_clock_voltage_dependency_table { 1376 u32 count; 1377 struct radeon_clock_voltage_dependency_entry *entries; 1378 }; 1379 1380 union radeon_cac_leakage_entry { 1381 struct { 1382 u16 vddc; 1383 u32 leakage; 1384 }; 1385 struct { 1386 u16 vddc1; 1387 u16 vddc2; 1388 u16 vddc3; 1389 }; 1390 }; 1391 1392 struct radeon_cac_leakage_table { 1393 u32 count; 1394 union radeon_cac_leakage_entry *entries; 1395 }; 1396 1397 struct radeon_phase_shedding_limits_entry { 1398 u16 voltage; 1399 u32 sclk; 1400 u32 mclk; 1401 }; 1402 1403 struct radeon_phase_shedding_limits_table { 1404 u32 count; 1405 struct radeon_phase_shedding_limits_entry *entries; 1406 }; 1407 1408 struct radeon_uvd_clock_voltage_dependency_entry { 1409 u32 vclk; 1410 u32 dclk; 1411 u16 v; 1412 }; 1413 1414 struct radeon_uvd_clock_voltage_dependency_table { 1415 u8 count; 1416 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1417 }; 1418 1419 struct radeon_vce_clock_voltage_dependency_entry { 1420 u32 ecclk; 1421 u32 evclk; 1422 u16 v; 1423 }; 1424 1425 struct radeon_vce_clock_voltage_dependency_table { 1426 u8 count; 1427 struct radeon_vce_clock_voltage_dependency_entry *entries; 1428 }; 1429 1430 struct radeon_ppm_table { 1431 u8 ppm_design; 1432 u16 cpu_core_number; 1433 u32 platform_tdp; 1434 u32 small_ac_platform_tdp; 1435 u32 platform_tdc; 1436 u32 small_ac_platform_tdc; 1437 u32 apu_tdp; 1438 u32 dgpu_tdp; 1439 u32 dgpu_ulv_power; 1440 u32 tj_max; 1441 }; 1442 1443 struct radeon_cac_tdp_table { 1444 u16 tdp; 1445 u16 configurable_tdp; 1446 u16 tdc; 1447 u16 battery_power_limit; 1448 u16 small_power_limit; 1449 u16 low_cac_leakage; 1450 u16 high_cac_leakage; 1451 u16 maximum_power_delivery_limit; 1452 }; 1453 1454 struct radeon_dpm_dynamic_state { 1455 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1456 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1457 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1458 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1459 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1460 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1461 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1462 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1463 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1464 struct radeon_clock_array valid_sclk_values; 1465 struct radeon_clock_array valid_mclk_values; 1466 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1467 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1468 u32 mclk_sclk_ratio; 1469 u32 sclk_mclk_delta; 1470 u16 vddc_vddci_delta; 1471 u16 min_vddc_for_pcie_gen2; 1472 struct radeon_cac_leakage_table cac_leakage_table; 1473 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1474 struct radeon_ppm_table *ppm_table; 1475 struct radeon_cac_tdp_table *cac_tdp_table; 1476 }; 1477 1478 struct radeon_dpm_fan { 1479 u16 t_min; 1480 u16 t_med; 1481 u16 t_high; 1482 u16 pwm_min; 1483 u16 pwm_med; 1484 u16 pwm_high; 1485 u8 t_hyst; 1486 u32 cycle_delay; 1487 u16 t_max; 1488 bool ucode_fan_control; 1489 }; 1490 1491 enum radeon_pcie_gen { 1492 RADEON_PCIE_GEN1 = 0, 1493 RADEON_PCIE_GEN2 = 1, 1494 RADEON_PCIE_GEN3 = 2, 1495 RADEON_PCIE_GEN_INVALID = 0xffff 1496 }; 1497 1498 enum radeon_dpm_forced_level { 1499 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1500 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1501 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1502 }; 1503 1504 struct radeon_vce_state { 1505 /* vce clocks */ 1506 u32 evclk; 1507 u32 ecclk; 1508 /* gpu clocks */ 1509 u32 sclk; 1510 u32 mclk; 1511 u8 clk_idx; 1512 u8 pstate; 1513 }; 1514 1515 struct radeon_dpm { 1516 struct radeon_ps *ps; 1517 /* number of valid power states */ 1518 int num_ps; 1519 /* current power state that is active */ 1520 struct radeon_ps *current_ps; 1521 /* requested power state */ 1522 struct radeon_ps *requested_ps; 1523 /* boot up power state */ 1524 struct radeon_ps *boot_ps; 1525 /* default uvd power state */ 1526 struct radeon_ps *uvd_ps; 1527 /* vce requirements */ 1528 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1529 enum radeon_vce_level vce_level; 1530 enum radeon_pm_state_type state; 1531 enum radeon_pm_state_type user_state; 1532 u32 platform_caps; 1533 u32 voltage_response_time; 1534 u32 backbias_response_time; 1535 void *priv; 1536 u32 new_active_crtcs; 1537 int new_active_crtc_count; 1538 u32 current_active_crtcs; 1539 int current_active_crtc_count; 1540 struct radeon_dpm_dynamic_state dyn_state; 1541 struct radeon_dpm_fan fan; 1542 u32 tdp_limit; 1543 u32 near_tdp_limit; 1544 u32 near_tdp_limit_adjusted; 1545 u32 sq_ramping_threshold; 1546 u32 cac_leakage; 1547 u16 tdp_od_limit; 1548 u32 tdp_adjustment; 1549 u16 load_line_slope; 1550 bool power_control; 1551 bool ac_power; 1552 /* special states active */ 1553 bool thermal_active; 1554 bool uvd_active; 1555 bool vce_active; 1556 /* thermal handling */ 1557 struct radeon_dpm_thermal thermal; 1558 /* forced levels */ 1559 enum radeon_dpm_forced_level forced_level; 1560 /* track UVD streams */ 1561 unsigned sd; 1562 unsigned hd; 1563 }; 1564 1565 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1566 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1567 1568 struct radeon_pm { 1569 struct lock mutex; 1570 /* write locked while reprogramming mclk */ 1571 struct lock mclk_lock; 1572 u32 active_crtcs; 1573 int active_crtc_count; 1574 int req_vblank; 1575 bool vblank_sync; 1576 fixed20_12 max_bandwidth; 1577 fixed20_12 igp_sideport_mclk; 1578 fixed20_12 igp_system_mclk; 1579 fixed20_12 igp_ht_link_clk; 1580 fixed20_12 igp_ht_link_width; 1581 fixed20_12 k8_bandwidth; 1582 fixed20_12 sideport_bandwidth; 1583 fixed20_12 ht_bandwidth; 1584 fixed20_12 core_bandwidth; 1585 fixed20_12 sclk; 1586 fixed20_12 mclk; 1587 fixed20_12 needed_bandwidth; 1588 struct radeon_power_state *power_state; 1589 /* number of valid power states */ 1590 int num_power_states; 1591 int current_power_state_index; 1592 int current_clock_mode_index; 1593 int requested_power_state_index; 1594 int requested_clock_mode_index; 1595 int default_power_state_index; 1596 u32 current_sclk; 1597 u32 current_mclk; 1598 u16 current_vddc; 1599 u16 current_vddci; 1600 u32 default_sclk; 1601 u32 default_mclk; 1602 u16 default_vddc; 1603 u16 default_vddci; 1604 struct radeon_i2c_chan *i2c_bus; 1605 /* selected pm method */ 1606 enum radeon_pm_method pm_method; 1607 /* dynpm power management */ 1608 #ifdef DUMBBELL_WIP 1609 struct delayed_work dynpm_idle_work; 1610 #endif /* DUMBBELL_WIP */ 1611 enum radeon_dynpm_state dynpm_state; 1612 enum radeon_dynpm_action dynpm_planned_action; 1613 unsigned long dynpm_action_timeout; 1614 bool dynpm_can_upclock; 1615 bool dynpm_can_downclock; 1616 /* profile-based power management */ 1617 enum radeon_pm_profile_type profile; 1618 int profile_index; 1619 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1620 /* internal thermal controller on rv6xx+ */ 1621 enum radeon_int_thermal_type int_thermal_type; 1622 struct ksensor *int_sensor; 1623 struct ksensordev *int_sensordev; 1624 /* dpm */ 1625 bool dpm_enabled; 1626 struct radeon_dpm dpm; 1627 }; 1628 1629 int radeon_pm_get_type_index(struct radeon_device *rdev, 1630 enum radeon_pm_state_type ps_type, 1631 int instance); 1632 /* 1633 * UVD 1634 */ 1635 #define RADEON_MAX_UVD_HANDLES 10 1636 #define RADEON_UVD_STACK_SIZE (1024*1024) 1637 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1638 1639 struct radeon_uvd { 1640 struct radeon_bo *vcpu_bo; 1641 void *cpu_addr; 1642 uint64_t gpu_addr; 1643 void *saved_bo; 1644 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1645 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1646 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1647 struct delayed_work idle_work; 1648 }; 1649 1650 int radeon_uvd_init(struct radeon_device *rdev); 1651 void radeon_uvd_fini(struct radeon_device *rdev); 1652 int radeon_uvd_suspend(struct radeon_device *rdev); 1653 int radeon_uvd_resume(struct radeon_device *rdev); 1654 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1655 uint32_t handle, struct radeon_fence **fence); 1656 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1657 uint32_t handle, struct radeon_fence **fence); 1658 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1659 uint32_t allowed_domains); 1660 void radeon_uvd_free_handles(struct radeon_device *rdev, 1661 struct drm_file *filp); 1662 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1663 void radeon_uvd_note_usage(struct radeon_device *rdev); 1664 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1665 unsigned vclk, unsigned dclk, 1666 unsigned vco_min, unsigned vco_max, 1667 unsigned fb_factor, unsigned fb_mask, 1668 unsigned pd_min, unsigned pd_max, 1669 unsigned pd_even, 1670 unsigned *optimal_fb_div, 1671 unsigned *optimal_vclk_div, 1672 unsigned *optimal_dclk_div); 1673 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1674 unsigned cg_upll_func_cntl); 1675 1676 /* 1677 * VCE 1678 */ 1679 #define RADEON_MAX_VCE_HANDLES 16 1680 #define RADEON_VCE_STACK_SIZE (1024*1024) 1681 #define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1682 1683 struct radeon_vce { 1684 struct radeon_bo *vcpu_bo; 1685 uint64_t gpu_addr; 1686 unsigned fw_version; 1687 unsigned fb_version; 1688 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1689 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1690 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1691 struct delayed_work idle_work; 1692 }; 1693 1694 int radeon_vce_init(struct radeon_device *rdev); 1695 void radeon_vce_fini(struct radeon_device *rdev); 1696 int radeon_vce_suspend(struct radeon_device *rdev); 1697 int radeon_vce_resume(struct radeon_device *rdev); 1698 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1699 uint32_t handle, struct radeon_fence **fence); 1700 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1701 uint32_t handle, struct radeon_fence **fence); 1702 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1703 void radeon_vce_note_usage(struct radeon_device *rdev); 1704 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1705 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1706 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1707 struct radeon_ring *ring, 1708 struct radeon_semaphore *semaphore, 1709 bool emit_wait); 1710 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1711 void radeon_vce_fence_emit(struct radeon_device *rdev, 1712 struct radeon_fence *fence); 1713 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1714 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1715 1716 struct r600_audio_pin { 1717 int channels; 1718 int rate; 1719 int bits_per_sample; 1720 u8 status_bits; 1721 u8 category_code; 1722 u32 offset; 1723 bool connected; 1724 u32 id; 1725 }; 1726 1727 struct r600_audio { 1728 bool enabled; 1729 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1730 int num_pins; 1731 }; 1732 1733 /* 1734 * Benchmarking 1735 */ 1736 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1737 1738 1739 /* 1740 * Testing 1741 */ 1742 void radeon_test_moves(struct radeon_device *rdev); 1743 void radeon_test_ring_sync(struct radeon_device *rdev, 1744 struct radeon_ring *cpA, 1745 struct radeon_ring *cpB); 1746 void radeon_test_syncing(struct radeon_device *rdev); 1747 1748 1749 /* 1750 * Debugfs 1751 */ 1752 struct radeon_debugfs { 1753 struct drm_info_list *files; 1754 unsigned num_files; 1755 }; 1756 1757 int radeon_debugfs_add_files(struct radeon_device *rdev, 1758 struct drm_info_list *files, 1759 unsigned nfiles); 1760 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1761 1762 /* 1763 * ASIC ring specific functions. 1764 */ 1765 struct radeon_asic_ring { 1766 /* ring read/write ptr handling */ 1767 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1768 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1769 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1770 1771 /* validating and patching of IBs */ 1772 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1773 int (*cs_parse)(struct radeon_cs_parser *p); 1774 1775 /* command emmit functions */ 1776 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1777 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1778 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1779 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1780 struct radeon_semaphore *semaphore, bool emit_wait); 1781 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1782 1783 /* testing functions */ 1784 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1785 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1786 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1787 1788 /* deprecated */ 1789 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1790 }; 1791 1792 /* 1793 * ASIC specific functions. 1794 */ 1795 struct radeon_asic { 1796 int (*init)(struct radeon_device *rdev); 1797 void (*fini)(struct radeon_device *rdev); 1798 int (*resume)(struct radeon_device *rdev); 1799 int (*suspend)(struct radeon_device *rdev); 1800 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1801 int (*asic_reset)(struct radeon_device *rdev); 1802 /* Flush the HDP cache via MMIO */ 1803 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1804 /* check if 3D engine is idle */ 1805 bool (*gui_idle)(struct radeon_device *rdev); 1806 /* wait for mc_idle */ 1807 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1808 /* get the reference clock */ 1809 u32 (*get_xclk)(struct radeon_device *rdev); 1810 /* get the gpu clock counter */ 1811 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1812 /* gart */ 1813 struct { 1814 void (*tlb_flush)(struct radeon_device *rdev); 1815 void (*set_page)(struct radeon_device *rdev, unsigned i, 1816 uint64_t addr, uint32_t flags); 1817 } gart; 1818 struct { 1819 int (*init)(struct radeon_device *rdev); 1820 void (*fini)(struct radeon_device *rdev); 1821 void (*copy_pages)(struct radeon_device *rdev, 1822 struct radeon_ib *ib, 1823 uint64_t pe, uint64_t src, 1824 unsigned count); 1825 void (*write_pages)(struct radeon_device *rdev, 1826 struct radeon_ib *ib, 1827 uint64_t pe, 1828 uint64_t addr, unsigned count, 1829 uint32_t incr, uint32_t flags); 1830 void (*set_pages)(struct radeon_device *rdev, 1831 struct radeon_ib *ib, 1832 uint64_t pe, 1833 uint64_t addr, unsigned count, 1834 uint32_t incr, uint32_t flags); 1835 void (*pad_ib)(struct radeon_ib *ib); 1836 } vm; 1837 /* ring specific callbacks */ 1838 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1839 /* irqs */ 1840 struct { 1841 int (*set)(struct radeon_device *rdev); 1842 irqreturn_t (*process)(struct radeon_device *rdev); 1843 } irq; 1844 /* displays */ 1845 struct { 1846 /* display watermarks */ 1847 void (*bandwidth_update)(struct radeon_device *rdev); 1848 /* get frame count */ 1849 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1850 /* wait for vblank */ 1851 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1852 /* set backlight level */ 1853 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1854 /* get backlight level */ 1855 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1856 /* audio callbacks */ 1857 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1858 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1859 } display; 1860 /* copy functions for bo handling */ 1861 struct { 1862 int (*blit)(struct radeon_device *rdev, 1863 uint64_t src_offset, 1864 uint64_t dst_offset, 1865 unsigned num_gpu_pages, 1866 struct radeon_fence **fence); 1867 u32 blit_ring_index; 1868 int (*dma)(struct radeon_device *rdev, 1869 uint64_t src_offset, 1870 uint64_t dst_offset, 1871 unsigned num_gpu_pages, 1872 struct radeon_fence **fence); 1873 u32 dma_ring_index; 1874 /* method used for bo copy */ 1875 int (*copy)(struct radeon_device *rdev, 1876 uint64_t src_offset, 1877 uint64_t dst_offset, 1878 unsigned num_gpu_pages, 1879 struct radeon_fence **fence); 1880 /* ring used for bo copies */ 1881 u32 copy_ring_index; 1882 } copy; 1883 /* surfaces */ 1884 struct { 1885 int (*set_reg)(struct radeon_device *rdev, int reg, 1886 uint32_t tiling_flags, uint32_t pitch, 1887 uint32_t offset, uint32_t obj_size); 1888 void (*clear_reg)(struct radeon_device *rdev, int reg); 1889 } surface; 1890 /* hotplug detect */ 1891 struct { 1892 void (*init)(struct radeon_device *rdev); 1893 void (*fini)(struct radeon_device *rdev); 1894 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1895 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1896 } hpd; 1897 /* static power management */ 1898 struct { 1899 void (*misc)(struct radeon_device *rdev); 1900 void (*prepare)(struct radeon_device *rdev); 1901 void (*finish)(struct radeon_device *rdev); 1902 void (*init_profile)(struct radeon_device *rdev); 1903 void (*get_dynpm_state)(struct radeon_device *rdev); 1904 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1905 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1906 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1907 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1908 int (*get_pcie_lanes)(struct radeon_device *rdev); 1909 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1910 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1911 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1912 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1913 int (*get_temperature)(struct radeon_device *rdev); 1914 } pm; 1915 /* dynamic power management */ 1916 struct { 1917 int (*init)(struct radeon_device *rdev); 1918 void (*setup_asic)(struct radeon_device *rdev); 1919 int (*enable)(struct radeon_device *rdev); 1920 int (*late_enable)(struct radeon_device *rdev); 1921 void (*disable)(struct radeon_device *rdev); 1922 int (*pre_set_power_state)(struct radeon_device *rdev); 1923 int (*set_power_state)(struct radeon_device *rdev); 1924 void (*post_set_power_state)(struct radeon_device *rdev); 1925 void (*display_configuration_changed)(struct radeon_device *rdev); 1926 void (*fini)(struct radeon_device *rdev); 1927 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1928 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1929 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1930 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1931 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1932 bool (*vblank_too_short)(struct radeon_device *rdev); 1933 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1934 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1935 } dpm; 1936 /* pageflipping */ 1937 struct { 1938 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1939 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1940 } pflip; 1941 }; 1942 1943 /* 1944 * Asic structures 1945 */ 1946 struct r100_asic { 1947 const unsigned *reg_safe_bm; 1948 unsigned reg_safe_bm_size; 1949 u32 hdp_cntl; 1950 }; 1951 1952 struct r300_asic { 1953 const unsigned *reg_safe_bm; 1954 unsigned reg_safe_bm_size; 1955 u32 resync_scratch; 1956 u32 hdp_cntl; 1957 }; 1958 1959 struct r600_asic { 1960 unsigned max_pipes; 1961 unsigned max_tile_pipes; 1962 unsigned max_simds; 1963 unsigned max_backends; 1964 unsigned max_gprs; 1965 unsigned max_threads; 1966 unsigned max_stack_entries; 1967 unsigned max_hw_contexts; 1968 unsigned max_gs_threads; 1969 unsigned sx_max_export_size; 1970 unsigned sx_max_export_pos_size; 1971 unsigned sx_max_export_smx_size; 1972 unsigned sq_num_cf_insts; 1973 unsigned tiling_nbanks; 1974 unsigned tiling_npipes; 1975 unsigned tiling_group_size; 1976 unsigned tile_config; 1977 unsigned backend_map; 1978 unsigned active_simds; 1979 }; 1980 1981 struct rv770_asic { 1982 unsigned max_pipes; 1983 unsigned max_tile_pipes; 1984 unsigned max_simds; 1985 unsigned max_backends; 1986 unsigned max_gprs; 1987 unsigned max_threads; 1988 unsigned max_stack_entries; 1989 unsigned max_hw_contexts; 1990 unsigned max_gs_threads; 1991 unsigned sx_max_export_size; 1992 unsigned sx_max_export_pos_size; 1993 unsigned sx_max_export_smx_size; 1994 unsigned sq_num_cf_insts; 1995 unsigned sx_num_of_sets; 1996 unsigned sc_prim_fifo_size; 1997 unsigned sc_hiz_tile_fifo_size; 1998 unsigned sc_earlyz_tile_fifo_fize; 1999 unsigned tiling_nbanks; 2000 unsigned tiling_npipes; 2001 unsigned tiling_group_size; 2002 unsigned tile_config; 2003 unsigned backend_map; 2004 unsigned active_simds; 2005 }; 2006 2007 struct evergreen_asic { 2008 unsigned num_ses; 2009 unsigned max_pipes; 2010 unsigned max_tile_pipes; 2011 unsigned max_simds; 2012 unsigned max_backends; 2013 unsigned max_gprs; 2014 unsigned max_threads; 2015 unsigned max_stack_entries; 2016 unsigned max_hw_contexts; 2017 unsigned max_gs_threads; 2018 unsigned sx_max_export_size; 2019 unsigned sx_max_export_pos_size; 2020 unsigned sx_max_export_smx_size; 2021 unsigned sq_num_cf_insts; 2022 unsigned sx_num_of_sets; 2023 unsigned sc_prim_fifo_size; 2024 unsigned sc_hiz_tile_fifo_size; 2025 unsigned sc_earlyz_tile_fifo_size; 2026 unsigned tiling_nbanks; 2027 unsigned tiling_npipes; 2028 unsigned tiling_group_size; 2029 unsigned tile_config; 2030 unsigned backend_map; 2031 unsigned active_simds; 2032 }; 2033 2034 struct cayman_asic { 2035 unsigned max_shader_engines; 2036 unsigned max_pipes_per_simd; 2037 unsigned max_tile_pipes; 2038 unsigned max_simds_per_se; 2039 unsigned max_backends_per_se; 2040 unsigned max_texture_channel_caches; 2041 unsigned max_gprs; 2042 unsigned max_threads; 2043 unsigned max_gs_threads; 2044 unsigned max_stack_entries; 2045 unsigned sx_num_of_sets; 2046 unsigned sx_max_export_size; 2047 unsigned sx_max_export_pos_size; 2048 unsigned sx_max_export_smx_size; 2049 unsigned max_hw_contexts; 2050 unsigned sq_num_cf_insts; 2051 unsigned sc_prim_fifo_size; 2052 unsigned sc_hiz_tile_fifo_size; 2053 unsigned sc_earlyz_tile_fifo_size; 2054 2055 unsigned num_shader_engines; 2056 unsigned num_shader_pipes_per_simd; 2057 unsigned num_tile_pipes; 2058 unsigned num_simds_per_se; 2059 unsigned num_backends_per_se; 2060 unsigned backend_disable_mask_per_asic; 2061 unsigned backend_map; 2062 unsigned num_texture_channel_caches; 2063 unsigned mem_max_burst_length_bytes; 2064 unsigned mem_row_size_in_kb; 2065 unsigned shader_engine_tile_size; 2066 unsigned num_gpus; 2067 unsigned multi_gpu_tile_size; 2068 2069 unsigned tile_config; 2070 unsigned active_simds; 2071 }; 2072 2073 struct si_asic { 2074 unsigned max_shader_engines; 2075 unsigned max_tile_pipes; 2076 unsigned max_cu_per_sh; 2077 unsigned max_sh_per_se; 2078 unsigned max_backends_per_se; 2079 unsigned max_texture_channel_caches; 2080 unsigned max_gprs; 2081 unsigned max_gs_threads; 2082 unsigned max_hw_contexts; 2083 unsigned sc_prim_fifo_size_frontend; 2084 unsigned sc_prim_fifo_size_backend; 2085 unsigned sc_hiz_tile_fifo_size; 2086 unsigned sc_earlyz_tile_fifo_size; 2087 2088 unsigned num_tile_pipes; 2089 unsigned backend_enable_mask; 2090 unsigned backend_disable_mask_per_asic; 2091 unsigned backend_map; 2092 unsigned num_texture_channel_caches; 2093 unsigned mem_max_burst_length_bytes; 2094 unsigned mem_row_size_in_kb; 2095 unsigned shader_engine_tile_size; 2096 unsigned num_gpus; 2097 unsigned multi_gpu_tile_size; 2098 2099 unsigned tile_config; 2100 uint32_t tile_mode_array[32]; 2101 uint32_t active_cus; 2102 }; 2103 2104 struct cik_asic { 2105 unsigned max_shader_engines; 2106 unsigned max_tile_pipes; 2107 unsigned max_cu_per_sh; 2108 unsigned max_sh_per_se; 2109 unsigned max_backends_per_se; 2110 unsigned max_texture_channel_caches; 2111 unsigned max_gprs; 2112 unsigned max_gs_threads; 2113 unsigned max_hw_contexts; 2114 unsigned sc_prim_fifo_size_frontend; 2115 unsigned sc_prim_fifo_size_backend; 2116 unsigned sc_hiz_tile_fifo_size; 2117 unsigned sc_earlyz_tile_fifo_size; 2118 2119 unsigned num_tile_pipes; 2120 unsigned backend_enable_mask; 2121 unsigned backend_disable_mask_per_asic; 2122 unsigned backend_map; 2123 unsigned num_texture_channel_caches; 2124 unsigned mem_max_burst_length_bytes; 2125 unsigned mem_row_size_in_kb; 2126 unsigned shader_engine_tile_size; 2127 unsigned num_gpus; 2128 unsigned multi_gpu_tile_size; 2129 2130 unsigned tile_config; 2131 uint32_t tile_mode_array[32]; 2132 uint32_t macrotile_mode_array[16]; 2133 uint32_t active_cus; 2134 }; 2135 2136 union radeon_asic_config { 2137 struct r300_asic r300; 2138 struct r100_asic r100; 2139 struct r600_asic r600; 2140 struct rv770_asic rv770; 2141 struct evergreen_asic evergreen; 2142 struct cayman_asic cayman; 2143 struct si_asic si; 2144 struct cik_asic cik; 2145 }; 2146 2147 /* 2148 * asic initizalization from radeon_asic.c 2149 */ 2150 int radeon_asic_init(struct radeon_device *rdev); 2151 2152 2153 /* 2154 * IOCTL. 2155 */ 2156 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2157 struct drm_file *filp); 2158 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2159 struct drm_file *filp); 2160 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2161 struct drm_file *file_priv); 2162 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2163 struct drm_file *file_priv); 2164 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2165 struct drm_file *file_priv); 2166 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2167 struct drm_file *file_priv); 2168 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2169 struct drm_file *filp); 2170 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2171 struct drm_file *filp); 2172 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2173 struct drm_file *filp); 2174 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2175 struct drm_file *filp); 2176 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2177 struct drm_file *filp); 2178 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2179 struct drm_file *filp); 2180 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2181 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2182 struct drm_file *filp); 2183 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2184 struct drm_file *filp); 2185 2186 /* VRAM scratch page for HDP bug, default vram page */ 2187 struct r600_vram_scratch { 2188 struct radeon_bo *robj; 2189 volatile uint32_t *ptr; 2190 u64 gpu_addr; 2191 }; 2192 2193 /* 2194 * ACPI 2195 */ 2196 struct radeon_atif_notification_cfg { 2197 bool enabled; 2198 int command_code; 2199 }; 2200 2201 struct radeon_atif_notifications { 2202 bool display_switch; 2203 bool expansion_mode_change; 2204 bool thermal_state; 2205 bool forced_power_state; 2206 bool system_power_state; 2207 bool display_conf_change; 2208 bool px_gfx_switch; 2209 bool brightness_change; 2210 bool dgpu_display_event; 2211 }; 2212 2213 struct radeon_atif_functions { 2214 bool system_params; 2215 bool sbios_requests; 2216 bool select_active_disp; 2217 bool lid_state; 2218 bool get_tv_standard; 2219 bool set_tv_standard; 2220 bool get_panel_expansion_mode; 2221 bool set_panel_expansion_mode; 2222 bool temperature_change; 2223 bool graphics_device_types; 2224 }; 2225 2226 struct radeon_atif { 2227 struct radeon_atif_notifications notifications; 2228 struct radeon_atif_functions functions; 2229 struct radeon_atif_notification_cfg notification_cfg; 2230 struct radeon_encoder *encoder_for_bl; 2231 }; 2232 2233 struct radeon_atcs_functions { 2234 bool get_ext_state; 2235 bool pcie_perf_req; 2236 bool pcie_dev_rdy; 2237 bool pcie_bus_width; 2238 }; 2239 2240 struct radeon_atcs { 2241 struct radeon_atcs_functions functions; 2242 }; 2243 2244 /* 2245 * Core structure, functions and helpers. 2246 */ 2247 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2248 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2249 2250 struct radeon_device { 2251 device_t dev; 2252 struct drm_device *ddev; 2253 struct pci_dev *pdev; 2254 struct lock exclusive_lock; 2255 /* ASIC */ 2256 union radeon_asic_config config; 2257 enum radeon_family family; 2258 unsigned long flags; 2259 int usec_timeout; 2260 enum radeon_pll_errata pll_errata; 2261 int num_gb_pipes; 2262 int num_z_pipes; 2263 int disp_priority; 2264 /* BIOS */ 2265 uint8_t *bios; 2266 bool is_atom_bios; 2267 uint16_t bios_header_start; 2268 struct radeon_bo *stollen_vga_memory; 2269 /* Register mmio */ 2270 resource_size_t rmmio_base; 2271 resource_size_t rmmio_size; 2272 /* protects concurrent MM_INDEX/DATA based register access */ 2273 struct spinlock mmio_idx_lock; 2274 /* protects concurrent SMC based register access */ 2275 struct spinlock smc_idx_lock; 2276 /* protects concurrent PLL register access */ 2277 struct spinlock pll_idx_lock; 2278 /* protects concurrent MC register access */ 2279 struct spinlock mc_idx_lock; 2280 /* protects concurrent PCIE register access */ 2281 struct spinlock pcie_idx_lock; 2282 /* protects concurrent PCIE_PORT register access */ 2283 struct spinlock pciep_idx_lock; 2284 /* protects concurrent PIF register access */ 2285 struct spinlock pif_idx_lock; 2286 /* protects concurrent CG register access */ 2287 struct spinlock cg_idx_lock; 2288 /* protects concurrent UVD register access */ 2289 struct spinlock uvd_idx_lock; 2290 /* protects concurrent RCU register access */ 2291 struct spinlock rcu_idx_lock; 2292 /* protects concurrent DIDT register access */ 2293 struct spinlock didt_idx_lock; 2294 /* protects concurrent ENDPOINT (audio) register access */ 2295 struct spinlock end_idx_lock; 2296 int rmmio_rid; 2297 struct resource *rmmio; 2298 radeon_rreg_t mc_rreg; 2299 radeon_wreg_t mc_wreg; 2300 radeon_rreg_t pll_rreg; 2301 radeon_wreg_t pll_wreg; 2302 uint32_t pcie_reg_mask; 2303 radeon_rreg_t pciep_rreg; 2304 radeon_wreg_t pciep_wreg; 2305 /* io port */ 2306 int rio_rid; 2307 struct resource *rio_mem; 2308 resource_size_t rio_mem_size; 2309 struct radeon_clock clock; 2310 struct radeon_mc mc; 2311 struct radeon_gart gart; 2312 struct radeon_mode_info mode_info; 2313 struct radeon_scratch scratch; 2314 struct radeon_doorbell doorbell; 2315 struct radeon_mman mman; 2316 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2317 wait_queue_head_t fence_queue; 2318 struct lock ring_lock; 2319 struct radeon_ring ring[RADEON_NUM_RINGS]; 2320 bool ib_pool_ready; 2321 struct radeon_sa_manager ring_tmp_bo; 2322 struct radeon_irq irq; 2323 struct radeon_asic *asic; 2324 struct radeon_gem gem; 2325 struct radeon_pm pm; 2326 struct radeon_uvd uvd; 2327 struct radeon_vce vce; 2328 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2329 struct radeon_wb wb; 2330 struct radeon_dummy_page dummy_page; 2331 bool shutdown; 2332 bool suspend; 2333 bool need_dma32; 2334 bool accel_working; 2335 bool fastfb_working; /* IGP feature*/ 2336 bool needs_reset, in_reset; 2337 bool fictitious_range_registered; 2338 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2339 const struct firmware *me_fw; /* all family ME firmware */ 2340 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2341 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2342 const struct firmware *mc_fw; /* NI MC firmware */ 2343 const struct firmware *ce_fw; /* SI CE firmware */ 2344 const struct firmware *mec_fw; /* CIK MEC firmware */ 2345 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2346 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2347 const struct firmware *smc_fw; /* SMC firmware */ 2348 const struct firmware *uvd_fw; /* UVD firmware */ 2349 const struct firmware *vce_fw; /* VCE firmware */ 2350 bool new_fw; 2351 struct r600_vram_scratch vram_scratch; 2352 int msi_enabled; /* msi enabled */ 2353 struct r600_ih ih; /* r6/700 interrupt ring */ 2354 struct radeon_rlc rlc; 2355 struct radeon_mec mec; 2356 struct taskqueue *tq; 2357 struct task hotplug_work; 2358 struct task audio_work; 2359 int num_crtc; /* number of crtcs */ 2360 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2361 bool has_uvd; 2362 struct r600_audio audio; /* audio stuff */ 2363 struct { 2364 ACPI_HANDLE handle; 2365 ACPI_NOTIFY_HANDLER notifier_call; 2366 } acpi; 2367 /* only one userspace can use Hyperz features or CMASK at a time */ 2368 struct drm_file *hyperz_filp; 2369 struct drm_file *cmask_filp; 2370 /* i2c buses */ 2371 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2372 /* debugfs */ 2373 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2374 unsigned debugfs_count; 2375 /* virtual memory */ 2376 struct radeon_vm_manager vm_manager; 2377 struct spinlock gpu_clock_mutex; 2378 /* memory stats */ 2379 atomic64_t vram_usage; 2380 atomic64_t gtt_usage; 2381 atomic64_t num_bytes_moved; 2382 /* ACPI interface */ 2383 struct radeon_atif atif; 2384 struct radeon_atcs atcs; 2385 /* srbm instance registers */ 2386 struct spinlock srbm_mutex; 2387 /* clock, powergating flags */ 2388 u32 cg_flags; 2389 u32 pg_flags; 2390 2391 #ifdef PM_TODO 2392 struct dev_pm_domain vga_pm_domain; 2393 #endif 2394 bool have_disp_power_ref; 2395 u32 px_quirk_flags; 2396 2397 /* tracking pinned memory */ 2398 u64 vram_pin_size; 2399 u64 gart_pin_size; 2400 }; 2401 2402 bool radeon_is_px(struct drm_device *dev); 2403 int radeon_device_init(struct radeon_device *rdev, 2404 struct drm_device *ddev, 2405 struct pci_dev *pdev, 2406 uint32_t flags); 2407 void radeon_device_fini(struct radeon_device *rdev); 2408 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2409 2410 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2411 bool always_indirect); 2412 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2413 bool always_indirect); 2414 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2415 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2416 2417 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2418 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2419 2420 /* 2421 * Cast helper 2422 */ 2423 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2424 2425 /* 2426 * Registers read & write functions. 2427 */ 2428 #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 2429 #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 2430 #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 2431 #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 2432 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2433 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2434 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 2435 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2436 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2437 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2438 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2439 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2440 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2441 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2442 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2443 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2444 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2445 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2446 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2447 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2448 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2449 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2450 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2451 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2452 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2453 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2454 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2455 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2456 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2457 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2458 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2459 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2460 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2461 #define WREG32_P(reg, val, mask) \ 2462 do { \ 2463 uint32_t tmp_ = RREG32(reg); \ 2464 tmp_ &= (mask); \ 2465 tmp_ |= ((val) & ~(mask)); \ 2466 WREG32(reg, tmp_); \ 2467 } while (0) 2468 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2469 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2470 #define WREG32_PLL_P(reg, val, mask) \ 2471 do { \ 2472 uint32_t tmp_ = RREG32_PLL(reg); \ 2473 tmp_ &= (mask); \ 2474 tmp_ |= ((val) & ~(mask)); \ 2475 WREG32_PLL(reg, tmp_); \ 2476 } while (0) 2477 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2478 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2479 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2480 2481 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2482 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2483 2484 /* 2485 * Indirect registers accessor 2486 */ 2487 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2488 { 2489 uint32_t r; 2490 2491 spin_lock(&rdev->pcie_idx_lock); 2492 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2493 r = RREG32(RADEON_PCIE_DATA); 2494 spin_unlock(&rdev->pcie_idx_lock); 2495 return r; 2496 } 2497 2498 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2499 { 2500 spin_lock(&rdev->pcie_idx_lock); 2501 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2502 WREG32(RADEON_PCIE_DATA, (v)); 2503 spin_unlock(&rdev->pcie_idx_lock); 2504 } 2505 2506 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2507 { 2508 u32 r; 2509 2510 spin_lock(&rdev->smc_idx_lock); 2511 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2512 r = RREG32(TN_SMC_IND_DATA_0); 2513 spin_unlock(&rdev->smc_idx_lock); 2514 return r; 2515 } 2516 2517 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2518 { 2519 spin_lock(&rdev->smc_idx_lock); 2520 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2521 WREG32(TN_SMC_IND_DATA_0, (v)); 2522 spin_unlock(&rdev->smc_idx_lock); 2523 } 2524 2525 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2526 { 2527 u32 r; 2528 2529 spin_lock(&rdev->rcu_idx_lock); 2530 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2531 r = RREG32(R600_RCU_DATA); 2532 spin_unlock(&rdev->rcu_idx_lock); 2533 return r; 2534 } 2535 2536 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2537 { 2538 spin_lock(&rdev->rcu_idx_lock); 2539 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2540 WREG32(R600_RCU_DATA, (v)); 2541 spin_unlock(&rdev->rcu_idx_lock); 2542 } 2543 2544 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2545 { 2546 u32 r; 2547 2548 spin_lock(&rdev->cg_idx_lock); 2549 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2550 r = RREG32(EVERGREEN_CG_IND_DATA); 2551 spin_unlock(&rdev->cg_idx_lock); 2552 return r; 2553 } 2554 2555 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2556 { 2557 spin_lock(&rdev->cg_idx_lock); 2558 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2559 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2560 spin_unlock(&rdev->cg_idx_lock); 2561 } 2562 2563 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2564 { 2565 u32 r; 2566 2567 spin_lock(&rdev->pif_idx_lock); 2568 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2569 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2570 spin_unlock(&rdev->pif_idx_lock); 2571 return r; 2572 } 2573 2574 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2575 { 2576 spin_lock(&rdev->pif_idx_lock); 2577 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2578 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2579 spin_unlock(&rdev->pif_idx_lock); 2580 } 2581 2582 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2583 { 2584 u32 r; 2585 2586 spin_lock(&rdev->pif_idx_lock); 2587 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2588 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2589 spin_unlock(&rdev->pif_idx_lock); 2590 return r; 2591 } 2592 2593 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2594 { 2595 spin_lock(&rdev->pif_idx_lock); 2596 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2597 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2598 spin_unlock(&rdev->pif_idx_lock); 2599 } 2600 2601 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2602 { 2603 u32 r; 2604 2605 spin_lock(&rdev->uvd_idx_lock); 2606 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2607 r = RREG32(R600_UVD_CTX_DATA); 2608 spin_unlock(&rdev->uvd_idx_lock); 2609 return r; 2610 } 2611 2612 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2613 { 2614 spin_lock(&rdev->uvd_idx_lock); 2615 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2616 WREG32(R600_UVD_CTX_DATA, (v)); 2617 spin_unlock(&rdev->uvd_idx_lock); 2618 } 2619 2620 2621 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2622 { 2623 u32 r; 2624 2625 spin_lock(&rdev->didt_idx_lock); 2626 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2627 r = RREG32(CIK_DIDT_IND_DATA); 2628 spin_unlock(&rdev->didt_idx_lock); 2629 return r; 2630 } 2631 2632 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2633 { 2634 spin_lock(&rdev->didt_idx_lock); 2635 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2636 WREG32(CIK_DIDT_IND_DATA, (v)); 2637 spin_unlock(&rdev->didt_idx_lock); 2638 } 2639 2640 void r100_pll_errata_after_index(struct radeon_device *rdev); 2641 2642 2643 /* 2644 * ASICs helpers. 2645 */ 2646 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2647 (rdev->pdev->device == 0x5969)) 2648 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2649 (rdev->family == CHIP_RV200) || \ 2650 (rdev->family == CHIP_RS100) || \ 2651 (rdev->family == CHIP_RS200) || \ 2652 (rdev->family == CHIP_RV250) || \ 2653 (rdev->family == CHIP_RV280) || \ 2654 (rdev->family == CHIP_RS300)) 2655 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2656 (rdev->family == CHIP_RV350) || \ 2657 (rdev->family == CHIP_R350) || \ 2658 (rdev->family == CHIP_RV380) || \ 2659 (rdev->family == CHIP_R420) || \ 2660 (rdev->family == CHIP_R423) || \ 2661 (rdev->family == CHIP_RV410) || \ 2662 (rdev->family == CHIP_RS400) || \ 2663 (rdev->family == CHIP_RS480)) 2664 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2665 (rdev->ddev->pdev->device == 0x9443) || \ 2666 (rdev->ddev->pdev->device == 0x944B) || \ 2667 (rdev->ddev->pdev->device == 0x9506) || \ 2668 (rdev->ddev->pdev->device == 0x9509) || \ 2669 (rdev->ddev->pdev->device == 0x950F) || \ 2670 (rdev->ddev->pdev->device == 0x689C) || \ 2671 (rdev->ddev->pdev->device == 0x689D)) 2672 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2673 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2674 (rdev->family == CHIP_RS690) || \ 2675 (rdev->family == CHIP_RS740) || \ 2676 (rdev->family >= CHIP_R600)) 2677 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2678 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2679 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2680 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2681 (rdev->flags & RADEON_IS_IGP)) 2682 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2683 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2684 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2685 (rdev->flags & RADEON_IS_IGP)) 2686 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2687 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2688 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2689 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2690 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2691 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2692 (rdev->family == CHIP_MULLINS)) 2693 2694 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2695 (rdev->ddev->pdev->device == 0x6850) || \ 2696 (rdev->ddev->pdev->device == 0x6858) || \ 2697 (rdev->ddev->pdev->device == 0x6859) || \ 2698 (rdev->ddev->pdev->device == 0x6840) || \ 2699 (rdev->ddev->pdev->device == 0x6841) || \ 2700 (rdev->ddev->pdev->device == 0x6842) || \ 2701 (rdev->ddev->pdev->device == 0x6843)) 2702 2703 /* 2704 * BIOS helpers. 2705 */ 2706 #define RBIOS8(i) (rdev->bios[i]) 2707 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2708 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2709 2710 int radeon_combios_init(struct radeon_device *rdev); 2711 void radeon_combios_fini(struct radeon_device *rdev); 2712 int radeon_atombios_init(struct radeon_device *rdev); 2713 void radeon_atombios_fini(struct radeon_device *rdev); 2714 2715 2716 /* 2717 * RING helpers. 2718 */ 2719 2720 /** 2721 * radeon_ring_write - write a value to the ring 2722 * 2723 * @ring: radeon_ring structure holding ring information 2724 * @v: dword (dw) value to write 2725 * 2726 * Write a value to the requested ring buffer (all asics). 2727 */ 2728 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2729 { 2730 if (ring->count_dw <= 0) 2731 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2732 2733 ring->ring[ring->wptr++] = v; 2734 ring->wptr &= ring->ptr_mask; 2735 ring->count_dw--; 2736 ring->ring_free_dw--; 2737 } 2738 2739 /* 2740 * ASICs macro. 2741 */ 2742 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2743 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2744 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2745 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2746 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2747 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2748 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2749 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2750 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) 2751 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2752 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2753 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2754 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2755 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2756 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2757 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2758 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2759 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2760 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2761 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2762 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2763 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) 2764 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2765 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2766 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2767 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2768 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2769 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2770 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2771 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2772 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2773 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2774 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2775 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2776 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2777 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2778 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2779 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2780 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2781 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2782 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2783 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2784 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2785 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2786 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2787 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2788 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2789 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2790 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2791 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2792 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2793 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2794 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2795 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2796 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2797 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2798 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2799 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2800 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2801 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2802 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2803 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2804 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2805 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2806 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2807 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2808 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2809 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2810 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2811 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2812 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2813 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2814 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2815 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2816 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2817 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2818 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2819 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2820 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2821 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2822 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2823 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2824 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2825 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2826 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2827 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2828 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2829 2830 /* Common functions */ 2831 /* AGP */ 2832 extern int radeon_gpu_reset(struct radeon_device *rdev); 2833 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2834 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2835 extern void radeon_agp_disable(struct radeon_device *rdev); 2836 extern int radeon_modeset_init(struct radeon_device *rdev); 2837 extern void radeon_modeset_fini(struct radeon_device *rdev); 2838 extern bool radeon_card_posted(struct radeon_device *rdev); 2839 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2840 extern void radeon_update_display_priority(struct radeon_device *rdev); 2841 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2842 extern void radeon_scratch_init(struct radeon_device *rdev); 2843 extern void radeon_wb_fini(struct radeon_device *rdev); 2844 extern int radeon_wb_init(struct radeon_device *rdev); 2845 extern void radeon_wb_disable(struct radeon_device *rdev); 2846 extern void radeon_surface_init(struct radeon_device *rdev); 2847 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2848 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2849 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2850 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2851 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2852 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2853 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2854 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2855 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2856 const u32 *registers, 2857 const u32 array_size); 2858 2859 /* 2860 * vm 2861 */ 2862 int radeon_vm_manager_init(struct radeon_device *rdev); 2863 void radeon_vm_manager_fini(struct radeon_device *rdev); 2864 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2865 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2866 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2867 struct radeon_vm *vm, 2868 struct list_head *head); 2869 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2870 struct radeon_vm *vm, int ring); 2871 void radeon_vm_flush(struct radeon_device *rdev, 2872 struct radeon_vm *vm, 2873 int ring); 2874 void radeon_vm_fence(struct radeon_device *rdev, 2875 struct radeon_vm *vm, 2876 struct radeon_fence *fence); 2877 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2878 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2879 struct radeon_vm *vm); 2880 int radeon_vm_clear_freed(struct radeon_device *rdev, 2881 struct radeon_vm *vm); 2882 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2883 struct radeon_vm *vm); 2884 int radeon_vm_bo_update(struct radeon_device *rdev, 2885 struct radeon_bo_va *bo_va, 2886 struct ttm_mem_reg *mem); 2887 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2888 struct radeon_bo *bo); 2889 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2890 struct radeon_bo *bo); 2891 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2892 struct radeon_vm *vm, 2893 struct radeon_bo *bo); 2894 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2895 struct radeon_bo_va *bo_va, 2896 uint64_t offset, 2897 uint32_t flags); 2898 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2899 struct radeon_bo_va *bo_va); 2900 2901 /* audio */ 2902 void r600_audio_update_hdmi(void *arg, int pending); 2903 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2904 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2905 void r600_audio_enable(struct radeon_device *rdev, 2906 struct r600_audio_pin *pin, 2907 u8 enable_mask); 2908 void dce6_audio_enable(struct radeon_device *rdev, 2909 struct r600_audio_pin *pin, 2910 u8 enable_mask); 2911 2912 /* 2913 * R600 vram scratch functions 2914 */ 2915 int r600_vram_scratch_init(struct radeon_device *rdev); 2916 void r600_vram_scratch_fini(struct radeon_device *rdev); 2917 2918 /* 2919 * r600 cs checking helper 2920 */ 2921 unsigned r600_mip_minify(unsigned size, unsigned level); 2922 bool r600_fmt_is_valid_color(u32 format); 2923 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2924 int r600_fmt_get_blocksize(u32 format); 2925 int r600_fmt_get_nblocksx(u32 format, u32 w); 2926 int r600_fmt_get_nblocksy(u32 format, u32 h); 2927 2928 /* 2929 * r600 functions used by radeon_encoder.c 2930 */ 2931 struct radeon_hdmi_acr { 2932 u32 clock; 2933 2934 int n_32khz; 2935 int cts_32khz; 2936 2937 int n_44_1khz; 2938 int cts_44_1khz; 2939 2940 int n_48khz; 2941 int cts_48khz; 2942 2943 }; 2944 2945 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2946 2947 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2948 u32 tiling_pipe_num, 2949 u32 max_rb_num, 2950 u32 total_max_rb_num, 2951 u32 enabled_rb_mask); 2952 2953 /* 2954 * evergreen functions used by radeon_encoder.c 2955 */ 2956 2957 extern int ni_init_microcode(struct radeon_device *rdev); 2958 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2959 extern void ni_fini_microcode(struct radeon_device *rdev); 2960 2961 /* radeon_acpi.c */ 2962 extern int radeon_acpi_init(struct radeon_device *rdev); 2963 extern void radeon_acpi_fini(struct radeon_device *rdev); 2964 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2965 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2966 u8 perf_req, bool advertise); 2967 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2968 2969 /* Prototypes added by @dumbbell. */ 2970 2971 /* atombios_encoders.c */ 2972 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 2973 struct drm_connector *drm_connector); 2974 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 2975 uint32_t supported_device, u16 caps); 2976 2977 /* radeon_atombios.c */ 2978 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2979 struct drm_display_mode *mode); 2980 2981 /* radeon_legacy_encoders.c */ 2982 void radeon_add_legacy_encoder(struct drm_device *dev, 2983 uint32_t encoder_enum, uint32_t supported_device); 2984 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2985 struct drm_connector *drm_connector); 2986 2987 /* radeon_pm.c */ 2988 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2989 2990 /* radeon_ttm.c */ 2991 int radeon_ttm_init(struct radeon_device *rdev); 2992 void radeon_ttm_fini(struct radeon_device *rdev); 2993 2994 /* r600.c */ 2995 int r600_ih_ring_alloc(struct radeon_device *rdev); 2996 void r600_ih_ring_fini(struct radeon_device *rdev); 2997 2998 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2999 struct radeon_cs_packet *pkt, 3000 unsigned idx); 3001 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3002 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3003 struct radeon_cs_packet *pkt); 3004 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3005 struct radeon_cs_reloc **cs_reloc, 3006 int nomm); 3007 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3008 uint32_t *vline_start_end, 3009 uint32_t *vline_status); 3010 3011 #include "radeon_object.h" 3012 3013 #endif 3014