1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon.h 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #ifndef __RADEON_H__ 32 #define __RADEON_H__ 33 34 /* TODO: Here are things that needs to be done : 35 * - surface allocator & initializer : (bit like scratch reg) should 36 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 37 * related to surface 38 * - WB : write back stuff (do it bit like scratch reg things) 39 * - Vblank : look at Jesse's rework and what we should do 40 * - r600/r700: gart & cp 41 * - cs : clean cs ioctl use bitmap & things like that. 42 * - power management stuff 43 * - Barrier in gart code 44 * - Unmappabled vram ? 45 * - TESTING, TESTING, TESTING 46 */ 47 48 /* Initialization path: 49 * We expect that acceleration initialization might fail for various 50 * reasons even thought we work hard to make it works on most 51 * configurations. In order to still have a working userspace in such 52 * situation the init path must succeed up to the memory controller 53 * initialization point. Failure before this point are considered as 54 * fatal error. Here is the init callchain : 55 * radeon_device_init perform common structure, mutex initialization 56 * asic_init setup the GPU memory layout and perform all 57 * one time initialization (failure in this 58 * function are considered fatal) 59 * asic_startup setup the GPU acceleration, in order to 60 * follow guideline the first thing this 61 * function should do is setting the GPU 62 * memory controller (only MC setup failure 63 * are considered as fatal) 64 */ 65 66 #include <sys/condvar.h> 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/linker.h> 70 #include <linux/firmware.h> 71 #include <linux/seq_file.h> 72 73 #include <contrib/dev/acpica/source/include/acpi.h> 74 #include <dev/acpica/acpivar.h> 75 76 #include <drm/ttm/ttm_bo_api.h> 77 #include <drm/ttm/ttm_bo_driver.h> 78 #include <drm/ttm/ttm_placement.h> 79 #include <drm/ttm/ttm_module.h> 80 #include <drm/ttm/ttm_execbuf_util.h> 81 82 #include <drm/drm_gem.h> 83 #define CONFIG_ACPI 1 84 85 #include "radeon_family.h" 86 #include "radeon_mode.h" 87 #include "radeon_reg.h" 88 89 /* 90 * Modules parameters. 91 */ 92 extern int radeon_no_wb; 93 extern int radeon_modeset; 94 extern int radeon_dynclks; 95 extern int radeon_r4xx_atom; 96 extern int radeon_agpmode; 97 extern int radeon_vram_limit; 98 extern int radeon_gart_size; 99 extern int radeon_benchmarking; 100 extern int radeon_testing; 101 extern int radeon_connector_table; 102 extern int radeon_tv; 103 extern int radeon_audio; 104 extern int radeon_disp_priority; 105 extern int radeon_hw_i2c; 106 extern int radeon_pcie_gen2; 107 extern int radeon_msi; 108 extern int radeon_lockup_timeout; 109 extern int radeon_fastfb; 110 extern int radeon_dpm; 111 extern int radeon_aspm; 112 extern int radeon_runtime_pm; 113 extern int radeon_hard_reset; 114 extern int radeon_vm_size; 115 extern int radeon_vm_block_size; 116 extern int radeon_deep_color; 117 extern int radeon_use_pflipirq; 118 extern int radeon_bapm; 119 extern int radeon_backlight; 120 121 /* 122 * Copy from radeon_drv.h so we don't have to include both and have conflicting 123 * symbol; 124 */ 125 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 126 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 127 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 128 #define RADEON_IB_POOL_SIZE 16 129 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 130 #define RADEONFB_CONN_LIMIT 4 131 #define RADEON_BIOS_NUM_SCRATCH 8 132 133 /* fence seq are set to this number when signaled */ 134 #define RADEON_FENCE_SIGNALED_SEQ 0LL 135 136 /* internal ring indices */ 137 /* r1xx+ has gfx CP ring */ 138 #define RADEON_RING_TYPE_GFX_INDEX 0 139 140 /* cayman has 2 compute CP rings */ 141 #define CAYMAN_RING_TYPE_CP1_INDEX 1 142 #define CAYMAN_RING_TYPE_CP2_INDEX 2 143 144 /* R600+ has an async dma ring */ 145 #define R600_RING_TYPE_DMA_INDEX 3 146 /* cayman add a second async dma ring */ 147 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 148 149 /* R600+ */ 150 #define R600_RING_TYPE_UVD_INDEX 5 151 152 /* TN+ */ 153 #define TN_RING_TYPE_VCE1_INDEX 6 154 #define TN_RING_TYPE_VCE2_INDEX 7 155 156 /* max number of rings */ 157 #define RADEON_NUM_RINGS 8 158 159 /* number of hw syncs before falling back on blocking */ 160 #define RADEON_NUM_SYNCS 4 161 162 /* hardcode those limit for now */ 163 #define RADEON_VA_IB_OFFSET (1 << 20) 164 #define RADEON_VA_RESERVED_SIZE (8 << 20) 165 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 166 167 /* hard reset data */ 168 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 169 170 /* reset flags */ 171 #define RADEON_RESET_GFX (1 << 0) 172 #define RADEON_RESET_COMPUTE (1 << 1) 173 #define RADEON_RESET_DMA (1 << 2) 174 #define RADEON_RESET_CP (1 << 3) 175 #define RADEON_RESET_GRBM (1 << 4) 176 #define RADEON_RESET_DMA1 (1 << 5) 177 #define RADEON_RESET_RLC (1 << 6) 178 #define RADEON_RESET_SEM (1 << 7) 179 #define RADEON_RESET_IH (1 << 8) 180 #define RADEON_RESET_VMC (1 << 9) 181 #define RADEON_RESET_MC (1 << 10) 182 #define RADEON_RESET_DISPLAY (1 << 11) 183 184 /* CG block flags */ 185 #define RADEON_CG_BLOCK_GFX (1 << 0) 186 #define RADEON_CG_BLOCK_MC (1 << 1) 187 #define RADEON_CG_BLOCK_SDMA (1 << 2) 188 #define RADEON_CG_BLOCK_UVD (1 << 3) 189 #define RADEON_CG_BLOCK_VCE (1 << 4) 190 #define RADEON_CG_BLOCK_HDP (1 << 5) 191 #define RADEON_CG_BLOCK_BIF (1 << 6) 192 193 /* CG flags */ 194 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 195 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 196 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 197 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 198 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 199 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 200 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 201 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 202 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 203 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 204 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 205 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 206 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 207 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 208 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 209 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 210 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 211 212 /* PG flags */ 213 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 214 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 215 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 216 #define RADEON_PG_SUPPORT_UVD (1 << 3) 217 #define RADEON_PG_SUPPORT_VCE (1 << 4) 218 #define RADEON_PG_SUPPORT_CP (1 << 5) 219 #define RADEON_PG_SUPPORT_GDS (1 << 6) 220 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 221 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 222 #define RADEON_PG_SUPPORT_ACP (1 << 9) 223 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 224 225 /* max cursor sizes (in pixels) */ 226 #define CURSOR_WIDTH 64 227 #define CURSOR_HEIGHT 64 228 229 #define CIK_CURSOR_WIDTH 128 230 #define CIK_CURSOR_HEIGHT 128 231 232 /* 233 * Errata workarounds. 234 */ 235 enum radeon_pll_errata { 236 CHIP_ERRATA_R300_CG = 0x00000001, 237 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 238 CHIP_ERRATA_PLL_DELAY = 0x00000004 239 }; 240 241 242 struct radeon_device; 243 244 245 /* 246 * BIOS. 247 */ 248 bool radeon_get_bios(struct radeon_device *rdev); 249 250 /* 251 * Dummy page 252 */ 253 struct radeon_dummy_page { 254 drm_dma_handle_t *dmah; 255 dma_addr_t addr; 256 }; 257 int radeon_dummy_page_init(struct radeon_device *rdev); 258 void radeon_dummy_page_fini(struct radeon_device *rdev); 259 260 261 /* 262 * Clocks 263 */ 264 struct radeon_clock { 265 struct radeon_pll p1pll; 266 struct radeon_pll p2pll; 267 struct radeon_pll dcpll; 268 struct radeon_pll spll; 269 struct radeon_pll mpll; 270 /* 10 Khz units */ 271 uint32_t default_mclk; 272 uint32_t default_sclk; 273 uint32_t default_dispclk; 274 uint32_t current_dispclk; 275 uint32_t dp_extclk; 276 uint32_t max_pixel_clock; 277 }; 278 279 /* 280 * Power management 281 */ 282 int radeon_pm_init(struct radeon_device *rdev); 283 int radeon_pm_late_init(struct radeon_device *rdev); 284 void radeon_pm_fini(struct radeon_device *rdev); 285 void radeon_pm_compute_clocks(struct radeon_device *rdev); 286 void radeon_pm_suspend(struct radeon_device *rdev); 287 void radeon_pm_resume(struct radeon_device *rdev); 288 void radeon_combios_get_power_modes(struct radeon_device *rdev); 289 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 290 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 291 u8 clock_type, 292 u32 clock, 293 bool strobe_mode, 294 struct atom_clock_dividers *dividers); 295 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 296 u32 clock, 297 bool strobe_mode, 298 struct atom_mpll_param *mpll_param); 299 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 300 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 301 u16 voltage_level, u8 voltage_type, 302 u32 *gpio_value, u32 *gpio_mask); 303 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 304 u32 eng_clock, u32 mem_clock); 305 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 306 u8 voltage_type, u16 *voltage_step); 307 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 308 u16 voltage_id, u16 *voltage); 309 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 310 u16 *voltage, 311 u16 leakage_idx); 312 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 313 u16 *leakage_id); 314 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 315 u16 *vddc, u16 *vddci, 316 u16 virtual_voltage_id, 317 u16 vbios_voltage_id); 318 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 319 u16 virtual_voltage_id, 320 u16 *voltage); 321 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 322 u8 voltage_type, 323 u16 nominal_voltage, 324 u16 *true_voltage); 325 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 326 u8 voltage_type, u16 *min_voltage); 327 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 328 u8 voltage_type, u16 *max_voltage); 329 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 330 u8 voltage_type, u8 voltage_mode, 331 struct atom_voltage_table *voltage_table); 332 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 333 u8 voltage_type, u8 voltage_mode); 334 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 335 u8 voltage_type, 336 u8 *svd_gpio_id, u8 *svc_gpio_id); 337 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 338 u32 mem_clock); 339 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 340 u32 mem_clock); 341 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 342 u8 module_index, 343 struct atom_mc_reg_table *reg_table); 344 int radeon_atom_get_memory_info(struct radeon_device *rdev, 345 u8 module_index, struct atom_memory_info *mem_info); 346 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 347 bool gddr5, u8 module_index, 348 struct atom_memory_clock_range_table *mclk_range_table); 349 void rs690_pm_info(struct radeon_device *rdev); 350 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 351 unsigned *bankh, unsigned *mtaspect, 352 unsigned *tile_split); 353 354 /* 355 * Fences. 356 */ 357 struct radeon_fence_driver { 358 uint32_t scratch_reg; 359 uint64_t gpu_addr; 360 volatile uint32_t *cpu_addr; 361 /* sync_seq is protected by ring emission lock */ 362 uint64_t sync_seq[RADEON_NUM_RINGS]; 363 atomic64_t last_seq; 364 bool initialized; 365 }; 366 367 struct radeon_fence { 368 struct radeon_device *rdev; 369 unsigned int kref; 370 /* protected by radeon_fence.lock */ 371 uint64_t seq; 372 /* RB, DMA, etc. */ 373 unsigned ring; 374 }; 375 376 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 377 int radeon_fence_driver_init(struct radeon_device *rdev); 378 void radeon_fence_driver_fini(struct radeon_device *rdev); 379 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 380 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 381 void radeon_fence_process(struct radeon_device *rdev, int ring); 382 bool radeon_fence_signaled(struct radeon_fence *fence); 383 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 384 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 385 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 386 int radeon_fence_wait_any(struct radeon_device *rdev, 387 struct radeon_fence **fences, 388 bool intr); 389 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 390 void radeon_fence_unref(struct radeon_fence **fence); 391 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 392 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 393 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 394 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 395 struct radeon_fence *b) 396 { 397 if (!a) { 398 return b; 399 } 400 401 if (!b) { 402 return a; 403 } 404 405 BUG_ON(a->ring != b->ring); 406 407 if (a->seq > b->seq) { 408 return a; 409 } else { 410 return b; 411 } 412 } 413 414 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 415 struct radeon_fence *b) 416 { 417 if (!a) { 418 return false; 419 } 420 421 if (!b) { 422 return true; 423 } 424 425 BUG_ON(a->ring != b->ring); 426 427 return a->seq < b->seq; 428 } 429 430 /* 431 * Tiling registers 432 */ 433 struct radeon_surface_reg { 434 struct radeon_bo *bo; 435 }; 436 437 #define RADEON_GEM_MAX_SURFACES 8 438 439 /* 440 * TTM. 441 */ 442 struct radeon_mman { 443 struct ttm_bo_global_ref bo_global_ref; 444 struct drm_global_reference mem_global_ref; 445 struct ttm_bo_device bdev; 446 bool mem_global_referenced; 447 bool initialized; 448 449 #if defined(CONFIG_DEBUG_FS) 450 struct dentry *vram; 451 struct dentry *gtt; 452 #endif 453 }; 454 455 /* bo virtual address in a specific vm */ 456 struct radeon_bo_va { 457 /* protected by bo being reserved */ 458 struct list_head bo_list; 459 uint64_t soffset; 460 uint64_t eoffset; 461 uint32_t flags; 462 uint64_t addr; 463 unsigned ref_count; 464 465 /* protected by vm mutex */ 466 struct list_head vm_list; 467 struct list_head vm_status; 468 469 /* constant after initialization */ 470 struct radeon_vm *vm; 471 struct radeon_bo *bo; 472 }; 473 474 struct radeon_bo { 475 /* Protected by gem.mutex */ 476 struct list_head list; 477 /* Protected by tbo.reserved */ 478 u32 initial_domain; 479 u32 placements[3]; 480 struct ttm_placement placement; 481 struct ttm_buffer_object tbo; 482 struct ttm_bo_kmap_obj kmap; 483 u32 flags; 484 unsigned pin_count; 485 void *kptr; 486 u32 tiling_flags; 487 u32 pitch; 488 int surface_reg; 489 /* list of all virtual address to which this bo 490 * is associated to 491 */ 492 struct list_head va; 493 /* Constant after initialization */ 494 struct radeon_device *rdev; 495 struct drm_gem_object gem_base; 496 497 struct ttm_bo_kmap_obj dma_buf_vmap; 498 pid_t pid; 499 }; 500 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 501 502 int radeon_gem_debugfs_init(struct radeon_device *rdev); 503 504 /* sub-allocation manager, it has to be protected by another lock. 505 * By conception this is an helper for other part of the driver 506 * like the indirect buffer or semaphore, which both have their 507 * locking. 508 * 509 * Principe is simple, we keep a list of sub allocation in offset 510 * order (first entry has offset == 0, last entry has the highest 511 * offset). 512 * 513 * When allocating new object we first check if there is room at 514 * the end total_size - (last_object_offset + last_object_size) >= 515 * alloc_size. If so we allocate new object there. 516 * 517 * When there is not enough room at the end, we start waiting for 518 * each sub object until we reach object_offset+object_size >= 519 * alloc_size, this object then become the sub object we return. 520 * 521 * Alignment can't be bigger than page size. 522 * 523 * Hole are not considered for allocation to keep things simple. 524 * Assumption is that there won't be hole (all object on same 525 * alignment). 526 */ 527 struct radeon_sa_manager { 528 struct cv wq; 529 struct lock wq_lock; 530 struct radeon_bo *bo; 531 struct list_head *hole; 532 struct list_head flist[RADEON_NUM_RINGS]; 533 struct list_head olist; 534 unsigned size; 535 uint64_t gpu_addr; 536 void *cpu_ptr; 537 uint32_t domain; 538 uint32_t align; 539 }; 540 541 struct radeon_sa_bo; 542 543 /* sub-allocation buffer */ 544 struct radeon_sa_bo { 545 struct list_head olist; 546 struct list_head flist; 547 struct radeon_sa_manager *manager; 548 unsigned soffset; 549 unsigned eoffset; 550 struct radeon_fence *fence; 551 }; 552 553 /* 554 * GEM objects. 555 */ 556 struct radeon_gem { 557 struct spinlock mutex; 558 struct list_head objects; 559 }; 560 561 int radeon_gem_init(struct radeon_device *rdev); 562 void radeon_gem_fini(struct radeon_device *rdev); 563 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 564 int alignment, int initial_domain, 565 u32 flags, bool kernel, 566 struct drm_gem_object **obj); 567 568 int radeon_mode_dumb_create(struct drm_file *file_priv, 569 struct drm_device *dev, 570 struct drm_mode_create_dumb *args); 571 int radeon_mode_dumb_mmap(struct drm_file *filp, 572 struct drm_device *dev, 573 uint32_t handle, uint64_t *offset_p); 574 575 /* 576 * Semaphores. 577 */ 578 struct radeon_semaphore { 579 struct radeon_sa_bo *sa_bo; 580 signed waiters; 581 uint64_t gpu_addr; 582 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 583 }; 584 585 int radeon_semaphore_create(struct radeon_device *rdev, 586 struct radeon_semaphore **semaphore); 587 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 588 struct radeon_semaphore *semaphore); 589 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 590 struct radeon_semaphore *semaphore); 591 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, 592 struct radeon_fence *fence); 593 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 594 struct radeon_semaphore *semaphore, 595 int waiting_ring); 596 void radeon_semaphore_free(struct radeon_device *rdev, 597 struct radeon_semaphore **semaphore, 598 struct radeon_fence *fence); 599 600 /* 601 * GART structures, functions & helpers 602 */ 603 struct radeon_mc; 604 605 #define RADEON_GPU_PAGE_SIZE 4096 606 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 607 #define RADEON_GPU_PAGE_SHIFT 12 608 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 609 610 #define RADEON_GART_PAGE_DUMMY 0 611 #define RADEON_GART_PAGE_VALID (1 << 0) 612 #define RADEON_GART_PAGE_READ (1 << 1) 613 #define RADEON_GART_PAGE_WRITE (1 << 2) 614 #define RADEON_GART_PAGE_SNOOP (1 << 3) 615 616 struct radeon_gart { 617 drm_dma_handle_t *dmah; 618 dma_addr_t table_addr; 619 struct radeon_bo *robj; 620 void *ptr; 621 unsigned num_gpu_pages; 622 unsigned num_cpu_pages; 623 unsigned table_size; 624 vm_page_t *pages; 625 dma_addr_t *pages_addr; 626 bool ready; 627 }; 628 629 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 630 void radeon_gart_table_ram_free(struct radeon_device *rdev); 631 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 632 void radeon_gart_table_vram_free(struct radeon_device *rdev); 633 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 634 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 635 int radeon_gart_init(struct radeon_device *rdev); 636 void radeon_gart_fini(struct radeon_device *rdev); 637 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 638 int pages); 639 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 640 int pages, vm_page_t *pagelist, 641 dma_addr_t *dma_addr, uint32_t flags); 642 643 644 /* 645 * GPU MC structures, functions & helpers 646 */ 647 struct radeon_mc { 648 resource_size_t aper_size; 649 resource_size_t aper_base; 650 resource_size_t agp_base; 651 /* for some chips with <= 32MB we need to lie 652 * about vram size near mc fb location */ 653 u64 mc_vram_size; 654 u64 visible_vram_size; 655 u64 gtt_size; 656 u64 gtt_start; 657 u64 gtt_end; 658 u64 vram_start; 659 u64 vram_end; 660 unsigned vram_width; 661 u64 real_vram_size; 662 int vram_mtrr; 663 bool vram_is_ddr; 664 bool igp_sideport_enabled; 665 u64 gtt_base_align; 666 u64 mc_mask; 667 }; 668 669 bool radeon_combios_sideport_present(struct radeon_device *rdev); 670 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 671 672 /* 673 * GPU scratch registers structures, functions & helpers 674 */ 675 struct radeon_scratch { 676 unsigned num_reg; 677 uint32_t reg_base; 678 bool free[32]; 679 uint32_t reg[32]; 680 }; 681 682 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 683 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 684 685 /* 686 * GPU doorbell structures, functions & helpers 687 */ 688 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 689 690 struct radeon_doorbell { 691 /* doorbell mmio */ 692 resource_size_t base; 693 resource_size_t size; 694 u32 __iomem *ptr; 695 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 696 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 697 }; 698 699 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 700 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 701 702 /* 703 * IRQS. 704 */ 705 706 struct radeon_flip_work { 707 struct work_struct flip_work; 708 struct work_struct unpin_work; 709 struct radeon_device *rdev; 710 int crtc_id; 711 uint64_t base; 712 struct drm_pending_vblank_event *event; 713 struct radeon_bo *old_rbo; 714 struct radeon_fence *fence; 715 }; 716 717 struct r500_irq_stat_regs { 718 u32 disp_int; 719 u32 hdmi0_status; 720 }; 721 722 struct r600_irq_stat_regs { 723 u32 disp_int; 724 u32 disp_int_cont; 725 u32 disp_int_cont2; 726 u32 d1grph_int; 727 u32 d2grph_int; 728 u32 hdmi0_status; 729 u32 hdmi1_status; 730 }; 731 732 struct evergreen_irq_stat_regs { 733 u32 disp_int; 734 u32 disp_int_cont; 735 u32 disp_int_cont2; 736 u32 disp_int_cont3; 737 u32 disp_int_cont4; 738 u32 disp_int_cont5; 739 u32 d1grph_int; 740 u32 d2grph_int; 741 u32 d3grph_int; 742 u32 d4grph_int; 743 u32 d5grph_int; 744 u32 d6grph_int; 745 u32 afmt_status1; 746 u32 afmt_status2; 747 u32 afmt_status3; 748 u32 afmt_status4; 749 u32 afmt_status5; 750 u32 afmt_status6; 751 }; 752 753 struct cik_irq_stat_regs { 754 u32 disp_int; 755 u32 disp_int_cont; 756 u32 disp_int_cont2; 757 u32 disp_int_cont3; 758 u32 disp_int_cont4; 759 u32 disp_int_cont5; 760 u32 disp_int_cont6; 761 u32 d1grph_int; 762 u32 d2grph_int; 763 u32 d3grph_int; 764 u32 d4grph_int; 765 u32 d5grph_int; 766 u32 d6grph_int; 767 }; 768 769 union radeon_irq_stat_regs { 770 struct r500_irq_stat_regs r500; 771 struct r600_irq_stat_regs r600; 772 struct evergreen_irq_stat_regs evergreen; 773 struct cik_irq_stat_regs cik; 774 }; 775 776 struct radeon_irq { 777 bool installed; 778 struct lock lock; 779 atomic_t ring_int[RADEON_NUM_RINGS]; 780 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 781 atomic_t pflip[RADEON_MAX_CRTCS]; 782 wait_queue_head_t vblank_queue; 783 bool hpd[RADEON_MAX_HPD_PINS]; 784 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 785 union radeon_irq_stat_regs stat_regs; 786 bool dpm_thermal; 787 }; 788 789 int radeon_irq_kms_init(struct radeon_device *rdev); 790 void radeon_irq_kms_fini(struct radeon_device *rdev); 791 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 792 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 793 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 794 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 795 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 796 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 797 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 798 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 799 800 /* 801 * CP & rings. 802 */ 803 804 struct radeon_ib { 805 struct radeon_sa_bo *sa_bo; 806 uint32_t length_dw; 807 uint64_t gpu_addr; 808 uint32_t *ptr; 809 int ring; 810 struct radeon_fence *fence; 811 struct radeon_vm *vm; 812 bool is_const_ib; 813 struct radeon_semaphore *semaphore; 814 }; 815 816 struct radeon_ring { 817 struct radeon_bo *ring_obj; 818 volatile uint32_t *ring; 819 unsigned rptr_offs; 820 unsigned rptr_save_reg; 821 u64 next_rptr_gpu_addr; 822 volatile u32 *next_rptr_cpu_addr; 823 unsigned wptr; 824 unsigned wptr_old; 825 unsigned ring_size; 826 unsigned ring_free_dw; 827 int count_dw; 828 atomic_t last_rptr; 829 atomic64_t last_activity; 830 uint64_t gpu_addr; 831 uint32_t align_mask; 832 uint32_t ptr_mask; 833 bool ready; 834 u32 nop; 835 u32 idx; 836 u64 last_semaphore_signal_addr; 837 u64 last_semaphore_wait_addr; 838 /* for CIK queues */ 839 u32 me; 840 u32 pipe; 841 u32 queue; 842 struct radeon_bo *mqd_obj; 843 u32 doorbell_index; 844 unsigned wptr_offs; 845 }; 846 847 struct radeon_mec { 848 struct radeon_bo *hpd_eop_obj; 849 u64 hpd_eop_gpu_addr; 850 u32 num_pipe; 851 u32 num_mec; 852 u32 num_queue; 853 }; 854 855 /* 856 * VM 857 */ 858 859 /* maximum number of VMIDs */ 860 #define RADEON_NUM_VM 16 861 862 /* number of entries in page table */ 863 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 864 865 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 866 #define RADEON_VM_PTB_ALIGN_SIZE 32768 867 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 868 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 869 870 #define R600_PTE_VALID (1 << 0) 871 #define R600_PTE_SYSTEM (1 << 1) 872 #define R600_PTE_SNOOPED (1 << 2) 873 #define R600_PTE_READABLE (1 << 5) 874 #define R600_PTE_WRITEABLE (1 << 6) 875 876 /* PTE (Page Table Entry) fragment field for different page sizes */ 877 #define R600_PTE_FRAG_4KB (0 << 7) 878 #define R600_PTE_FRAG_64KB (4 << 7) 879 #define R600_PTE_FRAG_256KB (6 << 7) 880 881 /* flags needed to be set so we can copy directly from the GART table */ 882 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 883 R600_PTE_SYSTEM | R600_PTE_VALID ) 884 885 struct radeon_vm_pt { 886 struct radeon_bo *bo; 887 uint64_t addr; 888 }; 889 890 struct radeon_vm { 891 struct list_head va; 892 unsigned id; 893 894 /* BOs moved, but not yet updated in the PT */ 895 struct list_head invalidated; 896 897 /* BOs freed, but not yet updated in the PT */ 898 struct list_head freed; 899 900 /* contains the page directory */ 901 struct radeon_bo *page_directory; 902 uint64_t pd_gpu_addr; 903 unsigned max_pde_used; 904 905 /* array of page tables, one for each page directory entry */ 906 struct radeon_vm_pt *page_tables; 907 908 struct radeon_bo_va *ib_bo_va; 909 910 struct lock mutex; 911 /* last fence for cs using this vm */ 912 struct radeon_fence *fence; 913 /* last flush or NULL if we still need to flush */ 914 struct radeon_fence *last_flush; 915 /* last use of vmid */ 916 struct radeon_fence *last_id_use; 917 }; 918 919 struct radeon_vm_manager { 920 struct radeon_fence *active[RADEON_NUM_VM]; 921 uint32_t max_pfn; 922 /* number of VMIDs */ 923 unsigned nvm; 924 /* vram base address for page table entry */ 925 u64 vram_base_offset; 926 /* is vm enabled? */ 927 bool enabled; 928 /* for hw to save the PD addr on suspend/resume */ 929 uint32_t saved_table_addr[RADEON_NUM_VM]; 930 }; 931 932 /* 933 * file private structure 934 */ 935 struct radeon_fpriv { 936 struct radeon_vm vm; 937 }; 938 939 /* 940 * R6xx+ IH ring 941 */ 942 struct r600_ih { 943 struct radeon_bo *ring_obj; 944 volatile uint32_t *ring; 945 unsigned rptr; 946 unsigned ring_size; 947 uint64_t gpu_addr; 948 uint32_t ptr_mask; 949 atomic_t lock; 950 bool enabled; 951 }; 952 953 /* 954 * RLC stuff 955 */ 956 #include "clearstate_defs.h" 957 958 struct radeon_rlc { 959 /* for power gating */ 960 struct radeon_bo *save_restore_obj; 961 uint64_t save_restore_gpu_addr; 962 volatile uint32_t *sr_ptr; 963 const u32 *reg_list; 964 u32 reg_list_size; 965 /* for clear state */ 966 struct radeon_bo *clear_state_obj; 967 uint64_t clear_state_gpu_addr; 968 volatile uint32_t *cs_ptr; 969 const struct cs_section_def *cs_data; 970 u32 clear_state_size; 971 /* for cp tables */ 972 struct radeon_bo *cp_table_obj; 973 uint64_t cp_table_gpu_addr; 974 volatile uint32_t *cp_table_ptr; 975 u32 cp_table_size; 976 }; 977 978 int radeon_ib_get(struct radeon_device *rdev, int ring, 979 struct radeon_ib *ib, struct radeon_vm *vm, 980 unsigned size); 981 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 982 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 983 struct radeon_ib *const_ib, bool hdp_flush); 984 int radeon_ib_pool_init(struct radeon_device *rdev); 985 void radeon_ib_pool_fini(struct radeon_device *rdev); 986 int radeon_ib_ring_tests(struct radeon_device *rdev); 987 /* Ring access between begin & end cannot sleep */ 988 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 989 struct radeon_ring *ring); 990 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 991 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 992 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 993 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 994 bool hdp_flush); 995 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 996 bool hdp_flush); 997 void radeon_ring_undo(struct radeon_ring *ring); 998 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 999 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1000 void radeon_ring_lockup_update(struct radeon_device *rdev, 1001 struct radeon_ring *ring); 1002 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1003 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1004 uint32_t **data); 1005 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1006 unsigned size, uint32_t *data); 1007 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1008 unsigned rptr_offs, u32 nop); 1009 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1010 1011 1012 /* r600 async dma */ 1013 void r600_dma_stop(struct radeon_device *rdev); 1014 int r600_dma_resume(struct radeon_device *rdev); 1015 void r600_dma_fini(struct radeon_device *rdev); 1016 1017 void cayman_dma_stop(struct radeon_device *rdev); 1018 int cayman_dma_resume(struct radeon_device *rdev); 1019 void cayman_dma_fini(struct radeon_device *rdev); 1020 1021 /* 1022 * CS. 1023 */ 1024 struct radeon_cs_reloc { 1025 struct drm_gem_object *gobj; 1026 struct radeon_bo *robj; 1027 struct ttm_validate_buffer tv; 1028 uint64_t gpu_offset; 1029 unsigned prefered_domains; 1030 unsigned allowed_domains; 1031 uint32_t tiling_flags; 1032 uint32_t handle; 1033 }; 1034 1035 struct radeon_cs_chunk { 1036 uint32_t chunk_id; 1037 uint32_t length_dw; 1038 uint32_t *kdata; 1039 void __user *user_ptr; 1040 }; 1041 1042 struct radeon_cs_parser { 1043 device_t dev; 1044 struct radeon_device *rdev; 1045 struct drm_file *filp; 1046 /* chunks */ 1047 unsigned nchunks; 1048 struct radeon_cs_chunk *chunks; 1049 uint64_t *chunks_array; 1050 /* IB */ 1051 unsigned idx; 1052 /* relocations */ 1053 unsigned nrelocs; 1054 struct radeon_cs_reloc *relocs; 1055 struct radeon_cs_reloc **relocs_ptr; 1056 struct radeon_cs_reloc *vm_bos; 1057 struct list_head validated; 1058 unsigned dma_reloc_idx; 1059 /* indices of various chunks */ 1060 int chunk_ib_idx; 1061 int chunk_relocs_idx; 1062 int chunk_flags_idx; 1063 int chunk_const_ib_idx; 1064 struct radeon_ib ib; 1065 struct radeon_ib const_ib; 1066 void *track; 1067 unsigned family; 1068 int parser_error; 1069 u32 cs_flags; 1070 u32 ring; 1071 s32 priority; 1072 struct ww_acquire_ctx ticket; 1073 }; 1074 1075 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1076 { 1077 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1078 1079 if (ibc->kdata) 1080 return ibc->kdata[idx]; 1081 return p->ib.ptr[idx]; 1082 } 1083 1084 1085 struct radeon_cs_packet { 1086 unsigned idx; 1087 unsigned type; 1088 unsigned reg; 1089 unsigned opcode; 1090 int count; 1091 unsigned one_reg_wr; 1092 }; 1093 1094 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1095 struct radeon_cs_packet *pkt, 1096 unsigned idx, unsigned reg); 1097 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1098 struct radeon_cs_packet *pkt); 1099 1100 1101 /* 1102 * AGP 1103 */ 1104 int radeon_agp_init(struct radeon_device *rdev); 1105 void radeon_agp_resume(struct radeon_device *rdev); 1106 void radeon_agp_suspend(struct radeon_device *rdev); 1107 void radeon_agp_fini(struct radeon_device *rdev); 1108 1109 1110 /* 1111 * Writeback 1112 */ 1113 struct radeon_wb { 1114 struct radeon_bo *wb_obj; 1115 volatile uint32_t *wb; 1116 uint64_t gpu_addr; 1117 bool enabled; 1118 bool use_event; 1119 }; 1120 1121 #define RADEON_WB_SCRATCH_OFFSET 0 1122 #define RADEON_WB_RING0_NEXT_RPTR 256 1123 #define RADEON_WB_CP_RPTR_OFFSET 1024 1124 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1125 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1126 #define R600_WB_DMA_RPTR_OFFSET 1792 1127 #define R600_WB_IH_WPTR_OFFSET 2048 1128 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1129 #define R600_WB_EVENT_OFFSET 3072 1130 #define CIK_WB_CP1_WPTR_OFFSET 3328 1131 #define CIK_WB_CP2_WPTR_OFFSET 3584 1132 1133 /** 1134 * struct radeon_pm - power management datas 1135 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1136 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1137 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1138 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1139 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1140 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1141 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1142 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1143 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1144 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1145 * @needed_bandwidth: current bandwidth needs 1146 * 1147 * It keeps track of various data needed to take powermanagement decision. 1148 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1149 * Equation between gpu/memory clock and available bandwidth is hw dependent 1150 * (type of memory, bus size, efficiency, ...) 1151 */ 1152 1153 enum radeon_pm_method { 1154 PM_METHOD_PROFILE, 1155 PM_METHOD_DYNPM, 1156 PM_METHOD_DPM, 1157 }; 1158 1159 enum radeon_dynpm_state { 1160 DYNPM_STATE_DISABLED, 1161 DYNPM_STATE_MINIMUM, 1162 DYNPM_STATE_PAUSED, 1163 DYNPM_STATE_ACTIVE, 1164 DYNPM_STATE_SUSPENDED, 1165 }; 1166 enum radeon_dynpm_action { 1167 DYNPM_ACTION_NONE, 1168 DYNPM_ACTION_MINIMUM, 1169 DYNPM_ACTION_DOWNCLOCK, 1170 DYNPM_ACTION_UPCLOCK, 1171 DYNPM_ACTION_DEFAULT 1172 }; 1173 1174 enum radeon_voltage_type { 1175 VOLTAGE_NONE = 0, 1176 VOLTAGE_GPIO, 1177 VOLTAGE_VDDC, 1178 VOLTAGE_SW 1179 }; 1180 1181 enum radeon_pm_state_type { 1182 /* not used for dpm */ 1183 POWER_STATE_TYPE_DEFAULT, 1184 POWER_STATE_TYPE_POWERSAVE, 1185 /* user selectable states */ 1186 POWER_STATE_TYPE_BATTERY, 1187 POWER_STATE_TYPE_BALANCED, 1188 POWER_STATE_TYPE_PERFORMANCE, 1189 /* internal states */ 1190 POWER_STATE_TYPE_INTERNAL_UVD, 1191 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1192 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1193 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1194 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1195 POWER_STATE_TYPE_INTERNAL_BOOT, 1196 POWER_STATE_TYPE_INTERNAL_THERMAL, 1197 POWER_STATE_TYPE_INTERNAL_ACPI, 1198 POWER_STATE_TYPE_INTERNAL_ULV, 1199 POWER_STATE_TYPE_INTERNAL_3DPERF, 1200 }; 1201 1202 enum radeon_pm_profile_type { 1203 PM_PROFILE_DEFAULT, 1204 PM_PROFILE_AUTO, 1205 PM_PROFILE_LOW, 1206 PM_PROFILE_MID, 1207 PM_PROFILE_HIGH, 1208 }; 1209 1210 #define PM_PROFILE_DEFAULT_IDX 0 1211 #define PM_PROFILE_LOW_SH_IDX 1 1212 #define PM_PROFILE_MID_SH_IDX 2 1213 #define PM_PROFILE_HIGH_SH_IDX 3 1214 #define PM_PROFILE_LOW_MH_IDX 4 1215 #define PM_PROFILE_MID_MH_IDX 5 1216 #define PM_PROFILE_HIGH_MH_IDX 6 1217 #define PM_PROFILE_MAX 7 1218 1219 struct radeon_pm_profile { 1220 int dpms_off_ps_idx; 1221 int dpms_on_ps_idx; 1222 int dpms_off_cm_idx; 1223 int dpms_on_cm_idx; 1224 }; 1225 1226 enum radeon_int_thermal_type { 1227 THERMAL_TYPE_NONE, 1228 THERMAL_TYPE_EXTERNAL, 1229 THERMAL_TYPE_EXTERNAL_GPIO, 1230 THERMAL_TYPE_RV6XX, 1231 THERMAL_TYPE_RV770, 1232 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1233 THERMAL_TYPE_EVERGREEN, 1234 THERMAL_TYPE_SUMO, 1235 THERMAL_TYPE_NI, 1236 THERMAL_TYPE_SI, 1237 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1238 THERMAL_TYPE_CI, 1239 THERMAL_TYPE_KV, 1240 }; 1241 1242 struct radeon_voltage { 1243 enum radeon_voltage_type type; 1244 /* gpio voltage */ 1245 struct radeon_gpio_rec gpio; 1246 u32 delay; /* delay in usec from voltage drop to sclk change */ 1247 bool active_high; /* voltage drop is active when bit is high */ 1248 /* VDDC voltage */ 1249 u8 vddc_id; /* index into vddc voltage table */ 1250 u8 vddci_id; /* index into vddci voltage table */ 1251 bool vddci_enabled; 1252 /* r6xx+ sw */ 1253 u16 voltage; 1254 /* evergreen+ vddci */ 1255 u16 vddci; 1256 }; 1257 1258 /* clock mode flags */ 1259 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1260 1261 struct radeon_pm_clock_info { 1262 /* memory clock */ 1263 u32 mclk; 1264 /* engine clock */ 1265 u32 sclk; 1266 /* voltage info */ 1267 struct radeon_voltage voltage; 1268 /* standardized clock flags */ 1269 u32 flags; 1270 }; 1271 1272 /* state flags */ 1273 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1274 1275 struct radeon_power_state { 1276 enum radeon_pm_state_type type; 1277 struct radeon_pm_clock_info *clock_info; 1278 /* number of valid clock modes in this power state */ 1279 int num_clock_modes; 1280 struct radeon_pm_clock_info *default_clock_mode; 1281 /* standardized state flags */ 1282 u32 flags; 1283 u32 misc; /* vbios specific flags */ 1284 u32 misc2; /* vbios specific flags */ 1285 int pcie_lanes; /* pcie lanes */ 1286 }; 1287 1288 /* 1289 * Some modes are overclocked by very low value, accept them 1290 */ 1291 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1292 1293 enum radeon_dpm_auto_throttle_src { 1294 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1295 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1296 }; 1297 1298 enum radeon_dpm_event_src { 1299 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1300 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1301 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1302 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1303 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1304 }; 1305 1306 #define RADEON_MAX_VCE_LEVELS 6 1307 1308 enum radeon_vce_level { 1309 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1310 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1311 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1312 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1313 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1314 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1315 }; 1316 1317 struct radeon_ps { 1318 u32 caps; /* vbios flags */ 1319 u32 class; /* vbios flags */ 1320 u32 class2; /* vbios flags */ 1321 /* UVD clocks */ 1322 u32 vclk; 1323 u32 dclk; 1324 /* VCE clocks */ 1325 u32 evclk; 1326 u32 ecclk; 1327 bool vce_active; 1328 enum radeon_vce_level vce_level; 1329 /* asic priv */ 1330 void *ps_priv; 1331 }; 1332 1333 struct radeon_dpm_thermal { 1334 /* thermal interrupt work */ 1335 struct task work; 1336 /* low temperature threshold */ 1337 int min_temp; 1338 /* high temperature threshold */ 1339 int max_temp; 1340 /* was interrupt low to high or high to low */ 1341 bool high_to_low; 1342 }; 1343 1344 enum radeon_clk_action 1345 { 1346 RADEON_SCLK_UP = 1, 1347 RADEON_SCLK_DOWN 1348 }; 1349 1350 struct radeon_blacklist_clocks 1351 { 1352 u32 sclk; 1353 u32 mclk; 1354 enum radeon_clk_action action; 1355 }; 1356 1357 struct radeon_clock_and_voltage_limits { 1358 u32 sclk; 1359 u32 mclk; 1360 u16 vddc; 1361 u16 vddci; 1362 }; 1363 1364 struct radeon_clock_array { 1365 u32 count; 1366 u32 *values; 1367 }; 1368 1369 struct radeon_clock_voltage_dependency_entry { 1370 u32 clk; 1371 u16 v; 1372 }; 1373 1374 struct radeon_clock_voltage_dependency_table { 1375 u32 count; 1376 struct radeon_clock_voltage_dependency_entry *entries; 1377 }; 1378 1379 union radeon_cac_leakage_entry { 1380 struct { 1381 u16 vddc; 1382 u32 leakage; 1383 }; 1384 struct { 1385 u16 vddc1; 1386 u16 vddc2; 1387 u16 vddc3; 1388 }; 1389 }; 1390 1391 struct radeon_cac_leakage_table { 1392 u32 count; 1393 union radeon_cac_leakage_entry *entries; 1394 }; 1395 1396 struct radeon_phase_shedding_limits_entry { 1397 u16 voltage; 1398 u32 sclk; 1399 u32 mclk; 1400 }; 1401 1402 struct radeon_phase_shedding_limits_table { 1403 u32 count; 1404 struct radeon_phase_shedding_limits_entry *entries; 1405 }; 1406 1407 struct radeon_uvd_clock_voltage_dependency_entry { 1408 u32 vclk; 1409 u32 dclk; 1410 u16 v; 1411 }; 1412 1413 struct radeon_uvd_clock_voltage_dependency_table { 1414 u8 count; 1415 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1416 }; 1417 1418 struct radeon_vce_clock_voltage_dependency_entry { 1419 u32 ecclk; 1420 u32 evclk; 1421 u16 v; 1422 }; 1423 1424 struct radeon_vce_clock_voltage_dependency_table { 1425 u8 count; 1426 struct radeon_vce_clock_voltage_dependency_entry *entries; 1427 }; 1428 1429 struct radeon_ppm_table { 1430 u8 ppm_design; 1431 u16 cpu_core_number; 1432 u32 platform_tdp; 1433 u32 small_ac_platform_tdp; 1434 u32 platform_tdc; 1435 u32 small_ac_platform_tdc; 1436 u32 apu_tdp; 1437 u32 dgpu_tdp; 1438 u32 dgpu_ulv_power; 1439 u32 tj_max; 1440 }; 1441 1442 struct radeon_cac_tdp_table { 1443 u16 tdp; 1444 u16 configurable_tdp; 1445 u16 tdc; 1446 u16 battery_power_limit; 1447 u16 small_power_limit; 1448 u16 low_cac_leakage; 1449 u16 high_cac_leakage; 1450 u16 maximum_power_delivery_limit; 1451 }; 1452 1453 struct radeon_dpm_dynamic_state { 1454 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1455 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1456 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1457 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1458 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1459 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1460 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1461 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1462 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1463 struct radeon_clock_array valid_sclk_values; 1464 struct radeon_clock_array valid_mclk_values; 1465 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1466 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1467 u32 mclk_sclk_ratio; 1468 u32 sclk_mclk_delta; 1469 u16 vddc_vddci_delta; 1470 u16 min_vddc_for_pcie_gen2; 1471 struct radeon_cac_leakage_table cac_leakage_table; 1472 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1473 struct radeon_ppm_table *ppm_table; 1474 struct radeon_cac_tdp_table *cac_tdp_table; 1475 }; 1476 1477 struct radeon_dpm_fan { 1478 u16 t_min; 1479 u16 t_med; 1480 u16 t_high; 1481 u16 pwm_min; 1482 u16 pwm_med; 1483 u16 pwm_high; 1484 u8 t_hyst; 1485 u32 cycle_delay; 1486 u16 t_max; 1487 bool ucode_fan_control; 1488 }; 1489 1490 enum radeon_pcie_gen { 1491 RADEON_PCIE_GEN1 = 0, 1492 RADEON_PCIE_GEN2 = 1, 1493 RADEON_PCIE_GEN3 = 2, 1494 RADEON_PCIE_GEN_INVALID = 0xffff 1495 }; 1496 1497 enum radeon_dpm_forced_level { 1498 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1499 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1500 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1501 }; 1502 1503 struct radeon_vce_state { 1504 /* vce clocks */ 1505 u32 evclk; 1506 u32 ecclk; 1507 /* gpu clocks */ 1508 u32 sclk; 1509 u32 mclk; 1510 u8 clk_idx; 1511 u8 pstate; 1512 }; 1513 1514 struct radeon_dpm { 1515 struct radeon_ps *ps; 1516 /* number of valid power states */ 1517 int num_ps; 1518 /* current power state that is active */ 1519 struct radeon_ps *current_ps; 1520 /* requested power state */ 1521 struct radeon_ps *requested_ps; 1522 /* boot up power state */ 1523 struct radeon_ps *boot_ps; 1524 /* default uvd power state */ 1525 struct radeon_ps *uvd_ps; 1526 /* vce requirements */ 1527 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1528 enum radeon_vce_level vce_level; 1529 enum radeon_pm_state_type state; 1530 enum radeon_pm_state_type user_state; 1531 u32 platform_caps; 1532 u32 voltage_response_time; 1533 u32 backbias_response_time; 1534 void *priv; 1535 u32 new_active_crtcs; 1536 int new_active_crtc_count; 1537 u32 current_active_crtcs; 1538 int current_active_crtc_count; 1539 struct radeon_dpm_dynamic_state dyn_state; 1540 struct radeon_dpm_fan fan; 1541 u32 tdp_limit; 1542 u32 near_tdp_limit; 1543 u32 near_tdp_limit_adjusted; 1544 u32 sq_ramping_threshold; 1545 u32 cac_leakage; 1546 u16 tdp_od_limit; 1547 u32 tdp_adjustment; 1548 u16 load_line_slope; 1549 bool power_control; 1550 bool ac_power; 1551 /* special states active */ 1552 bool thermal_active; 1553 bool uvd_active; 1554 bool vce_active; 1555 /* thermal handling */ 1556 struct radeon_dpm_thermal thermal; 1557 /* forced levels */ 1558 enum radeon_dpm_forced_level forced_level; 1559 /* track UVD streams */ 1560 unsigned sd; 1561 unsigned hd; 1562 }; 1563 1564 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1565 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1566 1567 struct radeon_pm { 1568 struct lock mutex; 1569 /* write locked while reprogramming mclk */ 1570 struct lock mclk_lock; 1571 u32 active_crtcs; 1572 int active_crtc_count; 1573 int req_vblank; 1574 bool vblank_sync; 1575 fixed20_12 max_bandwidth; 1576 fixed20_12 igp_sideport_mclk; 1577 fixed20_12 igp_system_mclk; 1578 fixed20_12 igp_ht_link_clk; 1579 fixed20_12 igp_ht_link_width; 1580 fixed20_12 k8_bandwidth; 1581 fixed20_12 sideport_bandwidth; 1582 fixed20_12 ht_bandwidth; 1583 fixed20_12 core_bandwidth; 1584 fixed20_12 sclk; 1585 fixed20_12 mclk; 1586 fixed20_12 needed_bandwidth; 1587 struct radeon_power_state *power_state; 1588 /* number of valid power states */ 1589 int num_power_states; 1590 int current_power_state_index; 1591 int current_clock_mode_index; 1592 int requested_power_state_index; 1593 int requested_clock_mode_index; 1594 int default_power_state_index; 1595 u32 current_sclk; 1596 u32 current_mclk; 1597 u16 current_vddc; 1598 u16 current_vddci; 1599 u32 default_sclk; 1600 u32 default_mclk; 1601 u16 default_vddc; 1602 u16 default_vddci; 1603 struct radeon_i2c_chan *i2c_bus; 1604 /* selected pm method */ 1605 enum radeon_pm_method pm_method; 1606 /* dynpm power management */ 1607 #ifdef DUMBBELL_WIP 1608 struct delayed_work dynpm_idle_work; 1609 #endif /* DUMBBELL_WIP */ 1610 enum radeon_dynpm_state dynpm_state; 1611 enum radeon_dynpm_action dynpm_planned_action; 1612 unsigned long dynpm_action_timeout; 1613 bool dynpm_can_upclock; 1614 bool dynpm_can_downclock; 1615 /* profile-based power management */ 1616 enum radeon_pm_profile_type profile; 1617 int profile_index; 1618 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1619 /* internal thermal controller on rv6xx+ */ 1620 enum radeon_int_thermal_type int_thermal_type; 1621 struct ksensor *int_sensor; 1622 struct ksensordev *int_sensordev; 1623 /* dpm */ 1624 bool dpm_enabled; 1625 struct radeon_dpm dpm; 1626 }; 1627 1628 int radeon_pm_get_type_index(struct radeon_device *rdev, 1629 enum radeon_pm_state_type ps_type, 1630 int instance); 1631 /* 1632 * UVD 1633 */ 1634 #define RADEON_MAX_UVD_HANDLES 10 1635 #define RADEON_UVD_STACK_SIZE (1024*1024) 1636 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1637 1638 struct radeon_uvd { 1639 struct radeon_bo *vcpu_bo; 1640 void *cpu_addr; 1641 uint64_t gpu_addr; 1642 void *saved_bo; 1643 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1644 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1645 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1646 struct delayed_work idle_work; 1647 }; 1648 1649 int radeon_uvd_init(struct radeon_device *rdev); 1650 void radeon_uvd_fini(struct radeon_device *rdev); 1651 int radeon_uvd_suspend(struct radeon_device *rdev); 1652 int radeon_uvd_resume(struct radeon_device *rdev); 1653 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1654 uint32_t handle, struct radeon_fence **fence); 1655 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1656 uint32_t handle, struct radeon_fence **fence); 1657 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); 1658 void radeon_uvd_free_handles(struct radeon_device *rdev, 1659 struct drm_file *filp); 1660 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1661 void radeon_uvd_note_usage(struct radeon_device *rdev); 1662 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1663 unsigned vclk, unsigned dclk, 1664 unsigned vco_min, unsigned vco_max, 1665 unsigned fb_factor, unsigned fb_mask, 1666 unsigned pd_min, unsigned pd_max, 1667 unsigned pd_even, 1668 unsigned *optimal_fb_div, 1669 unsigned *optimal_vclk_div, 1670 unsigned *optimal_dclk_div); 1671 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1672 unsigned cg_upll_func_cntl); 1673 1674 /* 1675 * VCE 1676 */ 1677 #define RADEON_MAX_VCE_HANDLES 16 1678 #define RADEON_VCE_STACK_SIZE (1024*1024) 1679 #define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1680 1681 struct radeon_vce { 1682 struct radeon_bo *vcpu_bo; 1683 uint64_t gpu_addr; 1684 unsigned fw_version; 1685 unsigned fb_version; 1686 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1687 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1688 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1689 struct delayed_work idle_work; 1690 }; 1691 1692 int radeon_vce_init(struct radeon_device *rdev); 1693 void radeon_vce_fini(struct radeon_device *rdev); 1694 int radeon_vce_suspend(struct radeon_device *rdev); 1695 int radeon_vce_resume(struct radeon_device *rdev); 1696 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1697 uint32_t handle, struct radeon_fence **fence); 1698 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1699 uint32_t handle, struct radeon_fence **fence); 1700 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1701 void radeon_vce_note_usage(struct radeon_device *rdev); 1702 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1703 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1704 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1705 struct radeon_ring *ring, 1706 struct radeon_semaphore *semaphore, 1707 bool emit_wait); 1708 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1709 void radeon_vce_fence_emit(struct radeon_device *rdev, 1710 struct radeon_fence *fence); 1711 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1712 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1713 1714 struct r600_audio_pin { 1715 int channels; 1716 int rate; 1717 int bits_per_sample; 1718 u8 status_bits; 1719 u8 category_code; 1720 u32 offset; 1721 bool connected; 1722 u32 id; 1723 }; 1724 1725 struct r600_audio { 1726 bool enabled; 1727 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1728 int num_pins; 1729 }; 1730 1731 /* 1732 * Benchmarking 1733 */ 1734 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1735 1736 1737 /* 1738 * Testing 1739 */ 1740 void radeon_test_moves(struct radeon_device *rdev); 1741 void radeon_test_ring_sync(struct radeon_device *rdev, 1742 struct radeon_ring *cpA, 1743 struct radeon_ring *cpB); 1744 void radeon_test_syncing(struct radeon_device *rdev); 1745 1746 1747 /* 1748 * Debugfs 1749 */ 1750 struct radeon_debugfs { 1751 struct drm_info_list *files; 1752 unsigned num_files; 1753 }; 1754 1755 int radeon_debugfs_add_files(struct radeon_device *rdev, 1756 struct drm_info_list *files, 1757 unsigned nfiles); 1758 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1759 1760 /* 1761 * ASIC ring specific functions. 1762 */ 1763 struct radeon_asic_ring { 1764 /* ring read/write ptr handling */ 1765 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1766 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1767 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1768 1769 /* validating and patching of IBs */ 1770 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1771 int (*cs_parse)(struct radeon_cs_parser *p); 1772 1773 /* command emmit functions */ 1774 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1775 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1776 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1777 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1778 struct radeon_semaphore *semaphore, bool emit_wait); 1779 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1780 1781 /* testing functions */ 1782 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1783 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1784 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1785 1786 /* deprecated */ 1787 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1788 }; 1789 1790 /* 1791 * ASIC specific functions. 1792 */ 1793 struct radeon_asic { 1794 int (*init)(struct radeon_device *rdev); 1795 void (*fini)(struct radeon_device *rdev); 1796 int (*resume)(struct radeon_device *rdev); 1797 int (*suspend)(struct radeon_device *rdev); 1798 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1799 int (*asic_reset)(struct radeon_device *rdev); 1800 /* Flush the HDP cache via MMIO */ 1801 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1802 /* check if 3D engine is idle */ 1803 bool (*gui_idle)(struct radeon_device *rdev); 1804 /* wait for mc_idle */ 1805 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1806 /* get the reference clock */ 1807 u32 (*get_xclk)(struct radeon_device *rdev); 1808 /* get the gpu clock counter */ 1809 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1810 /* gart */ 1811 struct { 1812 void (*tlb_flush)(struct radeon_device *rdev); 1813 void (*set_page)(struct radeon_device *rdev, unsigned i, 1814 uint64_t addr, uint32_t flags); 1815 } gart; 1816 struct { 1817 int (*init)(struct radeon_device *rdev); 1818 void (*fini)(struct radeon_device *rdev); 1819 void (*copy_pages)(struct radeon_device *rdev, 1820 struct radeon_ib *ib, 1821 uint64_t pe, uint64_t src, 1822 unsigned count); 1823 void (*write_pages)(struct radeon_device *rdev, 1824 struct radeon_ib *ib, 1825 uint64_t pe, 1826 uint64_t addr, unsigned count, 1827 uint32_t incr, uint32_t flags); 1828 void (*set_pages)(struct radeon_device *rdev, 1829 struct radeon_ib *ib, 1830 uint64_t pe, 1831 uint64_t addr, unsigned count, 1832 uint32_t incr, uint32_t flags); 1833 void (*pad_ib)(struct radeon_ib *ib); 1834 } vm; 1835 /* ring specific callbacks */ 1836 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1837 /* irqs */ 1838 struct { 1839 int (*set)(struct radeon_device *rdev); 1840 irqreturn_t (*process)(struct radeon_device *rdev); 1841 } irq; 1842 /* displays */ 1843 struct { 1844 /* display watermarks */ 1845 void (*bandwidth_update)(struct radeon_device *rdev); 1846 /* get frame count */ 1847 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1848 /* wait for vblank */ 1849 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1850 /* set backlight level */ 1851 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1852 /* get backlight level */ 1853 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1854 /* audio callbacks */ 1855 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1856 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1857 } display; 1858 /* copy functions for bo handling */ 1859 struct { 1860 int (*blit)(struct radeon_device *rdev, 1861 uint64_t src_offset, 1862 uint64_t dst_offset, 1863 unsigned num_gpu_pages, 1864 struct radeon_fence **fence); 1865 u32 blit_ring_index; 1866 int (*dma)(struct radeon_device *rdev, 1867 uint64_t src_offset, 1868 uint64_t dst_offset, 1869 unsigned num_gpu_pages, 1870 struct radeon_fence **fence); 1871 u32 dma_ring_index; 1872 /* method used for bo copy */ 1873 int (*copy)(struct radeon_device *rdev, 1874 uint64_t src_offset, 1875 uint64_t dst_offset, 1876 unsigned num_gpu_pages, 1877 struct radeon_fence **fence); 1878 /* ring used for bo copies */ 1879 u32 copy_ring_index; 1880 } copy; 1881 /* surfaces */ 1882 struct { 1883 int (*set_reg)(struct radeon_device *rdev, int reg, 1884 uint32_t tiling_flags, uint32_t pitch, 1885 uint32_t offset, uint32_t obj_size); 1886 void (*clear_reg)(struct radeon_device *rdev, int reg); 1887 } surface; 1888 /* hotplug detect */ 1889 struct { 1890 void (*init)(struct radeon_device *rdev); 1891 void (*fini)(struct radeon_device *rdev); 1892 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1893 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1894 } hpd; 1895 /* static power management */ 1896 struct { 1897 void (*misc)(struct radeon_device *rdev); 1898 void (*prepare)(struct radeon_device *rdev); 1899 void (*finish)(struct radeon_device *rdev); 1900 void (*init_profile)(struct radeon_device *rdev); 1901 void (*get_dynpm_state)(struct radeon_device *rdev); 1902 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1903 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1904 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1905 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1906 int (*get_pcie_lanes)(struct radeon_device *rdev); 1907 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1908 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1909 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1910 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1911 int (*get_temperature)(struct radeon_device *rdev); 1912 } pm; 1913 /* dynamic power management */ 1914 struct { 1915 int (*init)(struct radeon_device *rdev); 1916 void (*setup_asic)(struct radeon_device *rdev); 1917 int (*enable)(struct radeon_device *rdev); 1918 int (*late_enable)(struct radeon_device *rdev); 1919 void (*disable)(struct radeon_device *rdev); 1920 int (*pre_set_power_state)(struct radeon_device *rdev); 1921 int (*set_power_state)(struct radeon_device *rdev); 1922 void (*post_set_power_state)(struct radeon_device *rdev); 1923 void (*display_configuration_changed)(struct radeon_device *rdev); 1924 void (*fini)(struct radeon_device *rdev); 1925 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1926 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1927 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1928 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1929 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1930 bool (*vblank_too_short)(struct radeon_device *rdev); 1931 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1932 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1933 } dpm; 1934 /* pageflipping */ 1935 struct { 1936 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1937 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1938 } pflip; 1939 }; 1940 1941 /* 1942 * Asic structures 1943 */ 1944 struct r100_asic { 1945 const unsigned *reg_safe_bm; 1946 unsigned reg_safe_bm_size; 1947 u32 hdp_cntl; 1948 }; 1949 1950 struct r300_asic { 1951 const unsigned *reg_safe_bm; 1952 unsigned reg_safe_bm_size; 1953 u32 resync_scratch; 1954 u32 hdp_cntl; 1955 }; 1956 1957 struct r600_asic { 1958 unsigned max_pipes; 1959 unsigned max_tile_pipes; 1960 unsigned max_simds; 1961 unsigned max_backends; 1962 unsigned max_gprs; 1963 unsigned max_threads; 1964 unsigned max_stack_entries; 1965 unsigned max_hw_contexts; 1966 unsigned max_gs_threads; 1967 unsigned sx_max_export_size; 1968 unsigned sx_max_export_pos_size; 1969 unsigned sx_max_export_smx_size; 1970 unsigned sq_num_cf_insts; 1971 unsigned tiling_nbanks; 1972 unsigned tiling_npipes; 1973 unsigned tiling_group_size; 1974 unsigned tile_config; 1975 unsigned backend_map; 1976 unsigned active_simds; 1977 }; 1978 1979 struct rv770_asic { 1980 unsigned max_pipes; 1981 unsigned max_tile_pipes; 1982 unsigned max_simds; 1983 unsigned max_backends; 1984 unsigned max_gprs; 1985 unsigned max_threads; 1986 unsigned max_stack_entries; 1987 unsigned max_hw_contexts; 1988 unsigned max_gs_threads; 1989 unsigned sx_max_export_size; 1990 unsigned sx_max_export_pos_size; 1991 unsigned sx_max_export_smx_size; 1992 unsigned sq_num_cf_insts; 1993 unsigned sx_num_of_sets; 1994 unsigned sc_prim_fifo_size; 1995 unsigned sc_hiz_tile_fifo_size; 1996 unsigned sc_earlyz_tile_fifo_fize; 1997 unsigned tiling_nbanks; 1998 unsigned tiling_npipes; 1999 unsigned tiling_group_size; 2000 unsigned tile_config; 2001 unsigned backend_map; 2002 unsigned active_simds; 2003 }; 2004 2005 struct evergreen_asic { 2006 unsigned num_ses; 2007 unsigned max_pipes; 2008 unsigned max_tile_pipes; 2009 unsigned max_simds; 2010 unsigned max_backends; 2011 unsigned max_gprs; 2012 unsigned max_threads; 2013 unsigned max_stack_entries; 2014 unsigned max_hw_contexts; 2015 unsigned max_gs_threads; 2016 unsigned sx_max_export_size; 2017 unsigned sx_max_export_pos_size; 2018 unsigned sx_max_export_smx_size; 2019 unsigned sq_num_cf_insts; 2020 unsigned sx_num_of_sets; 2021 unsigned sc_prim_fifo_size; 2022 unsigned sc_hiz_tile_fifo_size; 2023 unsigned sc_earlyz_tile_fifo_size; 2024 unsigned tiling_nbanks; 2025 unsigned tiling_npipes; 2026 unsigned tiling_group_size; 2027 unsigned tile_config; 2028 unsigned backend_map; 2029 unsigned active_simds; 2030 }; 2031 2032 struct cayman_asic { 2033 unsigned max_shader_engines; 2034 unsigned max_pipes_per_simd; 2035 unsigned max_tile_pipes; 2036 unsigned max_simds_per_se; 2037 unsigned max_backends_per_se; 2038 unsigned max_texture_channel_caches; 2039 unsigned max_gprs; 2040 unsigned max_threads; 2041 unsigned max_gs_threads; 2042 unsigned max_stack_entries; 2043 unsigned sx_num_of_sets; 2044 unsigned sx_max_export_size; 2045 unsigned sx_max_export_pos_size; 2046 unsigned sx_max_export_smx_size; 2047 unsigned max_hw_contexts; 2048 unsigned sq_num_cf_insts; 2049 unsigned sc_prim_fifo_size; 2050 unsigned sc_hiz_tile_fifo_size; 2051 unsigned sc_earlyz_tile_fifo_size; 2052 2053 unsigned num_shader_engines; 2054 unsigned num_shader_pipes_per_simd; 2055 unsigned num_tile_pipes; 2056 unsigned num_simds_per_se; 2057 unsigned num_backends_per_se; 2058 unsigned backend_disable_mask_per_asic; 2059 unsigned backend_map; 2060 unsigned num_texture_channel_caches; 2061 unsigned mem_max_burst_length_bytes; 2062 unsigned mem_row_size_in_kb; 2063 unsigned shader_engine_tile_size; 2064 unsigned num_gpus; 2065 unsigned multi_gpu_tile_size; 2066 2067 unsigned tile_config; 2068 unsigned active_simds; 2069 }; 2070 2071 struct si_asic { 2072 unsigned max_shader_engines; 2073 unsigned max_tile_pipes; 2074 unsigned max_cu_per_sh; 2075 unsigned max_sh_per_se; 2076 unsigned max_backends_per_se; 2077 unsigned max_texture_channel_caches; 2078 unsigned max_gprs; 2079 unsigned max_gs_threads; 2080 unsigned max_hw_contexts; 2081 unsigned sc_prim_fifo_size_frontend; 2082 unsigned sc_prim_fifo_size_backend; 2083 unsigned sc_hiz_tile_fifo_size; 2084 unsigned sc_earlyz_tile_fifo_size; 2085 2086 unsigned num_tile_pipes; 2087 unsigned backend_enable_mask; 2088 unsigned backend_disable_mask_per_asic; 2089 unsigned backend_map; 2090 unsigned num_texture_channel_caches; 2091 unsigned mem_max_burst_length_bytes; 2092 unsigned mem_row_size_in_kb; 2093 unsigned shader_engine_tile_size; 2094 unsigned num_gpus; 2095 unsigned multi_gpu_tile_size; 2096 2097 unsigned tile_config; 2098 uint32_t tile_mode_array[32]; 2099 uint32_t active_cus; 2100 }; 2101 2102 struct cik_asic { 2103 unsigned max_shader_engines; 2104 unsigned max_tile_pipes; 2105 unsigned max_cu_per_sh; 2106 unsigned max_sh_per_se; 2107 unsigned max_backends_per_se; 2108 unsigned max_texture_channel_caches; 2109 unsigned max_gprs; 2110 unsigned max_gs_threads; 2111 unsigned max_hw_contexts; 2112 unsigned sc_prim_fifo_size_frontend; 2113 unsigned sc_prim_fifo_size_backend; 2114 unsigned sc_hiz_tile_fifo_size; 2115 unsigned sc_earlyz_tile_fifo_size; 2116 2117 unsigned num_tile_pipes; 2118 unsigned backend_enable_mask; 2119 unsigned backend_disable_mask_per_asic; 2120 unsigned backend_map; 2121 unsigned num_texture_channel_caches; 2122 unsigned mem_max_burst_length_bytes; 2123 unsigned mem_row_size_in_kb; 2124 unsigned shader_engine_tile_size; 2125 unsigned num_gpus; 2126 unsigned multi_gpu_tile_size; 2127 2128 unsigned tile_config; 2129 uint32_t tile_mode_array[32]; 2130 uint32_t macrotile_mode_array[16]; 2131 uint32_t active_cus; 2132 }; 2133 2134 union radeon_asic_config { 2135 struct r300_asic r300; 2136 struct r100_asic r100; 2137 struct r600_asic r600; 2138 struct rv770_asic rv770; 2139 struct evergreen_asic evergreen; 2140 struct cayman_asic cayman; 2141 struct si_asic si; 2142 struct cik_asic cik; 2143 }; 2144 2145 /* 2146 * asic initizalization from radeon_asic.c 2147 */ 2148 int radeon_asic_init(struct radeon_device *rdev); 2149 2150 2151 /* 2152 * IOCTL. 2153 */ 2154 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2155 struct drm_file *filp); 2156 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2157 struct drm_file *filp); 2158 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2159 struct drm_file *file_priv); 2160 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2161 struct drm_file *file_priv); 2162 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2163 struct drm_file *file_priv); 2164 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2165 struct drm_file *file_priv); 2166 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2167 struct drm_file *filp); 2168 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2169 struct drm_file *filp); 2170 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2171 struct drm_file *filp); 2172 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2173 struct drm_file *filp); 2174 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2175 struct drm_file *filp); 2176 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2177 struct drm_file *filp); 2178 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2179 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2180 struct drm_file *filp); 2181 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2182 struct drm_file *filp); 2183 2184 /* VRAM scratch page for HDP bug, default vram page */ 2185 struct r600_vram_scratch { 2186 struct radeon_bo *robj; 2187 volatile uint32_t *ptr; 2188 u64 gpu_addr; 2189 }; 2190 2191 /* 2192 * ACPI 2193 */ 2194 struct radeon_atif_notification_cfg { 2195 bool enabled; 2196 int command_code; 2197 }; 2198 2199 struct radeon_atif_notifications { 2200 bool display_switch; 2201 bool expansion_mode_change; 2202 bool thermal_state; 2203 bool forced_power_state; 2204 bool system_power_state; 2205 bool display_conf_change; 2206 bool px_gfx_switch; 2207 bool brightness_change; 2208 bool dgpu_display_event; 2209 }; 2210 2211 struct radeon_atif_functions { 2212 bool system_params; 2213 bool sbios_requests; 2214 bool select_active_disp; 2215 bool lid_state; 2216 bool get_tv_standard; 2217 bool set_tv_standard; 2218 bool get_panel_expansion_mode; 2219 bool set_panel_expansion_mode; 2220 bool temperature_change; 2221 bool graphics_device_types; 2222 }; 2223 2224 struct radeon_atif { 2225 struct radeon_atif_notifications notifications; 2226 struct radeon_atif_functions functions; 2227 struct radeon_atif_notification_cfg notification_cfg; 2228 struct radeon_encoder *encoder_for_bl; 2229 }; 2230 2231 struct radeon_atcs_functions { 2232 bool get_ext_state; 2233 bool pcie_perf_req; 2234 bool pcie_dev_rdy; 2235 bool pcie_bus_width; 2236 }; 2237 2238 struct radeon_atcs { 2239 struct radeon_atcs_functions functions; 2240 }; 2241 2242 /* 2243 * Core structure, functions and helpers. 2244 */ 2245 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2246 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2247 2248 struct radeon_device { 2249 device_t dev; 2250 struct drm_device *ddev; 2251 struct pci_dev *pdev; 2252 struct lock exclusive_lock; 2253 /* ASIC */ 2254 union radeon_asic_config config; 2255 enum radeon_family family; 2256 unsigned long flags; 2257 int usec_timeout; 2258 enum radeon_pll_errata pll_errata; 2259 int num_gb_pipes; 2260 int num_z_pipes; 2261 int disp_priority; 2262 /* BIOS */ 2263 uint8_t *bios; 2264 bool is_atom_bios; 2265 uint16_t bios_header_start; 2266 struct radeon_bo *stollen_vga_memory; 2267 /* Register mmio */ 2268 resource_size_t rmmio_base; 2269 resource_size_t rmmio_size; 2270 /* protects concurrent MM_INDEX/DATA based register access */ 2271 struct spinlock mmio_idx_lock; 2272 /* protects concurrent SMC based register access */ 2273 struct spinlock smc_idx_lock; 2274 /* protects concurrent PLL register access */ 2275 struct spinlock pll_idx_lock; 2276 /* protects concurrent MC register access */ 2277 struct spinlock mc_idx_lock; 2278 /* protects concurrent PCIE register access */ 2279 struct spinlock pcie_idx_lock; 2280 /* protects concurrent PCIE_PORT register access */ 2281 struct spinlock pciep_idx_lock; 2282 /* protects concurrent PIF register access */ 2283 struct spinlock pif_idx_lock; 2284 /* protects concurrent CG register access */ 2285 struct spinlock cg_idx_lock; 2286 /* protects concurrent UVD register access */ 2287 struct spinlock uvd_idx_lock; 2288 /* protects concurrent RCU register access */ 2289 struct spinlock rcu_idx_lock; 2290 /* protects concurrent DIDT register access */ 2291 struct spinlock didt_idx_lock; 2292 /* protects concurrent ENDPOINT (audio) register access */ 2293 struct spinlock end_idx_lock; 2294 int rmmio_rid; 2295 struct resource *rmmio; 2296 radeon_rreg_t mc_rreg; 2297 radeon_wreg_t mc_wreg; 2298 radeon_rreg_t pll_rreg; 2299 radeon_wreg_t pll_wreg; 2300 uint32_t pcie_reg_mask; 2301 radeon_rreg_t pciep_rreg; 2302 radeon_wreg_t pciep_wreg; 2303 /* io port */ 2304 int rio_rid; 2305 struct resource *rio_mem; 2306 resource_size_t rio_mem_size; 2307 struct radeon_clock clock; 2308 struct radeon_mc mc; 2309 struct radeon_gart gart; 2310 struct radeon_mode_info mode_info; 2311 struct radeon_scratch scratch; 2312 struct radeon_doorbell doorbell; 2313 struct radeon_mman mman; 2314 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2315 wait_queue_head_t fence_queue; 2316 struct lock ring_lock; 2317 struct radeon_ring ring[RADEON_NUM_RINGS]; 2318 bool ib_pool_ready; 2319 struct radeon_sa_manager ring_tmp_bo; 2320 struct radeon_irq irq; 2321 struct radeon_asic *asic; 2322 struct radeon_gem gem; 2323 struct radeon_pm pm; 2324 struct radeon_uvd uvd; 2325 struct radeon_vce vce; 2326 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2327 struct radeon_wb wb; 2328 struct radeon_dummy_page dummy_page; 2329 bool shutdown; 2330 bool suspend; 2331 bool need_dma32; 2332 bool accel_working; 2333 bool fastfb_working; /* IGP feature*/ 2334 bool needs_reset; 2335 bool fictitious_range_registered; 2336 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2337 const struct firmware *me_fw; /* all family ME firmware */ 2338 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2339 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2340 const struct firmware *mc_fw; /* NI MC firmware */ 2341 const struct firmware *ce_fw; /* SI CE firmware */ 2342 const struct firmware *mec_fw; /* CIK MEC firmware */ 2343 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2344 const struct firmware *smc_fw; /* SMC firmware */ 2345 const struct firmware *uvd_fw; /* UVD firmware */ 2346 const struct firmware *vce_fw; /* VCE firmware */ 2347 struct r600_vram_scratch vram_scratch; 2348 int msi_enabled; /* msi enabled */ 2349 struct r600_ih ih; /* r6/700 interrupt ring */ 2350 struct radeon_rlc rlc; 2351 struct radeon_mec mec; 2352 struct taskqueue *tq; 2353 struct task hotplug_work; 2354 struct task audio_work; 2355 struct task reset_work; 2356 int num_crtc; /* number of crtcs */ 2357 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2358 bool has_uvd; 2359 struct r600_audio audio; /* audio stuff */ 2360 struct { 2361 ACPI_HANDLE handle; 2362 ACPI_NOTIFY_HANDLER notifier_call; 2363 } acpi; 2364 /* only one userspace can use Hyperz features or CMASK at a time */ 2365 struct drm_file *hyperz_filp; 2366 struct drm_file *cmask_filp; 2367 /* i2c buses */ 2368 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2369 /* debugfs */ 2370 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2371 unsigned debugfs_count; 2372 /* virtual memory */ 2373 struct radeon_vm_manager vm_manager; 2374 struct spinlock gpu_clock_mutex; 2375 /* memory stats */ 2376 atomic64_t vram_usage; 2377 atomic64_t gtt_usage; 2378 atomic64_t num_bytes_moved; 2379 /* ACPI interface */ 2380 struct radeon_atif atif; 2381 struct radeon_atcs atcs; 2382 /* srbm instance registers */ 2383 struct spinlock srbm_mutex; 2384 /* clock, powergating flags */ 2385 u32 cg_flags; 2386 u32 pg_flags; 2387 2388 #ifdef PM_TODO 2389 struct dev_pm_domain vga_pm_domain; 2390 #endif 2391 bool have_disp_power_ref; 2392 u32 px_quirk_flags; 2393 2394 /* tracking pinned memory */ 2395 u64 vram_pin_size; 2396 u64 gart_pin_size; 2397 }; 2398 2399 bool radeon_is_px(struct drm_device *dev); 2400 int radeon_device_init(struct radeon_device *rdev, 2401 struct drm_device *ddev, 2402 struct pci_dev *pdev, 2403 uint32_t flags); 2404 void radeon_device_fini(struct radeon_device *rdev); 2405 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2406 2407 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2408 bool always_indirect); 2409 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2410 bool always_indirect); 2411 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2412 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2413 2414 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2415 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2416 2417 /* 2418 * Cast helper 2419 */ 2420 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2421 2422 /* 2423 * Registers read & write functions. 2424 */ 2425 #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 2426 #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 2427 #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 2428 #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 2429 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2430 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2431 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 2432 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2433 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2434 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2435 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2436 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2437 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2438 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2439 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2440 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2441 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2442 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2443 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2444 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2445 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2446 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2447 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2448 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2449 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2450 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2451 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2452 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2453 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2454 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2455 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2456 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2457 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2458 #define WREG32_P(reg, val, mask) \ 2459 do { \ 2460 uint32_t tmp_ = RREG32(reg); \ 2461 tmp_ &= (mask); \ 2462 tmp_ |= ((val) & ~(mask)); \ 2463 WREG32(reg, tmp_); \ 2464 } while (0) 2465 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2466 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2467 #define WREG32_PLL_P(reg, val, mask) \ 2468 do { \ 2469 uint32_t tmp_ = RREG32_PLL(reg); \ 2470 tmp_ &= (mask); \ 2471 tmp_ |= ((val) & ~(mask)); \ 2472 WREG32_PLL(reg, tmp_); \ 2473 } while (0) 2474 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2475 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2476 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2477 2478 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2479 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2480 2481 /* 2482 * Indirect registers accessor 2483 */ 2484 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2485 { 2486 uint32_t r; 2487 2488 spin_lock(&rdev->pcie_idx_lock); 2489 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2490 r = RREG32(RADEON_PCIE_DATA); 2491 spin_unlock(&rdev->pcie_idx_lock); 2492 return r; 2493 } 2494 2495 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2496 { 2497 spin_lock(&rdev->pcie_idx_lock); 2498 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2499 WREG32(RADEON_PCIE_DATA, (v)); 2500 spin_unlock(&rdev->pcie_idx_lock); 2501 } 2502 2503 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2504 { 2505 u32 r; 2506 2507 spin_lock(&rdev->smc_idx_lock); 2508 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2509 r = RREG32(TN_SMC_IND_DATA_0); 2510 spin_unlock(&rdev->smc_idx_lock); 2511 return r; 2512 } 2513 2514 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2515 { 2516 spin_lock(&rdev->smc_idx_lock); 2517 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2518 WREG32(TN_SMC_IND_DATA_0, (v)); 2519 spin_unlock(&rdev->smc_idx_lock); 2520 } 2521 2522 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2523 { 2524 u32 r; 2525 2526 spin_lock(&rdev->rcu_idx_lock); 2527 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2528 r = RREG32(R600_RCU_DATA); 2529 spin_unlock(&rdev->rcu_idx_lock); 2530 return r; 2531 } 2532 2533 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2534 { 2535 spin_lock(&rdev->rcu_idx_lock); 2536 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2537 WREG32(R600_RCU_DATA, (v)); 2538 spin_unlock(&rdev->rcu_idx_lock); 2539 } 2540 2541 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2542 { 2543 u32 r; 2544 2545 spin_lock(&rdev->cg_idx_lock); 2546 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2547 r = RREG32(EVERGREEN_CG_IND_DATA); 2548 spin_unlock(&rdev->cg_idx_lock); 2549 return r; 2550 } 2551 2552 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2553 { 2554 spin_lock(&rdev->cg_idx_lock); 2555 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2556 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2557 spin_unlock(&rdev->cg_idx_lock); 2558 } 2559 2560 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2561 { 2562 u32 r; 2563 2564 spin_lock(&rdev->pif_idx_lock); 2565 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2566 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2567 spin_unlock(&rdev->pif_idx_lock); 2568 return r; 2569 } 2570 2571 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2572 { 2573 spin_lock(&rdev->pif_idx_lock); 2574 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2575 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2576 spin_unlock(&rdev->pif_idx_lock); 2577 } 2578 2579 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2580 { 2581 u32 r; 2582 2583 spin_lock(&rdev->pif_idx_lock); 2584 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2585 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2586 spin_unlock(&rdev->pif_idx_lock); 2587 return r; 2588 } 2589 2590 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2591 { 2592 spin_lock(&rdev->pif_idx_lock); 2593 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2594 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2595 spin_unlock(&rdev->pif_idx_lock); 2596 } 2597 2598 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2599 { 2600 u32 r; 2601 2602 spin_lock(&rdev->uvd_idx_lock); 2603 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2604 r = RREG32(R600_UVD_CTX_DATA); 2605 spin_unlock(&rdev->uvd_idx_lock); 2606 return r; 2607 } 2608 2609 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2610 { 2611 spin_lock(&rdev->uvd_idx_lock); 2612 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2613 WREG32(R600_UVD_CTX_DATA, (v)); 2614 spin_unlock(&rdev->uvd_idx_lock); 2615 } 2616 2617 2618 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2619 { 2620 u32 r; 2621 2622 spin_lock(&rdev->didt_idx_lock); 2623 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2624 r = RREG32(CIK_DIDT_IND_DATA); 2625 spin_unlock(&rdev->didt_idx_lock); 2626 return r; 2627 } 2628 2629 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2630 { 2631 spin_lock(&rdev->didt_idx_lock); 2632 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2633 WREG32(CIK_DIDT_IND_DATA, (v)); 2634 spin_unlock(&rdev->didt_idx_lock); 2635 } 2636 2637 void r100_pll_errata_after_index(struct radeon_device *rdev); 2638 2639 2640 /* 2641 * ASICs helpers. 2642 */ 2643 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2644 (rdev->pdev->device == 0x5969)) 2645 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2646 (rdev->family == CHIP_RV200) || \ 2647 (rdev->family == CHIP_RS100) || \ 2648 (rdev->family == CHIP_RS200) || \ 2649 (rdev->family == CHIP_RV250) || \ 2650 (rdev->family == CHIP_RV280) || \ 2651 (rdev->family == CHIP_RS300)) 2652 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2653 (rdev->family == CHIP_RV350) || \ 2654 (rdev->family == CHIP_R350) || \ 2655 (rdev->family == CHIP_RV380) || \ 2656 (rdev->family == CHIP_R420) || \ 2657 (rdev->family == CHIP_R423) || \ 2658 (rdev->family == CHIP_RV410) || \ 2659 (rdev->family == CHIP_RS400) || \ 2660 (rdev->family == CHIP_RS480)) 2661 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2662 (rdev->ddev->pdev->device == 0x9443) || \ 2663 (rdev->ddev->pdev->device == 0x944B) || \ 2664 (rdev->ddev->pdev->device == 0x9506) || \ 2665 (rdev->ddev->pdev->device == 0x9509) || \ 2666 (rdev->ddev->pdev->device == 0x950F) || \ 2667 (rdev->ddev->pdev->device == 0x689C) || \ 2668 (rdev->ddev->pdev->device == 0x689D)) 2669 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2670 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2671 (rdev->family == CHIP_RS690) || \ 2672 (rdev->family == CHIP_RS740) || \ 2673 (rdev->family >= CHIP_R600)) 2674 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2675 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2676 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2677 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2678 (rdev->flags & RADEON_IS_IGP)) 2679 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2680 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2681 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2682 (rdev->flags & RADEON_IS_IGP)) 2683 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2684 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2685 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2686 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2687 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2688 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2689 (rdev->family == CHIP_MULLINS)) 2690 2691 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2692 (rdev->ddev->pdev->device == 0x6850) || \ 2693 (rdev->ddev->pdev->device == 0x6858) || \ 2694 (rdev->ddev->pdev->device == 0x6859) || \ 2695 (rdev->ddev->pdev->device == 0x6840) || \ 2696 (rdev->ddev->pdev->device == 0x6841) || \ 2697 (rdev->ddev->pdev->device == 0x6842) || \ 2698 (rdev->ddev->pdev->device == 0x6843)) 2699 2700 /* 2701 * BIOS helpers. 2702 */ 2703 #define RBIOS8(i) (rdev->bios[i]) 2704 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2705 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2706 2707 int radeon_combios_init(struct radeon_device *rdev); 2708 void radeon_combios_fini(struct radeon_device *rdev); 2709 int radeon_atombios_init(struct radeon_device *rdev); 2710 void radeon_atombios_fini(struct radeon_device *rdev); 2711 2712 2713 /* 2714 * RING helpers. 2715 */ 2716 #if !defined(DRM_DEBUG_CODE) || DRM_DEBUG_CODE == 0 2717 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2718 { 2719 ring->ring[ring->wptr++] = v; 2720 ring->wptr &= ring->ptr_mask; 2721 ring->count_dw--; 2722 ring->ring_free_dw--; 2723 } 2724 #else 2725 /* With debugging this is just too big to inline */ 2726 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 2727 #endif 2728 2729 /* 2730 * ASICs macro. 2731 */ 2732 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2733 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2734 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2735 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2736 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2737 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2738 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2739 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2740 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) 2741 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2742 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2743 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2744 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2745 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2746 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2747 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2748 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2749 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2750 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2751 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2752 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2753 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) 2754 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2755 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2756 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2757 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2758 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2759 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2760 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2761 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2762 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2763 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2764 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2765 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2766 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2767 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2768 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2769 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2770 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2771 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2772 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2773 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2774 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2775 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2776 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2777 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2778 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2779 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2780 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2781 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2782 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2783 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2784 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2785 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2786 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2787 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2788 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2789 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2790 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2791 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2792 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2793 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2794 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2795 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2796 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2797 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2798 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2799 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2800 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2801 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2802 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2803 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2804 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2805 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2806 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2807 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2808 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2809 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2810 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2811 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2812 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2813 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2814 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2815 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2816 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2817 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2818 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2819 2820 /* Common functions */ 2821 /* AGP */ 2822 extern int radeon_gpu_reset(struct radeon_device *rdev); 2823 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2824 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2825 extern void radeon_agp_disable(struct radeon_device *rdev); 2826 extern int radeon_modeset_init(struct radeon_device *rdev); 2827 extern void radeon_modeset_fini(struct radeon_device *rdev); 2828 extern bool radeon_card_posted(struct radeon_device *rdev); 2829 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2830 extern void radeon_update_display_priority(struct radeon_device *rdev); 2831 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2832 extern void radeon_scratch_init(struct radeon_device *rdev); 2833 extern void radeon_wb_fini(struct radeon_device *rdev); 2834 extern int radeon_wb_init(struct radeon_device *rdev); 2835 extern void radeon_wb_disable(struct radeon_device *rdev); 2836 extern void radeon_surface_init(struct radeon_device *rdev); 2837 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2838 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2839 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2840 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2841 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2842 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2843 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2844 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2845 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2846 const u32 *registers, 2847 const u32 array_size); 2848 2849 /* 2850 * vm 2851 */ 2852 int radeon_vm_manager_init(struct radeon_device *rdev); 2853 void radeon_vm_manager_fini(struct radeon_device *rdev); 2854 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2855 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2856 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2857 struct radeon_vm *vm, 2858 struct list_head *head); 2859 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2860 struct radeon_vm *vm, int ring); 2861 void radeon_vm_flush(struct radeon_device *rdev, 2862 struct radeon_vm *vm, 2863 int ring); 2864 void radeon_vm_fence(struct radeon_device *rdev, 2865 struct radeon_vm *vm, 2866 struct radeon_fence *fence); 2867 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2868 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2869 struct radeon_vm *vm); 2870 int radeon_vm_clear_freed(struct radeon_device *rdev, 2871 struct radeon_vm *vm); 2872 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2873 struct radeon_vm *vm); 2874 int radeon_vm_bo_update(struct radeon_device *rdev, 2875 struct radeon_bo_va *bo_va, 2876 struct ttm_mem_reg *mem); 2877 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2878 struct radeon_bo *bo); 2879 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2880 struct radeon_bo *bo); 2881 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2882 struct radeon_vm *vm, 2883 struct radeon_bo *bo); 2884 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2885 struct radeon_bo_va *bo_va, 2886 uint64_t offset, 2887 uint32_t flags); 2888 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2889 struct radeon_bo_va *bo_va); 2890 2891 /* audio */ 2892 void r600_audio_update_hdmi(void *arg, int pending); 2893 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2894 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2895 void r600_audio_enable(struct radeon_device *rdev, 2896 struct r600_audio_pin *pin, 2897 bool enable); 2898 void dce6_audio_enable(struct radeon_device *rdev, 2899 struct r600_audio_pin *pin, 2900 bool enable); 2901 2902 /* 2903 * R600 vram scratch functions 2904 */ 2905 int r600_vram_scratch_init(struct radeon_device *rdev); 2906 void r600_vram_scratch_fini(struct radeon_device *rdev); 2907 2908 /* 2909 * r600 cs checking helper 2910 */ 2911 unsigned r600_mip_minify(unsigned size, unsigned level); 2912 bool r600_fmt_is_valid_color(u32 format); 2913 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2914 int r600_fmt_get_blocksize(u32 format); 2915 int r600_fmt_get_nblocksx(u32 format, u32 w); 2916 int r600_fmt_get_nblocksy(u32 format, u32 h); 2917 2918 /* 2919 * r600 functions used by radeon_encoder.c 2920 */ 2921 struct radeon_hdmi_acr { 2922 u32 clock; 2923 2924 int n_32khz; 2925 int cts_32khz; 2926 2927 int n_44_1khz; 2928 int cts_44_1khz; 2929 2930 int n_48khz; 2931 int cts_48khz; 2932 2933 }; 2934 2935 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2936 2937 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2938 u32 tiling_pipe_num, 2939 u32 max_rb_num, 2940 u32 total_max_rb_num, 2941 u32 enabled_rb_mask); 2942 2943 /* 2944 * evergreen functions used by radeon_encoder.c 2945 */ 2946 2947 extern int ni_init_microcode(struct radeon_device *rdev); 2948 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2949 extern void ni_fini_microcode(struct radeon_device *rdev); 2950 2951 /* radeon_acpi.c */ 2952 extern int radeon_acpi_init(struct radeon_device *rdev); 2953 extern void radeon_acpi_fini(struct radeon_device *rdev); 2954 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2955 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2956 u8 perf_req, bool advertise); 2957 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2958 2959 /* Prototypes added by @dumbbell. */ 2960 2961 /* atombios_encoders.c */ 2962 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 2963 struct drm_connector *drm_connector); 2964 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 2965 uint32_t supported_device, u16 caps); 2966 2967 /* radeon_atombios.c */ 2968 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2969 struct drm_display_mode *mode); 2970 2971 /* radeon_legacy_encoders.c */ 2972 void radeon_add_legacy_encoder(struct drm_device *dev, 2973 uint32_t encoder_enum, uint32_t supported_device); 2974 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2975 struct drm_connector *drm_connector); 2976 2977 /* radeon_pm.c */ 2978 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2979 2980 /* radeon_ttm.c */ 2981 int radeon_ttm_init(struct radeon_device *rdev); 2982 void radeon_ttm_fini(struct radeon_device *rdev); 2983 2984 /* r600.c */ 2985 int r600_ih_ring_alloc(struct radeon_device *rdev); 2986 void r600_ih_ring_fini(struct radeon_device *rdev); 2987 2988 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2989 struct radeon_cs_packet *pkt, 2990 unsigned idx); 2991 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2992 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2993 struct radeon_cs_packet *pkt); 2994 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2995 struct radeon_cs_reloc **cs_reloc, 2996 int nomm); 2997 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2998 uint32_t *vline_start_end, 2999 uint32_t *vline_status); 3000 3001 #include "radeon_object.h" 3002 3003 #endif 3004