1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #ifndef __RADEON_H__ 30 #define __RADEON_H__ 31 32 /* TODO: Here are things that needs to be done : 33 * - surface allocator & initializer : (bit like scratch reg) should 34 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 35 * related to surface 36 * - WB : write back stuff (do it bit like scratch reg things) 37 * - Vblank : look at Jesse's rework and what we should do 38 * - r600/r700: gart & cp 39 * - cs : clean cs ioctl use bitmap & things like that. 40 * - power management stuff 41 * - Barrier in gart code 42 * - Unmappabled vram ? 43 * - TESTING, TESTING, TESTING 44 */ 45 46 /* Initialization path: 47 * We expect that acceleration initialization might fail for various 48 * reasons even thought we work hard to make it works on most 49 * configurations. In order to still have a working userspace in such 50 * situation the init path must succeed up to the memory controller 51 * initialization point. Failure before this point are considered as 52 * fatal error. Here is the init callchain : 53 * radeon_device_init perform common structure, mutex initialization 54 * asic_init setup the GPU memory layout and perform all 55 * one time initialization (failure in this 56 * function are considered fatal) 57 * asic_startup setup the GPU acceleration, in order to 58 * follow guideline the first thing this 59 * function should do is setting the GPU 60 * memory controller (only MC setup failure 61 * are considered as fatal) 62 */ 63 64 #include <sys/condvar.h> 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/linker.h> 68 #include <linux/firmware.h> 69 70 #include <contrib/dev/acpica/source/include/acpi.h> 71 #include <dev/acpica/acpivar.h> 72 73 #include <linux/atomic.h> 74 #include <linux/wait.h> 75 #include <linux/list.h> 76 #include <linux/kref.h> 77 #include <linux/interval_tree.h> 78 #include <linux/hashtable.h> 79 #include <linux/fence.h> 80 81 #include <drm/ttm/ttm_bo_api.h> 82 #include <drm/ttm/ttm_bo_driver.h> 83 #include <drm/ttm/ttm_placement.h> 84 #include <drm/ttm/ttm_module.h> 85 #include <drm/ttm/ttm_execbuf_util.h> 86 87 #include <drm/drm_gem.h> 88 89 #include "radeon_family.h" 90 #include "radeon_mode.h" 91 #include "radeon_reg.h" 92 93 /* 94 * Modules parameters. 95 */ 96 extern int radeon_no_wb; 97 extern int radeon_modeset; 98 extern int radeon_dynclks; 99 extern int radeon_r4xx_atom; 100 extern int radeon_agpmode; 101 extern int radeon_vram_limit; 102 extern int radeon_gart_size; 103 extern int radeon_benchmarking; 104 extern int radeon_testing; 105 extern int radeon_connector_table; 106 extern int radeon_tv; 107 extern int radeon_audio; 108 extern int radeon_disp_priority; 109 extern int radeon_hw_i2c; 110 extern int radeon_pcie_gen2; 111 extern int radeon_msi; 112 extern int radeon_lockup_timeout; 113 extern int radeon_fastfb; 114 extern int radeon_dpm; 115 extern int radeon_aspm; 116 extern int radeon_runtime_pm; 117 extern int radeon_hard_reset; 118 extern int radeon_vm_size; 119 extern int radeon_vm_block_size; 120 extern int radeon_deep_color; 121 extern int radeon_use_pflipirq; 122 extern int radeon_bapm; 123 extern int radeon_backlight; 124 125 /* 126 * Copy from radeon_drv.h so we don't have to include both and have conflicting 127 * symbol; 128 */ 129 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 130 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 131 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 132 #define RADEON_IB_POOL_SIZE 16 133 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 134 #define RADEONFB_CONN_LIMIT 4 135 #define RADEON_BIOS_NUM_SCRATCH 8 136 137 /* internal ring indices */ 138 /* r1xx+ has gfx CP ring */ 139 #define RADEON_RING_TYPE_GFX_INDEX 0 140 141 /* cayman has 2 compute CP rings */ 142 #define CAYMAN_RING_TYPE_CP1_INDEX 1 143 #define CAYMAN_RING_TYPE_CP2_INDEX 2 144 145 /* R600+ has an async dma ring */ 146 #define R600_RING_TYPE_DMA_INDEX 3 147 /* cayman add a second async dma ring */ 148 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 149 150 /* R600+ */ 151 #define R600_RING_TYPE_UVD_INDEX 5 152 153 /* TN+ */ 154 #define TN_RING_TYPE_VCE1_INDEX 6 155 #define TN_RING_TYPE_VCE2_INDEX 7 156 157 /* max number of rings */ 158 #define RADEON_NUM_RINGS 8 159 160 /* number of hw syncs before falling back on blocking */ 161 #define RADEON_NUM_SYNCS 4 162 163 /* hardcode those limit for now */ 164 #define RADEON_VA_IB_OFFSET (1 << 20) 165 #define RADEON_VA_RESERVED_SIZE (8 << 20) 166 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 167 168 /* hard reset data */ 169 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 170 171 /* reset flags */ 172 #define RADEON_RESET_GFX (1 << 0) 173 #define RADEON_RESET_COMPUTE (1 << 1) 174 #define RADEON_RESET_DMA (1 << 2) 175 #define RADEON_RESET_CP (1 << 3) 176 #define RADEON_RESET_GRBM (1 << 4) 177 #define RADEON_RESET_DMA1 (1 << 5) 178 #define RADEON_RESET_RLC (1 << 6) 179 #define RADEON_RESET_SEM (1 << 7) 180 #define RADEON_RESET_IH (1 << 8) 181 #define RADEON_RESET_VMC (1 << 9) 182 #define RADEON_RESET_MC (1 << 10) 183 #define RADEON_RESET_DISPLAY (1 << 11) 184 185 /* CG block flags */ 186 #define RADEON_CG_BLOCK_GFX (1 << 0) 187 #define RADEON_CG_BLOCK_MC (1 << 1) 188 #define RADEON_CG_BLOCK_SDMA (1 << 2) 189 #define RADEON_CG_BLOCK_UVD (1 << 3) 190 #define RADEON_CG_BLOCK_VCE (1 << 4) 191 #define RADEON_CG_BLOCK_HDP (1 << 5) 192 #define RADEON_CG_BLOCK_BIF (1 << 6) 193 194 /* CG flags */ 195 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 196 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 197 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 198 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 199 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 200 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 201 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 202 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 203 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 204 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 205 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 206 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 207 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 208 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 209 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 210 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 211 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 212 213 /* PG flags */ 214 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 215 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 216 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 217 #define RADEON_PG_SUPPORT_UVD (1 << 3) 218 #define RADEON_PG_SUPPORT_VCE (1 << 4) 219 #define RADEON_PG_SUPPORT_CP (1 << 5) 220 #define RADEON_PG_SUPPORT_GDS (1 << 6) 221 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 222 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 223 #define RADEON_PG_SUPPORT_ACP (1 << 9) 224 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 225 226 /* max cursor sizes (in pixels) */ 227 #define CURSOR_WIDTH 64 228 #define CURSOR_HEIGHT 64 229 230 #define CIK_CURSOR_WIDTH 128 231 #define CIK_CURSOR_HEIGHT 128 232 233 /* 234 * Errata workarounds. 235 */ 236 enum radeon_pll_errata { 237 CHIP_ERRATA_R300_CG = 0x00000001, 238 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 239 CHIP_ERRATA_PLL_DELAY = 0x00000004 240 }; 241 242 243 struct radeon_device; 244 245 246 /* 247 * BIOS. 248 */ 249 bool radeon_get_bios(struct radeon_device *rdev); 250 251 /* 252 * Dummy page 253 */ 254 struct radeon_dummy_page { 255 struct drm_dma_handle *dmah; 256 dma_addr_t addr; 257 }; 258 int radeon_dummy_page_init(struct radeon_device *rdev); 259 void radeon_dummy_page_fini(struct radeon_device *rdev); 260 261 262 /* 263 * Clocks 264 */ 265 struct radeon_clock { 266 struct radeon_pll p1pll; 267 struct radeon_pll p2pll; 268 struct radeon_pll dcpll; 269 struct radeon_pll spll; 270 struct radeon_pll mpll; 271 /* 10 Khz units */ 272 uint32_t default_mclk; 273 uint32_t default_sclk; 274 uint32_t default_dispclk; 275 uint32_t current_dispclk; 276 uint32_t dp_extclk; 277 uint32_t max_pixel_clock; 278 }; 279 280 /* 281 * Power management 282 */ 283 int radeon_pm_init(struct radeon_device *rdev); 284 int radeon_pm_late_init(struct radeon_device *rdev); 285 void radeon_pm_fini(struct radeon_device *rdev); 286 void radeon_pm_compute_clocks(struct radeon_device *rdev); 287 void radeon_pm_suspend(struct radeon_device *rdev); 288 void radeon_pm_resume(struct radeon_device *rdev); 289 void radeon_combios_get_power_modes(struct radeon_device *rdev); 290 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 291 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 292 u8 clock_type, 293 u32 clock, 294 bool strobe_mode, 295 struct atom_clock_dividers *dividers); 296 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 297 u32 clock, 298 bool strobe_mode, 299 struct atom_mpll_param *mpll_param); 300 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 301 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 302 u16 voltage_level, u8 voltage_type, 303 u32 *gpio_value, u32 *gpio_mask); 304 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 305 u32 eng_clock, u32 mem_clock); 306 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 307 u8 voltage_type, u16 *voltage_step); 308 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 309 u16 voltage_id, u16 *voltage); 310 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 311 u16 *voltage, 312 u16 leakage_idx); 313 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 314 u16 *leakage_id); 315 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 316 u16 *vddc, u16 *vddci, 317 u16 virtual_voltage_id, 318 u16 vbios_voltage_id); 319 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 320 u16 virtual_voltage_id, 321 u16 *voltage); 322 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 323 u8 voltage_type, 324 u16 nominal_voltage, 325 u16 *true_voltage); 326 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 327 u8 voltage_type, u16 *min_voltage); 328 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 329 u8 voltage_type, u16 *max_voltage); 330 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 331 u8 voltage_type, u8 voltage_mode, 332 struct atom_voltage_table *voltage_table); 333 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 334 u8 voltage_type, u8 voltage_mode); 335 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 336 u8 voltage_type, 337 u8 *svd_gpio_id, u8 *svc_gpio_id); 338 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 339 u32 mem_clock); 340 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 341 u32 mem_clock); 342 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 343 u8 module_index, 344 struct atom_mc_reg_table *reg_table); 345 int radeon_atom_get_memory_info(struct radeon_device *rdev, 346 u8 module_index, struct atom_memory_info *mem_info); 347 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 348 bool gddr5, u8 module_index, 349 struct atom_memory_clock_range_table *mclk_range_table); 350 void rs690_pm_info(struct radeon_device *rdev); 351 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 352 unsigned *bankh, unsigned *mtaspect, 353 unsigned *tile_split); 354 355 /* 356 * Fences. 357 */ 358 struct radeon_fence_driver { 359 struct radeon_device *rdev; 360 uint32_t scratch_reg; 361 uint64_t gpu_addr; 362 volatile uint32_t *cpu_addr; 363 /* sync_seq is protected by ring emission lock */ 364 uint64_t sync_seq[RADEON_NUM_RINGS]; 365 atomic64_t last_seq; 366 bool initialized, delayed_irq; 367 struct delayed_work lockup_work; 368 }; 369 370 struct radeon_fence { 371 struct fence base; 372 373 struct radeon_device *rdev; 374 uint64_t seq; 375 /* RB, DMA, etc. */ 376 unsigned ring; 377 378 wait_queue_t fence_wake; 379 }; 380 381 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 382 int radeon_fence_driver_init(struct radeon_device *rdev); 383 void radeon_fence_driver_fini(struct radeon_device *rdev); 384 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 385 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 386 void radeon_fence_process(struct radeon_device *rdev, int ring); 387 bool radeon_fence_signaled(struct radeon_fence *fence); 388 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 389 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 390 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 391 int radeon_fence_wait_any(struct radeon_device *rdev, 392 struct radeon_fence **fences, 393 bool intr); 394 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 395 void radeon_fence_unref(struct radeon_fence **fence); 396 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 397 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 398 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 399 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 400 struct radeon_fence *b) 401 { 402 if (!a) { 403 return b; 404 } 405 406 if (!b) { 407 return a; 408 } 409 410 BUG_ON(a->ring != b->ring); 411 412 if (a->seq > b->seq) { 413 return a; 414 } else { 415 return b; 416 } 417 } 418 419 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 420 struct radeon_fence *b) 421 { 422 if (!a) { 423 return false; 424 } 425 426 if (!b) { 427 return true; 428 } 429 430 BUG_ON(a->ring != b->ring); 431 432 return a->seq < b->seq; 433 } 434 435 /* 436 * Tiling registers 437 */ 438 struct radeon_surface_reg { 439 struct radeon_bo *bo; 440 }; 441 442 #define RADEON_GEM_MAX_SURFACES 8 443 444 /* 445 * TTM. 446 */ 447 struct radeon_mman { 448 struct ttm_bo_global_ref bo_global_ref; 449 struct drm_global_reference mem_global_ref; 450 struct ttm_bo_device bdev; 451 bool mem_global_referenced; 452 bool initialized; 453 454 #if defined(CONFIG_DEBUG_FS) 455 struct dentry *vram; 456 struct dentry *gtt; 457 #endif 458 }; 459 460 /* bo virtual address in a specific vm */ 461 struct radeon_bo_va { 462 /* protected by bo being reserved */ 463 struct list_head bo_list; 464 uint32_t flags; 465 uint64_t addr; 466 unsigned ref_count; 467 468 /* protected by vm mutex */ 469 struct interval_tree_node it; 470 struct list_head vm_status; 471 472 /* constant after initialization */ 473 struct radeon_vm *vm; 474 struct radeon_bo *bo; 475 }; 476 477 struct radeon_bo { 478 /* Protected by gem.mutex */ 479 struct list_head list; 480 /* Protected by tbo.reserved */ 481 u32 initial_domain; 482 struct ttm_place placements[3]; 483 struct ttm_placement placement; 484 struct ttm_buffer_object tbo; 485 struct ttm_bo_kmap_obj kmap; 486 u32 flags; 487 unsigned pin_count; 488 void *kptr; 489 u32 tiling_flags; 490 u32 pitch; 491 int surface_reg; 492 /* list of all virtual address to which this bo 493 * is associated to 494 */ 495 struct list_head va; 496 /* Constant after initialization */ 497 struct radeon_device *rdev; 498 struct drm_gem_object gem_base; 499 500 struct ttm_bo_kmap_obj dma_buf_vmap; 501 pid_t pid; 502 503 struct radeon_mn *mn; 504 struct interval_tree_node mn_it; 505 }; 506 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 507 508 int radeon_gem_debugfs_init(struct radeon_device *rdev); 509 510 /* sub-allocation manager, it has to be protected by another lock. 511 * By conception this is an helper for other part of the driver 512 * like the indirect buffer or semaphore, which both have their 513 * locking. 514 * 515 * Principe is simple, we keep a list of sub allocation in offset 516 * order (first entry has offset == 0, last entry has the highest 517 * offset). 518 * 519 * When allocating new object we first check if there is room at 520 * the end total_size - (last_object_offset + last_object_size) >= 521 * alloc_size. If so we allocate new object there. 522 * 523 * When there is not enough room at the end, we start waiting for 524 * each sub object until we reach object_offset+object_size >= 525 * alloc_size, this object then become the sub object we return. 526 * 527 * Alignment can't be bigger than page size. 528 * 529 * Hole are not considered for allocation to keep things simple. 530 * Assumption is that there won't be hole (all object on same 531 * alignment). 532 */ 533 struct radeon_sa_manager { 534 struct cv wq; 535 struct lock wq_lock; 536 struct radeon_bo *bo; 537 struct list_head *hole; 538 struct list_head flist[RADEON_NUM_RINGS]; 539 struct list_head olist; 540 unsigned size; 541 u64 gpu_addr; 542 void *cpu_ptr; 543 uint32_t domain; 544 uint32_t align; 545 }; 546 547 struct radeon_sa_bo; 548 549 /* sub-allocation buffer */ 550 struct radeon_sa_bo { 551 struct list_head olist; 552 struct list_head flist; 553 struct radeon_sa_manager *manager; 554 unsigned soffset; 555 unsigned eoffset; 556 struct radeon_fence *fence; 557 }; 558 559 /* 560 * GEM objects. 561 */ 562 struct radeon_gem { 563 struct lock mutex; 564 struct list_head objects; 565 }; 566 567 int radeon_gem_init(struct radeon_device *rdev); 568 void radeon_gem_fini(struct radeon_device *rdev); 569 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 570 int alignment, int initial_domain, 571 u32 flags, bool kernel, 572 struct drm_gem_object **obj); 573 574 int radeon_mode_dumb_create(struct drm_file *file_priv, 575 struct drm_device *dev, 576 struct drm_mode_create_dumb *args); 577 int radeon_mode_dumb_mmap(struct drm_file *filp, 578 struct drm_device *dev, 579 uint32_t handle, uint64_t *offset_p); 580 581 /* 582 * Semaphores. 583 */ 584 struct radeon_semaphore { 585 struct radeon_sa_bo *sa_bo; 586 signed waiters; 587 uint64_t gpu_addr; 588 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 589 }; 590 591 int radeon_semaphore_create(struct radeon_device *rdev, 592 struct radeon_semaphore **semaphore); 593 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 594 struct radeon_semaphore *semaphore); 595 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 596 struct radeon_semaphore *semaphore); 597 void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore, 598 struct radeon_fence *fence); 599 int radeon_semaphore_sync_resv(struct radeon_device *rdev, 600 struct radeon_semaphore *semaphore, 601 struct reservation_object *resv, 602 bool shared); 603 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 604 struct radeon_semaphore *semaphore, 605 int waiting_ring); 606 void radeon_semaphore_free(struct radeon_device *rdev, 607 struct radeon_semaphore **semaphore, 608 struct radeon_fence *fence); 609 610 /* 611 * GART structures, functions & helpers 612 */ 613 struct radeon_mc; 614 615 #define RADEON_GPU_PAGE_SIZE 4096 616 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 617 #define RADEON_GPU_PAGE_SHIFT 12 618 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 619 620 #define RADEON_GART_PAGE_DUMMY 0 621 #define RADEON_GART_PAGE_VALID (1 << 0) 622 #define RADEON_GART_PAGE_READ (1 << 1) 623 #define RADEON_GART_PAGE_WRITE (1 << 2) 624 #define RADEON_GART_PAGE_SNOOP (1 << 3) 625 626 struct radeon_gart { 627 struct drm_dma_handle *dmah; 628 dma_addr_t table_addr; 629 struct radeon_bo *robj; 630 void *ptr; 631 unsigned num_gpu_pages; 632 unsigned num_cpu_pages; 633 unsigned table_size; 634 struct page **pages; 635 dma_addr_t *pages_addr; 636 bool ready; 637 }; 638 639 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 640 void radeon_gart_table_ram_free(struct radeon_device *rdev); 641 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 642 void radeon_gart_table_vram_free(struct radeon_device *rdev); 643 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 644 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 645 int radeon_gart_init(struct radeon_device *rdev); 646 void radeon_gart_fini(struct radeon_device *rdev); 647 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 648 int pages); 649 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 650 int pages, struct page **pagelist, 651 dma_addr_t *dma_addr, uint32_t flags); 652 653 654 /* 655 * GPU MC structures, functions & helpers 656 */ 657 struct radeon_mc { 658 resource_size_t aper_size; 659 resource_size_t aper_base; 660 resource_size_t agp_base; 661 /* for some chips with <= 32MB we need to lie 662 * about vram size near mc fb location */ 663 u64 mc_vram_size; 664 u64 visible_vram_size; 665 u64 gtt_size; 666 u64 gtt_start; 667 u64 gtt_end; 668 u64 vram_start; 669 u64 vram_end; 670 unsigned vram_width; 671 u64 real_vram_size; 672 int vram_mtrr; 673 bool vram_is_ddr; 674 bool igp_sideport_enabled; 675 u64 gtt_base_align; 676 u64 mc_mask; 677 }; 678 679 bool radeon_combios_sideport_present(struct radeon_device *rdev); 680 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 681 682 /* 683 * GPU scratch registers structures, functions & helpers 684 */ 685 struct radeon_scratch { 686 unsigned num_reg; 687 uint32_t reg_base; 688 bool free[32]; 689 uint32_t reg[32]; 690 }; 691 692 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 693 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 694 695 /* 696 * GPU doorbell structures, functions & helpers 697 */ 698 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 699 700 struct radeon_doorbell { 701 /* doorbell mmio */ 702 resource_size_t base; 703 resource_size_t size; 704 u32 __iomem *ptr; 705 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 706 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 707 }; 708 709 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 710 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 711 712 /* 713 * IRQS. 714 */ 715 716 struct radeon_flip_work { 717 struct work_struct flip_work; 718 struct work_struct unpin_work; 719 struct radeon_device *rdev; 720 int crtc_id; 721 uint64_t base; 722 struct drm_pending_vblank_event *event; 723 struct radeon_bo *old_rbo; 724 struct radeon_fence *fence; 725 }; 726 727 struct r500_irq_stat_regs { 728 u32 disp_int; 729 u32 hdmi0_status; 730 }; 731 732 struct r600_irq_stat_regs { 733 u32 disp_int; 734 u32 disp_int_cont; 735 u32 disp_int_cont2; 736 u32 d1grph_int; 737 u32 d2grph_int; 738 u32 hdmi0_status; 739 u32 hdmi1_status; 740 }; 741 742 struct evergreen_irq_stat_regs { 743 u32 disp_int; 744 u32 disp_int_cont; 745 u32 disp_int_cont2; 746 u32 disp_int_cont3; 747 u32 disp_int_cont4; 748 u32 disp_int_cont5; 749 u32 d1grph_int; 750 u32 d2grph_int; 751 u32 d3grph_int; 752 u32 d4grph_int; 753 u32 d5grph_int; 754 u32 d6grph_int; 755 u32 afmt_status1; 756 u32 afmt_status2; 757 u32 afmt_status3; 758 u32 afmt_status4; 759 u32 afmt_status5; 760 u32 afmt_status6; 761 }; 762 763 struct cik_irq_stat_regs { 764 u32 disp_int; 765 u32 disp_int_cont; 766 u32 disp_int_cont2; 767 u32 disp_int_cont3; 768 u32 disp_int_cont4; 769 u32 disp_int_cont5; 770 u32 disp_int_cont6; 771 u32 d1grph_int; 772 u32 d2grph_int; 773 u32 d3grph_int; 774 u32 d4grph_int; 775 u32 d5grph_int; 776 u32 d6grph_int; 777 }; 778 779 union radeon_irq_stat_regs { 780 struct r500_irq_stat_regs r500; 781 struct r600_irq_stat_regs r600; 782 struct evergreen_irq_stat_regs evergreen; 783 struct cik_irq_stat_regs cik; 784 }; 785 786 struct radeon_irq { 787 bool installed; 788 struct lock lock; 789 atomic_t ring_int[RADEON_NUM_RINGS]; 790 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 791 atomic_t pflip[RADEON_MAX_CRTCS]; 792 wait_queue_head_t vblank_queue; 793 bool hpd[RADEON_MAX_HPD_PINS]; 794 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 795 union radeon_irq_stat_regs stat_regs; 796 bool dpm_thermal; 797 }; 798 799 int radeon_irq_kms_init(struct radeon_device *rdev); 800 void radeon_irq_kms_fini(struct radeon_device *rdev); 801 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 802 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 803 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 804 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 805 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 806 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 807 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 808 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 809 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 810 811 /* 812 * CP & rings. 813 */ 814 815 struct radeon_ib { 816 struct radeon_sa_bo *sa_bo; 817 uint32_t length_dw; 818 uint64_t gpu_addr; 819 uint32_t *ptr; 820 int ring; 821 struct radeon_fence *fence; 822 struct radeon_vm *vm; 823 bool is_const_ib; 824 struct radeon_semaphore *semaphore; 825 }; 826 827 struct radeon_ring { 828 struct radeon_bo *ring_obj; 829 volatile uint32_t *ring; 830 unsigned rptr_offs; 831 unsigned rptr_save_reg; 832 u64 next_rptr_gpu_addr; 833 volatile u32 *next_rptr_cpu_addr; 834 unsigned wptr; 835 unsigned wptr_old; 836 unsigned ring_size; 837 unsigned ring_free_dw; 838 int count_dw; 839 atomic_t last_rptr; 840 atomic64_t last_activity; 841 uint64_t gpu_addr; 842 uint32_t align_mask; 843 uint32_t ptr_mask; 844 bool ready; 845 u32 nop; 846 u32 idx; 847 u64 last_semaphore_signal_addr; 848 u64 last_semaphore_wait_addr; 849 /* for CIK queues */ 850 u32 me; 851 u32 pipe; 852 u32 queue; 853 struct radeon_bo *mqd_obj; 854 u32 doorbell_index; 855 unsigned wptr_offs; 856 }; 857 858 struct radeon_mec { 859 struct radeon_bo *hpd_eop_obj; 860 u64 hpd_eop_gpu_addr; 861 u32 num_pipe; 862 u32 num_mec; 863 u32 num_queue; 864 }; 865 866 /* 867 * VM 868 */ 869 870 /* maximum number of VMIDs */ 871 #define RADEON_NUM_VM 16 872 873 /* number of entries in page table */ 874 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 875 876 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 877 #define RADEON_VM_PTB_ALIGN_SIZE 32768 878 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 879 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 880 881 #define R600_PTE_VALID (1 << 0) 882 #define R600_PTE_SYSTEM (1 << 1) 883 #define R600_PTE_SNOOPED (1 << 2) 884 #define R600_PTE_READABLE (1 << 5) 885 #define R600_PTE_WRITEABLE (1 << 6) 886 887 /* PTE (Page Table Entry) fragment field for different page sizes */ 888 #define R600_PTE_FRAG_4KB (0 << 7) 889 #define R600_PTE_FRAG_64KB (4 << 7) 890 #define R600_PTE_FRAG_256KB (6 << 7) 891 892 /* flags needed to be set so we can copy directly from the GART table */ 893 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 894 R600_PTE_SYSTEM | R600_PTE_VALID ) 895 896 struct radeon_vm_pt { 897 struct radeon_bo *bo; 898 uint64_t addr; 899 }; 900 901 struct radeon_vm { 902 struct lock mutex; 903 904 struct rb_root va; 905 unsigned id; 906 907 /* BOs moved, but not yet updated in the PT */ 908 struct list_head invalidated; 909 910 /* BOs freed, but not yet updated in the PT */ 911 struct list_head freed; 912 913 /* contains the page directory */ 914 struct radeon_bo *page_directory; 915 uint64_t pd_gpu_addr; 916 unsigned max_pde_used; 917 918 /* array of page tables, one for each page directory entry */ 919 struct radeon_vm_pt *page_tables; 920 921 struct radeon_bo_va *ib_bo_va; 922 923 /* last fence for cs using this vm */ 924 struct radeon_fence *fence; 925 /* last flush or NULL if we still need to flush */ 926 struct radeon_fence *last_flush; 927 /* last use of vmid */ 928 struct radeon_fence *last_id_use; 929 }; 930 931 struct radeon_vm_manager { 932 struct radeon_fence *active[RADEON_NUM_VM]; 933 uint32_t max_pfn; 934 /* number of VMIDs */ 935 unsigned nvm; 936 /* vram base address for page table entry */ 937 u64 vram_base_offset; 938 /* is vm enabled? */ 939 bool enabled; 940 /* for hw to save the PD addr on suspend/resume */ 941 uint32_t saved_table_addr[RADEON_NUM_VM]; 942 }; 943 944 /* 945 * file private structure 946 */ 947 struct radeon_fpriv { 948 struct radeon_vm vm; 949 }; 950 951 /* 952 * R6xx+ IH ring 953 */ 954 struct r600_ih { 955 struct radeon_bo *ring_obj; 956 volatile uint32_t *ring; 957 unsigned rptr; 958 unsigned ring_size; 959 uint64_t gpu_addr; 960 uint32_t ptr_mask; 961 atomic_t lock; 962 bool enabled; 963 }; 964 965 /* 966 * RLC stuff 967 */ 968 #include "clearstate_defs.h" 969 970 struct radeon_rlc { 971 /* for power gating */ 972 struct radeon_bo *save_restore_obj; 973 u64 save_restore_gpu_addr; 974 volatile uint32_t *sr_ptr; 975 const u32 *reg_list; 976 u32 reg_list_size; 977 /* for clear state */ 978 struct radeon_bo *clear_state_obj; 979 u64 clear_state_gpu_addr; 980 volatile uint32_t *cs_ptr; 981 const struct cs_section_def *cs_data; 982 u32 clear_state_size; 983 /* for cp tables */ 984 struct radeon_bo *cp_table_obj; 985 u64 cp_table_gpu_addr; 986 volatile uint32_t *cp_table_ptr; 987 u32 cp_table_size; 988 }; 989 990 int radeon_ib_get(struct radeon_device *rdev, int ring, 991 struct radeon_ib *ib, struct radeon_vm *vm, 992 unsigned size); 993 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 994 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 995 struct radeon_ib *const_ib, bool hdp_flush); 996 int radeon_ib_pool_init(struct radeon_device *rdev); 997 void radeon_ib_pool_fini(struct radeon_device *rdev); 998 int radeon_ib_ring_tests(struct radeon_device *rdev); 999 /* Ring access between begin & end cannot sleep */ 1000 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1001 struct radeon_ring *ring); 1002 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1003 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1004 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1005 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1006 bool hdp_flush); 1007 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1008 bool hdp_flush); 1009 void radeon_ring_undo(struct radeon_ring *ring); 1010 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1011 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1012 void radeon_ring_lockup_update(struct radeon_device *rdev, 1013 struct radeon_ring *ring); 1014 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1015 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1016 uint32_t **data); 1017 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1018 unsigned size, uint32_t *data); 1019 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1020 unsigned rptr_offs, u32 nop); 1021 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1022 1023 1024 /* r600 async dma */ 1025 void r600_dma_stop(struct radeon_device *rdev); 1026 int r600_dma_resume(struct radeon_device *rdev); 1027 void r600_dma_fini(struct radeon_device *rdev); 1028 1029 void cayman_dma_stop(struct radeon_device *rdev); 1030 int cayman_dma_resume(struct radeon_device *rdev); 1031 void cayman_dma_fini(struct radeon_device *rdev); 1032 1033 /* 1034 * CS. 1035 */ 1036 struct radeon_cs_reloc { 1037 struct drm_gem_object *gobj; 1038 struct radeon_bo *robj; 1039 struct ttm_validate_buffer tv; 1040 uint64_t gpu_offset; 1041 unsigned prefered_domains; 1042 unsigned allowed_domains; 1043 uint32_t tiling_flags; 1044 uint32_t handle; 1045 }; 1046 1047 struct radeon_cs_chunk { 1048 uint32_t chunk_id; 1049 uint32_t length_dw; 1050 uint32_t *kdata; 1051 void __user *user_ptr; 1052 }; 1053 1054 struct radeon_cs_parser { 1055 struct device *dev; 1056 struct radeon_device *rdev; 1057 struct drm_file *filp; 1058 /* chunks */ 1059 unsigned nchunks; 1060 struct radeon_cs_chunk *chunks; 1061 uint64_t *chunks_array; 1062 /* IB */ 1063 unsigned idx; 1064 /* relocations */ 1065 unsigned nrelocs; 1066 struct radeon_cs_reloc *relocs; 1067 struct radeon_cs_reloc **relocs_ptr; 1068 struct radeon_cs_reloc *vm_bos; 1069 struct list_head validated; 1070 unsigned dma_reloc_idx; 1071 /* indices of various chunks */ 1072 int chunk_ib_idx; 1073 int chunk_relocs_idx; 1074 int chunk_flags_idx; 1075 int chunk_const_ib_idx; 1076 struct radeon_ib ib; 1077 struct radeon_ib const_ib; 1078 void *track; 1079 unsigned family; 1080 int parser_error; 1081 u32 cs_flags; 1082 u32 ring; 1083 s32 priority; 1084 struct ww_acquire_ctx ticket; 1085 }; 1086 1087 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1088 { 1089 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1090 1091 if (ibc->kdata) 1092 return ibc->kdata[idx]; 1093 return p->ib.ptr[idx]; 1094 } 1095 1096 1097 struct radeon_cs_packet { 1098 unsigned idx; 1099 unsigned type; 1100 unsigned reg; 1101 unsigned opcode; 1102 int count; 1103 unsigned one_reg_wr; 1104 }; 1105 1106 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1107 struct radeon_cs_packet *pkt, 1108 unsigned idx, unsigned reg); 1109 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1110 struct radeon_cs_packet *pkt); 1111 1112 1113 /* 1114 * AGP 1115 */ 1116 int radeon_agp_init(struct radeon_device *rdev); 1117 void radeon_agp_resume(struct radeon_device *rdev); 1118 void radeon_agp_suspend(struct radeon_device *rdev); 1119 void radeon_agp_fini(struct radeon_device *rdev); 1120 1121 1122 /* 1123 * Writeback 1124 */ 1125 struct radeon_wb { 1126 struct radeon_bo *wb_obj; 1127 volatile uint32_t *wb; 1128 uint64_t gpu_addr; 1129 bool enabled; 1130 bool use_event; 1131 }; 1132 1133 #define RADEON_WB_SCRATCH_OFFSET 0 1134 #define RADEON_WB_RING0_NEXT_RPTR 256 1135 #define RADEON_WB_CP_RPTR_OFFSET 1024 1136 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1137 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1138 #define R600_WB_DMA_RPTR_OFFSET 1792 1139 #define R600_WB_IH_WPTR_OFFSET 2048 1140 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1141 #define R600_WB_EVENT_OFFSET 3072 1142 #define CIK_WB_CP1_WPTR_OFFSET 3328 1143 #define CIK_WB_CP2_WPTR_OFFSET 3584 1144 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1145 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1146 1147 /** 1148 * struct radeon_pm - power management datas 1149 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1150 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1151 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1152 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1153 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1154 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1155 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1156 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1157 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1158 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1159 * @needed_bandwidth: current bandwidth needs 1160 * 1161 * It keeps track of various data needed to take powermanagement decision. 1162 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1163 * Equation between gpu/memory clock and available bandwidth is hw dependent 1164 * (type of memory, bus size, efficiency, ...) 1165 */ 1166 1167 enum radeon_pm_method { 1168 PM_METHOD_PROFILE, 1169 PM_METHOD_DYNPM, 1170 PM_METHOD_DPM, 1171 }; 1172 1173 enum radeon_dynpm_state { 1174 DYNPM_STATE_DISABLED, 1175 DYNPM_STATE_MINIMUM, 1176 DYNPM_STATE_PAUSED, 1177 DYNPM_STATE_ACTIVE, 1178 DYNPM_STATE_SUSPENDED, 1179 }; 1180 enum radeon_dynpm_action { 1181 DYNPM_ACTION_NONE, 1182 DYNPM_ACTION_MINIMUM, 1183 DYNPM_ACTION_DOWNCLOCK, 1184 DYNPM_ACTION_UPCLOCK, 1185 DYNPM_ACTION_DEFAULT 1186 }; 1187 1188 enum radeon_voltage_type { 1189 VOLTAGE_NONE = 0, 1190 VOLTAGE_GPIO, 1191 VOLTAGE_VDDC, 1192 VOLTAGE_SW 1193 }; 1194 1195 enum radeon_pm_state_type { 1196 /* not used for dpm */ 1197 POWER_STATE_TYPE_DEFAULT, 1198 POWER_STATE_TYPE_POWERSAVE, 1199 /* user selectable states */ 1200 POWER_STATE_TYPE_BATTERY, 1201 POWER_STATE_TYPE_BALANCED, 1202 POWER_STATE_TYPE_PERFORMANCE, 1203 /* internal states */ 1204 POWER_STATE_TYPE_INTERNAL_UVD, 1205 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1206 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1207 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1208 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1209 POWER_STATE_TYPE_INTERNAL_BOOT, 1210 POWER_STATE_TYPE_INTERNAL_THERMAL, 1211 POWER_STATE_TYPE_INTERNAL_ACPI, 1212 POWER_STATE_TYPE_INTERNAL_ULV, 1213 POWER_STATE_TYPE_INTERNAL_3DPERF, 1214 }; 1215 1216 enum radeon_pm_profile_type { 1217 PM_PROFILE_DEFAULT, 1218 PM_PROFILE_AUTO, 1219 PM_PROFILE_LOW, 1220 PM_PROFILE_MID, 1221 PM_PROFILE_HIGH, 1222 }; 1223 1224 #define PM_PROFILE_DEFAULT_IDX 0 1225 #define PM_PROFILE_LOW_SH_IDX 1 1226 #define PM_PROFILE_MID_SH_IDX 2 1227 #define PM_PROFILE_HIGH_SH_IDX 3 1228 #define PM_PROFILE_LOW_MH_IDX 4 1229 #define PM_PROFILE_MID_MH_IDX 5 1230 #define PM_PROFILE_HIGH_MH_IDX 6 1231 #define PM_PROFILE_MAX 7 1232 1233 struct radeon_pm_profile { 1234 int dpms_off_ps_idx; 1235 int dpms_on_ps_idx; 1236 int dpms_off_cm_idx; 1237 int dpms_on_cm_idx; 1238 }; 1239 1240 enum radeon_int_thermal_type { 1241 THERMAL_TYPE_NONE, 1242 THERMAL_TYPE_EXTERNAL, 1243 THERMAL_TYPE_EXTERNAL_GPIO, 1244 THERMAL_TYPE_RV6XX, 1245 THERMAL_TYPE_RV770, 1246 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1247 THERMAL_TYPE_EVERGREEN, 1248 THERMAL_TYPE_SUMO, 1249 THERMAL_TYPE_NI, 1250 THERMAL_TYPE_SI, 1251 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1252 THERMAL_TYPE_CI, 1253 THERMAL_TYPE_KV, 1254 }; 1255 1256 struct radeon_voltage { 1257 enum radeon_voltage_type type; 1258 /* gpio voltage */ 1259 struct radeon_gpio_rec gpio; 1260 u32 delay; /* delay in usec from voltage drop to sclk change */ 1261 bool active_high; /* voltage drop is active when bit is high */ 1262 /* VDDC voltage */ 1263 u8 vddc_id; /* index into vddc voltage table */ 1264 u8 vddci_id; /* index into vddci voltage table */ 1265 bool vddci_enabled; 1266 /* r6xx+ sw */ 1267 u16 voltage; 1268 /* evergreen+ vddci */ 1269 u16 vddci; 1270 }; 1271 1272 /* clock mode flags */ 1273 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1274 1275 struct radeon_pm_clock_info { 1276 /* memory clock */ 1277 u32 mclk; 1278 /* engine clock */ 1279 u32 sclk; 1280 /* voltage info */ 1281 struct radeon_voltage voltage; 1282 /* standardized clock flags */ 1283 u32 flags; 1284 }; 1285 1286 /* state flags */ 1287 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1288 1289 struct radeon_power_state { 1290 enum radeon_pm_state_type type; 1291 struct radeon_pm_clock_info *clock_info; 1292 /* number of valid clock modes in this power state */ 1293 int num_clock_modes; 1294 struct radeon_pm_clock_info *default_clock_mode; 1295 /* standardized state flags */ 1296 u32 flags; 1297 u32 misc; /* vbios specific flags */ 1298 u32 misc2; /* vbios specific flags */ 1299 int pcie_lanes; /* pcie lanes */ 1300 }; 1301 1302 /* 1303 * Some modes are overclocked by very low value, accept them 1304 */ 1305 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1306 1307 enum radeon_dpm_auto_throttle_src { 1308 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1309 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1310 }; 1311 1312 enum radeon_dpm_event_src { 1313 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1314 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1315 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1316 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1317 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1318 }; 1319 1320 #define RADEON_MAX_VCE_LEVELS 6 1321 1322 enum radeon_vce_level { 1323 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1324 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1325 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1326 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1327 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1328 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1329 }; 1330 1331 struct radeon_ps { 1332 u32 caps; /* vbios flags */ 1333 u32 class; /* vbios flags */ 1334 u32 class2; /* vbios flags */ 1335 /* UVD clocks */ 1336 u32 vclk; 1337 u32 dclk; 1338 /* VCE clocks */ 1339 u32 evclk; 1340 u32 ecclk; 1341 bool vce_active; 1342 enum radeon_vce_level vce_level; 1343 /* asic priv */ 1344 void *ps_priv; 1345 }; 1346 1347 struct radeon_dpm_thermal { 1348 /* thermal interrupt work */ 1349 struct work_struct work; 1350 /* low temperature threshold */ 1351 int min_temp; 1352 /* high temperature threshold */ 1353 int max_temp; 1354 /* was interrupt low to high or high to low */ 1355 bool high_to_low; 1356 }; 1357 1358 enum radeon_clk_action 1359 { 1360 RADEON_SCLK_UP = 1, 1361 RADEON_SCLK_DOWN 1362 }; 1363 1364 struct radeon_blacklist_clocks 1365 { 1366 u32 sclk; 1367 u32 mclk; 1368 enum radeon_clk_action action; 1369 }; 1370 1371 struct radeon_clock_and_voltage_limits { 1372 u32 sclk; 1373 u32 mclk; 1374 u16 vddc; 1375 u16 vddci; 1376 }; 1377 1378 struct radeon_clock_array { 1379 u32 count; 1380 u32 *values; 1381 }; 1382 1383 struct radeon_clock_voltage_dependency_entry { 1384 u32 clk; 1385 u16 v; 1386 }; 1387 1388 struct radeon_clock_voltage_dependency_table { 1389 u32 count; 1390 struct radeon_clock_voltage_dependency_entry *entries; 1391 }; 1392 1393 union radeon_cac_leakage_entry { 1394 struct { 1395 u16 vddc; 1396 u32 leakage; 1397 }; 1398 struct { 1399 u16 vddc1; 1400 u16 vddc2; 1401 u16 vddc3; 1402 }; 1403 }; 1404 1405 struct radeon_cac_leakage_table { 1406 u32 count; 1407 union radeon_cac_leakage_entry *entries; 1408 }; 1409 1410 struct radeon_phase_shedding_limits_entry { 1411 u16 voltage; 1412 u32 sclk; 1413 u32 mclk; 1414 }; 1415 1416 struct radeon_phase_shedding_limits_table { 1417 u32 count; 1418 struct radeon_phase_shedding_limits_entry *entries; 1419 }; 1420 1421 struct radeon_uvd_clock_voltage_dependency_entry { 1422 u32 vclk; 1423 u32 dclk; 1424 u16 v; 1425 }; 1426 1427 struct radeon_uvd_clock_voltage_dependency_table { 1428 u8 count; 1429 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1430 }; 1431 1432 struct radeon_vce_clock_voltage_dependency_entry { 1433 u32 ecclk; 1434 u32 evclk; 1435 u16 v; 1436 }; 1437 1438 struct radeon_vce_clock_voltage_dependency_table { 1439 u8 count; 1440 struct radeon_vce_clock_voltage_dependency_entry *entries; 1441 }; 1442 1443 struct radeon_ppm_table { 1444 u8 ppm_design; 1445 u16 cpu_core_number; 1446 u32 platform_tdp; 1447 u32 small_ac_platform_tdp; 1448 u32 platform_tdc; 1449 u32 small_ac_platform_tdc; 1450 u32 apu_tdp; 1451 u32 dgpu_tdp; 1452 u32 dgpu_ulv_power; 1453 u32 tj_max; 1454 }; 1455 1456 struct radeon_cac_tdp_table { 1457 u16 tdp; 1458 u16 configurable_tdp; 1459 u16 tdc; 1460 u16 battery_power_limit; 1461 u16 small_power_limit; 1462 u16 low_cac_leakage; 1463 u16 high_cac_leakage; 1464 u16 maximum_power_delivery_limit; 1465 }; 1466 1467 struct radeon_dpm_dynamic_state { 1468 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1469 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1470 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1471 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1472 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1473 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1474 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1475 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1476 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1477 struct radeon_clock_array valid_sclk_values; 1478 struct radeon_clock_array valid_mclk_values; 1479 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1480 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1481 u32 mclk_sclk_ratio; 1482 u32 sclk_mclk_delta; 1483 u16 vddc_vddci_delta; 1484 u16 min_vddc_for_pcie_gen2; 1485 struct radeon_cac_leakage_table cac_leakage_table; 1486 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1487 struct radeon_ppm_table *ppm_table; 1488 struct radeon_cac_tdp_table *cac_tdp_table; 1489 }; 1490 1491 struct radeon_dpm_fan { 1492 u16 t_min; 1493 u16 t_med; 1494 u16 t_high; 1495 u16 pwm_min; 1496 u16 pwm_med; 1497 u16 pwm_high; 1498 u8 t_hyst; 1499 u32 cycle_delay; 1500 u16 t_max; 1501 bool ucode_fan_control; 1502 }; 1503 1504 enum radeon_pcie_gen { 1505 RADEON_PCIE_GEN1 = 0, 1506 RADEON_PCIE_GEN2 = 1, 1507 RADEON_PCIE_GEN3 = 2, 1508 RADEON_PCIE_GEN_INVALID = 0xffff 1509 }; 1510 1511 enum radeon_dpm_forced_level { 1512 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1513 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1514 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1515 }; 1516 1517 struct radeon_vce_state { 1518 /* vce clocks */ 1519 u32 evclk; 1520 u32 ecclk; 1521 /* gpu clocks */ 1522 u32 sclk; 1523 u32 mclk; 1524 u8 clk_idx; 1525 u8 pstate; 1526 }; 1527 1528 struct radeon_dpm { 1529 struct radeon_ps *ps; 1530 /* number of valid power states */ 1531 int num_ps; 1532 /* current power state that is active */ 1533 struct radeon_ps *current_ps; 1534 /* requested power state */ 1535 struct radeon_ps *requested_ps; 1536 /* boot up power state */ 1537 struct radeon_ps *boot_ps; 1538 /* default uvd power state */ 1539 struct radeon_ps *uvd_ps; 1540 /* vce requirements */ 1541 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1542 enum radeon_vce_level vce_level; 1543 enum radeon_pm_state_type state; 1544 enum radeon_pm_state_type user_state; 1545 u32 platform_caps; 1546 u32 voltage_response_time; 1547 u32 backbias_response_time; 1548 void *priv; 1549 u32 new_active_crtcs; 1550 int new_active_crtc_count; 1551 u32 current_active_crtcs; 1552 int current_active_crtc_count; 1553 struct radeon_dpm_dynamic_state dyn_state; 1554 struct radeon_dpm_fan fan; 1555 u32 tdp_limit; 1556 u32 near_tdp_limit; 1557 u32 near_tdp_limit_adjusted; 1558 u32 sq_ramping_threshold; 1559 u32 cac_leakage; 1560 u16 tdp_od_limit; 1561 u32 tdp_adjustment; 1562 u16 load_line_slope; 1563 bool power_control; 1564 bool ac_power; 1565 /* special states active */ 1566 bool thermal_active; 1567 bool uvd_active; 1568 bool vce_active; 1569 /* thermal handling */ 1570 struct radeon_dpm_thermal thermal; 1571 /* forced levels */ 1572 enum radeon_dpm_forced_level forced_level; 1573 /* track UVD streams */ 1574 unsigned sd; 1575 unsigned hd; 1576 }; 1577 1578 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1579 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1580 1581 struct radeon_pm { 1582 struct lock mutex; 1583 /* write locked while reprogramming mclk */ 1584 struct lock mclk_lock; 1585 u32 active_crtcs; 1586 int active_crtc_count; 1587 int req_vblank; 1588 bool vblank_sync; 1589 fixed20_12 max_bandwidth; 1590 fixed20_12 igp_sideport_mclk; 1591 fixed20_12 igp_system_mclk; 1592 fixed20_12 igp_ht_link_clk; 1593 fixed20_12 igp_ht_link_width; 1594 fixed20_12 k8_bandwidth; 1595 fixed20_12 sideport_bandwidth; 1596 fixed20_12 ht_bandwidth; 1597 fixed20_12 core_bandwidth; 1598 fixed20_12 sclk; 1599 fixed20_12 mclk; 1600 fixed20_12 needed_bandwidth; 1601 struct radeon_power_state *power_state; 1602 /* number of valid power states */ 1603 int num_power_states; 1604 int current_power_state_index; 1605 int current_clock_mode_index; 1606 int requested_power_state_index; 1607 int requested_clock_mode_index; 1608 int default_power_state_index; 1609 u32 current_sclk; 1610 u32 current_mclk; 1611 u16 current_vddc; 1612 u16 current_vddci; 1613 u32 default_sclk; 1614 u32 default_mclk; 1615 u16 default_vddc; 1616 u16 default_vddci; 1617 struct radeon_i2c_chan *i2c_bus; 1618 /* selected pm method */ 1619 enum radeon_pm_method pm_method; 1620 /* dynpm power management */ 1621 #ifdef DUMBBELL_WIP 1622 struct delayed_work dynpm_idle_work; 1623 #endif /* DUMBBELL_WIP */ 1624 enum radeon_dynpm_state dynpm_state; 1625 enum radeon_dynpm_action dynpm_planned_action; 1626 unsigned long dynpm_action_timeout; 1627 bool dynpm_can_upclock; 1628 bool dynpm_can_downclock; 1629 /* profile-based power management */ 1630 enum radeon_pm_profile_type profile; 1631 int profile_index; 1632 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1633 /* internal thermal controller on rv6xx+ */ 1634 enum radeon_int_thermal_type int_thermal_type; 1635 struct ksensor *int_sensor; 1636 struct ksensordev *int_sensordev; 1637 /* dpm */ 1638 bool dpm_enabled; 1639 struct radeon_dpm dpm; 1640 }; 1641 1642 int radeon_pm_get_type_index(struct radeon_device *rdev, 1643 enum radeon_pm_state_type ps_type, 1644 int instance); 1645 /* 1646 * UVD 1647 */ 1648 #define RADEON_MAX_UVD_HANDLES 10 1649 #define RADEON_UVD_STACK_SIZE (1024*1024) 1650 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1651 1652 struct radeon_uvd { 1653 struct radeon_bo *vcpu_bo; 1654 void *cpu_addr; 1655 u64 gpu_addr; 1656 void *saved_bo; 1657 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1658 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1659 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1660 struct delayed_work idle_work; 1661 }; 1662 1663 int radeon_uvd_init(struct radeon_device *rdev); 1664 void radeon_uvd_fini(struct radeon_device *rdev); 1665 int radeon_uvd_suspend(struct radeon_device *rdev); 1666 int radeon_uvd_resume(struct radeon_device *rdev); 1667 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1668 uint32_t handle, struct radeon_fence **fence); 1669 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1670 uint32_t handle, struct radeon_fence **fence); 1671 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1672 uint32_t allowed_domains); 1673 void radeon_uvd_free_handles(struct radeon_device *rdev, 1674 struct drm_file *filp); 1675 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1676 void radeon_uvd_note_usage(struct radeon_device *rdev); 1677 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1678 unsigned vclk, unsigned dclk, 1679 unsigned vco_min, unsigned vco_max, 1680 unsigned fb_factor, unsigned fb_mask, 1681 unsigned pd_min, unsigned pd_max, 1682 unsigned pd_even, 1683 unsigned *optimal_fb_div, 1684 unsigned *optimal_vclk_div, 1685 unsigned *optimal_dclk_div); 1686 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1687 unsigned cg_upll_func_cntl); 1688 1689 /* 1690 * VCE 1691 */ 1692 #define RADEON_MAX_VCE_HANDLES 16 1693 #define RADEON_VCE_STACK_SIZE (1024*1024) 1694 #define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1695 1696 struct radeon_vce { 1697 struct radeon_bo *vcpu_bo; 1698 u64 gpu_addr; 1699 unsigned fw_version; 1700 unsigned fb_version; 1701 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1702 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1703 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1704 struct delayed_work idle_work; 1705 }; 1706 1707 int radeon_vce_init(struct radeon_device *rdev); 1708 void radeon_vce_fini(struct radeon_device *rdev); 1709 int radeon_vce_suspend(struct radeon_device *rdev); 1710 int radeon_vce_resume(struct radeon_device *rdev); 1711 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1712 uint32_t handle, struct radeon_fence **fence); 1713 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1714 uint32_t handle, struct radeon_fence **fence); 1715 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1716 void radeon_vce_note_usage(struct radeon_device *rdev); 1717 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1718 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1719 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1720 struct radeon_ring *ring, 1721 struct radeon_semaphore *semaphore, 1722 bool emit_wait); 1723 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1724 void radeon_vce_fence_emit(struct radeon_device *rdev, 1725 struct radeon_fence *fence); 1726 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1727 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1728 1729 struct r600_audio_pin { 1730 int channels; 1731 int rate; 1732 int bits_per_sample; 1733 u8 status_bits; 1734 u8 category_code; 1735 u32 offset; 1736 bool connected; 1737 u32 id; 1738 }; 1739 1740 struct r600_audio { 1741 bool enabled; 1742 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1743 int num_pins; 1744 }; 1745 1746 /* 1747 * Benchmarking 1748 */ 1749 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1750 1751 1752 /* 1753 * Testing 1754 */ 1755 void radeon_test_moves(struct radeon_device *rdev); 1756 void radeon_test_ring_sync(struct radeon_device *rdev, 1757 struct radeon_ring *cpA, 1758 struct radeon_ring *cpB); 1759 void radeon_test_syncing(struct radeon_device *rdev); 1760 1761 /* 1762 * MMU Notifier 1763 */ 1764 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1765 void radeon_mn_unregister(struct radeon_bo *bo); 1766 1767 /* 1768 * Debugfs 1769 */ 1770 struct radeon_debugfs { 1771 struct drm_info_list *files; 1772 unsigned num_files; 1773 }; 1774 1775 int radeon_debugfs_add_files(struct radeon_device *rdev, 1776 struct drm_info_list *files, 1777 unsigned nfiles); 1778 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1779 1780 /* 1781 * ASIC ring specific functions. 1782 */ 1783 struct radeon_asic_ring { 1784 /* ring read/write ptr handling */ 1785 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1786 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1787 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1788 1789 /* validating and patching of IBs */ 1790 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1791 int (*cs_parse)(struct radeon_cs_parser *p); 1792 1793 /* command emmit functions */ 1794 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1795 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1796 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1797 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1798 struct radeon_semaphore *semaphore, bool emit_wait); 1799 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1800 1801 /* testing functions */ 1802 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1803 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1804 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1805 1806 /* deprecated */ 1807 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1808 }; 1809 1810 /* 1811 * ASIC specific functions. 1812 */ 1813 struct radeon_asic { 1814 int (*init)(struct radeon_device *rdev); 1815 void (*fini)(struct radeon_device *rdev); 1816 int (*resume)(struct radeon_device *rdev); 1817 int (*suspend)(struct radeon_device *rdev); 1818 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1819 int (*asic_reset)(struct radeon_device *rdev); 1820 /* Flush the HDP cache via MMIO */ 1821 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1822 /* check if 3D engine is idle */ 1823 bool (*gui_idle)(struct radeon_device *rdev); 1824 /* wait for mc_idle */ 1825 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1826 /* get the reference clock */ 1827 u32 (*get_xclk)(struct radeon_device *rdev); 1828 /* get the gpu clock counter */ 1829 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1830 /* gart */ 1831 struct { 1832 void (*tlb_flush)(struct radeon_device *rdev); 1833 void (*set_page)(struct radeon_device *rdev, unsigned i, 1834 uint64_t addr, uint32_t flags); 1835 } gart; 1836 struct { 1837 int (*init)(struct radeon_device *rdev); 1838 void (*fini)(struct radeon_device *rdev); 1839 void (*copy_pages)(struct radeon_device *rdev, 1840 struct radeon_ib *ib, 1841 uint64_t pe, uint64_t src, 1842 unsigned count); 1843 void (*write_pages)(struct radeon_device *rdev, 1844 struct radeon_ib *ib, 1845 uint64_t pe, 1846 uint64_t addr, unsigned count, 1847 uint32_t incr, uint32_t flags); 1848 void (*set_pages)(struct radeon_device *rdev, 1849 struct radeon_ib *ib, 1850 uint64_t pe, 1851 uint64_t addr, unsigned count, 1852 uint32_t incr, uint32_t flags); 1853 void (*pad_ib)(struct radeon_ib *ib); 1854 } vm; 1855 /* ring specific callbacks */ 1856 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1857 /* irqs */ 1858 struct { 1859 int (*set)(struct radeon_device *rdev); 1860 irqreturn_t (*process)(struct radeon_device *rdev); 1861 } irq; 1862 /* displays */ 1863 struct { 1864 /* display watermarks */ 1865 void (*bandwidth_update)(struct radeon_device *rdev); 1866 /* get frame count */ 1867 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1868 /* wait for vblank */ 1869 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1870 /* set backlight level */ 1871 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1872 /* get backlight level */ 1873 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1874 /* audio callbacks */ 1875 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1876 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1877 } display; 1878 /* copy functions for bo handling */ 1879 struct { 1880 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1881 uint64_t src_offset, 1882 uint64_t dst_offset, 1883 unsigned num_gpu_pages, 1884 struct reservation_object *resv); 1885 u32 blit_ring_index; 1886 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1887 uint64_t src_offset, 1888 uint64_t dst_offset, 1889 unsigned num_gpu_pages, 1890 struct reservation_object *resv); 1891 u32 dma_ring_index; 1892 /* method used for bo copy */ 1893 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1894 uint64_t src_offset, 1895 uint64_t dst_offset, 1896 unsigned num_gpu_pages, 1897 struct reservation_object *resv); 1898 /* ring used for bo copies */ 1899 u32 copy_ring_index; 1900 } copy; 1901 /* surfaces */ 1902 struct { 1903 int (*set_reg)(struct radeon_device *rdev, int reg, 1904 uint32_t tiling_flags, uint32_t pitch, 1905 uint32_t offset, uint32_t obj_size); 1906 void (*clear_reg)(struct radeon_device *rdev, int reg); 1907 } surface; 1908 /* hotplug detect */ 1909 struct { 1910 void (*init)(struct radeon_device *rdev); 1911 void (*fini)(struct radeon_device *rdev); 1912 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1913 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1914 } hpd; 1915 /* static power management */ 1916 struct { 1917 void (*misc)(struct radeon_device *rdev); 1918 void (*prepare)(struct radeon_device *rdev); 1919 void (*finish)(struct radeon_device *rdev); 1920 void (*init_profile)(struct radeon_device *rdev); 1921 void (*get_dynpm_state)(struct radeon_device *rdev); 1922 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1923 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1924 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1925 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1926 int (*get_pcie_lanes)(struct radeon_device *rdev); 1927 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1928 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1929 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1930 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1931 int (*get_temperature)(struct radeon_device *rdev); 1932 } pm; 1933 /* dynamic power management */ 1934 struct { 1935 int (*init)(struct radeon_device *rdev); 1936 void (*setup_asic)(struct radeon_device *rdev); 1937 int (*enable)(struct radeon_device *rdev); 1938 int (*late_enable)(struct radeon_device *rdev); 1939 void (*disable)(struct radeon_device *rdev); 1940 int (*pre_set_power_state)(struct radeon_device *rdev); 1941 int (*set_power_state)(struct radeon_device *rdev); 1942 void (*post_set_power_state)(struct radeon_device *rdev); 1943 void (*display_configuration_changed)(struct radeon_device *rdev); 1944 void (*fini)(struct radeon_device *rdev); 1945 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1946 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1947 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1948 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1949 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1950 bool (*vblank_too_short)(struct radeon_device *rdev); 1951 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1952 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1953 } dpm; 1954 /* pageflipping */ 1955 struct { 1956 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1957 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1958 } pflip; 1959 }; 1960 1961 /* 1962 * Asic structures 1963 */ 1964 struct r100_asic { 1965 const unsigned *reg_safe_bm; 1966 unsigned reg_safe_bm_size; 1967 u32 hdp_cntl; 1968 }; 1969 1970 struct r300_asic { 1971 const unsigned *reg_safe_bm; 1972 unsigned reg_safe_bm_size; 1973 u32 resync_scratch; 1974 u32 hdp_cntl; 1975 }; 1976 1977 struct r600_asic { 1978 unsigned max_pipes; 1979 unsigned max_tile_pipes; 1980 unsigned max_simds; 1981 unsigned max_backends; 1982 unsigned max_gprs; 1983 unsigned max_threads; 1984 unsigned max_stack_entries; 1985 unsigned max_hw_contexts; 1986 unsigned max_gs_threads; 1987 unsigned sx_max_export_size; 1988 unsigned sx_max_export_pos_size; 1989 unsigned sx_max_export_smx_size; 1990 unsigned sq_num_cf_insts; 1991 unsigned tiling_nbanks; 1992 unsigned tiling_npipes; 1993 unsigned tiling_group_size; 1994 unsigned tile_config; 1995 unsigned backend_map; 1996 unsigned active_simds; 1997 }; 1998 1999 struct rv770_asic { 2000 unsigned max_pipes; 2001 unsigned max_tile_pipes; 2002 unsigned max_simds; 2003 unsigned max_backends; 2004 unsigned max_gprs; 2005 unsigned max_threads; 2006 unsigned max_stack_entries; 2007 unsigned max_hw_contexts; 2008 unsigned max_gs_threads; 2009 unsigned sx_max_export_size; 2010 unsigned sx_max_export_pos_size; 2011 unsigned sx_max_export_smx_size; 2012 unsigned sq_num_cf_insts; 2013 unsigned sx_num_of_sets; 2014 unsigned sc_prim_fifo_size; 2015 unsigned sc_hiz_tile_fifo_size; 2016 unsigned sc_earlyz_tile_fifo_fize; 2017 unsigned tiling_nbanks; 2018 unsigned tiling_npipes; 2019 unsigned tiling_group_size; 2020 unsigned tile_config; 2021 unsigned backend_map; 2022 unsigned active_simds; 2023 }; 2024 2025 struct evergreen_asic { 2026 unsigned num_ses; 2027 unsigned max_pipes; 2028 unsigned max_tile_pipes; 2029 unsigned max_simds; 2030 unsigned max_backends; 2031 unsigned max_gprs; 2032 unsigned max_threads; 2033 unsigned max_stack_entries; 2034 unsigned max_hw_contexts; 2035 unsigned max_gs_threads; 2036 unsigned sx_max_export_size; 2037 unsigned sx_max_export_pos_size; 2038 unsigned sx_max_export_smx_size; 2039 unsigned sq_num_cf_insts; 2040 unsigned sx_num_of_sets; 2041 unsigned sc_prim_fifo_size; 2042 unsigned sc_hiz_tile_fifo_size; 2043 unsigned sc_earlyz_tile_fifo_size; 2044 unsigned tiling_nbanks; 2045 unsigned tiling_npipes; 2046 unsigned tiling_group_size; 2047 unsigned tile_config; 2048 unsigned backend_map; 2049 unsigned active_simds; 2050 }; 2051 2052 struct cayman_asic { 2053 unsigned max_shader_engines; 2054 unsigned max_pipes_per_simd; 2055 unsigned max_tile_pipes; 2056 unsigned max_simds_per_se; 2057 unsigned max_backends_per_se; 2058 unsigned max_texture_channel_caches; 2059 unsigned max_gprs; 2060 unsigned max_threads; 2061 unsigned max_gs_threads; 2062 unsigned max_stack_entries; 2063 unsigned sx_num_of_sets; 2064 unsigned sx_max_export_size; 2065 unsigned sx_max_export_pos_size; 2066 unsigned sx_max_export_smx_size; 2067 unsigned max_hw_contexts; 2068 unsigned sq_num_cf_insts; 2069 unsigned sc_prim_fifo_size; 2070 unsigned sc_hiz_tile_fifo_size; 2071 unsigned sc_earlyz_tile_fifo_size; 2072 2073 unsigned num_shader_engines; 2074 unsigned num_shader_pipes_per_simd; 2075 unsigned num_tile_pipes; 2076 unsigned num_simds_per_se; 2077 unsigned num_backends_per_se; 2078 unsigned backend_disable_mask_per_asic; 2079 unsigned backend_map; 2080 unsigned num_texture_channel_caches; 2081 unsigned mem_max_burst_length_bytes; 2082 unsigned mem_row_size_in_kb; 2083 unsigned shader_engine_tile_size; 2084 unsigned num_gpus; 2085 unsigned multi_gpu_tile_size; 2086 2087 unsigned tile_config; 2088 unsigned active_simds; 2089 }; 2090 2091 struct si_asic { 2092 unsigned max_shader_engines; 2093 unsigned max_tile_pipes; 2094 unsigned max_cu_per_sh; 2095 unsigned max_sh_per_se; 2096 unsigned max_backends_per_se; 2097 unsigned max_texture_channel_caches; 2098 unsigned max_gprs; 2099 unsigned max_gs_threads; 2100 unsigned max_hw_contexts; 2101 unsigned sc_prim_fifo_size_frontend; 2102 unsigned sc_prim_fifo_size_backend; 2103 unsigned sc_hiz_tile_fifo_size; 2104 unsigned sc_earlyz_tile_fifo_size; 2105 2106 unsigned num_tile_pipes; 2107 unsigned backend_enable_mask; 2108 unsigned backend_disable_mask_per_asic; 2109 unsigned backend_map; 2110 unsigned num_texture_channel_caches; 2111 unsigned mem_max_burst_length_bytes; 2112 unsigned mem_row_size_in_kb; 2113 unsigned shader_engine_tile_size; 2114 unsigned num_gpus; 2115 unsigned multi_gpu_tile_size; 2116 2117 unsigned tile_config; 2118 uint32_t tile_mode_array[32]; 2119 uint32_t active_cus; 2120 }; 2121 2122 struct cik_asic { 2123 unsigned max_shader_engines; 2124 unsigned max_tile_pipes; 2125 unsigned max_cu_per_sh; 2126 unsigned max_sh_per_se; 2127 unsigned max_backends_per_se; 2128 unsigned max_texture_channel_caches; 2129 unsigned max_gprs; 2130 unsigned max_gs_threads; 2131 unsigned max_hw_contexts; 2132 unsigned sc_prim_fifo_size_frontend; 2133 unsigned sc_prim_fifo_size_backend; 2134 unsigned sc_hiz_tile_fifo_size; 2135 unsigned sc_earlyz_tile_fifo_size; 2136 2137 unsigned num_tile_pipes; 2138 unsigned backend_enable_mask; 2139 unsigned backend_disable_mask_per_asic; 2140 unsigned backend_map; 2141 unsigned num_texture_channel_caches; 2142 unsigned mem_max_burst_length_bytes; 2143 unsigned mem_row_size_in_kb; 2144 unsigned shader_engine_tile_size; 2145 unsigned num_gpus; 2146 unsigned multi_gpu_tile_size; 2147 2148 unsigned tile_config; 2149 uint32_t tile_mode_array[32]; 2150 uint32_t macrotile_mode_array[16]; 2151 uint32_t active_cus; 2152 }; 2153 2154 union radeon_asic_config { 2155 struct r300_asic r300; 2156 struct r100_asic r100; 2157 struct r600_asic r600; 2158 struct rv770_asic rv770; 2159 struct evergreen_asic evergreen; 2160 struct cayman_asic cayman; 2161 struct si_asic si; 2162 struct cik_asic cik; 2163 }; 2164 2165 /* 2166 * asic initizalization from radeon_asic.c 2167 */ 2168 int radeon_asic_init(struct radeon_device *rdev); 2169 2170 2171 /* 2172 * IOCTL. 2173 */ 2174 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2175 struct drm_file *filp); 2176 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2177 struct drm_file *filp); 2178 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2179 struct drm_file *filp); 2180 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2181 struct drm_file *file_priv); 2182 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2183 struct drm_file *file_priv); 2184 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2185 struct drm_file *file_priv); 2186 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2187 struct drm_file *file_priv); 2188 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2189 struct drm_file *filp); 2190 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2191 struct drm_file *filp); 2192 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2193 struct drm_file *filp); 2194 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2195 struct drm_file *filp); 2196 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2197 struct drm_file *filp); 2198 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2199 struct drm_file *filp); 2200 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2201 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2202 struct drm_file *filp); 2203 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2204 struct drm_file *filp); 2205 2206 /* VRAM scratch page for HDP bug, default vram page */ 2207 struct r600_vram_scratch { 2208 struct radeon_bo *robj; 2209 volatile uint32_t *ptr; 2210 u64 gpu_addr; 2211 }; 2212 2213 /* 2214 * ACPI 2215 */ 2216 struct radeon_atif_notification_cfg { 2217 bool enabled; 2218 int command_code; 2219 }; 2220 2221 struct radeon_atif_notifications { 2222 bool display_switch; 2223 bool expansion_mode_change; 2224 bool thermal_state; 2225 bool forced_power_state; 2226 bool system_power_state; 2227 bool display_conf_change; 2228 bool px_gfx_switch; 2229 bool brightness_change; 2230 bool dgpu_display_event; 2231 }; 2232 2233 struct radeon_atif_functions { 2234 bool system_params; 2235 bool sbios_requests; 2236 bool select_active_disp; 2237 bool lid_state; 2238 bool get_tv_standard; 2239 bool set_tv_standard; 2240 bool get_panel_expansion_mode; 2241 bool set_panel_expansion_mode; 2242 bool temperature_change; 2243 bool graphics_device_types; 2244 }; 2245 2246 struct radeon_atif { 2247 struct radeon_atif_notifications notifications; 2248 struct radeon_atif_functions functions; 2249 struct radeon_atif_notification_cfg notification_cfg; 2250 struct radeon_encoder *encoder_for_bl; 2251 }; 2252 2253 struct radeon_atcs_functions { 2254 bool get_ext_state; 2255 bool pcie_perf_req; 2256 bool pcie_dev_rdy; 2257 bool pcie_bus_width; 2258 }; 2259 2260 struct radeon_atcs { 2261 struct radeon_atcs_functions functions; 2262 }; 2263 2264 /* 2265 * Core structure, functions and helpers. 2266 */ 2267 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2268 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2269 2270 struct radeon_device { 2271 struct device *dev; 2272 struct drm_device *ddev; 2273 struct pci_dev *pdev; 2274 struct lock exclusive_lock; 2275 /* ASIC */ 2276 union radeon_asic_config config; 2277 enum radeon_family family; 2278 unsigned long flags; 2279 int usec_timeout; 2280 enum radeon_pll_errata pll_errata; 2281 int num_gb_pipes; 2282 int num_z_pipes; 2283 int disp_priority; 2284 /* BIOS */ 2285 uint8_t *bios; 2286 bool is_atom_bios; 2287 uint16_t bios_header_start; 2288 struct radeon_bo *stollen_vga_memory; 2289 /* Register mmio */ 2290 resource_size_t rmmio_base; 2291 resource_size_t rmmio_size; 2292 /* protects concurrent MM_INDEX/DATA based register access */ 2293 struct spinlock mmio_idx_lock; 2294 /* protects concurrent SMC based register access */ 2295 struct spinlock smc_idx_lock; 2296 /* protects concurrent PLL register access */ 2297 struct spinlock pll_idx_lock; 2298 /* protects concurrent MC register access */ 2299 struct spinlock mc_idx_lock; 2300 /* protects concurrent PCIE register access */ 2301 struct spinlock pcie_idx_lock; 2302 /* protects concurrent PCIE_PORT register access */ 2303 struct spinlock pciep_idx_lock; 2304 /* protects concurrent PIF register access */ 2305 struct spinlock pif_idx_lock; 2306 /* protects concurrent CG register access */ 2307 struct spinlock cg_idx_lock; 2308 /* protects concurrent UVD register access */ 2309 struct spinlock uvd_idx_lock; 2310 /* protects concurrent RCU register access */ 2311 struct spinlock rcu_idx_lock; 2312 /* protects concurrent DIDT register access */ 2313 struct spinlock didt_idx_lock; 2314 /* protects concurrent ENDPOINT (audio) register access */ 2315 struct spinlock end_idx_lock; 2316 int rmmio_rid; 2317 struct resource *rmmio; 2318 radeon_rreg_t mc_rreg; 2319 radeon_wreg_t mc_wreg; 2320 radeon_rreg_t pll_rreg; 2321 radeon_wreg_t pll_wreg; 2322 uint32_t pcie_reg_mask; 2323 radeon_rreg_t pciep_rreg; 2324 radeon_wreg_t pciep_wreg; 2325 /* io port */ 2326 int rio_rid; 2327 struct resource *rio_mem; 2328 resource_size_t rio_mem_size; 2329 struct radeon_clock clock; 2330 struct radeon_mc mc; 2331 struct radeon_gart gart; 2332 struct radeon_mode_info mode_info; 2333 struct radeon_scratch scratch; 2334 struct radeon_doorbell doorbell; 2335 struct radeon_mman mman; 2336 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2337 wait_queue_head_t fence_queue; 2338 unsigned fence_context; 2339 struct lock ring_lock; 2340 struct radeon_ring ring[RADEON_NUM_RINGS]; 2341 bool ib_pool_ready; 2342 struct radeon_sa_manager ring_tmp_bo; 2343 struct radeon_irq irq; 2344 struct radeon_asic *asic; 2345 struct radeon_gem gem; 2346 struct radeon_pm pm; 2347 struct radeon_uvd uvd; 2348 struct radeon_vce vce; 2349 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2350 struct radeon_wb wb; 2351 struct radeon_dummy_page dummy_page; 2352 bool shutdown; 2353 bool suspend; 2354 bool need_dma32; 2355 bool accel_working; 2356 bool fastfb_working; /* IGP feature*/ 2357 bool needs_reset, in_reset; 2358 bool fictitious_range_registered; 2359 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2360 const struct firmware *me_fw; /* all family ME firmware */ 2361 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2362 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2363 const struct firmware *mc_fw; /* NI MC firmware */ 2364 const struct firmware *ce_fw; /* SI CE firmware */ 2365 const struct firmware *mec_fw; /* CIK MEC firmware */ 2366 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2367 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2368 const struct firmware *smc_fw; /* SMC firmware */ 2369 const struct firmware *uvd_fw; /* UVD firmware */ 2370 const struct firmware *vce_fw; /* VCE firmware */ 2371 bool new_fw; 2372 struct r600_vram_scratch vram_scratch; 2373 int msi_enabled; /* msi enabled */ 2374 struct r600_ih ih; /* r6/700 interrupt ring */ 2375 struct radeon_rlc rlc; 2376 struct radeon_mec mec; 2377 struct work_struct hotplug_work; 2378 struct work_struct audio_work; 2379 int num_crtc; /* number of crtcs */ 2380 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2381 bool has_uvd; 2382 struct r600_audio audio; /* audio stuff */ 2383 struct { 2384 ACPI_HANDLE handle; 2385 ACPI_NOTIFY_HANDLER notifier_call; 2386 } acpi; 2387 /* only one userspace can use Hyperz features or CMASK at a time */ 2388 struct drm_file *hyperz_filp; 2389 struct drm_file *cmask_filp; 2390 /* i2c buses */ 2391 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2392 /* debugfs */ 2393 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2394 unsigned debugfs_count; 2395 /* virtual memory */ 2396 struct radeon_vm_manager vm_manager; 2397 struct lock gpu_clock_mutex; 2398 /* memory stats */ 2399 atomic64_t vram_usage; 2400 atomic64_t gtt_usage; 2401 atomic64_t num_bytes_moved; 2402 /* ACPI interface */ 2403 struct radeon_atif atif; 2404 struct radeon_atcs atcs; 2405 /* srbm instance registers */ 2406 struct lock srbm_mutex; 2407 /* clock, powergating flags */ 2408 u32 cg_flags; 2409 u32 pg_flags; 2410 2411 #ifdef PM_TODO 2412 struct dev_pm_domain vga_pm_domain; 2413 #endif 2414 bool have_disp_power_ref; 2415 u32 px_quirk_flags; 2416 2417 /* tracking pinned memory */ 2418 u64 vram_pin_size; 2419 u64 gart_pin_size; 2420 2421 struct lock mn_lock; 2422 DECLARE_HASHTABLE(mn_hash, 7); 2423 }; 2424 2425 bool radeon_is_px(struct drm_device *dev); 2426 int radeon_device_init(struct radeon_device *rdev, 2427 struct drm_device *ddev, 2428 struct pci_dev *pdev, 2429 uint32_t flags); 2430 void radeon_device_fini(struct radeon_device *rdev); 2431 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2432 2433 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2434 bool always_indirect); 2435 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2436 bool always_indirect); 2437 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2438 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2439 2440 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2441 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2442 2443 /* 2444 * Cast helper 2445 */ 2446 extern const struct fence_ops radeon_fence_ops; 2447 2448 static inline struct radeon_fence *to_radeon_fence(struct fence *f) 2449 { 2450 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2451 2452 if (__f->base.ops == &radeon_fence_ops) 2453 return __f; 2454 2455 return NULL; 2456 } 2457 2458 /* 2459 * Registers read & write functions. 2460 */ 2461 #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 2462 #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 2463 #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 2464 #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 2465 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2466 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2467 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 2468 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2469 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2470 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2471 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2472 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2473 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2474 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2475 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2476 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2477 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2478 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2479 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2480 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2481 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2482 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2483 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2484 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2485 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2486 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2487 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2488 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2489 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2490 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2491 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2492 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2493 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2494 #define WREG32_P(reg, val, mask) \ 2495 do { \ 2496 uint32_t tmp_ = RREG32(reg); \ 2497 tmp_ &= (mask); \ 2498 tmp_ |= ((val) & ~(mask)); \ 2499 WREG32(reg, tmp_); \ 2500 } while (0) 2501 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2502 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2503 #define WREG32_PLL_P(reg, val, mask) \ 2504 do { \ 2505 uint32_t tmp_ = RREG32_PLL(reg); \ 2506 tmp_ &= (mask); \ 2507 tmp_ |= ((val) & ~(mask)); \ 2508 WREG32_PLL(reg, tmp_); \ 2509 } while (0) 2510 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2511 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2512 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2513 2514 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2515 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2516 2517 /* 2518 * Indirect registers accessor 2519 */ 2520 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2521 { 2522 uint32_t r; 2523 2524 spin_lock(&rdev->pcie_idx_lock); 2525 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2526 r = RREG32(RADEON_PCIE_DATA); 2527 spin_unlock(&rdev->pcie_idx_lock); 2528 return r; 2529 } 2530 2531 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2532 { 2533 spin_lock(&rdev->pcie_idx_lock); 2534 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2535 WREG32(RADEON_PCIE_DATA, (v)); 2536 spin_unlock(&rdev->pcie_idx_lock); 2537 } 2538 2539 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2540 { 2541 u32 r; 2542 2543 spin_lock(&rdev->smc_idx_lock); 2544 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2545 r = RREG32(TN_SMC_IND_DATA_0); 2546 spin_unlock(&rdev->smc_idx_lock); 2547 return r; 2548 } 2549 2550 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2551 { 2552 spin_lock(&rdev->smc_idx_lock); 2553 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2554 WREG32(TN_SMC_IND_DATA_0, (v)); 2555 spin_unlock(&rdev->smc_idx_lock); 2556 } 2557 2558 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2559 { 2560 u32 r; 2561 2562 spin_lock(&rdev->rcu_idx_lock); 2563 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2564 r = RREG32(R600_RCU_DATA); 2565 spin_unlock(&rdev->rcu_idx_lock); 2566 return r; 2567 } 2568 2569 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2570 { 2571 spin_lock(&rdev->rcu_idx_lock); 2572 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2573 WREG32(R600_RCU_DATA, (v)); 2574 spin_unlock(&rdev->rcu_idx_lock); 2575 } 2576 2577 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2578 { 2579 u32 r; 2580 2581 spin_lock(&rdev->cg_idx_lock); 2582 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2583 r = RREG32(EVERGREEN_CG_IND_DATA); 2584 spin_unlock(&rdev->cg_idx_lock); 2585 return r; 2586 } 2587 2588 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2589 { 2590 spin_lock(&rdev->cg_idx_lock); 2591 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2592 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2593 spin_unlock(&rdev->cg_idx_lock); 2594 } 2595 2596 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2597 { 2598 u32 r; 2599 2600 spin_lock(&rdev->pif_idx_lock); 2601 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2602 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2603 spin_unlock(&rdev->pif_idx_lock); 2604 return r; 2605 } 2606 2607 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2608 { 2609 spin_lock(&rdev->pif_idx_lock); 2610 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2611 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2612 spin_unlock(&rdev->pif_idx_lock); 2613 } 2614 2615 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2616 { 2617 u32 r; 2618 2619 spin_lock(&rdev->pif_idx_lock); 2620 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2621 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2622 spin_unlock(&rdev->pif_idx_lock); 2623 return r; 2624 } 2625 2626 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2627 { 2628 spin_lock(&rdev->pif_idx_lock); 2629 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2630 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2631 spin_unlock(&rdev->pif_idx_lock); 2632 } 2633 2634 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2635 { 2636 u32 r; 2637 2638 spin_lock(&rdev->uvd_idx_lock); 2639 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2640 r = RREG32(R600_UVD_CTX_DATA); 2641 spin_unlock(&rdev->uvd_idx_lock); 2642 return r; 2643 } 2644 2645 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2646 { 2647 spin_lock(&rdev->uvd_idx_lock); 2648 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2649 WREG32(R600_UVD_CTX_DATA, (v)); 2650 spin_unlock(&rdev->uvd_idx_lock); 2651 } 2652 2653 2654 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2655 { 2656 u32 r; 2657 2658 spin_lock(&rdev->didt_idx_lock); 2659 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2660 r = RREG32(CIK_DIDT_IND_DATA); 2661 spin_unlock(&rdev->didt_idx_lock); 2662 return r; 2663 } 2664 2665 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2666 { 2667 spin_lock(&rdev->didt_idx_lock); 2668 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2669 WREG32(CIK_DIDT_IND_DATA, (v)); 2670 spin_unlock(&rdev->didt_idx_lock); 2671 } 2672 2673 void r100_pll_errata_after_index(struct radeon_device *rdev); 2674 2675 2676 /* 2677 * ASICs helpers. 2678 */ 2679 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2680 (rdev->pdev->device == 0x5969)) 2681 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2682 (rdev->family == CHIP_RV200) || \ 2683 (rdev->family == CHIP_RS100) || \ 2684 (rdev->family == CHIP_RS200) || \ 2685 (rdev->family == CHIP_RV250) || \ 2686 (rdev->family == CHIP_RV280) || \ 2687 (rdev->family == CHIP_RS300)) 2688 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2689 (rdev->family == CHIP_RV350) || \ 2690 (rdev->family == CHIP_R350) || \ 2691 (rdev->family == CHIP_RV380) || \ 2692 (rdev->family == CHIP_R420) || \ 2693 (rdev->family == CHIP_R423) || \ 2694 (rdev->family == CHIP_RV410) || \ 2695 (rdev->family == CHIP_RS400) || \ 2696 (rdev->family == CHIP_RS480)) 2697 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2698 (rdev->ddev->pdev->device == 0x9443) || \ 2699 (rdev->ddev->pdev->device == 0x944B) || \ 2700 (rdev->ddev->pdev->device == 0x9506) || \ 2701 (rdev->ddev->pdev->device == 0x9509) || \ 2702 (rdev->ddev->pdev->device == 0x950F) || \ 2703 (rdev->ddev->pdev->device == 0x689C) || \ 2704 (rdev->ddev->pdev->device == 0x689D)) 2705 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2706 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2707 (rdev->family == CHIP_RS690) || \ 2708 (rdev->family == CHIP_RS740) || \ 2709 (rdev->family >= CHIP_R600)) 2710 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2711 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2712 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2713 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2714 (rdev->flags & RADEON_IS_IGP)) 2715 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2716 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2717 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2718 (rdev->flags & RADEON_IS_IGP)) 2719 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2720 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2721 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2722 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2723 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2724 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2725 (rdev->family == CHIP_MULLINS)) 2726 2727 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2728 (rdev->ddev->pdev->device == 0x6850) || \ 2729 (rdev->ddev->pdev->device == 0x6858) || \ 2730 (rdev->ddev->pdev->device == 0x6859) || \ 2731 (rdev->ddev->pdev->device == 0x6840) || \ 2732 (rdev->ddev->pdev->device == 0x6841) || \ 2733 (rdev->ddev->pdev->device == 0x6842) || \ 2734 (rdev->ddev->pdev->device == 0x6843)) 2735 2736 /* 2737 * BIOS helpers. 2738 */ 2739 #define RBIOS8(i) (rdev->bios[i]) 2740 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2741 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2742 2743 int radeon_combios_init(struct radeon_device *rdev); 2744 void radeon_combios_fini(struct radeon_device *rdev); 2745 int radeon_atombios_init(struct radeon_device *rdev); 2746 void radeon_atombios_fini(struct radeon_device *rdev); 2747 2748 2749 /* 2750 * RING helpers. 2751 */ 2752 2753 /** 2754 * radeon_ring_write - write a value to the ring 2755 * 2756 * @ring: radeon_ring structure holding ring information 2757 * @v: dword (dw) value to write 2758 * 2759 * Write a value to the requested ring buffer (all asics). 2760 */ 2761 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2762 { 2763 if (ring->count_dw <= 0) 2764 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2765 2766 ring->ring[ring->wptr++] = v; 2767 ring->wptr &= ring->ptr_mask; 2768 ring->count_dw--; 2769 ring->ring_free_dw--; 2770 } 2771 2772 /* 2773 * ASICs macro. 2774 */ 2775 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2776 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2777 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2778 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2779 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2780 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2781 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2782 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2783 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) 2784 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2785 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2786 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2787 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2788 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2789 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2790 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2791 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2792 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2793 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2794 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2795 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2796 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) 2797 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2798 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2799 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2800 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2801 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2802 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2803 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2804 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2805 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2806 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2807 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2808 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2809 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2810 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2811 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2812 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2813 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2814 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2815 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2816 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2817 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2818 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2819 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2820 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2821 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2822 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2823 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2824 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2825 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2826 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2827 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2828 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2829 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2830 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2831 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2832 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2833 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2834 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2835 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2836 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2837 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2838 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2839 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2840 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2841 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2842 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2843 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2844 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2845 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2846 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2847 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2848 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2849 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2850 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2851 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2852 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2853 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2854 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2855 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2856 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2857 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2858 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2859 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2860 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2861 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2862 2863 /* Common functions */ 2864 /* AGP */ 2865 extern int radeon_gpu_reset(struct radeon_device *rdev); 2866 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2867 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2868 extern void radeon_agp_disable(struct radeon_device *rdev); 2869 extern int radeon_modeset_init(struct radeon_device *rdev); 2870 extern void radeon_modeset_fini(struct radeon_device *rdev); 2871 extern bool radeon_card_posted(struct radeon_device *rdev); 2872 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2873 extern void radeon_update_display_priority(struct radeon_device *rdev); 2874 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2875 extern void radeon_scratch_init(struct radeon_device *rdev); 2876 extern void radeon_wb_fini(struct radeon_device *rdev); 2877 extern int radeon_wb_init(struct radeon_device *rdev); 2878 extern void radeon_wb_disable(struct radeon_device *rdev); 2879 extern void radeon_surface_init(struct radeon_device *rdev); 2880 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2881 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2882 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2883 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2884 uint32_t flags); 2885 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2886 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2887 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2888 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2889 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2890 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2891 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2892 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2893 const u32 *registers, 2894 const u32 array_size); 2895 2896 /* 2897 * vm 2898 */ 2899 int radeon_vm_manager_init(struct radeon_device *rdev); 2900 void radeon_vm_manager_fini(struct radeon_device *rdev); 2901 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2902 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2903 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2904 struct radeon_vm *vm, 2905 struct list_head *head); 2906 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2907 struct radeon_vm *vm, int ring); 2908 void radeon_vm_flush(struct radeon_device *rdev, 2909 struct radeon_vm *vm, 2910 int ring); 2911 void radeon_vm_fence(struct radeon_device *rdev, 2912 struct radeon_vm *vm, 2913 struct radeon_fence *fence); 2914 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2915 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2916 struct radeon_vm *vm); 2917 int radeon_vm_clear_freed(struct radeon_device *rdev, 2918 struct radeon_vm *vm); 2919 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2920 struct radeon_vm *vm); 2921 int radeon_vm_bo_update(struct radeon_device *rdev, 2922 struct radeon_bo_va *bo_va, 2923 struct ttm_mem_reg *mem); 2924 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2925 struct radeon_bo *bo); 2926 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2927 struct radeon_bo *bo); 2928 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2929 struct radeon_vm *vm, 2930 struct radeon_bo *bo); 2931 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2932 struct radeon_bo_va *bo_va, 2933 uint64_t offset, 2934 uint32_t flags); 2935 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2936 struct radeon_bo_va *bo_va); 2937 2938 /* audio */ 2939 void r600_audio_update_hdmi(struct work_struct *work); 2940 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2941 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2942 void r600_audio_enable(struct radeon_device *rdev, 2943 struct r600_audio_pin *pin, 2944 u8 enable_mask); 2945 void dce6_audio_enable(struct radeon_device *rdev, 2946 struct r600_audio_pin *pin, 2947 u8 enable_mask); 2948 2949 /* 2950 * R600 vram scratch functions 2951 */ 2952 int r600_vram_scratch_init(struct radeon_device *rdev); 2953 void r600_vram_scratch_fini(struct radeon_device *rdev); 2954 2955 /* 2956 * r600 cs checking helper 2957 */ 2958 unsigned r600_mip_minify(unsigned size, unsigned level); 2959 bool r600_fmt_is_valid_color(u32 format); 2960 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2961 int r600_fmt_get_blocksize(u32 format); 2962 int r600_fmt_get_nblocksx(u32 format, u32 w); 2963 int r600_fmt_get_nblocksy(u32 format, u32 h); 2964 2965 /* 2966 * r600 functions used by radeon_encoder.c 2967 */ 2968 struct radeon_hdmi_acr { 2969 u32 clock; 2970 2971 int n_32khz; 2972 int cts_32khz; 2973 2974 int n_44_1khz; 2975 int cts_44_1khz; 2976 2977 int n_48khz; 2978 int cts_48khz; 2979 2980 }; 2981 2982 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2983 2984 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2985 u32 tiling_pipe_num, 2986 u32 max_rb_num, 2987 u32 total_max_rb_num, 2988 u32 enabled_rb_mask); 2989 2990 /* 2991 * evergreen functions used by radeon_encoder.c 2992 */ 2993 2994 extern int ni_init_microcode(struct radeon_device *rdev); 2995 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2996 extern void ni_fini_microcode(struct radeon_device *rdev); 2997 2998 /* radeon_acpi.c */ 2999 extern int radeon_acpi_init(struct radeon_device *rdev); 3000 extern void radeon_acpi_fini(struct radeon_device *rdev); 3001 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 3002 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 3003 u8 perf_req, bool advertise); 3004 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 3005 3006 /* Prototypes added by @dumbbell. */ 3007 3008 /* atombios_encoders.c */ 3009 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 3010 struct drm_connector *drm_connector); 3011 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 3012 uint32_t supported_device, u16 caps); 3013 3014 /* radeon_atombios.c */ 3015 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 3016 struct drm_display_mode *mode); 3017 3018 /* radeon_legacy_encoders.c */ 3019 void radeon_add_legacy_encoder(struct drm_device *dev, 3020 uint32_t encoder_enum, uint32_t supported_device); 3021 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 3022 struct drm_connector *drm_connector); 3023 3024 /* radeon_pm.c */ 3025 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 3026 3027 /* radeon_ttm.c */ 3028 int radeon_ttm_init(struct radeon_device *rdev); 3029 void radeon_ttm_fini(struct radeon_device *rdev); 3030 3031 /* r600.c */ 3032 int r600_ih_ring_alloc(struct radeon_device *rdev); 3033 void r600_ih_ring_fini(struct radeon_device *rdev); 3034 3035 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3036 struct radeon_cs_packet *pkt, 3037 unsigned idx); 3038 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3039 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3040 struct radeon_cs_packet *pkt); 3041 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3042 struct radeon_cs_reloc **cs_reloc, 3043 int nomm); 3044 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3045 uint32_t *vline_start_end, 3046 uint32_t *vline_status); 3047 3048 #include "radeon_object.h" 3049 3050 #endif 3051