1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "atom.h" 36 #include "rv770_dpm.h" 37 #include "ni_dpm.h" 38 39 /* 40 * Registers accessors functions. 41 */ 42 /** 43 * radeon_invalid_rreg - dummy reg read function 44 * 45 * @rdev: radeon device pointer 46 * @reg: offset of register 47 * 48 * Dummy register read function. Used for register blocks 49 * that certain asics don't have (all asics). 50 * Returns the value in the register. 51 */ 52 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 53 { 54 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 55 BUG_ON(1); 56 return 0; 57 } 58 59 /** 60 * radeon_invalid_wreg - dummy reg write function 61 * 62 * @rdev: radeon device pointer 63 * @reg: offset of register 64 * @v: value to write to the register 65 * 66 * Dummy register read function. Used for register blocks 67 * that certain asics don't have (all asics). 68 */ 69 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 70 { 71 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 72 reg, v); 73 BUG_ON(1); 74 } 75 76 /** 77 * radeon_register_accessor_init - sets up the register accessor callbacks 78 * 79 * @rdev: radeon device pointer 80 * 81 * Sets up the register accessor callbacks for various register 82 * apertures. Not all asics have all apertures (all asics). 83 */ 84 static void radeon_register_accessor_init(struct radeon_device *rdev) 85 { 86 rdev->mc_rreg = &radeon_invalid_rreg; 87 rdev->mc_wreg = &radeon_invalid_wreg; 88 rdev->pll_rreg = &radeon_invalid_rreg; 89 rdev->pll_wreg = &radeon_invalid_wreg; 90 rdev->pciep_rreg = &radeon_invalid_rreg; 91 rdev->pciep_wreg = &radeon_invalid_wreg; 92 93 /* Don't change order as we are overridding accessor. */ 94 if (rdev->family < CHIP_RV515) { 95 rdev->pcie_reg_mask = 0xff; 96 } else { 97 rdev->pcie_reg_mask = 0x7ff; 98 } 99 /* FIXME: not sure here */ 100 if (rdev->family <= CHIP_R580) { 101 rdev->pll_rreg = &r100_pll_rreg; 102 rdev->pll_wreg = &r100_pll_wreg; 103 } 104 if (rdev->family >= CHIP_R420) { 105 rdev->mc_rreg = &r420_mc_rreg; 106 rdev->mc_wreg = &r420_mc_wreg; 107 } 108 if (rdev->family >= CHIP_RV515) { 109 rdev->mc_rreg = &rv515_mc_rreg; 110 rdev->mc_wreg = &rv515_mc_wreg; 111 } 112 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 113 rdev->mc_rreg = &rs400_mc_rreg; 114 rdev->mc_wreg = &rs400_mc_wreg; 115 } 116 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 117 rdev->mc_rreg = &rs690_mc_rreg; 118 rdev->mc_wreg = &rs690_mc_wreg; 119 } 120 if (rdev->family == CHIP_RS600) { 121 rdev->mc_rreg = &rs600_mc_rreg; 122 rdev->mc_wreg = &rs600_mc_wreg; 123 } 124 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 125 rdev->mc_rreg = &rs780_mc_rreg; 126 rdev->mc_wreg = &rs780_mc_wreg; 127 } 128 129 if (rdev->family >= CHIP_BONAIRE) { 130 rdev->pciep_rreg = &cik_pciep_rreg; 131 rdev->pciep_wreg = &cik_pciep_wreg; 132 } else if (rdev->family >= CHIP_R600) { 133 rdev->pciep_rreg = &r600_pciep_rreg; 134 rdev->pciep_wreg = &r600_pciep_wreg; 135 } 136 } 137 138 139 /* helper to disable agp */ 140 /** 141 * radeon_agp_disable - AGP disable helper function 142 * 143 * @rdev: radeon device pointer 144 * 145 * Removes AGP flags and changes the gart callbacks on AGP 146 * cards when using the internal gart rather than AGP (all asics). 147 */ 148 void radeon_agp_disable(struct radeon_device *rdev) 149 { 150 rdev->flags &= ~RADEON_IS_AGP; 151 if (rdev->family >= CHIP_R600) { 152 DRM_INFO("Forcing AGP to PCIE mode\n"); 153 rdev->flags |= RADEON_IS_PCIE; 154 } else if (rdev->family >= CHIP_RV515 || 155 rdev->family == CHIP_RV380 || 156 rdev->family == CHIP_RV410 || 157 rdev->family == CHIP_R423) { 158 DRM_INFO("Forcing AGP to PCIE mode\n"); 159 rdev->flags |= RADEON_IS_PCIE; 160 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 161 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 162 } else { 163 DRM_INFO("Forcing AGP to PCI mode\n"); 164 rdev->flags |= RADEON_IS_PCI; 165 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 166 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 167 } 168 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 169 } 170 171 /* 172 * ASIC 173 */ 174 175 static struct radeon_asic_ring r100_gfx_ring = { 176 .ib_execute = &r100_ring_ib_execute, 177 .emit_fence = &r100_fence_ring_emit, 178 .emit_semaphore = &r100_semaphore_ring_emit, 179 .cs_parse = &r100_cs_parse, 180 .ring_start = &r100_ring_start, 181 .ring_test = &r100_ring_test, 182 .ib_test = &r100_ib_test, 183 .is_lockup = &r100_gpu_is_lockup, 184 .get_rptr = &r100_gfx_get_rptr, 185 .get_wptr = &r100_gfx_get_wptr, 186 .set_wptr = &r100_gfx_set_wptr, 187 }; 188 189 static struct radeon_asic r100_asic = { 190 .init = &r100_init, 191 .fini = &r100_fini, 192 .suspend = &r100_suspend, 193 .resume = &r100_resume, 194 .vga_set_state = &r100_vga_set_state, 195 .asic_reset = &r100_asic_reset, 196 .mmio_hdp_flush = NULL, 197 .gui_idle = &r100_gui_idle, 198 .mc_wait_for_idle = &r100_mc_wait_for_idle, 199 .gart = { 200 .tlb_flush = &r100_pci_gart_tlb_flush, 201 .set_page = &r100_pci_gart_set_page, 202 }, 203 .ring = { 204 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 205 }, 206 .irq = { 207 .set = &r100_irq_set, 208 .process = &r100_irq_process, 209 }, 210 .display = { 211 .bandwidth_update = &r100_bandwidth_update, 212 .get_vblank_counter = &r100_get_vblank_counter, 213 .wait_for_vblank = &r100_wait_for_vblank, 214 .set_backlight_level = &radeon_legacy_set_backlight_level, 215 .get_backlight_level = &radeon_legacy_get_backlight_level, 216 }, 217 .copy = { 218 .blit = &r100_copy_blit, 219 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 220 .dma = NULL, 221 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 222 .copy = &r100_copy_blit, 223 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 224 }, 225 .surface = { 226 .set_reg = r100_set_surface_reg, 227 .clear_reg = r100_clear_surface_reg, 228 }, 229 .hpd = { 230 .init = &r100_hpd_init, 231 .fini = &r100_hpd_fini, 232 .sense = &r100_hpd_sense, 233 .set_polarity = &r100_hpd_set_polarity, 234 }, 235 .pm = { 236 .misc = &r100_pm_misc, 237 .prepare = &r100_pm_prepare, 238 .finish = &r100_pm_finish, 239 .init_profile = &r100_pm_init_profile, 240 .get_dynpm_state = &r100_pm_get_dynpm_state, 241 .get_engine_clock = &radeon_legacy_get_engine_clock, 242 .set_engine_clock = &radeon_legacy_set_engine_clock, 243 .get_memory_clock = &radeon_legacy_get_memory_clock, 244 .set_memory_clock = NULL, 245 .get_pcie_lanes = NULL, 246 .set_pcie_lanes = NULL, 247 .set_clock_gating = &radeon_legacy_set_clock_gating, 248 }, 249 .pflip = { 250 .page_flip = &r100_page_flip, 251 .page_flip_pending = &r100_page_flip_pending, 252 }, 253 }; 254 255 static struct radeon_asic r200_asic = { 256 .init = &r100_init, 257 .fini = &r100_fini, 258 .suspend = &r100_suspend, 259 .resume = &r100_resume, 260 .vga_set_state = &r100_vga_set_state, 261 .asic_reset = &r100_asic_reset, 262 .mmio_hdp_flush = NULL, 263 .gui_idle = &r100_gui_idle, 264 .mc_wait_for_idle = &r100_mc_wait_for_idle, 265 .gart = { 266 .tlb_flush = &r100_pci_gart_tlb_flush, 267 .set_page = &r100_pci_gart_set_page, 268 }, 269 .ring = { 270 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 271 }, 272 .irq = { 273 .set = &r100_irq_set, 274 .process = &r100_irq_process, 275 }, 276 .display = { 277 .bandwidth_update = &r100_bandwidth_update, 278 .get_vblank_counter = &r100_get_vblank_counter, 279 .wait_for_vblank = &r100_wait_for_vblank, 280 .set_backlight_level = &radeon_legacy_set_backlight_level, 281 .get_backlight_level = &radeon_legacy_get_backlight_level, 282 }, 283 .copy = { 284 .blit = &r100_copy_blit, 285 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 286 .dma = &r200_copy_dma, 287 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 288 .copy = &r100_copy_blit, 289 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 290 }, 291 .surface = { 292 .set_reg = r100_set_surface_reg, 293 .clear_reg = r100_clear_surface_reg, 294 }, 295 .hpd = { 296 .init = &r100_hpd_init, 297 .fini = &r100_hpd_fini, 298 .sense = &r100_hpd_sense, 299 .set_polarity = &r100_hpd_set_polarity, 300 }, 301 .pm = { 302 .misc = &r100_pm_misc, 303 .prepare = &r100_pm_prepare, 304 .finish = &r100_pm_finish, 305 .init_profile = &r100_pm_init_profile, 306 .get_dynpm_state = &r100_pm_get_dynpm_state, 307 .get_engine_clock = &radeon_legacy_get_engine_clock, 308 .set_engine_clock = &radeon_legacy_set_engine_clock, 309 .get_memory_clock = &radeon_legacy_get_memory_clock, 310 .set_memory_clock = NULL, 311 .get_pcie_lanes = NULL, 312 .set_pcie_lanes = NULL, 313 .set_clock_gating = &radeon_legacy_set_clock_gating, 314 }, 315 .pflip = { 316 .page_flip = &r100_page_flip, 317 .page_flip_pending = &r100_page_flip_pending, 318 }, 319 }; 320 321 static struct radeon_asic_ring r300_gfx_ring = { 322 .ib_execute = &r100_ring_ib_execute, 323 .emit_fence = &r300_fence_ring_emit, 324 .emit_semaphore = &r100_semaphore_ring_emit, 325 .cs_parse = &r300_cs_parse, 326 .ring_start = &r300_ring_start, 327 .ring_test = &r100_ring_test, 328 .ib_test = &r100_ib_test, 329 .is_lockup = &r100_gpu_is_lockup, 330 .get_rptr = &r100_gfx_get_rptr, 331 .get_wptr = &r100_gfx_get_wptr, 332 .set_wptr = &r100_gfx_set_wptr, 333 }; 334 335 static struct radeon_asic r300_asic = { 336 .init = &r300_init, 337 .fini = &r300_fini, 338 .suspend = &r300_suspend, 339 .resume = &r300_resume, 340 .vga_set_state = &r100_vga_set_state, 341 .asic_reset = &r300_asic_reset, 342 .mmio_hdp_flush = NULL, 343 .gui_idle = &r100_gui_idle, 344 .mc_wait_for_idle = &r300_mc_wait_for_idle, 345 .gart = { 346 .tlb_flush = &r100_pci_gart_tlb_flush, 347 .set_page = &r100_pci_gart_set_page, 348 }, 349 .ring = { 350 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 351 }, 352 .irq = { 353 .set = &r100_irq_set, 354 .process = &r100_irq_process, 355 }, 356 .display = { 357 .bandwidth_update = &r100_bandwidth_update, 358 .get_vblank_counter = &r100_get_vblank_counter, 359 .wait_for_vblank = &r100_wait_for_vblank, 360 .set_backlight_level = &radeon_legacy_set_backlight_level, 361 .get_backlight_level = &radeon_legacy_get_backlight_level, 362 }, 363 .copy = { 364 .blit = &r100_copy_blit, 365 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 366 .dma = &r200_copy_dma, 367 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 368 .copy = &r100_copy_blit, 369 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 370 }, 371 .surface = { 372 .set_reg = r100_set_surface_reg, 373 .clear_reg = r100_clear_surface_reg, 374 }, 375 .hpd = { 376 .init = &r100_hpd_init, 377 .fini = &r100_hpd_fini, 378 .sense = &r100_hpd_sense, 379 .set_polarity = &r100_hpd_set_polarity, 380 }, 381 .pm = { 382 .misc = &r100_pm_misc, 383 .prepare = &r100_pm_prepare, 384 .finish = &r100_pm_finish, 385 .init_profile = &r100_pm_init_profile, 386 .get_dynpm_state = &r100_pm_get_dynpm_state, 387 .get_engine_clock = &radeon_legacy_get_engine_clock, 388 .set_engine_clock = &radeon_legacy_set_engine_clock, 389 .get_memory_clock = &radeon_legacy_get_memory_clock, 390 .set_memory_clock = NULL, 391 .get_pcie_lanes = &rv370_get_pcie_lanes, 392 .set_pcie_lanes = &rv370_set_pcie_lanes, 393 .set_clock_gating = &radeon_legacy_set_clock_gating, 394 }, 395 .pflip = { 396 .page_flip = &r100_page_flip, 397 .page_flip_pending = &r100_page_flip_pending, 398 }, 399 }; 400 401 static struct radeon_asic r300_asic_pcie = { 402 .init = &r300_init, 403 .fini = &r300_fini, 404 .suspend = &r300_suspend, 405 .resume = &r300_resume, 406 .vga_set_state = &r100_vga_set_state, 407 .asic_reset = &r300_asic_reset, 408 .mmio_hdp_flush = NULL, 409 .gui_idle = &r100_gui_idle, 410 .mc_wait_for_idle = &r300_mc_wait_for_idle, 411 .gart = { 412 .tlb_flush = &rv370_pcie_gart_tlb_flush, 413 .set_page = &rv370_pcie_gart_set_page, 414 }, 415 .ring = { 416 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 417 }, 418 .irq = { 419 .set = &r100_irq_set, 420 .process = &r100_irq_process, 421 }, 422 .display = { 423 .bandwidth_update = &r100_bandwidth_update, 424 .get_vblank_counter = &r100_get_vblank_counter, 425 .wait_for_vblank = &r100_wait_for_vblank, 426 .set_backlight_level = &radeon_legacy_set_backlight_level, 427 .get_backlight_level = &radeon_legacy_get_backlight_level, 428 }, 429 .copy = { 430 .blit = &r100_copy_blit, 431 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 432 .dma = &r200_copy_dma, 433 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 434 .copy = &r100_copy_blit, 435 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 436 }, 437 .surface = { 438 .set_reg = r100_set_surface_reg, 439 .clear_reg = r100_clear_surface_reg, 440 }, 441 .hpd = { 442 .init = &r100_hpd_init, 443 .fini = &r100_hpd_fini, 444 .sense = &r100_hpd_sense, 445 .set_polarity = &r100_hpd_set_polarity, 446 }, 447 .pm = { 448 .misc = &r100_pm_misc, 449 .prepare = &r100_pm_prepare, 450 .finish = &r100_pm_finish, 451 .init_profile = &r100_pm_init_profile, 452 .get_dynpm_state = &r100_pm_get_dynpm_state, 453 .get_engine_clock = &radeon_legacy_get_engine_clock, 454 .set_engine_clock = &radeon_legacy_set_engine_clock, 455 .get_memory_clock = &radeon_legacy_get_memory_clock, 456 .set_memory_clock = NULL, 457 .get_pcie_lanes = &rv370_get_pcie_lanes, 458 .set_pcie_lanes = &rv370_set_pcie_lanes, 459 .set_clock_gating = &radeon_legacy_set_clock_gating, 460 }, 461 .pflip = { 462 .page_flip = &r100_page_flip, 463 .page_flip_pending = &r100_page_flip_pending, 464 }, 465 }; 466 467 static struct radeon_asic r420_asic = { 468 .init = &r420_init, 469 .fini = &r420_fini, 470 .suspend = &r420_suspend, 471 .resume = &r420_resume, 472 .vga_set_state = &r100_vga_set_state, 473 .asic_reset = &r300_asic_reset, 474 .mmio_hdp_flush = NULL, 475 .gui_idle = &r100_gui_idle, 476 .mc_wait_for_idle = &r300_mc_wait_for_idle, 477 .gart = { 478 .tlb_flush = &rv370_pcie_gart_tlb_flush, 479 .set_page = &rv370_pcie_gart_set_page, 480 }, 481 .ring = { 482 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 483 }, 484 .irq = { 485 .set = &r100_irq_set, 486 .process = &r100_irq_process, 487 }, 488 .display = { 489 .bandwidth_update = &r100_bandwidth_update, 490 .get_vblank_counter = &r100_get_vblank_counter, 491 .wait_for_vblank = &r100_wait_for_vblank, 492 .set_backlight_level = &atombios_set_backlight_level, 493 .get_backlight_level = &atombios_get_backlight_level, 494 }, 495 .copy = { 496 .blit = &r100_copy_blit, 497 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 498 .dma = &r200_copy_dma, 499 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 500 .copy = &r100_copy_blit, 501 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 502 }, 503 .surface = { 504 .set_reg = r100_set_surface_reg, 505 .clear_reg = r100_clear_surface_reg, 506 }, 507 .hpd = { 508 .init = &r100_hpd_init, 509 .fini = &r100_hpd_fini, 510 .sense = &r100_hpd_sense, 511 .set_polarity = &r100_hpd_set_polarity, 512 }, 513 .pm = { 514 .misc = &r100_pm_misc, 515 .prepare = &r100_pm_prepare, 516 .finish = &r100_pm_finish, 517 .init_profile = &r420_pm_init_profile, 518 .get_dynpm_state = &r100_pm_get_dynpm_state, 519 .get_engine_clock = &radeon_atom_get_engine_clock, 520 .set_engine_clock = &radeon_atom_set_engine_clock, 521 .get_memory_clock = &radeon_atom_get_memory_clock, 522 .set_memory_clock = &radeon_atom_set_memory_clock, 523 .get_pcie_lanes = &rv370_get_pcie_lanes, 524 .set_pcie_lanes = &rv370_set_pcie_lanes, 525 .set_clock_gating = &radeon_atom_set_clock_gating, 526 }, 527 .pflip = { 528 .page_flip = &r100_page_flip, 529 .page_flip_pending = &r100_page_flip_pending, 530 }, 531 }; 532 533 static struct radeon_asic rs400_asic = { 534 .init = &rs400_init, 535 .fini = &rs400_fini, 536 .suspend = &rs400_suspend, 537 .resume = &rs400_resume, 538 .vga_set_state = &r100_vga_set_state, 539 .asic_reset = &r300_asic_reset, 540 .mmio_hdp_flush = NULL, 541 .gui_idle = &r100_gui_idle, 542 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 543 .gart = { 544 .tlb_flush = &rs400_gart_tlb_flush, 545 .set_page = &rs400_gart_set_page, 546 }, 547 .ring = { 548 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 549 }, 550 .irq = { 551 .set = &r100_irq_set, 552 .process = &r100_irq_process, 553 }, 554 .display = { 555 .bandwidth_update = &r100_bandwidth_update, 556 .get_vblank_counter = &r100_get_vblank_counter, 557 .wait_for_vblank = &r100_wait_for_vblank, 558 .set_backlight_level = &radeon_legacy_set_backlight_level, 559 .get_backlight_level = &radeon_legacy_get_backlight_level, 560 }, 561 .copy = { 562 .blit = &r100_copy_blit, 563 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 564 .dma = &r200_copy_dma, 565 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 566 .copy = &r100_copy_blit, 567 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 568 }, 569 .surface = { 570 .set_reg = r100_set_surface_reg, 571 .clear_reg = r100_clear_surface_reg, 572 }, 573 .hpd = { 574 .init = &r100_hpd_init, 575 .fini = &r100_hpd_fini, 576 .sense = &r100_hpd_sense, 577 .set_polarity = &r100_hpd_set_polarity, 578 }, 579 .pm = { 580 .misc = &r100_pm_misc, 581 .prepare = &r100_pm_prepare, 582 .finish = &r100_pm_finish, 583 .init_profile = &r100_pm_init_profile, 584 .get_dynpm_state = &r100_pm_get_dynpm_state, 585 .get_engine_clock = &radeon_legacy_get_engine_clock, 586 .set_engine_clock = &radeon_legacy_set_engine_clock, 587 .get_memory_clock = &radeon_legacy_get_memory_clock, 588 .set_memory_clock = NULL, 589 .get_pcie_lanes = NULL, 590 .set_pcie_lanes = NULL, 591 .set_clock_gating = &radeon_legacy_set_clock_gating, 592 }, 593 .pflip = { 594 .page_flip = &r100_page_flip, 595 .page_flip_pending = &r100_page_flip_pending, 596 }, 597 }; 598 599 static struct radeon_asic rs600_asic = { 600 .init = &rs600_init, 601 .fini = &rs600_fini, 602 .suspend = &rs600_suspend, 603 .resume = &rs600_resume, 604 .vga_set_state = &r100_vga_set_state, 605 .asic_reset = &rs600_asic_reset, 606 .mmio_hdp_flush = NULL, 607 .gui_idle = &r100_gui_idle, 608 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 609 .gart = { 610 .tlb_flush = &rs600_gart_tlb_flush, 611 .set_page = &rs600_gart_set_page, 612 }, 613 .ring = { 614 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 615 }, 616 .irq = { 617 .set = &rs600_irq_set, 618 .process = &rs600_irq_process, 619 }, 620 .display = { 621 .bandwidth_update = &rs600_bandwidth_update, 622 .get_vblank_counter = &rs600_get_vblank_counter, 623 .wait_for_vblank = &avivo_wait_for_vblank, 624 .set_backlight_level = &atombios_set_backlight_level, 625 .get_backlight_level = &atombios_get_backlight_level, 626 .hdmi_enable = &r600_hdmi_enable, 627 .hdmi_setmode = &r600_hdmi_setmode, 628 }, 629 .copy = { 630 .blit = &r100_copy_blit, 631 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 632 .dma = &r200_copy_dma, 633 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 634 .copy = &r100_copy_blit, 635 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 636 }, 637 .surface = { 638 .set_reg = r100_set_surface_reg, 639 .clear_reg = r100_clear_surface_reg, 640 }, 641 .hpd = { 642 .init = &rs600_hpd_init, 643 .fini = &rs600_hpd_fini, 644 .sense = &rs600_hpd_sense, 645 .set_polarity = &rs600_hpd_set_polarity, 646 }, 647 .pm = { 648 .misc = &rs600_pm_misc, 649 .prepare = &rs600_pm_prepare, 650 .finish = &rs600_pm_finish, 651 .init_profile = &r420_pm_init_profile, 652 .get_dynpm_state = &r100_pm_get_dynpm_state, 653 .get_engine_clock = &radeon_atom_get_engine_clock, 654 .set_engine_clock = &radeon_atom_set_engine_clock, 655 .get_memory_clock = &radeon_atom_get_memory_clock, 656 .set_memory_clock = &radeon_atom_set_memory_clock, 657 .get_pcie_lanes = NULL, 658 .set_pcie_lanes = NULL, 659 .set_clock_gating = &radeon_atom_set_clock_gating, 660 }, 661 .pflip = { 662 .page_flip = &rs600_page_flip, 663 .page_flip_pending = &rs600_page_flip_pending, 664 }, 665 }; 666 667 static struct radeon_asic rs690_asic = { 668 .init = &rs690_init, 669 .fini = &rs690_fini, 670 .suspend = &rs690_suspend, 671 .resume = &rs690_resume, 672 .vga_set_state = &r100_vga_set_state, 673 .asic_reset = &rs600_asic_reset, 674 .mmio_hdp_flush = NULL, 675 .gui_idle = &r100_gui_idle, 676 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 677 .gart = { 678 .tlb_flush = &rs400_gart_tlb_flush, 679 .set_page = &rs400_gart_set_page, 680 }, 681 .ring = { 682 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 683 }, 684 .irq = { 685 .set = &rs600_irq_set, 686 .process = &rs600_irq_process, 687 }, 688 .display = { 689 .get_vblank_counter = &rs600_get_vblank_counter, 690 .bandwidth_update = &rs690_bandwidth_update, 691 .wait_for_vblank = &avivo_wait_for_vblank, 692 .set_backlight_level = &atombios_set_backlight_level, 693 .get_backlight_level = &atombios_get_backlight_level, 694 .hdmi_enable = &r600_hdmi_enable, 695 .hdmi_setmode = &r600_hdmi_setmode, 696 }, 697 .copy = { 698 .blit = &r100_copy_blit, 699 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 700 .dma = &r200_copy_dma, 701 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 702 .copy = &r200_copy_dma, 703 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 704 }, 705 .surface = { 706 .set_reg = r100_set_surface_reg, 707 .clear_reg = r100_clear_surface_reg, 708 }, 709 .hpd = { 710 .init = &rs600_hpd_init, 711 .fini = &rs600_hpd_fini, 712 .sense = &rs600_hpd_sense, 713 .set_polarity = &rs600_hpd_set_polarity, 714 }, 715 .pm = { 716 .misc = &rs600_pm_misc, 717 .prepare = &rs600_pm_prepare, 718 .finish = &rs600_pm_finish, 719 .init_profile = &r420_pm_init_profile, 720 .get_dynpm_state = &r100_pm_get_dynpm_state, 721 .get_engine_clock = &radeon_atom_get_engine_clock, 722 .set_engine_clock = &radeon_atom_set_engine_clock, 723 .get_memory_clock = &radeon_atom_get_memory_clock, 724 .set_memory_clock = &radeon_atom_set_memory_clock, 725 .get_pcie_lanes = NULL, 726 .set_pcie_lanes = NULL, 727 .set_clock_gating = &radeon_atom_set_clock_gating, 728 }, 729 .pflip = { 730 .page_flip = &rs600_page_flip, 731 .page_flip_pending = &rs600_page_flip_pending, 732 }, 733 }; 734 735 static struct radeon_asic rv515_asic = { 736 .init = &rv515_init, 737 .fini = &rv515_fini, 738 .suspend = &rv515_suspend, 739 .resume = &rv515_resume, 740 .vga_set_state = &r100_vga_set_state, 741 .asic_reset = &rs600_asic_reset, 742 .mmio_hdp_flush = NULL, 743 .gui_idle = &r100_gui_idle, 744 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 745 .gart = { 746 .tlb_flush = &rv370_pcie_gart_tlb_flush, 747 .set_page = &rv370_pcie_gart_set_page, 748 }, 749 .ring = { 750 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 751 }, 752 .irq = { 753 .set = &rs600_irq_set, 754 .process = &rs600_irq_process, 755 }, 756 .display = { 757 .get_vblank_counter = &rs600_get_vblank_counter, 758 .bandwidth_update = &rv515_bandwidth_update, 759 .wait_for_vblank = &avivo_wait_for_vblank, 760 .set_backlight_level = &atombios_set_backlight_level, 761 .get_backlight_level = &atombios_get_backlight_level, 762 }, 763 .copy = { 764 .blit = &r100_copy_blit, 765 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 766 .dma = &r200_copy_dma, 767 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 768 .copy = &r100_copy_blit, 769 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 770 }, 771 .surface = { 772 .set_reg = r100_set_surface_reg, 773 .clear_reg = r100_clear_surface_reg, 774 }, 775 .hpd = { 776 .init = &rs600_hpd_init, 777 .fini = &rs600_hpd_fini, 778 .sense = &rs600_hpd_sense, 779 .set_polarity = &rs600_hpd_set_polarity, 780 }, 781 .pm = { 782 .misc = &rs600_pm_misc, 783 .prepare = &rs600_pm_prepare, 784 .finish = &rs600_pm_finish, 785 .init_profile = &r420_pm_init_profile, 786 .get_dynpm_state = &r100_pm_get_dynpm_state, 787 .get_engine_clock = &radeon_atom_get_engine_clock, 788 .set_engine_clock = &radeon_atom_set_engine_clock, 789 .get_memory_clock = &radeon_atom_get_memory_clock, 790 .set_memory_clock = &radeon_atom_set_memory_clock, 791 .get_pcie_lanes = &rv370_get_pcie_lanes, 792 .set_pcie_lanes = &rv370_set_pcie_lanes, 793 .set_clock_gating = &radeon_atom_set_clock_gating, 794 }, 795 .pflip = { 796 .page_flip = &rs600_page_flip, 797 .page_flip_pending = &rs600_page_flip_pending, 798 }, 799 }; 800 801 static struct radeon_asic r520_asic = { 802 .init = &r520_init, 803 .fini = &rv515_fini, 804 .suspend = &rv515_suspend, 805 .resume = &r520_resume, 806 .vga_set_state = &r100_vga_set_state, 807 .asic_reset = &rs600_asic_reset, 808 .mmio_hdp_flush = NULL, 809 .gui_idle = &r100_gui_idle, 810 .mc_wait_for_idle = &r520_mc_wait_for_idle, 811 .gart = { 812 .tlb_flush = &rv370_pcie_gart_tlb_flush, 813 .set_page = &rv370_pcie_gart_set_page, 814 }, 815 .ring = { 816 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 817 }, 818 .irq = { 819 .set = &rs600_irq_set, 820 .process = &rs600_irq_process, 821 }, 822 .display = { 823 .bandwidth_update = &rv515_bandwidth_update, 824 .get_vblank_counter = &rs600_get_vblank_counter, 825 .wait_for_vblank = &avivo_wait_for_vblank, 826 .set_backlight_level = &atombios_set_backlight_level, 827 .get_backlight_level = &atombios_get_backlight_level, 828 }, 829 .copy = { 830 .blit = &r100_copy_blit, 831 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 832 .dma = &r200_copy_dma, 833 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 834 .copy = &r100_copy_blit, 835 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 836 }, 837 .surface = { 838 .set_reg = r100_set_surface_reg, 839 .clear_reg = r100_clear_surface_reg, 840 }, 841 .hpd = { 842 .init = &rs600_hpd_init, 843 .fini = &rs600_hpd_fini, 844 .sense = &rs600_hpd_sense, 845 .set_polarity = &rs600_hpd_set_polarity, 846 }, 847 .pm = { 848 .misc = &rs600_pm_misc, 849 .prepare = &rs600_pm_prepare, 850 .finish = &rs600_pm_finish, 851 .init_profile = &r420_pm_init_profile, 852 .get_dynpm_state = &r100_pm_get_dynpm_state, 853 .get_engine_clock = &radeon_atom_get_engine_clock, 854 .set_engine_clock = &radeon_atom_set_engine_clock, 855 .get_memory_clock = &radeon_atom_get_memory_clock, 856 .set_memory_clock = &radeon_atom_set_memory_clock, 857 .get_pcie_lanes = &rv370_get_pcie_lanes, 858 .set_pcie_lanes = &rv370_set_pcie_lanes, 859 .set_clock_gating = &radeon_atom_set_clock_gating, 860 }, 861 .pflip = { 862 .page_flip = &rs600_page_flip, 863 .page_flip_pending = &rs600_page_flip_pending, 864 }, 865 }; 866 867 static struct radeon_asic_ring r600_gfx_ring = { 868 .ib_execute = &r600_ring_ib_execute, 869 .emit_fence = &r600_fence_ring_emit, 870 .emit_semaphore = &r600_semaphore_ring_emit, 871 .cs_parse = &r600_cs_parse, 872 .ring_test = &r600_ring_test, 873 .ib_test = &r600_ib_test, 874 .is_lockup = &r600_gfx_is_lockup, 875 .get_rptr = &r600_gfx_get_rptr, 876 .get_wptr = &r600_gfx_get_wptr, 877 .set_wptr = &r600_gfx_set_wptr, 878 }; 879 880 static struct radeon_asic_ring r600_dma_ring = { 881 .ib_execute = &r600_dma_ring_ib_execute, 882 .emit_fence = &r600_dma_fence_ring_emit, 883 .emit_semaphore = &r600_dma_semaphore_ring_emit, 884 .cs_parse = &r600_dma_cs_parse, 885 .ring_test = &r600_dma_ring_test, 886 .ib_test = &r600_dma_ib_test, 887 .is_lockup = &r600_dma_is_lockup, 888 .get_rptr = &r600_dma_get_rptr, 889 .get_wptr = &r600_dma_get_wptr, 890 .set_wptr = &r600_dma_set_wptr, 891 }; 892 893 static struct radeon_asic r600_asic = { 894 .init = &r600_init, 895 .fini = &r600_fini, 896 .suspend = &r600_suspend, 897 .resume = &r600_resume, 898 .vga_set_state = &r600_vga_set_state, 899 .asic_reset = &r600_asic_reset, 900 .mmio_hdp_flush = r600_mmio_hdp_flush, 901 .gui_idle = &r600_gui_idle, 902 .mc_wait_for_idle = &r600_mc_wait_for_idle, 903 .get_xclk = &r600_get_xclk, 904 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 905 .gart = { 906 .tlb_flush = &r600_pcie_gart_tlb_flush, 907 .set_page = &rs600_gart_set_page, 908 }, 909 .ring = { 910 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 911 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 912 }, 913 .irq = { 914 .set = &r600_irq_set, 915 .process = &r600_irq_process, 916 }, 917 .display = { 918 .bandwidth_update = &rv515_bandwidth_update, 919 .get_vblank_counter = &rs600_get_vblank_counter, 920 .wait_for_vblank = &avivo_wait_for_vblank, 921 .set_backlight_level = &atombios_set_backlight_level, 922 .get_backlight_level = &atombios_get_backlight_level, 923 .hdmi_enable = &r600_hdmi_enable, 924 .hdmi_setmode = &r600_hdmi_setmode, 925 }, 926 .copy = { 927 .blit = &r600_copy_cpdma, 928 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 929 .dma = &r600_copy_dma, 930 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 931 .copy = &r600_copy_cpdma, 932 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 933 }, 934 .surface = { 935 .set_reg = r600_set_surface_reg, 936 .clear_reg = r600_clear_surface_reg, 937 }, 938 .hpd = { 939 .init = &r600_hpd_init, 940 .fini = &r600_hpd_fini, 941 .sense = &r600_hpd_sense, 942 .set_polarity = &r600_hpd_set_polarity, 943 }, 944 .pm = { 945 .misc = &r600_pm_misc, 946 .prepare = &rs600_pm_prepare, 947 .finish = &rs600_pm_finish, 948 .init_profile = &r600_pm_init_profile, 949 .get_dynpm_state = &r600_pm_get_dynpm_state, 950 .get_engine_clock = &radeon_atom_get_engine_clock, 951 .set_engine_clock = &radeon_atom_set_engine_clock, 952 .get_memory_clock = &radeon_atom_get_memory_clock, 953 .set_memory_clock = &radeon_atom_set_memory_clock, 954 .get_pcie_lanes = &r600_get_pcie_lanes, 955 .set_pcie_lanes = &r600_set_pcie_lanes, 956 .set_clock_gating = NULL, 957 .get_temperature = &rv6xx_get_temp, 958 }, 959 .pflip = { 960 .page_flip = &rs600_page_flip, 961 .page_flip_pending = &rs600_page_flip_pending, 962 }, 963 }; 964 965 static struct radeon_asic_ring rv6xx_uvd_ring = { 966 .ib_execute = &uvd_v1_0_ib_execute, 967 .emit_fence = &uvd_v1_0_fence_emit, 968 .emit_semaphore = &uvd_v1_0_semaphore_emit, 969 .cs_parse = &radeon_uvd_cs_parse, 970 .ring_test = &uvd_v1_0_ring_test, 971 .ib_test = &uvd_v1_0_ib_test, 972 .is_lockup = &radeon_ring_test_lockup, 973 .get_rptr = &uvd_v1_0_get_rptr, 974 .get_wptr = &uvd_v1_0_get_wptr, 975 .set_wptr = &uvd_v1_0_set_wptr, 976 }; 977 978 static struct radeon_asic rv6xx_asic = { 979 .init = &r600_init, 980 .fini = &r600_fini, 981 .suspend = &r600_suspend, 982 .resume = &r600_resume, 983 .vga_set_state = &r600_vga_set_state, 984 .asic_reset = &r600_asic_reset, 985 .mmio_hdp_flush = r600_mmio_hdp_flush, 986 .gui_idle = &r600_gui_idle, 987 .mc_wait_for_idle = &r600_mc_wait_for_idle, 988 .get_xclk = &r600_get_xclk, 989 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 990 .gart = { 991 .tlb_flush = &r600_pcie_gart_tlb_flush, 992 .set_page = &rs600_gart_set_page, 993 }, 994 .ring = { 995 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 996 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 997 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 998 }, 999 .irq = { 1000 .set = &r600_irq_set, 1001 .process = &r600_irq_process, 1002 }, 1003 .display = { 1004 .bandwidth_update = &rv515_bandwidth_update, 1005 .get_vblank_counter = &rs600_get_vblank_counter, 1006 .wait_for_vblank = &avivo_wait_for_vblank, 1007 .set_backlight_level = &atombios_set_backlight_level, 1008 .get_backlight_level = &atombios_get_backlight_level, 1009 .hdmi_enable = &r600_hdmi_enable, 1010 .hdmi_setmode = &r600_hdmi_setmode, 1011 }, 1012 .copy = { 1013 .blit = &r600_copy_cpdma, 1014 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1015 .dma = &r600_copy_dma, 1016 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1017 .copy = &r600_copy_cpdma, 1018 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1019 }, 1020 .surface = { 1021 .set_reg = r600_set_surface_reg, 1022 .clear_reg = r600_clear_surface_reg, 1023 }, 1024 .hpd = { 1025 .init = &r600_hpd_init, 1026 .fini = &r600_hpd_fini, 1027 .sense = &r600_hpd_sense, 1028 .set_polarity = &r600_hpd_set_polarity, 1029 }, 1030 .pm = { 1031 .misc = &r600_pm_misc, 1032 .prepare = &rs600_pm_prepare, 1033 .finish = &rs600_pm_finish, 1034 .init_profile = &r600_pm_init_profile, 1035 .get_dynpm_state = &r600_pm_get_dynpm_state, 1036 .get_engine_clock = &radeon_atom_get_engine_clock, 1037 .set_engine_clock = &radeon_atom_set_engine_clock, 1038 .get_memory_clock = &radeon_atom_get_memory_clock, 1039 .set_memory_clock = &radeon_atom_set_memory_clock, 1040 .get_pcie_lanes = &r600_get_pcie_lanes, 1041 .set_pcie_lanes = &r600_set_pcie_lanes, 1042 .set_clock_gating = NULL, 1043 .get_temperature = &rv6xx_get_temp, 1044 .set_uvd_clocks = &r600_set_uvd_clocks, 1045 }, 1046 .dpm = { 1047 .init = &rv6xx_dpm_init, 1048 .setup_asic = &rv6xx_setup_asic, 1049 .enable = &rv6xx_dpm_enable, 1050 .late_enable = &r600_dpm_late_enable, 1051 .disable = &rv6xx_dpm_disable, 1052 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1053 .set_power_state = &rv6xx_dpm_set_power_state, 1054 .post_set_power_state = &r600_dpm_post_set_power_state, 1055 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1056 .fini = &rv6xx_dpm_fini, 1057 .get_sclk = &rv6xx_dpm_get_sclk, 1058 .get_mclk = &rv6xx_dpm_get_mclk, 1059 .print_power_state = &rv6xx_dpm_print_power_state, 1060 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1061 .force_performance_level = &rv6xx_dpm_force_performance_level, 1062 }, 1063 .pflip = { 1064 .page_flip = &rs600_page_flip, 1065 .page_flip_pending = &rs600_page_flip_pending, 1066 }, 1067 }; 1068 1069 static struct radeon_asic rs780_asic = { 1070 .init = &r600_init, 1071 .fini = &r600_fini, 1072 .suspend = &r600_suspend, 1073 .resume = &r600_resume, 1074 .vga_set_state = &r600_vga_set_state, 1075 .asic_reset = &r600_asic_reset, 1076 .mmio_hdp_flush = r600_mmio_hdp_flush, 1077 .gui_idle = &r600_gui_idle, 1078 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1079 .get_xclk = &r600_get_xclk, 1080 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1081 .gart = { 1082 .tlb_flush = &r600_pcie_gart_tlb_flush, 1083 .set_page = &rs600_gart_set_page, 1084 }, 1085 .ring = { 1086 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1087 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1088 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1089 }, 1090 .irq = { 1091 .set = &r600_irq_set, 1092 .process = &r600_irq_process, 1093 }, 1094 .display = { 1095 .bandwidth_update = &rs690_bandwidth_update, 1096 .get_vblank_counter = &rs600_get_vblank_counter, 1097 .wait_for_vblank = &avivo_wait_for_vblank, 1098 .set_backlight_level = &atombios_set_backlight_level, 1099 .get_backlight_level = &atombios_get_backlight_level, 1100 .hdmi_enable = &r600_hdmi_enable, 1101 .hdmi_setmode = &r600_hdmi_setmode, 1102 }, 1103 .copy = { 1104 .blit = &r600_copy_cpdma, 1105 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1106 .dma = &r600_copy_dma, 1107 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1108 .copy = &r600_copy_cpdma, 1109 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1110 }, 1111 .surface = { 1112 .set_reg = r600_set_surface_reg, 1113 .clear_reg = r600_clear_surface_reg, 1114 }, 1115 .hpd = { 1116 .init = &r600_hpd_init, 1117 .fini = &r600_hpd_fini, 1118 .sense = &r600_hpd_sense, 1119 .set_polarity = &r600_hpd_set_polarity, 1120 }, 1121 .pm = { 1122 .misc = &r600_pm_misc, 1123 .prepare = &rs600_pm_prepare, 1124 .finish = &rs600_pm_finish, 1125 .init_profile = &rs780_pm_init_profile, 1126 .get_dynpm_state = &r600_pm_get_dynpm_state, 1127 .get_engine_clock = &radeon_atom_get_engine_clock, 1128 .set_engine_clock = &radeon_atom_set_engine_clock, 1129 .get_memory_clock = NULL, 1130 .set_memory_clock = NULL, 1131 .get_pcie_lanes = NULL, 1132 .set_pcie_lanes = NULL, 1133 .set_clock_gating = NULL, 1134 .get_temperature = &rv6xx_get_temp, 1135 .set_uvd_clocks = &r600_set_uvd_clocks, 1136 }, 1137 .dpm = { 1138 .init = &rs780_dpm_init, 1139 .setup_asic = &rs780_dpm_setup_asic, 1140 .enable = &rs780_dpm_enable, 1141 .late_enable = &r600_dpm_late_enable, 1142 .disable = &rs780_dpm_disable, 1143 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1144 .set_power_state = &rs780_dpm_set_power_state, 1145 .post_set_power_state = &r600_dpm_post_set_power_state, 1146 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1147 .fini = &rs780_dpm_fini, 1148 .get_sclk = &rs780_dpm_get_sclk, 1149 .get_mclk = &rs780_dpm_get_mclk, 1150 .print_power_state = &rs780_dpm_print_power_state, 1151 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, 1152 .force_performance_level = &rs780_dpm_force_performance_level, 1153 }, 1154 .pflip = { 1155 .page_flip = &rs600_page_flip, 1156 .page_flip_pending = &rs600_page_flip_pending, 1157 }, 1158 }; 1159 1160 static struct radeon_asic_ring rv770_uvd_ring = { 1161 .ib_execute = &uvd_v1_0_ib_execute, 1162 .emit_fence = &uvd_v2_2_fence_emit, 1163 .emit_semaphore = &uvd_v1_0_semaphore_emit, 1164 .cs_parse = &radeon_uvd_cs_parse, 1165 .ring_test = &uvd_v1_0_ring_test, 1166 .ib_test = &uvd_v1_0_ib_test, 1167 .is_lockup = &radeon_ring_test_lockup, 1168 .get_rptr = &uvd_v1_0_get_rptr, 1169 .get_wptr = &uvd_v1_0_get_wptr, 1170 .set_wptr = &uvd_v1_0_set_wptr, 1171 }; 1172 1173 static struct radeon_asic rv770_asic = { 1174 .init = &rv770_init, 1175 .fini = &rv770_fini, 1176 .suspend = &rv770_suspend, 1177 .resume = &rv770_resume, 1178 .asic_reset = &r600_asic_reset, 1179 .vga_set_state = &r600_vga_set_state, 1180 .mmio_hdp_flush = r600_mmio_hdp_flush, 1181 .gui_idle = &r600_gui_idle, 1182 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1183 .get_xclk = &rv770_get_xclk, 1184 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1185 .gart = { 1186 .tlb_flush = &r600_pcie_gart_tlb_flush, 1187 .set_page = &rs600_gart_set_page, 1188 }, 1189 .ring = { 1190 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1191 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1192 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1193 }, 1194 .irq = { 1195 .set = &r600_irq_set, 1196 .process = &r600_irq_process, 1197 }, 1198 .display = { 1199 .bandwidth_update = &rv515_bandwidth_update, 1200 .get_vblank_counter = &rs600_get_vblank_counter, 1201 .wait_for_vblank = &avivo_wait_for_vblank, 1202 .set_backlight_level = &atombios_set_backlight_level, 1203 .get_backlight_level = &atombios_get_backlight_level, 1204 .hdmi_enable = &r600_hdmi_enable, 1205 .hdmi_setmode = &dce3_1_hdmi_setmode, 1206 }, 1207 .copy = { 1208 .blit = &r600_copy_cpdma, 1209 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1210 .dma = &rv770_copy_dma, 1211 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1212 .copy = &rv770_copy_dma, 1213 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1214 }, 1215 .surface = { 1216 .set_reg = r600_set_surface_reg, 1217 .clear_reg = r600_clear_surface_reg, 1218 }, 1219 .hpd = { 1220 .init = &r600_hpd_init, 1221 .fini = &r600_hpd_fini, 1222 .sense = &r600_hpd_sense, 1223 .set_polarity = &r600_hpd_set_polarity, 1224 }, 1225 .pm = { 1226 .misc = &rv770_pm_misc, 1227 .prepare = &rs600_pm_prepare, 1228 .finish = &rs600_pm_finish, 1229 .init_profile = &r600_pm_init_profile, 1230 .get_dynpm_state = &r600_pm_get_dynpm_state, 1231 .get_engine_clock = &radeon_atom_get_engine_clock, 1232 .set_engine_clock = &radeon_atom_set_engine_clock, 1233 .get_memory_clock = &radeon_atom_get_memory_clock, 1234 .set_memory_clock = &radeon_atom_set_memory_clock, 1235 .get_pcie_lanes = &r600_get_pcie_lanes, 1236 .set_pcie_lanes = &r600_set_pcie_lanes, 1237 .set_clock_gating = &radeon_atom_set_clock_gating, 1238 .set_uvd_clocks = &rv770_set_uvd_clocks, 1239 .get_temperature = &rv770_get_temp, 1240 }, 1241 .dpm = { 1242 .init = &rv770_dpm_init, 1243 .setup_asic = &rv770_dpm_setup_asic, 1244 .enable = &rv770_dpm_enable, 1245 .late_enable = &rv770_dpm_late_enable, 1246 .disable = &rv770_dpm_disable, 1247 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1248 .set_power_state = &rv770_dpm_set_power_state, 1249 .post_set_power_state = &r600_dpm_post_set_power_state, 1250 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1251 .fini = &rv770_dpm_fini, 1252 .get_sclk = &rv770_dpm_get_sclk, 1253 .get_mclk = &rv770_dpm_get_mclk, 1254 .print_power_state = &rv770_dpm_print_power_state, 1255 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1256 .force_performance_level = &rv770_dpm_force_performance_level, 1257 .vblank_too_short = &rv770_dpm_vblank_too_short, 1258 }, 1259 .pflip = { 1260 .page_flip = &rv770_page_flip, 1261 .page_flip_pending = &rv770_page_flip_pending, 1262 }, 1263 }; 1264 1265 static struct radeon_asic_ring evergreen_gfx_ring = { 1266 .ib_execute = &evergreen_ring_ib_execute, 1267 .emit_fence = &r600_fence_ring_emit, 1268 .emit_semaphore = &r600_semaphore_ring_emit, 1269 .cs_parse = &evergreen_cs_parse, 1270 .ring_test = &r600_ring_test, 1271 .ib_test = &r600_ib_test, 1272 .is_lockup = &evergreen_gfx_is_lockup, 1273 .get_rptr = &r600_gfx_get_rptr, 1274 .get_wptr = &r600_gfx_get_wptr, 1275 .set_wptr = &r600_gfx_set_wptr, 1276 }; 1277 1278 static struct radeon_asic_ring evergreen_dma_ring = { 1279 .ib_execute = &evergreen_dma_ring_ib_execute, 1280 .emit_fence = &evergreen_dma_fence_ring_emit, 1281 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1282 .cs_parse = &evergreen_dma_cs_parse, 1283 .ring_test = &r600_dma_ring_test, 1284 .ib_test = &r600_dma_ib_test, 1285 .is_lockup = &evergreen_dma_is_lockup, 1286 .get_rptr = &r600_dma_get_rptr, 1287 .get_wptr = &r600_dma_get_wptr, 1288 .set_wptr = &r600_dma_set_wptr, 1289 }; 1290 1291 static struct radeon_asic evergreen_asic = { 1292 .init = &evergreen_init, 1293 .fini = &evergreen_fini, 1294 .suspend = &evergreen_suspend, 1295 .resume = &evergreen_resume, 1296 .asic_reset = &evergreen_asic_reset, 1297 .vga_set_state = &r600_vga_set_state, 1298 .mmio_hdp_flush = r600_mmio_hdp_flush, 1299 .gui_idle = &r600_gui_idle, 1300 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1301 .get_xclk = &rv770_get_xclk, 1302 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1303 .gart = { 1304 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1305 .set_page = &rs600_gart_set_page, 1306 }, 1307 .ring = { 1308 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1309 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1310 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1311 }, 1312 .irq = { 1313 .set = &evergreen_irq_set, 1314 .process = &evergreen_irq_process, 1315 }, 1316 .display = { 1317 .bandwidth_update = &evergreen_bandwidth_update, 1318 .get_vblank_counter = &evergreen_get_vblank_counter, 1319 .wait_for_vblank = &dce4_wait_for_vblank, 1320 .set_backlight_level = &atombios_set_backlight_level, 1321 .get_backlight_level = &atombios_get_backlight_level, 1322 .hdmi_enable = &evergreen_hdmi_enable, 1323 .hdmi_setmode = &evergreen_hdmi_setmode, 1324 }, 1325 .copy = { 1326 .blit = &r600_copy_cpdma, 1327 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1328 .dma = &evergreen_copy_dma, 1329 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1330 .copy = &evergreen_copy_dma, 1331 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1332 }, 1333 .surface = { 1334 .set_reg = r600_set_surface_reg, 1335 .clear_reg = r600_clear_surface_reg, 1336 }, 1337 .hpd = { 1338 .init = &evergreen_hpd_init, 1339 .fini = &evergreen_hpd_fini, 1340 .sense = &evergreen_hpd_sense, 1341 .set_polarity = &evergreen_hpd_set_polarity, 1342 }, 1343 .pm = { 1344 .misc = &evergreen_pm_misc, 1345 .prepare = &evergreen_pm_prepare, 1346 .finish = &evergreen_pm_finish, 1347 .init_profile = &r600_pm_init_profile, 1348 .get_dynpm_state = &r600_pm_get_dynpm_state, 1349 .get_engine_clock = &radeon_atom_get_engine_clock, 1350 .set_engine_clock = &radeon_atom_set_engine_clock, 1351 .get_memory_clock = &radeon_atom_get_memory_clock, 1352 .set_memory_clock = &radeon_atom_set_memory_clock, 1353 .get_pcie_lanes = &r600_get_pcie_lanes, 1354 .set_pcie_lanes = &r600_set_pcie_lanes, 1355 .set_clock_gating = NULL, 1356 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1357 .get_temperature = &evergreen_get_temp, 1358 }, 1359 .dpm = { 1360 .init = &cypress_dpm_init, 1361 .setup_asic = &cypress_dpm_setup_asic, 1362 .enable = &cypress_dpm_enable, 1363 .late_enable = &rv770_dpm_late_enable, 1364 .disable = &cypress_dpm_disable, 1365 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1366 .set_power_state = &cypress_dpm_set_power_state, 1367 .post_set_power_state = &r600_dpm_post_set_power_state, 1368 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1369 .fini = &cypress_dpm_fini, 1370 .get_sclk = &rv770_dpm_get_sclk, 1371 .get_mclk = &rv770_dpm_get_mclk, 1372 .print_power_state = &rv770_dpm_print_power_state, 1373 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1374 .force_performance_level = &rv770_dpm_force_performance_level, 1375 .vblank_too_short = &cypress_dpm_vblank_too_short, 1376 }, 1377 .pflip = { 1378 .page_flip = &evergreen_page_flip, 1379 .page_flip_pending = &evergreen_page_flip_pending, 1380 }, 1381 }; 1382 1383 static struct radeon_asic sumo_asic = { 1384 .init = &evergreen_init, 1385 .fini = &evergreen_fini, 1386 .suspend = &evergreen_suspend, 1387 .resume = &evergreen_resume, 1388 .asic_reset = &evergreen_asic_reset, 1389 .vga_set_state = &r600_vga_set_state, 1390 .mmio_hdp_flush = r600_mmio_hdp_flush, 1391 .gui_idle = &r600_gui_idle, 1392 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1393 .get_xclk = &r600_get_xclk, 1394 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1395 .gart = { 1396 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1397 .set_page = &rs600_gart_set_page, 1398 }, 1399 .ring = { 1400 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1401 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1402 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1403 }, 1404 .irq = { 1405 .set = &evergreen_irq_set, 1406 .process = &evergreen_irq_process, 1407 }, 1408 .display = { 1409 .bandwidth_update = &evergreen_bandwidth_update, 1410 .get_vblank_counter = &evergreen_get_vblank_counter, 1411 .wait_for_vblank = &dce4_wait_for_vblank, 1412 .set_backlight_level = &atombios_set_backlight_level, 1413 .get_backlight_level = &atombios_get_backlight_level, 1414 .hdmi_enable = &evergreen_hdmi_enable, 1415 .hdmi_setmode = &evergreen_hdmi_setmode, 1416 }, 1417 .copy = { 1418 .blit = &r600_copy_cpdma, 1419 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1420 .dma = &evergreen_copy_dma, 1421 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1422 .copy = &evergreen_copy_dma, 1423 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1424 }, 1425 .surface = { 1426 .set_reg = r600_set_surface_reg, 1427 .clear_reg = r600_clear_surface_reg, 1428 }, 1429 .hpd = { 1430 .init = &evergreen_hpd_init, 1431 .fini = &evergreen_hpd_fini, 1432 .sense = &evergreen_hpd_sense, 1433 .set_polarity = &evergreen_hpd_set_polarity, 1434 }, 1435 .pm = { 1436 .misc = &evergreen_pm_misc, 1437 .prepare = &evergreen_pm_prepare, 1438 .finish = &evergreen_pm_finish, 1439 .init_profile = &sumo_pm_init_profile, 1440 .get_dynpm_state = &r600_pm_get_dynpm_state, 1441 .get_engine_clock = &radeon_atom_get_engine_clock, 1442 .set_engine_clock = &radeon_atom_set_engine_clock, 1443 .get_memory_clock = NULL, 1444 .set_memory_clock = NULL, 1445 .get_pcie_lanes = NULL, 1446 .set_pcie_lanes = NULL, 1447 .set_clock_gating = NULL, 1448 .set_uvd_clocks = &sumo_set_uvd_clocks, 1449 .get_temperature = &sumo_get_temp, 1450 }, 1451 .dpm = { 1452 .init = &sumo_dpm_init, 1453 .setup_asic = &sumo_dpm_setup_asic, 1454 .enable = &sumo_dpm_enable, 1455 .late_enable = &sumo_dpm_late_enable, 1456 .disable = &sumo_dpm_disable, 1457 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1458 .set_power_state = &sumo_dpm_set_power_state, 1459 .post_set_power_state = &sumo_dpm_post_set_power_state, 1460 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1461 .fini = &sumo_dpm_fini, 1462 .get_sclk = &sumo_dpm_get_sclk, 1463 .get_mclk = &sumo_dpm_get_mclk, 1464 .print_power_state = &sumo_dpm_print_power_state, 1465 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1466 .force_performance_level = &sumo_dpm_force_performance_level, 1467 }, 1468 .pflip = { 1469 .page_flip = &evergreen_page_flip, 1470 .page_flip_pending = &evergreen_page_flip_pending, 1471 }, 1472 }; 1473 1474 static struct radeon_asic btc_asic = { 1475 .init = &evergreen_init, 1476 .fini = &evergreen_fini, 1477 .suspend = &evergreen_suspend, 1478 .resume = &evergreen_resume, 1479 .asic_reset = &evergreen_asic_reset, 1480 .vga_set_state = &r600_vga_set_state, 1481 .mmio_hdp_flush = r600_mmio_hdp_flush, 1482 .gui_idle = &r600_gui_idle, 1483 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1484 .get_xclk = &rv770_get_xclk, 1485 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1486 .gart = { 1487 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1488 .set_page = &rs600_gart_set_page, 1489 }, 1490 .ring = { 1491 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1492 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1493 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1494 }, 1495 .irq = { 1496 .set = &evergreen_irq_set, 1497 .process = &evergreen_irq_process, 1498 }, 1499 .display = { 1500 .bandwidth_update = &evergreen_bandwidth_update, 1501 .get_vblank_counter = &evergreen_get_vblank_counter, 1502 .wait_for_vblank = &dce4_wait_for_vblank, 1503 .set_backlight_level = &atombios_set_backlight_level, 1504 .get_backlight_level = &atombios_get_backlight_level, 1505 .hdmi_enable = &evergreen_hdmi_enable, 1506 .hdmi_setmode = &evergreen_hdmi_setmode, 1507 }, 1508 .copy = { 1509 .blit = &r600_copy_cpdma, 1510 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1511 .dma = &evergreen_copy_dma, 1512 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1513 .copy = &evergreen_copy_dma, 1514 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1515 }, 1516 .surface = { 1517 .set_reg = r600_set_surface_reg, 1518 .clear_reg = r600_clear_surface_reg, 1519 }, 1520 .hpd = { 1521 .init = &evergreen_hpd_init, 1522 .fini = &evergreen_hpd_fini, 1523 .sense = &evergreen_hpd_sense, 1524 .set_polarity = &evergreen_hpd_set_polarity, 1525 }, 1526 .pm = { 1527 .misc = &evergreen_pm_misc, 1528 .prepare = &evergreen_pm_prepare, 1529 .finish = &evergreen_pm_finish, 1530 .init_profile = &btc_pm_init_profile, 1531 .get_dynpm_state = &r600_pm_get_dynpm_state, 1532 .get_engine_clock = &radeon_atom_get_engine_clock, 1533 .set_engine_clock = &radeon_atom_set_engine_clock, 1534 .get_memory_clock = &radeon_atom_get_memory_clock, 1535 .set_memory_clock = &radeon_atom_set_memory_clock, 1536 .get_pcie_lanes = &r600_get_pcie_lanes, 1537 .set_pcie_lanes = &r600_set_pcie_lanes, 1538 .set_clock_gating = NULL, 1539 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1540 .get_temperature = &evergreen_get_temp, 1541 }, 1542 .dpm = { 1543 .init = &btc_dpm_init, 1544 .setup_asic = &btc_dpm_setup_asic, 1545 .enable = &btc_dpm_enable, 1546 .late_enable = &rv770_dpm_late_enable, 1547 .disable = &btc_dpm_disable, 1548 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1549 .set_power_state = &btc_dpm_set_power_state, 1550 .post_set_power_state = &btc_dpm_post_set_power_state, 1551 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1552 .fini = &btc_dpm_fini, 1553 .get_sclk = &btc_dpm_get_sclk, 1554 .get_mclk = &btc_dpm_get_mclk, 1555 .print_power_state = &rv770_dpm_print_power_state, 1556 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, 1557 .force_performance_level = &rv770_dpm_force_performance_level, 1558 .vblank_too_short = &btc_dpm_vblank_too_short, 1559 }, 1560 .pflip = { 1561 .page_flip = &evergreen_page_flip, 1562 .page_flip_pending = &evergreen_page_flip_pending, 1563 }, 1564 }; 1565 1566 static struct radeon_asic_ring cayman_gfx_ring = { 1567 .ib_execute = &cayman_ring_ib_execute, 1568 .ib_parse = &evergreen_ib_parse, 1569 .emit_fence = &cayman_fence_ring_emit, 1570 .emit_semaphore = &r600_semaphore_ring_emit, 1571 .cs_parse = &evergreen_cs_parse, 1572 .ring_test = &r600_ring_test, 1573 .ib_test = &r600_ib_test, 1574 .is_lockup = &cayman_gfx_is_lockup, 1575 .vm_flush = &cayman_vm_flush, 1576 .get_rptr = &cayman_gfx_get_rptr, 1577 .get_wptr = &cayman_gfx_get_wptr, 1578 .set_wptr = &cayman_gfx_set_wptr, 1579 }; 1580 1581 static struct radeon_asic_ring cayman_dma_ring = { 1582 .ib_execute = &cayman_dma_ring_ib_execute, 1583 .ib_parse = &evergreen_dma_ib_parse, 1584 .emit_fence = &evergreen_dma_fence_ring_emit, 1585 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1586 .cs_parse = &evergreen_dma_cs_parse, 1587 .ring_test = &r600_dma_ring_test, 1588 .ib_test = &r600_dma_ib_test, 1589 .is_lockup = &cayman_dma_is_lockup, 1590 .vm_flush = &cayman_dma_vm_flush, 1591 .get_rptr = &cayman_dma_get_rptr, 1592 .get_wptr = &cayman_dma_get_wptr, 1593 .set_wptr = &cayman_dma_set_wptr 1594 }; 1595 1596 static struct radeon_asic_ring cayman_uvd_ring = { 1597 .ib_execute = &uvd_v1_0_ib_execute, 1598 .emit_fence = &uvd_v2_2_fence_emit, 1599 .emit_semaphore = &uvd_v3_1_semaphore_emit, 1600 .cs_parse = &radeon_uvd_cs_parse, 1601 .ring_test = &uvd_v1_0_ring_test, 1602 .ib_test = &uvd_v1_0_ib_test, 1603 .is_lockup = &radeon_ring_test_lockup, 1604 .get_rptr = &uvd_v1_0_get_rptr, 1605 .get_wptr = &uvd_v1_0_get_wptr, 1606 .set_wptr = &uvd_v1_0_set_wptr, 1607 }; 1608 1609 static struct radeon_asic cayman_asic = { 1610 .init = &cayman_init, 1611 .fini = &cayman_fini, 1612 .suspend = &cayman_suspend, 1613 .resume = &cayman_resume, 1614 .asic_reset = &cayman_asic_reset, 1615 .vga_set_state = &r600_vga_set_state, 1616 .mmio_hdp_flush = r600_mmio_hdp_flush, 1617 .gui_idle = &r600_gui_idle, 1618 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1619 .get_xclk = &rv770_get_xclk, 1620 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1621 .gart = { 1622 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1623 .set_page = &rs600_gart_set_page, 1624 }, 1625 .vm = { 1626 .init = &cayman_vm_init, 1627 .fini = &cayman_vm_fini, 1628 .copy_pages = &cayman_dma_vm_copy_pages, 1629 .write_pages = &cayman_dma_vm_write_pages, 1630 .set_pages = &cayman_dma_vm_set_pages, 1631 .pad_ib = &cayman_dma_vm_pad_ib, 1632 }, 1633 .ring = { 1634 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1635 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1636 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1637 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1638 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1639 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1640 }, 1641 .irq = { 1642 .set = &evergreen_irq_set, 1643 .process = &evergreen_irq_process, 1644 }, 1645 .display = { 1646 .bandwidth_update = &evergreen_bandwidth_update, 1647 .get_vblank_counter = &evergreen_get_vblank_counter, 1648 .wait_for_vblank = &dce4_wait_for_vblank, 1649 .set_backlight_level = &atombios_set_backlight_level, 1650 .get_backlight_level = &atombios_get_backlight_level, 1651 .hdmi_enable = &evergreen_hdmi_enable, 1652 .hdmi_setmode = &evergreen_hdmi_setmode, 1653 }, 1654 .copy = { 1655 .blit = &r600_copy_cpdma, 1656 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1657 .dma = &evergreen_copy_dma, 1658 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1659 .copy = &evergreen_copy_dma, 1660 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1661 }, 1662 .surface = { 1663 .set_reg = r600_set_surface_reg, 1664 .clear_reg = r600_clear_surface_reg, 1665 }, 1666 .hpd = { 1667 .init = &evergreen_hpd_init, 1668 .fini = &evergreen_hpd_fini, 1669 .sense = &evergreen_hpd_sense, 1670 .set_polarity = &evergreen_hpd_set_polarity, 1671 }, 1672 .pm = { 1673 .misc = &evergreen_pm_misc, 1674 .prepare = &evergreen_pm_prepare, 1675 .finish = &evergreen_pm_finish, 1676 .init_profile = &btc_pm_init_profile, 1677 .get_dynpm_state = &r600_pm_get_dynpm_state, 1678 .get_engine_clock = &radeon_atom_get_engine_clock, 1679 .set_engine_clock = &radeon_atom_set_engine_clock, 1680 .get_memory_clock = &radeon_atom_get_memory_clock, 1681 .set_memory_clock = &radeon_atom_set_memory_clock, 1682 .get_pcie_lanes = &r600_get_pcie_lanes, 1683 .set_pcie_lanes = &r600_set_pcie_lanes, 1684 .set_clock_gating = NULL, 1685 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1686 .get_temperature = &evergreen_get_temp, 1687 }, 1688 .dpm = { 1689 .init = &ni_dpm_init, 1690 .setup_asic = &ni_dpm_setup_asic, 1691 .enable = &ni_dpm_enable, 1692 .late_enable = &rv770_dpm_late_enable, 1693 .disable = &ni_dpm_disable, 1694 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1695 .set_power_state = &ni_dpm_set_power_state, 1696 .post_set_power_state = &ni_dpm_post_set_power_state, 1697 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1698 .fini = &ni_dpm_fini, 1699 .get_sclk = &ni_dpm_get_sclk, 1700 .get_mclk = &ni_dpm_get_mclk, 1701 .print_power_state = &ni_dpm_print_power_state, 1702 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1703 .force_performance_level = &ni_dpm_force_performance_level, 1704 .vblank_too_short = &ni_dpm_vblank_too_short, 1705 }, 1706 .pflip = { 1707 .page_flip = &evergreen_page_flip, 1708 .page_flip_pending = &evergreen_page_flip_pending, 1709 }, 1710 }; 1711 1712 static struct radeon_asic trinity_asic = { 1713 .init = &cayman_init, 1714 .fini = &cayman_fini, 1715 .suspend = &cayman_suspend, 1716 .resume = &cayman_resume, 1717 .asic_reset = &cayman_asic_reset, 1718 .vga_set_state = &r600_vga_set_state, 1719 .mmio_hdp_flush = r600_mmio_hdp_flush, 1720 .gui_idle = &r600_gui_idle, 1721 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1722 .get_xclk = &r600_get_xclk, 1723 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1724 .gart = { 1725 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1726 .set_page = &rs600_gart_set_page, 1727 }, 1728 .vm = { 1729 .init = &cayman_vm_init, 1730 .fini = &cayman_vm_fini, 1731 .copy_pages = &cayman_dma_vm_copy_pages, 1732 .write_pages = &cayman_dma_vm_write_pages, 1733 .set_pages = &cayman_dma_vm_set_pages, 1734 .pad_ib = &cayman_dma_vm_pad_ib, 1735 }, 1736 .ring = { 1737 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1738 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1739 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1740 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1741 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1742 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1743 }, 1744 .irq = { 1745 .set = &evergreen_irq_set, 1746 .process = &evergreen_irq_process, 1747 }, 1748 .display = { 1749 .bandwidth_update = &dce6_bandwidth_update, 1750 .get_vblank_counter = &evergreen_get_vblank_counter, 1751 .wait_for_vblank = &dce4_wait_for_vblank, 1752 .set_backlight_level = &atombios_set_backlight_level, 1753 .get_backlight_level = &atombios_get_backlight_level, 1754 .hdmi_enable = &evergreen_hdmi_enable, 1755 .hdmi_setmode = &evergreen_hdmi_setmode, 1756 }, 1757 .copy = { 1758 .blit = &r600_copy_cpdma, 1759 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1760 .dma = &evergreen_copy_dma, 1761 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1762 .copy = &evergreen_copy_dma, 1763 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1764 }, 1765 .surface = { 1766 .set_reg = r600_set_surface_reg, 1767 .clear_reg = r600_clear_surface_reg, 1768 }, 1769 .hpd = { 1770 .init = &evergreen_hpd_init, 1771 .fini = &evergreen_hpd_fini, 1772 .sense = &evergreen_hpd_sense, 1773 .set_polarity = &evergreen_hpd_set_polarity, 1774 }, 1775 .pm = { 1776 .misc = &evergreen_pm_misc, 1777 .prepare = &evergreen_pm_prepare, 1778 .finish = &evergreen_pm_finish, 1779 .init_profile = &sumo_pm_init_profile, 1780 .get_dynpm_state = &r600_pm_get_dynpm_state, 1781 .get_engine_clock = &radeon_atom_get_engine_clock, 1782 .set_engine_clock = &radeon_atom_set_engine_clock, 1783 .get_memory_clock = NULL, 1784 .set_memory_clock = NULL, 1785 .get_pcie_lanes = NULL, 1786 .set_pcie_lanes = NULL, 1787 .set_clock_gating = NULL, 1788 .set_uvd_clocks = &sumo_set_uvd_clocks, 1789 .get_temperature = &tn_get_temp, 1790 }, 1791 .dpm = { 1792 .init = &trinity_dpm_init, 1793 .setup_asic = &trinity_dpm_setup_asic, 1794 .enable = &trinity_dpm_enable, 1795 .late_enable = &trinity_dpm_late_enable, 1796 .disable = &trinity_dpm_disable, 1797 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 1798 .set_power_state = &trinity_dpm_set_power_state, 1799 .post_set_power_state = &trinity_dpm_post_set_power_state, 1800 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 1801 .fini = &trinity_dpm_fini, 1802 .get_sclk = &trinity_dpm_get_sclk, 1803 .get_mclk = &trinity_dpm_get_mclk, 1804 .print_power_state = &trinity_dpm_print_power_state, 1805 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 1806 .force_performance_level = &trinity_dpm_force_performance_level, 1807 .enable_bapm = &trinity_dpm_enable_bapm, 1808 }, 1809 .pflip = { 1810 .page_flip = &evergreen_page_flip, 1811 .page_flip_pending = &evergreen_page_flip_pending, 1812 }, 1813 }; 1814 1815 static struct radeon_asic_ring si_gfx_ring = { 1816 .ib_execute = &si_ring_ib_execute, 1817 .ib_parse = &si_ib_parse, 1818 .emit_fence = &si_fence_ring_emit, 1819 .emit_semaphore = &r600_semaphore_ring_emit, 1820 .cs_parse = NULL, 1821 .ring_test = &r600_ring_test, 1822 .ib_test = &r600_ib_test, 1823 .is_lockup = &si_gfx_is_lockup, 1824 .vm_flush = &si_vm_flush, 1825 .get_rptr = &cayman_gfx_get_rptr, 1826 .get_wptr = &cayman_gfx_get_wptr, 1827 .set_wptr = &cayman_gfx_set_wptr, 1828 }; 1829 1830 static struct radeon_asic_ring si_dma_ring = { 1831 .ib_execute = &cayman_dma_ring_ib_execute, 1832 .ib_parse = &evergreen_dma_ib_parse, 1833 .emit_fence = &evergreen_dma_fence_ring_emit, 1834 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1835 .cs_parse = NULL, 1836 .ring_test = &r600_dma_ring_test, 1837 .ib_test = &r600_dma_ib_test, 1838 .is_lockup = &si_dma_is_lockup, 1839 .vm_flush = &si_dma_vm_flush, 1840 .get_rptr = &cayman_dma_get_rptr, 1841 .get_wptr = &cayman_dma_get_wptr, 1842 .set_wptr = &cayman_dma_set_wptr, 1843 }; 1844 1845 static struct radeon_asic si_asic = { 1846 .init = &si_init, 1847 .fini = &si_fini, 1848 .suspend = &si_suspend, 1849 .resume = &si_resume, 1850 .asic_reset = &si_asic_reset, 1851 .vga_set_state = &r600_vga_set_state, 1852 .mmio_hdp_flush = r600_mmio_hdp_flush, 1853 .gui_idle = &r600_gui_idle, 1854 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1855 .get_xclk = &si_get_xclk, 1856 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1857 .gart = { 1858 .tlb_flush = &si_pcie_gart_tlb_flush, 1859 .set_page = &rs600_gart_set_page, 1860 }, 1861 .vm = { 1862 .init = &si_vm_init, 1863 .fini = &si_vm_fini, 1864 .copy_pages = &si_dma_vm_copy_pages, 1865 .write_pages = &si_dma_vm_write_pages, 1866 .set_pages = &si_dma_vm_set_pages, 1867 .pad_ib = &cayman_dma_vm_pad_ib, 1868 }, 1869 .ring = { 1870 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, 1871 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, 1872 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, 1873 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, 1874 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, 1875 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1876 }, 1877 .irq = { 1878 .set = &si_irq_set, 1879 .process = &si_irq_process, 1880 }, 1881 .display = { 1882 .bandwidth_update = &dce6_bandwidth_update, 1883 .get_vblank_counter = &evergreen_get_vblank_counter, 1884 .wait_for_vblank = &dce4_wait_for_vblank, 1885 .set_backlight_level = &atombios_set_backlight_level, 1886 .get_backlight_level = &atombios_get_backlight_level, 1887 .hdmi_enable = &evergreen_hdmi_enable, 1888 .hdmi_setmode = &evergreen_hdmi_setmode, 1889 }, 1890 .copy = { 1891 .blit = &r600_copy_cpdma, 1892 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1893 .dma = &si_copy_dma, 1894 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1895 .copy = &si_copy_dma, 1896 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1897 }, 1898 .surface = { 1899 .set_reg = r600_set_surface_reg, 1900 .clear_reg = r600_clear_surface_reg, 1901 }, 1902 .hpd = { 1903 .init = &evergreen_hpd_init, 1904 .fini = &evergreen_hpd_fini, 1905 .sense = &evergreen_hpd_sense, 1906 .set_polarity = &evergreen_hpd_set_polarity, 1907 }, 1908 .pm = { 1909 .misc = &evergreen_pm_misc, 1910 .prepare = &evergreen_pm_prepare, 1911 .finish = &evergreen_pm_finish, 1912 .init_profile = &sumo_pm_init_profile, 1913 .get_dynpm_state = &r600_pm_get_dynpm_state, 1914 .get_engine_clock = &radeon_atom_get_engine_clock, 1915 .set_engine_clock = &radeon_atom_set_engine_clock, 1916 .get_memory_clock = &radeon_atom_get_memory_clock, 1917 .set_memory_clock = &radeon_atom_set_memory_clock, 1918 .get_pcie_lanes = &r600_get_pcie_lanes, 1919 .set_pcie_lanes = &r600_set_pcie_lanes, 1920 .set_clock_gating = NULL, 1921 .set_uvd_clocks = &si_set_uvd_clocks, 1922 .get_temperature = &si_get_temp, 1923 }, 1924 .dpm = { 1925 .init = &si_dpm_init, 1926 .setup_asic = &si_dpm_setup_asic, 1927 .enable = &si_dpm_enable, 1928 .late_enable = &si_dpm_late_enable, 1929 .disable = &si_dpm_disable, 1930 .pre_set_power_state = &si_dpm_pre_set_power_state, 1931 .set_power_state = &si_dpm_set_power_state, 1932 .post_set_power_state = &si_dpm_post_set_power_state, 1933 .display_configuration_changed = &si_dpm_display_configuration_changed, 1934 .fini = &si_dpm_fini, 1935 .get_sclk = &ni_dpm_get_sclk, 1936 .get_mclk = &ni_dpm_get_mclk, 1937 .print_power_state = &ni_dpm_print_power_state, 1938 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 1939 .force_performance_level = &si_dpm_force_performance_level, 1940 .vblank_too_short = &ni_dpm_vblank_too_short, 1941 }, 1942 .pflip = { 1943 .page_flip = &evergreen_page_flip, 1944 .page_flip_pending = &evergreen_page_flip_pending, 1945 }, 1946 }; 1947 1948 static struct radeon_asic_ring ci_gfx_ring = { 1949 .ib_execute = &cik_ring_ib_execute, 1950 .ib_parse = &cik_ib_parse, 1951 .emit_fence = &cik_fence_gfx_ring_emit, 1952 .emit_semaphore = &cik_semaphore_ring_emit, 1953 .cs_parse = NULL, 1954 .ring_test = &cik_ring_test, 1955 .ib_test = &cik_ib_test, 1956 .is_lockup = &cik_gfx_is_lockup, 1957 .vm_flush = &cik_vm_flush, 1958 .get_rptr = &cik_gfx_get_rptr, 1959 .get_wptr = &cik_gfx_get_wptr, 1960 .set_wptr = &cik_gfx_set_wptr, 1961 }; 1962 1963 static struct radeon_asic_ring ci_cp_ring = { 1964 .ib_execute = &cik_ring_ib_execute, 1965 .ib_parse = &cik_ib_parse, 1966 .emit_fence = &cik_fence_compute_ring_emit, 1967 .emit_semaphore = &cik_semaphore_ring_emit, 1968 .cs_parse = NULL, 1969 .ring_test = &cik_ring_test, 1970 .ib_test = &cik_ib_test, 1971 .is_lockup = &cik_gfx_is_lockup, 1972 .vm_flush = &cik_vm_flush, 1973 .get_rptr = &cik_compute_get_rptr, 1974 .get_wptr = &cik_compute_get_wptr, 1975 .set_wptr = &cik_compute_set_wptr, 1976 }; 1977 1978 static struct radeon_asic_ring ci_dma_ring = { 1979 .ib_execute = &cik_sdma_ring_ib_execute, 1980 .ib_parse = &cik_ib_parse, 1981 .emit_fence = &cik_sdma_fence_ring_emit, 1982 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 1983 .cs_parse = NULL, 1984 .ring_test = &cik_sdma_ring_test, 1985 .ib_test = &cik_sdma_ib_test, 1986 .is_lockup = &cik_sdma_is_lockup, 1987 .vm_flush = &cik_dma_vm_flush, 1988 .get_rptr = &cik_sdma_get_rptr, 1989 .get_wptr = &cik_sdma_get_wptr, 1990 .set_wptr = &cik_sdma_set_wptr, 1991 }; 1992 1993 static struct radeon_asic_ring ci_vce_ring = { 1994 .ib_execute = &radeon_vce_ib_execute, 1995 .emit_fence = &radeon_vce_fence_emit, 1996 .emit_semaphore = &radeon_vce_semaphore_emit, 1997 .cs_parse = &radeon_vce_cs_parse, 1998 .ring_test = &radeon_vce_ring_test, 1999 .ib_test = &radeon_vce_ib_test, 2000 .is_lockup = &radeon_ring_test_lockup, 2001 .get_rptr = &vce_v1_0_get_rptr, 2002 .get_wptr = &vce_v1_0_get_wptr, 2003 .set_wptr = &vce_v1_0_set_wptr, 2004 }; 2005 2006 static struct radeon_asic ci_asic = { 2007 .init = &cik_init, 2008 .fini = &cik_fini, 2009 .suspend = &cik_suspend, 2010 .resume = &cik_resume, 2011 .asic_reset = &cik_asic_reset, 2012 .vga_set_state = &r600_vga_set_state, 2013 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2014 .gui_idle = &r600_gui_idle, 2015 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2016 .get_xclk = &cik_get_xclk, 2017 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2018 .gart = { 2019 .tlb_flush = &cik_pcie_gart_tlb_flush, 2020 .set_page = &rs600_gart_set_page, 2021 }, 2022 .vm = { 2023 .init = &cik_vm_init, 2024 .fini = &cik_vm_fini, 2025 .copy_pages = &cik_sdma_vm_copy_pages, 2026 .write_pages = &cik_sdma_vm_write_pages, 2027 .set_pages = &cik_sdma_vm_set_pages, 2028 .pad_ib = &cik_sdma_vm_pad_ib, 2029 }, 2030 .ring = { 2031 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2032 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2033 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2034 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2035 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2036 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2037 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2038 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2039 }, 2040 .irq = { 2041 .set = &cik_irq_set, 2042 .process = &cik_irq_process, 2043 }, 2044 .display = { 2045 .bandwidth_update = &dce8_bandwidth_update, 2046 .get_vblank_counter = &evergreen_get_vblank_counter, 2047 .wait_for_vblank = &dce4_wait_for_vblank, 2048 .set_backlight_level = &atombios_set_backlight_level, 2049 .get_backlight_level = &atombios_get_backlight_level, 2050 .hdmi_enable = &evergreen_hdmi_enable, 2051 .hdmi_setmode = &evergreen_hdmi_setmode, 2052 }, 2053 .copy = { 2054 .blit = &cik_copy_cpdma, 2055 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2056 .dma = &cik_copy_dma, 2057 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2058 .copy = &cik_copy_dma, 2059 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2060 }, 2061 .surface = { 2062 .set_reg = r600_set_surface_reg, 2063 .clear_reg = r600_clear_surface_reg, 2064 }, 2065 .hpd = { 2066 .init = &evergreen_hpd_init, 2067 .fini = &evergreen_hpd_fini, 2068 .sense = &evergreen_hpd_sense, 2069 .set_polarity = &evergreen_hpd_set_polarity, 2070 }, 2071 .pm = { 2072 .misc = &evergreen_pm_misc, 2073 .prepare = &evergreen_pm_prepare, 2074 .finish = &evergreen_pm_finish, 2075 .init_profile = &sumo_pm_init_profile, 2076 .get_dynpm_state = &r600_pm_get_dynpm_state, 2077 .get_engine_clock = &radeon_atom_get_engine_clock, 2078 .set_engine_clock = &radeon_atom_set_engine_clock, 2079 .get_memory_clock = &radeon_atom_get_memory_clock, 2080 .set_memory_clock = &radeon_atom_set_memory_clock, 2081 .get_pcie_lanes = NULL, 2082 .set_pcie_lanes = NULL, 2083 .set_clock_gating = NULL, 2084 .set_uvd_clocks = &cik_set_uvd_clocks, 2085 .set_vce_clocks = &cik_set_vce_clocks, 2086 .get_temperature = &ci_get_temp, 2087 }, 2088 .dpm = { 2089 .init = &ci_dpm_init, 2090 .setup_asic = &ci_dpm_setup_asic, 2091 .enable = &ci_dpm_enable, 2092 .late_enable = &ci_dpm_late_enable, 2093 .disable = &ci_dpm_disable, 2094 .pre_set_power_state = &ci_dpm_pre_set_power_state, 2095 .set_power_state = &ci_dpm_set_power_state, 2096 .post_set_power_state = &ci_dpm_post_set_power_state, 2097 .display_configuration_changed = &ci_dpm_display_configuration_changed, 2098 .fini = &ci_dpm_fini, 2099 .get_sclk = &ci_dpm_get_sclk, 2100 .get_mclk = &ci_dpm_get_mclk, 2101 .print_power_state = &ci_dpm_print_power_state, 2102 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, 2103 .force_performance_level = &ci_dpm_force_performance_level, 2104 .vblank_too_short = &ci_dpm_vblank_too_short, 2105 .powergate_uvd = &ci_dpm_powergate_uvd, 2106 }, 2107 .pflip = { 2108 .page_flip = &evergreen_page_flip, 2109 .page_flip_pending = &evergreen_page_flip_pending, 2110 }, 2111 }; 2112 2113 static struct radeon_asic kv_asic = { 2114 .init = &cik_init, 2115 .fini = &cik_fini, 2116 .suspend = &cik_suspend, 2117 .resume = &cik_resume, 2118 .asic_reset = &cik_asic_reset, 2119 .vga_set_state = &r600_vga_set_state, 2120 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2121 .gui_idle = &r600_gui_idle, 2122 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2123 .get_xclk = &cik_get_xclk, 2124 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2125 .gart = { 2126 .tlb_flush = &cik_pcie_gart_tlb_flush, 2127 .set_page = &rs600_gart_set_page, 2128 }, 2129 .vm = { 2130 .init = &cik_vm_init, 2131 .fini = &cik_vm_fini, 2132 .copy_pages = &cik_sdma_vm_copy_pages, 2133 .write_pages = &cik_sdma_vm_write_pages, 2134 .set_pages = &cik_sdma_vm_set_pages, 2135 .pad_ib = &cik_sdma_vm_pad_ib, 2136 }, 2137 .ring = { 2138 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2139 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2140 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2141 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2142 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2143 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2144 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2145 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2146 }, 2147 .irq = { 2148 .set = &cik_irq_set, 2149 .process = &cik_irq_process, 2150 }, 2151 .display = { 2152 .bandwidth_update = &dce8_bandwidth_update, 2153 .get_vblank_counter = &evergreen_get_vblank_counter, 2154 .wait_for_vblank = &dce4_wait_for_vblank, 2155 .set_backlight_level = &atombios_set_backlight_level, 2156 .get_backlight_level = &atombios_get_backlight_level, 2157 .hdmi_enable = &evergreen_hdmi_enable, 2158 .hdmi_setmode = &evergreen_hdmi_setmode, 2159 }, 2160 .copy = { 2161 .blit = &cik_copy_cpdma, 2162 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2163 .dma = &cik_copy_dma, 2164 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2165 .copy = &cik_copy_dma, 2166 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2167 }, 2168 .surface = { 2169 .set_reg = r600_set_surface_reg, 2170 .clear_reg = r600_clear_surface_reg, 2171 }, 2172 .hpd = { 2173 .init = &evergreen_hpd_init, 2174 .fini = &evergreen_hpd_fini, 2175 .sense = &evergreen_hpd_sense, 2176 .set_polarity = &evergreen_hpd_set_polarity, 2177 }, 2178 .pm = { 2179 .misc = &evergreen_pm_misc, 2180 .prepare = &evergreen_pm_prepare, 2181 .finish = &evergreen_pm_finish, 2182 .init_profile = &sumo_pm_init_profile, 2183 .get_dynpm_state = &r600_pm_get_dynpm_state, 2184 .get_engine_clock = &radeon_atom_get_engine_clock, 2185 .set_engine_clock = &radeon_atom_set_engine_clock, 2186 .get_memory_clock = &radeon_atom_get_memory_clock, 2187 .set_memory_clock = &radeon_atom_set_memory_clock, 2188 .get_pcie_lanes = NULL, 2189 .set_pcie_lanes = NULL, 2190 .set_clock_gating = NULL, 2191 .set_uvd_clocks = &cik_set_uvd_clocks, 2192 .set_vce_clocks = &cik_set_vce_clocks, 2193 .get_temperature = &kv_get_temp, 2194 }, 2195 .dpm = { 2196 .init = &kv_dpm_init, 2197 .setup_asic = &kv_dpm_setup_asic, 2198 .enable = &kv_dpm_enable, 2199 .late_enable = &kv_dpm_late_enable, 2200 .disable = &kv_dpm_disable, 2201 .pre_set_power_state = &kv_dpm_pre_set_power_state, 2202 .set_power_state = &kv_dpm_set_power_state, 2203 .post_set_power_state = &kv_dpm_post_set_power_state, 2204 .display_configuration_changed = &kv_dpm_display_configuration_changed, 2205 .fini = &kv_dpm_fini, 2206 .get_sclk = &kv_dpm_get_sclk, 2207 .get_mclk = &kv_dpm_get_mclk, 2208 .print_power_state = &kv_dpm_print_power_state, 2209 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 2210 .force_performance_level = &kv_dpm_force_performance_level, 2211 .powergate_uvd = &kv_dpm_powergate_uvd, 2212 .enable_bapm = &kv_dpm_enable_bapm, 2213 }, 2214 .pflip = { 2215 .page_flip = &evergreen_page_flip, 2216 .page_flip_pending = &evergreen_page_flip_pending, 2217 }, 2218 }; 2219 2220 /** 2221 * radeon_asic_init - register asic specific callbacks 2222 * 2223 * @rdev: radeon device pointer 2224 * 2225 * Registers the appropriate asic specific callbacks for each 2226 * chip family. Also sets other asics specific info like the number 2227 * of crtcs and the register aperture accessors (all asics). 2228 * Returns 0 for success. 2229 */ 2230 int radeon_asic_init(struct radeon_device *rdev) 2231 { 2232 radeon_register_accessor_init(rdev); 2233 2234 /* set the number of crtcs */ 2235 if (rdev->flags & RADEON_SINGLE_CRTC) 2236 rdev->num_crtc = 1; 2237 else 2238 rdev->num_crtc = 2; 2239 2240 rdev->has_uvd = false; 2241 2242 switch (rdev->family) { 2243 case CHIP_R100: 2244 case CHIP_RV100: 2245 case CHIP_RS100: 2246 case CHIP_RV200: 2247 case CHIP_RS200: 2248 rdev->asic = &r100_asic; 2249 break; 2250 case CHIP_R200: 2251 case CHIP_RV250: 2252 case CHIP_RS300: 2253 case CHIP_RV280: 2254 rdev->asic = &r200_asic; 2255 break; 2256 case CHIP_R300: 2257 case CHIP_R350: 2258 case CHIP_RV350: 2259 case CHIP_RV380: 2260 if (rdev->flags & RADEON_IS_PCIE) 2261 rdev->asic = &r300_asic_pcie; 2262 else 2263 rdev->asic = &r300_asic; 2264 break; 2265 case CHIP_R420: 2266 case CHIP_R423: 2267 case CHIP_RV410: 2268 rdev->asic = &r420_asic; 2269 /* handle macs */ 2270 if (rdev->bios == NULL) { 2271 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2272 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2273 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2274 rdev->asic->pm.set_memory_clock = NULL; 2275 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2276 } 2277 break; 2278 case CHIP_RS400: 2279 case CHIP_RS480: 2280 rdev->asic = &rs400_asic; 2281 break; 2282 case CHIP_RS600: 2283 rdev->asic = &rs600_asic; 2284 break; 2285 case CHIP_RS690: 2286 case CHIP_RS740: 2287 rdev->asic = &rs690_asic; 2288 break; 2289 case CHIP_RV515: 2290 rdev->asic = &rv515_asic; 2291 break; 2292 case CHIP_R520: 2293 case CHIP_RV530: 2294 case CHIP_RV560: 2295 case CHIP_RV570: 2296 case CHIP_R580: 2297 rdev->asic = &r520_asic; 2298 break; 2299 case CHIP_R600: 2300 rdev->asic = &r600_asic; 2301 break; 2302 case CHIP_RV610: 2303 case CHIP_RV630: 2304 case CHIP_RV620: 2305 case CHIP_RV635: 2306 case CHIP_RV670: 2307 rdev->asic = &rv6xx_asic; 2308 rdev->has_uvd = true; 2309 break; 2310 case CHIP_RS780: 2311 case CHIP_RS880: 2312 rdev->asic = &rs780_asic; 2313 /* 760G/780V/880V don't have UVD */ 2314 if ((rdev->pdev->device == 0x9616)|| 2315 (rdev->pdev->device == 0x9611)|| 2316 (rdev->pdev->device == 0x9613)|| 2317 (rdev->pdev->device == 0x9711)|| 2318 (rdev->pdev->device == 0x9713)) 2319 rdev->has_uvd = false; 2320 else 2321 rdev->has_uvd = true; 2322 break; 2323 case CHIP_RV770: 2324 case CHIP_RV730: 2325 case CHIP_RV710: 2326 case CHIP_RV740: 2327 rdev->asic = &rv770_asic; 2328 rdev->has_uvd = true; 2329 break; 2330 case CHIP_CEDAR: 2331 case CHIP_REDWOOD: 2332 case CHIP_JUNIPER: 2333 case CHIP_CYPRESS: 2334 case CHIP_HEMLOCK: 2335 /* set num crtcs */ 2336 if (rdev->family == CHIP_CEDAR) 2337 rdev->num_crtc = 4; 2338 else 2339 rdev->num_crtc = 6; 2340 rdev->asic = &evergreen_asic; 2341 rdev->has_uvd = true; 2342 break; 2343 case CHIP_PALM: 2344 case CHIP_SUMO: 2345 case CHIP_SUMO2: 2346 rdev->asic = &sumo_asic; 2347 rdev->has_uvd = true; 2348 break; 2349 case CHIP_BARTS: 2350 case CHIP_TURKS: 2351 case CHIP_CAICOS: 2352 /* set num crtcs */ 2353 if (rdev->family == CHIP_CAICOS) 2354 rdev->num_crtc = 4; 2355 else 2356 rdev->num_crtc = 6; 2357 rdev->asic = &btc_asic; 2358 rdev->has_uvd = true; 2359 break; 2360 case CHIP_CAYMAN: 2361 rdev->asic = &cayman_asic; 2362 /* set num crtcs */ 2363 rdev->num_crtc = 6; 2364 rdev->has_uvd = true; 2365 break; 2366 case CHIP_ARUBA: 2367 rdev->asic = &trinity_asic; 2368 /* set num crtcs */ 2369 rdev->num_crtc = 4; 2370 rdev->has_uvd = true; 2371 break; 2372 case CHIP_TAHITI: 2373 case CHIP_PITCAIRN: 2374 case CHIP_VERDE: 2375 case CHIP_OLAND: 2376 case CHIP_HAINAN: 2377 rdev->asic = &si_asic; 2378 /* set num crtcs */ 2379 if (rdev->family == CHIP_HAINAN) 2380 rdev->num_crtc = 0; 2381 else if (rdev->family == CHIP_OLAND) 2382 rdev->num_crtc = 2; 2383 else 2384 rdev->num_crtc = 6; 2385 if (rdev->family == CHIP_HAINAN) 2386 rdev->has_uvd = false; 2387 else 2388 rdev->has_uvd = true; 2389 switch (rdev->family) { 2390 case CHIP_TAHITI: 2391 rdev->cg_flags = 2392 RADEON_CG_SUPPORT_GFX_MGCG | 2393 RADEON_CG_SUPPORT_GFX_MGLS | 2394 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2395 RADEON_CG_SUPPORT_GFX_CGLS | 2396 RADEON_CG_SUPPORT_GFX_CGTS | 2397 RADEON_CG_SUPPORT_GFX_CP_LS | 2398 RADEON_CG_SUPPORT_MC_MGCG | 2399 RADEON_CG_SUPPORT_SDMA_MGCG | 2400 RADEON_CG_SUPPORT_BIF_LS | 2401 RADEON_CG_SUPPORT_VCE_MGCG | 2402 RADEON_CG_SUPPORT_UVD_MGCG | 2403 RADEON_CG_SUPPORT_HDP_LS | 2404 RADEON_CG_SUPPORT_HDP_MGCG; 2405 rdev->pg_flags = 0; 2406 break; 2407 case CHIP_PITCAIRN: 2408 rdev->cg_flags = 2409 RADEON_CG_SUPPORT_GFX_MGCG | 2410 RADEON_CG_SUPPORT_GFX_MGLS | 2411 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2412 RADEON_CG_SUPPORT_GFX_CGLS | 2413 RADEON_CG_SUPPORT_GFX_CGTS | 2414 RADEON_CG_SUPPORT_GFX_CP_LS | 2415 RADEON_CG_SUPPORT_GFX_RLC_LS | 2416 RADEON_CG_SUPPORT_MC_LS | 2417 RADEON_CG_SUPPORT_MC_MGCG | 2418 RADEON_CG_SUPPORT_SDMA_MGCG | 2419 RADEON_CG_SUPPORT_BIF_LS | 2420 RADEON_CG_SUPPORT_VCE_MGCG | 2421 RADEON_CG_SUPPORT_UVD_MGCG | 2422 RADEON_CG_SUPPORT_HDP_LS | 2423 RADEON_CG_SUPPORT_HDP_MGCG; 2424 rdev->pg_flags = 0; 2425 break; 2426 case CHIP_VERDE: 2427 rdev->cg_flags = 2428 RADEON_CG_SUPPORT_GFX_MGCG | 2429 RADEON_CG_SUPPORT_GFX_MGLS | 2430 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2431 RADEON_CG_SUPPORT_GFX_CGLS | 2432 RADEON_CG_SUPPORT_GFX_CGTS | 2433 RADEON_CG_SUPPORT_GFX_CP_LS | 2434 RADEON_CG_SUPPORT_GFX_RLC_LS | 2435 RADEON_CG_SUPPORT_MC_LS | 2436 RADEON_CG_SUPPORT_MC_MGCG | 2437 RADEON_CG_SUPPORT_SDMA_MGCG | 2438 RADEON_CG_SUPPORT_BIF_LS | 2439 RADEON_CG_SUPPORT_VCE_MGCG | 2440 RADEON_CG_SUPPORT_UVD_MGCG | 2441 RADEON_CG_SUPPORT_HDP_LS | 2442 RADEON_CG_SUPPORT_HDP_MGCG; 2443 rdev->pg_flags = 0 | 2444 /*RADEON_PG_SUPPORT_GFX_PG | */ 2445 RADEON_PG_SUPPORT_SDMA; 2446 break; 2447 case CHIP_OLAND: 2448 rdev->cg_flags = 2449 RADEON_CG_SUPPORT_GFX_MGCG | 2450 RADEON_CG_SUPPORT_GFX_MGLS | 2451 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2452 RADEON_CG_SUPPORT_GFX_CGLS | 2453 RADEON_CG_SUPPORT_GFX_CGTS | 2454 RADEON_CG_SUPPORT_GFX_CP_LS | 2455 RADEON_CG_SUPPORT_GFX_RLC_LS | 2456 RADEON_CG_SUPPORT_MC_LS | 2457 RADEON_CG_SUPPORT_MC_MGCG | 2458 RADEON_CG_SUPPORT_SDMA_MGCG | 2459 RADEON_CG_SUPPORT_BIF_LS | 2460 RADEON_CG_SUPPORT_UVD_MGCG | 2461 RADEON_CG_SUPPORT_HDP_LS | 2462 RADEON_CG_SUPPORT_HDP_MGCG; 2463 rdev->pg_flags = 0; 2464 break; 2465 case CHIP_HAINAN: 2466 rdev->cg_flags = 2467 RADEON_CG_SUPPORT_GFX_MGCG | 2468 RADEON_CG_SUPPORT_GFX_MGLS | 2469 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2470 RADEON_CG_SUPPORT_GFX_CGLS | 2471 RADEON_CG_SUPPORT_GFX_CGTS | 2472 RADEON_CG_SUPPORT_GFX_CP_LS | 2473 RADEON_CG_SUPPORT_GFX_RLC_LS | 2474 RADEON_CG_SUPPORT_MC_LS | 2475 RADEON_CG_SUPPORT_MC_MGCG | 2476 RADEON_CG_SUPPORT_SDMA_MGCG | 2477 RADEON_CG_SUPPORT_BIF_LS | 2478 RADEON_CG_SUPPORT_HDP_LS | 2479 RADEON_CG_SUPPORT_HDP_MGCG; 2480 rdev->pg_flags = 0; 2481 break; 2482 default: 2483 rdev->cg_flags = 0; 2484 rdev->pg_flags = 0; 2485 break; 2486 } 2487 break; 2488 case CHIP_BONAIRE: 2489 case CHIP_HAWAII: 2490 rdev->asic = &ci_asic; 2491 rdev->num_crtc = 6; 2492 rdev->has_uvd = true; 2493 if (rdev->family == CHIP_BONAIRE) { 2494 rdev->cg_flags = 2495 RADEON_CG_SUPPORT_GFX_MGCG | 2496 RADEON_CG_SUPPORT_GFX_MGLS | 2497 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2498 RADEON_CG_SUPPORT_GFX_CGLS | 2499 RADEON_CG_SUPPORT_GFX_CGTS | 2500 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2501 RADEON_CG_SUPPORT_GFX_CP_LS | 2502 RADEON_CG_SUPPORT_MC_LS | 2503 RADEON_CG_SUPPORT_MC_MGCG | 2504 RADEON_CG_SUPPORT_SDMA_MGCG | 2505 RADEON_CG_SUPPORT_SDMA_LS | 2506 RADEON_CG_SUPPORT_BIF_LS | 2507 RADEON_CG_SUPPORT_VCE_MGCG | 2508 RADEON_CG_SUPPORT_UVD_MGCG | 2509 RADEON_CG_SUPPORT_HDP_LS | 2510 RADEON_CG_SUPPORT_HDP_MGCG; 2511 rdev->pg_flags = 0; 2512 } else { 2513 rdev->cg_flags = 2514 RADEON_CG_SUPPORT_GFX_MGCG | 2515 RADEON_CG_SUPPORT_GFX_MGLS | 2516 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2517 RADEON_CG_SUPPORT_GFX_CGLS | 2518 RADEON_CG_SUPPORT_GFX_CGTS | 2519 RADEON_CG_SUPPORT_GFX_CP_LS | 2520 RADEON_CG_SUPPORT_MC_LS | 2521 RADEON_CG_SUPPORT_MC_MGCG | 2522 RADEON_CG_SUPPORT_SDMA_MGCG | 2523 RADEON_CG_SUPPORT_SDMA_LS | 2524 RADEON_CG_SUPPORT_BIF_LS | 2525 RADEON_CG_SUPPORT_VCE_MGCG | 2526 RADEON_CG_SUPPORT_UVD_MGCG | 2527 RADEON_CG_SUPPORT_HDP_LS | 2528 RADEON_CG_SUPPORT_HDP_MGCG; 2529 rdev->pg_flags = 0; 2530 } 2531 break; 2532 case CHIP_KAVERI: 2533 case CHIP_KABINI: 2534 case CHIP_MULLINS: 2535 rdev->asic = &kv_asic; 2536 /* set num crtcs */ 2537 if (rdev->family == CHIP_KAVERI) { 2538 rdev->num_crtc = 4; 2539 rdev->cg_flags = 2540 RADEON_CG_SUPPORT_GFX_MGCG | 2541 RADEON_CG_SUPPORT_GFX_MGLS | 2542 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2543 RADEON_CG_SUPPORT_GFX_CGLS | 2544 RADEON_CG_SUPPORT_GFX_CGTS | 2545 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2546 RADEON_CG_SUPPORT_GFX_CP_LS | 2547 RADEON_CG_SUPPORT_SDMA_MGCG | 2548 RADEON_CG_SUPPORT_SDMA_LS | 2549 RADEON_CG_SUPPORT_BIF_LS | 2550 RADEON_CG_SUPPORT_VCE_MGCG | 2551 RADEON_CG_SUPPORT_UVD_MGCG | 2552 RADEON_CG_SUPPORT_HDP_LS | 2553 RADEON_CG_SUPPORT_HDP_MGCG; 2554 rdev->pg_flags = 0; 2555 /*RADEON_PG_SUPPORT_GFX_PG | 2556 RADEON_PG_SUPPORT_GFX_SMG | 2557 RADEON_PG_SUPPORT_GFX_DMG | 2558 RADEON_PG_SUPPORT_UVD | 2559 RADEON_PG_SUPPORT_VCE | 2560 RADEON_PG_SUPPORT_CP | 2561 RADEON_PG_SUPPORT_GDS | 2562 RADEON_PG_SUPPORT_RLC_SMU_HS | 2563 RADEON_PG_SUPPORT_ACP | 2564 RADEON_PG_SUPPORT_SAMU;*/ 2565 } else { 2566 rdev->num_crtc = 2; 2567 rdev->cg_flags = 2568 RADEON_CG_SUPPORT_GFX_MGCG | 2569 RADEON_CG_SUPPORT_GFX_MGLS | 2570 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2571 RADEON_CG_SUPPORT_GFX_CGLS | 2572 RADEON_CG_SUPPORT_GFX_CGTS | 2573 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2574 RADEON_CG_SUPPORT_GFX_CP_LS | 2575 RADEON_CG_SUPPORT_SDMA_MGCG | 2576 RADEON_CG_SUPPORT_SDMA_LS | 2577 RADEON_CG_SUPPORT_BIF_LS | 2578 RADEON_CG_SUPPORT_VCE_MGCG | 2579 RADEON_CG_SUPPORT_UVD_MGCG | 2580 RADEON_CG_SUPPORT_HDP_LS | 2581 RADEON_CG_SUPPORT_HDP_MGCG; 2582 rdev->pg_flags = 0; 2583 /*RADEON_PG_SUPPORT_GFX_PG | 2584 RADEON_PG_SUPPORT_GFX_SMG | 2585 RADEON_PG_SUPPORT_UVD | 2586 RADEON_PG_SUPPORT_VCE | 2587 RADEON_PG_SUPPORT_CP | 2588 RADEON_PG_SUPPORT_GDS | 2589 RADEON_PG_SUPPORT_RLC_SMU_HS | 2590 RADEON_PG_SUPPORT_SAMU;*/ 2591 } 2592 rdev->has_uvd = true; 2593 break; 2594 default: 2595 /* FIXME: not supported yet */ 2596 return -EINVAL; 2597 } 2598 2599 if (rdev->flags & RADEON_IS_IGP) { 2600 rdev->asic->pm.get_memory_clock = NULL; 2601 rdev->asic->pm.set_memory_clock = NULL; 2602 } 2603 2604 return 0; 2605 } 2606 2607