1 /* 2 * Copyright 2008 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Jerome Glisse <glisse@freedesktop.org> 26 * 27 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_cs.c 254885 2013-08-25 19:37:15Z dumbbell $ 28 */ 29 30 #include <drm/drmP.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 35 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) 36 { 37 struct drm_device *ddev = p->rdev->ddev; 38 struct radeon_cs_chunk *chunk; 39 unsigned i, j; 40 bool duplicate; 41 42 if (p->chunk_relocs_idx == -1) { 43 return 0; 44 } 45 chunk = &p->chunks[p->chunk_relocs_idx]; 46 p->dma_reloc_idx = 0; 47 /* FIXME: we assume that each relocs use 4 dwords */ 48 p->nrelocs = chunk->length_dw / 4; 49 p->relocs_ptr = kmalloc(p->nrelocs * sizeof(void *), M_DRM, 50 M_ZERO | M_WAITOK); 51 if (p->relocs_ptr == NULL) { 52 return -ENOMEM; 53 } 54 p->relocs = kmalloc(p->nrelocs * sizeof(struct radeon_cs_reloc), 55 M_DRM, M_ZERO | M_WAITOK); 56 if (p->relocs == NULL) { 57 return -ENOMEM; 58 } 59 for (i = 0; i < p->nrelocs; i++) { 60 struct drm_radeon_cs_reloc *r; 61 62 duplicate = false; 63 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; 64 for (j = 0; j < i; j++) { 65 if (r->handle == p->relocs[j].handle) { 66 p->relocs_ptr[i] = &p->relocs[j]; 67 duplicate = true; 68 break; 69 } 70 } 71 if (!duplicate) { 72 p->relocs[i].gobj = drm_gem_object_lookup(ddev, 73 p->filp, 74 r->handle); 75 if (p->relocs[i].gobj == NULL) { 76 DRM_ERROR("gem object lookup failed 0x%x\n", 77 r->handle); 78 return -ENOENT; 79 } 80 p->relocs_ptr[i] = &p->relocs[i]; 81 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); 82 p->relocs[i].lobj.bo = p->relocs[i].robj; 83 p->relocs[i].lobj.wdomain = r->write_domain; 84 p->relocs[i].lobj.rdomain = r->read_domains; 85 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; 86 p->relocs[i].handle = r->handle; 87 p->relocs[i].flags = r->flags; 88 radeon_bo_list_add_object(&p->relocs[i].lobj, 89 &p->validated); 90 91 } else 92 p->relocs[i].handle = 0; 93 } 94 return radeon_bo_list_validate(&p->validated); 95 } 96 97 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) 98 { 99 p->priority = priority; 100 101 switch (ring) { 102 default: 103 DRM_ERROR("unknown ring id: %d\n", ring); 104 return -EINVAL; 105 case RADEON_CS_RING_GFX: 106 p->ring = RADEON_RING_TYPE_GFX_INDEX; 107 break; 108 case RADEON_CS_RING_COMPUTE: 109 if (p->rdev->family >= CHIP_TAHITI) { 110 if (p->priority > 0) 111 p->ring = CAYMAN_RING_TYPE_CP1_INDEX; 112 else 113 p->ring = CAYMAN_RING_TYPE_CP2_INDEX; 114 } else 115 p->ring = RADEON_RING_TYPE_GFX_INDEX; 116 break; 117 case RADEON_CS_RING_DMA: 118 if (p->rdev->family >= CHIP_CAYMAN) { 119 if (p->priority > 0) 120 p->ring = R600_RING_TYPE_DMA_INDEX; 121 else 122 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX; 123 } else if (p->rdev->family >= CHIP_R600) { 124 p->ring = R600_RING_TYPE_DMA_INDEX; 125 } else { 126 return -EINVAL; 127 } 128 break; 129 } 130 return 0; 131 } 132 133 static void radeon_cs_sync_rings(struct radeon_cs_parser *p) 134 { 135 int i; 136 137 for (i = 0; i < p->nrelocs; i++) { 138 if (!p->relocs[i].robj) 139 continue; 140 141 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj); 142 } 143 } 144 145 /* XXX: note that this is called from the legacy UMS CS ioctl as well */ 146 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) 147 { 148 struct drm_radeon_cs *cs = data; 149 uint64_t *chunk_array_ptr; 150 unsigned size, i; 151 u32 ring = RADEON_CS_RING_GFX; 152 s32 priority = 0; 153 154 if (!cs->num_chunks) { 155 return 0; 156 } 157 /* get chunks */ 158 INIT_LIST_HEAD(&p->validated); 159 p->idx = 0; 160 p->ib.sa_bo = NULL; 161 p->ib.semaphore = NULL; 162 p->const_ib.sa_bo = NULL; 163 p->const_ib.semaphore = NULL; 164 p->chunk_ib_idx = -1; 165 p->chunk_relocs_idx = -1; 166 p->chunk_flags_idx = -1; 167 p->chunk_const_ib_idx = -1; 168 p->chunks_array = kmalloc(cs->num_chunks * sizeof(uint64_t), 169 M_DRM, M_ZERO | M_WAITOK); 170 if (p->chunks_array == NULL) { 171 return -ENOMEM; 172 } 173 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); 174 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr, 175 sizeof(uint64_t)*cs->num_chunks)) { 176 return -EFAULT; 177 } 178 p->cs_flags = 0; 179 p->nchunks = cs->num_chunks; 180 p->chunks = kmalloc(p->nchunks * sizeof(struct radeon_cs_chunk), 181 M_DRM, M_ZERO | M_WAITOK); 182 if (p->chunks == NULL) { 183 return -ENOMEM; 184 } 185 for (i = 0; i < p->nchunks; i++) { 186 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; 187 struct drm_radeon_cs_chunk user_chunk; 188 uint32_t __user *cdata; 189 190 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; 191 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr, 192 sizeof(struct drm_radeon_cs_chunk))) { 193 return -EFAULT; 194 } 195 p->chunks[i].length_dw = user_chunk.length_dw; 196 p->chunks[i].kdata = NULL; 197 p->chunks[i].chunk_id = user_chunk.chunk_id; 198 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data; 199 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { 200 p->chunk_relocs_idx = i; 201 } 202 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { 203 p->chunk_ib_idx = i; 204 /* zero length IB isn't useful */ 205 if (p->chunks[i].length_dw == 0) 206 return -EINVAL; 207 } 208 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) { 209 p->chunk_const_ib_idx = i; 210 /* zero length CONST IB isn't useful */ 211 if (p->chunks[i].length_dw == 0) 212 return -EINVAL; 213 } 214 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 215 p->chunk_flags_idx = i; 216 /* zero length flags aren't useful */ 217 if (p->chunks[i].length_dw == 0) 218 return -EINVAL; 219 } 220 221 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; 222 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) || 223 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) { 224 size = p->chunks[i].length_dw * sizeof(uint32_t); 225 p->chunks[i].kdata = kmalloc(size, M_DRM, 226 M_WAITOK); 227 if (p->chunks[i].kdata == NULL) { 228 return -ENOMEM; 229 } 230 if (DRM_COPY_FROM_USER(p->chunks[i].kdata, 231 p->chunks[i].user_ptr, size)) { 232 return -EFAULT; 233 } 234 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 235 p->cs_flags = p->chunks[i].kdata[0]; 236 if (p->chunks[i].length_dw > 1) 237 ring = p->chunks[i].kdata[1]; 238 if (p->chunks[i].length_dw > 2) 239 priority = (s32)p->chunks[i].kdata[2]; 240 } 241 } 242 } 243 244 /* these are KMS only */ 245 if (p->rdev) { 246 if ((p->cs_flags & RADEON_CS_USE_VM) && 247 !p->rdev->vm_manager.enabled) { 248 DRM_ERROR("VM not active on asic!\n"); 249 return -EINVAL; 250 } 251 252 /* we only support VM on SI+ */ 253 if ((p->rdev->family >= CHIP_TAHITI) && 254 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { 255 DRM_ERROR("VM required on SI+!\n"); 256 return -EINVAL; 257 } 258 259 if (radeon_cs_get_ring(p, ring, priority)) 260 return -EINVAL; 261 } 262 263 /* deal with non-vm */ 264 if ((p->chunk_ib_idx != -1) && 265 ((p->cs_flags & RADEON_CS_USE_VM) == 0) && 266 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) { 267 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) { 268 DRM_ERROR("cs IB too big: %d\n", 269 p->chunks[p->chunk_ib_idx].length_dw); 270 return -EINVAL; 271 } 272 if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) { 273 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, 274 M_DRM, 275 M_WAITOK); 276 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, 277 M_DRM, 278 M_WAITOK); 279 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL || 280 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) { 281 drm_free(p->chunks[p->chunk_ib_idx].kpage[0], 282 M_DRM); 283 drm_free(p->chunks[p->chunk_ib_idx].kpage[1], 284 M_DRM); 285 p->chunks[p->chunk_ib_idx].kpage[0] = NULL; 286 p->chunks[p->chunk_ib_idx].kpage[1] = NULL; 287 return -ENOMEM; 288 } 289 } 290 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1; 291 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1; 292 p->chunks[p->chunk_ib_idx].last_copied_page = -1; 293 p->chunks[p->chunk_ib_idx].last_page_index = 294 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE; 295 } 296 297 return 0; 298 } 299 300 /** 301 * cs_parser_fini() - clean parser states 302 * @parser: parser structure holding parsing context. 303 * @error: error number 304 * 305 * If error is set than unvalidate buffer, otherwise just free memory 306 * used by parsing context. 307 **/ 308 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) 309 { 310 unsigned i; 311 312 if (!error) { 313 ttm_eu_fence_buffer_objects(&parser->validated, 314 parser->ib.fence); 315 } else { 316 ttm_eu_backoff_reservation(&parser->validated); 317 } 318 319 if (parser->relocs != NULL) { 320 for (i = 0; i < parser->nrelocs; i++) { 321 if (parser->relocs[i].gobj) 322 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj); 323 } 324 } 325 drm_free(parser->track, M_DRM); 326 drm_free(parser->relocs, M_DRM); 327 drm_free(parser->relocs_ptr, M_DRM); 328 for (i = 0; i < parser->nchunks; i++) { 329 drm_free(parser->chunks[i].kdata, M_DRM); 330 if ((parser->rdev->flags & RADEON_IS_AGP)) { 331 drm_free(parser->chunks[i].kpage[0], M_DRM); 332 drm_free(parser->chunks[i].kpage[1], M_DRM); 333 } 334 } 335 drm_free(parser->chunks, M_DRM); 336 drm_free(parser->chunks_array, M_DRM); 337 radeon_ib_free(parser->rdev, &parser->ib); 338 radeon_ib_free(parser->rdev, &parser->const_ib); 339 } 340 341 static int radeon_cs_ib_chunk(struct radeon_device *rdev, 342 struct radeon_cs_parser *parser) 343 { 344 struct radeon_cs_chunk *ib_chunk; 345 int r; 346 347 if (parser->chunk_ib_idx == -1) 348 return 0; 349 350 if (parser->cs_flags & RADEON_CS_USE_VM) 351 return 0; 352 353 ib_chunk = &parser->chunks[parser->chunk_ib_idx]; 354 /* Copy the packet into the IB, the parser will read from the 355 * input memory (cached) and write to the IB (which can be 356 * uncached). 357 */ 358 r = radeon_ib_get(rdev, parser->ring, &parser->ib, 359 NULL, ib_chunk->length_dw * 4); 360 if (r) { 361 DRM_ERROR("Failed to get ib !\n"); 362 return r; 363 } 364 parser->ib.length_dw = ib_chunk->length_dw; 365 r = radeon_cs_parse(rdev, parser->ring, parser); 366 if (r || parser->parser_error) { 367 DRM_ERROR("Invalid command stream !\n"); 368 return r; 369 } 370 r = radeon_cs_finish_pages(parser); 371 if (r) { 372 DRM_ERROR("Invalid command stream !\n"); 373 return r; 374 } 375 radeon_cs_sync_rings(parser); 376 r = radeon_ib_schedule(rdev, &parser->ib, NULL); 377 if (r) { 378 DRM_ERROR("Failed to schedule IB !\n"); 379 } 380 return r; 381 } 382 383 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser, 384 struct radeon_vm *vm) 385 { 386 struct radeon_device *rdev = parser->rdev; 387 struct radeon_bo_list *lobj; 388 struct radeon_bo *bo; 389 int r; 390 391 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem); 392 if (r) { 393 return r; 394 } 395 list_for_each_entry(lobj, &parser->validated, tv.head) { 396 bo = lobj->bo; 397 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem); 398 if (r) { 399 return r; 400 } 401 } 402 return 0; 403 } 404 405 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, 406 struct radeon_cs_parser *parser) 407 { 408 struct radeon_cs_chunk *ib_chunk; 409 struct radeon_fpriv *fpriv = parser->filp->driver_priv; 410 struct radeon_vm *vm = &fpriv->vm; 411 int r; 412 413 if (parser->chunk_ib_idx == -1) 414 return 0; 415 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) 416 return 0; 417 418 if ((rdev->family >= CHIP_TAHITI) && 419 (parser->chunk_const_ib_idx != -1)) { 420 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx]; 421 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 422 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); 423 return -EINVAL; 424 } 425 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, 426 vm, ib_chunk->length_dw * 4); 427 if (r) { 428 DRM_ERROR("Failed to get const ib !\n"); 429 return r; 430 } 431 parser->const_ib.is_const_ib = true; 432 parser->const_ib.length_dw = ib_chunk->length_dw; 433 /* Copy the packet into the IB */ 434 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr, 435 ib_chunk->length_dw * 4)) { 436 return -EFAULT; 437 } 438 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib); 439 if (r) { 440 return r; 441 } 442 } 443 444 ib_chunk = &parser->chunks[parser->chunk_ib_idx]; 445 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 446 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); 447 return -EINVAL; 448 } 449 r = radeon_ib_get(rdev, parser->ring, &parser->ib, 450 vm, ib_chunk->length_dw * 4); 451 if (r) { 452 DRM_ERROR("Failed to get ib !\n"); 453 return r; 454 } 455 parser->ib.length_dw = ib_chunk->length_dw; 456 /* Copy the packet into the IB */ 457 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr, 458 ib_chunk->length_dw * 4)) { 459 return -EFAULT; 460 } 461 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib); 462 if (r) { 463 return r; 464 } 465 466 lockmgr(&rdev->vm_manager.lock, LK_EXCLUSIVE); 467 lockmgr(&vm->mutex, LK_EXCLUSIVE); 468 r = radeon_vm_alloc_pt(rdev, vm); 469 if (r) { 470 goto out; 471 } 472 r = radeon_bo_vm_update_pte(parser, vm); 473 if (r) { 474 goto out; 475 } 476 radeon_cs_sync_rings(parser); 477 radeon_ib_sync_to(&parser->ib, vm->fence); 478 radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id( 479 rdev, vm, parser->ring)); 480 481 if ((rdev->family >= CHIP_TAHITI) && 482 (parser->chunk_const_ib_idx != -1)) { 483 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib); 484 } else { 485 r = radeon_ib_schedule(rdev, &parser->ib, NULL); 486 } 487 488 if (!r) { 489 radeon_vm_fence(rdev, vm, parser->ib.fence); 490 } 491 492 out: 493 radeon_vm_add_to_lru(rdev, vm); 494 lockmgr(&vm->mutex, LK_RELEASE); 495 lockmgr(&rdev->vm_manager.lock, LK_RELEASE); 496 return r; 497 } 498 499 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) 500 { 501 if (r == -EDEADLK) { 502 r = radeon_gpu_reset(rdev); 503 if (!r) 504 r = -EAGAIN; 505 } 506 return r; 507 } 508 509 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 510 { 511 struct radeon_device *rdev = dev->dev_private; 512 struct radeon_cs_parser parser; 513 int r; 514 515 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE); 516 if (!rdev->accel_working) { 517 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 518 return -EBUSY; 519 } 520 /* initialize parser */ 521 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 522 parser.filp = filp; 523 parser.rdev = rdev; 524 parser.dev = rdev->dev; 525 parser.family = rdev->family; 526 r = radeon_cs_parser_init(&parser, data); 527 if (r) { 528 DRM_ERROR("Failed to initialize parser !\n"); 529 radeon_cs_parser_fini(&parser, r); 530 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 531 r = radeon_cs_handle_lockup(rdev, r); 532 return r; 533 } 534 r = radeon_cs_parser_relocs(&parser); 535 if (r) { 536 if (r != -ERESTARTSYS) 537 DRM_ERROR("Failed to parse relocation %d!\n", r); 538 radeon_cs_parser_fini(&parser, r); 539 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 540 r = radeon_cs_handle_lockup(rdev, r); 541 return r; 542 } 543 r = radeon_cs_ib_chunk(rdev, &parser); 544 if (r) { 545 goto out; 546 } 547 r = radeon_cs_ib_vm_chunk(rdev, &parser); 548 if (r) { 549 goto out; 550 } 551 out: 552 radeon_cs_parser_fini(&parser, r); 553 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 554 r = radeon_cs_handle_lockup(rdev, r); 555 return r; 556 } 557 558 int radeon_cs_finish_pages(struct radeon_cs_parser *p) 559 { 560 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 561 int i; 562 int size = PAGE_SIZE; 563 564 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) { 565 if (i == ibc->last_page_index) { 566 size = (ibc->length_dw * 4) % PAGE_SIZE; 567 if (size == 0) 568 size = PAGE_SIZE; 569 } 570 571 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), 572 (char *)ibc->user_ptr + (i * PAGE_SIZE), 573 size)) 574 return -EFAULT; 575 } 576 return 0; 577 } 578 579 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx) 580 { 581 int new_page; 582 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 583 int i; 584 int size = PAGE_SIZE; 585 bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ? 586 false : true; 587 588 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) { 589 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), 590 (char *)ibc->user_ptr + (i * PAGE_SIZE), 591 PAGE_SIZE)) { 592 p->parser_error = -EFAULT; 593 return 0; 594 } 595 } 596 597 if (pg_idx == ibc->last_page_index) { 598 size = (ibc->length_dw * 4) % PAGE_SIZE; 599 if (size == 0) 600 size = PAGE_SIZE; 601 } 602 603 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1; 604 if (copy1) 605 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4)); 606 607 if (DRM_COPY_FROM_USER(ibc->kpage[new_page], 608 (char *)ibc->user_ptr + (pg_idx * PAGE_SIZE), 609 size)) { 610 p->parser_error = -EFAULT; 611 return 0; 612 } 613 614 /* copy to IB for non single case */ 615 if (!copy1) 616 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size); 617 618 ibc->last_copied_page = pg_idx; 619 ibc->kpage_idx[new_page] = pg_idx; 620 621 return new_page; 622 } 623 624 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 625 { 626 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 627 u32 pg_idx, pg_offset; 628 u32 idx_value = 0; 629 int new_page; 630 631 pg_idx = (idx * 4) / PAGE_SIZE; 632 pg_offset = (idx * 4) % PAGE_SIZE; 633 634 if (ibc->kpage_idx[0] == pg_idx) 635 return ibc->kpage[0][pg_offset/4]; 636 if (ibc->kpage_idx[1] == pg_idx) 637 return ibc->kpage[1][pg_offset/4]; 638 639 new_page = radeon_cs_update_pages(p, pg_idx); 640 if (new_page < 0) { 641 p->parser_error = new_page; 642 return 0; 643 } 644 645 idx_value = ibc->kpage[new_page][pg_offset/4]; 646 return idx_value; 647 } 648 649 /** 650 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet 651 * @parser: parser structure holding parsing context. 652 * @pkt: where to store packet information 653 * 654 * Assume that chunk_ib_index is properly set. Will return -EINVAL 655 * if packet is bigger than remaining ib size. or if packets is unknown. 656 **/ 657 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 658 struct radeon_cs_packet *pkt, 659 unsigned idx) 660 { 661 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 662 struct radeon_device *rdev = p->rdev; 663 uint32_t header; 664 665 if (idx >= ib_chunk->length_dw) { 666 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 667 idx, ib_chunk->length_dw); 668 return -EINVAL; 669 } 670 header = radeon_get_ib_value(p, idx); 671 pkt->idx = idx; 672 pkt->type = RADEON_CP_PACKET_GET_TYPE(header); 673 pkt->count = RADEON_CP_PACKET_GET_COUNT(header); 674 pkt->one_reg_wr = 0; 675 switch (pkt->type) { 676 case RADEON_PACKET_TYPE0: 677 if (rdev->family < CHIP_R600) { 678 pkt->reg = R100_CP_PACKET0_GET_REG(header); 679 pkt->one_reg_wr = 680 RADEON_CP_PACKET0_GET_ONE_REG_WR(header); 681 } else 682 pkt->reg = R600_CP_PACKET0_GET_REG(header); 683 break; 684 case RADEON_PACKET_TYPE3: 685 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header); 686 break; 687 case RADEON_PACKET_TYPE2: 688 pkt->count = -1; 689 break; 690 default: 691 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 692 return -EINVAL; 693 } 694 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 695 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 696 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 697 return -EINVAL; 698 } 699 return 0; 700 } 701 702 /** 703 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP 704 * @p: structure holding the parser context. 705 * 706 * Check if the next packet is NOP relocation packet3. 707 **/ 708 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) 709 { 710 struct radeon_cs_packet p3reloc; 711 int r; 712 713 r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 714 if (r) 715 return false; 716 if (p3reloc.type != RADEON_PACKET_TYPE3) 717 return false; 718 if (p3reloc.opcode != RADEON_PACKET3_NOP) 719 return false; 720 return true; 721 } 722 723 /** 724 * radeon_cs_dump_packet() - dump raw packet context 725 * @p: structure holding the parser context. 726 * @pkt: structure holding the packet. 727 * 728 * Used mostly for debugging and error reporting. 729 **/ 730 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 731 struct radeon_cs_packet *pkt) 732 { 733 volatile uint32_t *ib; 734 unsigned i; 735 unsigned idx; 736 737 ib = p->ib.ptr; 738 idx = pkt->idx; 739 for (i = 0; i <= (pkt->count + 1); i++, idx++) 740 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 741 } 742 743 /** 744 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet 745 * @parser: parser structure holding parsing context. 746 * @data: pointer to relocation data 747 * @offset_start: starting offset 748 * @offset_mask: offset mask (to align start offset on) 749 * @reloc: reloc informations 750 * 751 * Check if next packet is relocation packet3, do bo validation and compute 752 * GPU offset using the provided start. 753 **/ 754 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 755 struct radeon_cs_reloc **cs_reloc, 756 int nomm) 757 { 758 struct radeon_cs_chunk *relocs_chunk; 759 struct radeon_cs_packet p3reloc; 760 unsigned idx; 761 int r; 762 763 if (p->chunk_relocs_idx == -1) { 764 DRM_ERROR("No relocation chunk !\n"); 765 return -EINVAL; 766 } 767 *cs_reloc = NULL; 768 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 769 r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 770 if (r) 771 return r; 772 p->idx += p3reloc.count + 2; 773 if (p3reloc.type != RADEON_PACKET_TYPE3 || 774 p3reloc.opcode != RADEON_PACKET3_NOP) { 775 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 776 p3reloc.idx); 777 radeon_cs_dump_packet(p, &p3reloc); 778 return -EINVAL; 779 } 780 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 781 if (idx >= relocs_chunk->length_dw) { 782 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 783 idx, relocs_chunk->length_dw); 784 radeon_cs_dump_packet(p, &p3reloc); 785 return -EINVAL; 786 } 787 /* FIXME: we assume reloc size is 4 dwords */ 788 if (nomm) { 789 *cs_reloc = p->relocs; 790 (*cs_reloc)->lobj.gpu_offset = 791 (u64)relocs_chunk->kdata[idx + 3] << 32; 792 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; 793 } else 794 *cs_reloc = p->relocs_ptr[(idx / 4)]; 795 return 0; 796 } 797