1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * 26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_display.c 254885 2013-08-25 19:37:15Z dumbbell $ 27 */ 28 29 #include <drm/drmP.h> 30 #include <uapi_drm/radeon_drm.h> 31 #include "radeon.h" 32 33 #include "atom.h" 34 35 #ifdef PM_TODO 36 #include <linux/pm_runtime.h> 37 #endif 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_plane_helper.h> 40 #include <drm/drm_edid.h> 41 #include <linux/err.h> 42 43 #include <linux/gcd.h> 44 45 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 46 { 47 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 48 struct drm_device *dev = crtc->dev; 49 struct radeon_device *rdev = dev->dev_private; 50 int i; 51 52 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 53 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 54 55 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 56 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 57 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 58 59 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 60 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 61 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 62 63 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 64 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 65 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 66 67 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 68 for (i = 0; i < 256; i++) { 69 WREG32(AVIVO_DC_LUT_30_COLOR, 70 (radeon_crtc->lut_r[i] << 20) | 71 (radeon_crtc->lut_g[i] << 10) | 72 (radeon_crtc->lut_b[i] << 0)); 73 } 74 75 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 76 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 77 } 78 79 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 80 { 81 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 82 struct drm_device *dev = crtc->dev; 83 struct radeon_device *rdev = dev->dev_private; 84 int i; 85 86 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 87 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 88 89 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 90 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 91 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 92 93 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 94 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 95 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 96 97 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 98 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 99 100 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 101 for (i = 0; i < 256; i++) { 102 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 103 (radeon_crtc->lut_r[i] << 20) | 104 (radeon_crtc->lut_g[i] << 10) | 105 (radeon_crtc->lut_b[i] << 0)); 106 } 107 } 108 109 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 110 { 111 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 112 struct drm_device *dev = crtc->dev; 113 struct radeon_device *rdev = dev->dev_private; 114 int i; 115 116 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 117 118 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 119 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 120 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 121 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 122 NI_GRPH_PRESCALE_BYPASS); 123 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 124 NI_OVL_PRESCALE_BYPASS); 125 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 126 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 127 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 128 129 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 130 131 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 132 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 133 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 134 135 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 136 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 137 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 138 139 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 140 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 141 142 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 143 for (i = 0; i < 256; i++) { 144 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 145 (radeon_crtc->lut_r[i] << 20) | 146 (radeon_crtc->lut_g[i] << 10) | 147 (radeon_crtc->lut_b[i] << 0)); 148 } 149 150 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 151 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 152 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 153 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 154 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 155 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 156 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 157 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 158 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 159 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 160 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 161 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 162 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | 163 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 164 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 165 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 166 if (ASIC_IS_DCE8(rdev)) { 167 /* XXX this only needs to be programmed once per crtc at startup, 168 * not sure where the best place for it is 169 */ 170 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 171 CIK_CURSOR_ALPHA_BLND_ENA); 172 } 173 } 174 175 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 176 { 177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 178 struct drm_device *dev = crtc->dev; 179 struct radeon_device *rdev = dev->dev_private; 180 int i; 181 uint32_t dac2_cntl; 182 183 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 184 if (radeon_crtc->crtc_id == 0) 185 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 186 else 187 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 188 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 189 190 WREG8(RADEON_PALETTE_INDEX, 0); 191 for (i = 0; i < 256; i++) { 192 WREG32(RADEON_PALETTE_30_DATA, 193 (radeon_crtc->lut_r[i] << 20) | 194 (radeon_crtc->lut_g[i] << 10) | 195 (radeon_crtc->lut_b[i] << 0)); 196 } 197 } 198 199 void radeon_crtc_load_lut(struct drm_crtc *crtc) 200 { 201 struct drm_device *dev = crtc->dev; 202 struct radeon_device *rdev = dev->dev_private; 203 204 if (!crtc->enabled) 205 return; 206 207 if (ASIC_IS_DCE5(rdev)) 208 dce5_crtc_load_lut(crtc); 209 else if (ASIC_IS_DCE4(rdev)) 210 dce4_crtc_load_lut(crtc); 211 else if (ASIC_IS_AVIVO(rdev)) 212 avivo_crtc_load_lut(crtc); 213 else 214 legacy_crtc_load_lut(crtc); 215 } 216 217 /** Sets the color ramps on behalf of fbcon */ 218 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 219 u16 blue, int regno) 220 { 221 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 222 223 radeon_crtc->lut_r[regno] = red >> 6; 224 radeon_crtc->lut_g[regno] = green >> 6; 225 radeon_crtc->lut_b[regno] = blue >> 6; 226 } 227 228 /** Gets the color ramps on behalf of fbcon */ 229 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 230 u16 *blue, int regno) 231 { 232 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 233 234 *red = radeon_crtc->lut_r[regno] << 6; 235 *green = radeon_crtc->lut_g[regno] << 6; 236 *blue = radeon_crtc->lut_b[regno] << 6; 237 } 238 239 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 240 u16 *blue, uint32_t start, uint32_t size) 241 { 242 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 243 int end = (start + size > 256) ? 256 : start + size, i; 244 245 /* userspace palettes are always correct as is */ 246 for (i = start; i < end; i++) { 247 radeon_crtc->lut_r[i] = red[i] >> 6; 248 radeon_crtc->lut_g[i] = green[i] >> 6; 249 radeon_crtc->lut_b[i] = blue[i] >> 6; 250 } 251 radeon_crtc_load_lut(crtc); 252 } 253 254 static void radeon_crtc_destroy(struct drm_crtc *crtc) 255 { 256 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 257 258 drm_crtc_cleanup(crtc); 259 destroy_workqueue(radeon_crtc->flip_queue); 260 kfree(radeon_crtc); 261 } 262 263 /** 264 * radeon_unpin_work_func - unpin old buffer object 265 * 266 * @__work - kernel work item 267 * 268 * Unpin the old frame buffer object outside of the interrupt handler 269 */ 270 static void radeon_unpin_work_func(struct work_struct *__work) 271 { 272 struct radeon_flip_work *work = 273 container_of(__work, struct radeon_flip_work, unpin_work); 274 int r; 275 276 /* unpin of the old buffer */ 277 r = radeon_bo_reserve(work->old_rbo, false); 278 if (likely(r == 0)) { 279 r = radeon_bo_unpin(work->old_rbo); 280 if (unlikely(r != 0)) { 281 DRM_ERROR("failed to unpin buffer after flip\n"); 282 } 283 radeon_bo_unreserve(work->old_rbo); 284 } else 285 DRM_ERROR("failed to reserve buffer after flip\n"); 286 287 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 288 kfree(work); 289 } 290 291 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 292 { 293 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 294 u32 update_pending; 295 int vpos, hpos; 296 297 /* can happen during initialization */ 298 if (radeon_crtc == NULL) 299 return; 300 301 /* Skip the pageflip completion check below (based on polling) on 302 * asics which reliably support hw pageflip completion irqs. pflip 303 * irqs are a reliable and race-free method of handling pageflip 304 * completion detection. A use_pflipirq module parameter < 2 allows 305 * to override this in case of asics with faulty pflip irqs. 306 * A module parameter of 0 would only use this polling based path, 307 * a parameter of 1 would use pflip irq only as a backup to this 308 * path, as in Linux 3.16. 309 */ 310 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 311 return; 312 313 lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE); 314 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 315 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 316 "RADEON_FLIP_SUBMITTED(%d)\n", 317 radeon_crtc->flip_status, 318 RADEON_FLIP_SUBMITTED); 319 lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 320 return; 321 } 322 323 update_pending = radeon_page_flip_pending(rdev, crtc_id); 324 325 /* Has the pageflip already completed in crtc, or is it certain 326 * to complete in this vblank? 327 */ 328 if (update_pending && 329 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0, 330 &vpos, &hpos, NULL, NULL)) && 331 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 332 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 333 /* crtc didn't flip in this target vblank interval, 334 * but flip is pending in crtc. Based on the current 335 * scanout position we know that the current frame is 336 * (nearly) complete and the flip will (likely) 337 * complete before the start of the next frame. 338 */ 339 update_pending = 0; 340 } 341 lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 342 if (!update_pending) 343 radeon_crtc_handle_flip(rdev, crtc_id); 344 } 345 346 /** 347 * radeon_crtc_handle_flip - page flip completed 348 * 349 * @rdev: radeon device pointer 350 * @crtc_id: crtc number this event is for 351 * 352 * Called when we are sure that a page flip for this crtc is completed. 353 */ 354 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 355 { 356 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 357 struct radeon_flip_work *work; 358 359 /* this can happen at init */ 360 if (radeon_crtc == NULL) 361 return; 362 363 lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE); 364 work = radeon_crtc->flip_work; 365 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 366 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 367 "RADEON_FLIP_SUBMITTED(%d)\n", 368 radeon_crtc->flip_status, 369 RADEON_FLIP_SUBMITTED); 370 lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 371 return; 372 } 373 374 /* Pageflip completed. Clean up. */ 375 radeon_crtc->flip_status = RADEON_FLIP_NONE; 376 radeon_crtc->flip_work = NULL; 377 378 /* wakeup userspace */ 379 if (work->event) 380 drm_send_vblank_event(rdev->ddev, crtc_id, work->event); 381 382 lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 383 384 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 385 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 386 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 387 } 388 389 /** 390 * radeon_flip_work_func - page flip framebuffer 391 * 392 * @work - kernel work item 393 * 394 * Wait for the buffer object to become idle and do the actual page flip 395 */ 396 static void radeon_flip_work_func(struct work_struct *__work) 397 { 398 struct radeon_flip_work *work = 399 container_of(__work, struct radeon_flip_work, flip_work); 400 struct radeon_device *rdev = work->rdev; 401 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 402 403 struct drm_crtc *crtc = &radeon_crtc->base; 404 int r; 405 406 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE); 407 if (work->fence) { 408 r = radeon_fence_wait(work->fence, false); 409 if (r == -EDEADLK) { 410 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 411 do { 412 r = radeon_gpu_reset(rdev); 413 } while (r == -EAGAIN); 414 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE); 415 } 416 if (r) 417 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 418 419 /* We continue with the page flip even if we failed to wait on 420 * the fence, otherwise the DRM core and userspace will be 421 * confused about which BO the CRTC is scanning out 422 */ 423 424 radeon_fence_unref(&work->fence); 425 } 426 427 /* We borrow the event spin lock for protecting flip_status */ 428 lockmgr(&crtc->dev->event_lock, LK_EXCLUSIVE); 429 430 /* set the proper interrupt */ 431 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 432 433 /* do the flip (mmio) */ 434 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base); 435 436 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 437 lockmgr(&crtc->dev->event_lock, LK_RELEASE); 438 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 439 } 440 441 static int radeon_crtc_page_flip(struct drm_crtc *crtc, 442 struct drm_framebuffer *fb, 443 struct drm_pending_vblank_event *event, 444 uint32_t page_flip_flags) 445 { 446 struct drm_device *dev = crtc->dev; 447 struct radeon_device *rdev = dev->dev_private; 448 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 449 struct radeon_framebuffer *old_radeon_fb; 450 struct radeon_framebuffer *new_radeon_fb; 451 struct drm_gem_object *obj; 452 struct radeon_flip_work *work; 453 struct radeon_bo *new_rbo; 454 uint32_t tiling_flags, pitch_pixels; 455 uint64_t base; 456 int r; 457 458 work = kzalloc(sizeof *work, GFP_KERNEL); 459 if (work == NULL) 460 return -ENOMEM; 461 462 INIT_WORK(&work->flip_work, radeon_flip_work_func); 463 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 464 465 work->rdev = rdev; 466 work->crtc_id = radeon_crtc->crtc_id; 467 work->event = event; 468 469 /* schedule unpin of the old buffer */ 470 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 471 obj = old_radeon_fb->obj; 472 473 /* take a reference to the old object */ 474 drm_gem_object_reference(obj); 475 work->old_rbo = gem_to_radeon_bo(obj); 476 477 new_radeon_fb = to_radeon_framebuffer(fb); 478 obj = new_radeon_fb->obj; 479 new_rbo = gem_to_radeon_bo(obj); 480 481 lockmgr(&new_rbo->tbo.bdev->fence_lock, LK_EXCLUSIVE); 482 if (new_rbo->tbo.sync_obj) 483 work->fence = radeon_fence_ref(new_rbo->tbo.sync_obj); 484 lockmgr(&new_rbo->tbo.bdev->fence_lock, LK_RELEASE); 485 486 /* pin the new buffer */ 487 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 488 work->old_rbo, new_rbo); 489 490 r = radeon_bo_reserve(new_rbo, false); 491 if (unlikely(r != 0)) { 492 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 493 goto cleanup; 494 } 495 /* Only 27 bit offset for legacy CRTC */ 496 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 497 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 498 if (unlikely(r != 0)) { 499 radeon_bo_unreserve(new_rbo); 500 r = -EINVAL; 501 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 502 goto cleanup; 503 } 504 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 505 radeon_bo_unreserve(new_rbo); 506 507 if (!ASIC_IS_AVIVO(rdev)) { 508 /* crtc offset is from display base addr not FB location */ 509 base -= radeon_crtc->legacy_display_base_addr; 510 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 511 512 if (tiling_flags & RADEON_TILING_MACRO) { 513 if (ASIC_IS_R300(rdev)) { 514 base &= ~0x7ff; 515 } else { 516 int byteshift = fb->bits_per_pixel >> 4; 517 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 518 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 519 } 520 } else { 521 int offset = crtc->y * pitch_pixels + crtc->x; 522 switch (fb->bits_per_pixel) { 523 case 8: 524 default: 525 offset *= 1; 526 break; 527 case 15: 528 case 16: 529 offset *= 2; 530 break; 531 case 24: 532 offset *= 3; 533 break; 534 case 32: 535 offset *= 4; 536 break; 537 } 538 base += offset; 539 } 540 base &= ~7; 541 } 542 work->base = base; 543 544 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id); 545 if (r) { 546 DRM_ERROR("failed to get vblank before flip\n"); 547 goto pflip_cleanup; 548 } 549 550 /* We borrow the event spin lock for protecting flip_work */ 551 lockmgr(&crtc->dev->event_lock, LK_EXCLUSIVE); 552 553 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 554 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 555 lockmgr(&crtc->dev->event_lock, LK_RELEASE); 556 r = -EBUSY; 557 goto vblank_cleanup; 558 } 559 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 560 radeon_crtc->flip_work = work; 561 562 /* update crtc fb */ 563 crtc->primary->fb = fb; 564 565 lockmgr(&crtc->dev->event_lock, LK_RELEASE); 566 567 queue_work(radeon_crtc->flip_queue, &work->flip_work); 568 return 0; 569 570 vblank_cleanup: 571 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id); 572 573 pflip_cleanup: 574 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 575 DRM_ERROR("failed to reserve new rbo in error path\n"); 576 goto cleanup; 577 } 578 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 579 DRM_ERROR("failed to unpin new rbo in error path\n"); 580 } 581 radeon_bo_unreserve(new_rbo); 582 583 cleanup: 584 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 585 radeon_fence_unref(&work->fence); 586 kfree(work); 587 588 return r; 589 } 590 591 static int 592 radeon_crtc_set_config(struct drm_mode_set *set) 593 { 594 struct drm_device *dev; 595 struct radeon_device *rdev; 596 struct drm_crtc *crtc; 597 bool active = false; 598 int ret; 599 600 if (!set || !set->crtc) 601 return -EINVAL; 602 603 dev = set->crtc->dev; 604 605 #ifdef PM_TODO 606 ret = pm_runtime_get_sync(dev->dev); 607 if (ret < 0) 608 return ret; 609 #endif 610 611 ret = drm_crtc_helper_set_config(set); 612 613 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 614 if (crtc->enabled) 615 active = true; 616 617 #ifdef PM_TODO 618 pm_runtime_mark_last_busy(dev->dev); 619 #endif 620 621 rdev = dev->dev_private; 622 /* if we have active crtcs and we don't have a power ref, 623 take the current one */ 624 if (active && !rdev->have_disp_power_ref) { 625 rdev->have_disp_power_ref = true; 626 return ret; 627 } 628 /* if we have no active crtcs, then drop the power ref 629 we got before */ 630 if (!active && rdev->have_disp_power_ref) { 631 #ifdef PM_TODO 632 pm_runtime_put_autosuspend(dev->dev); 633 #endif 634 rdev->have_disp_power_ref = false; 635 } 636 637 /* drop the power reference we got coming in here */ 638 #ifdef PM_TODO 639 pm_runtime_put_autosuspend(dev->dev); 640 #endif 641 return ret; 642 } 643 static const struct drm_crtc_funcs radeon_crtc_funcs = { 644 .cursor_set = radeon_crtc_cursor_set, 645 .cursor_move = radeon_crtc_cursor_move, 646 .gamma_set = radeon_crtc_gamma_set, 647 .set_config = radeon_crtc_set_config, 648 .destroy = radeon_crtc_destroy, 649 .page_flip = radeon_crtc_page_flip, 650 }; 651 652 static void radeon_crtc_init(struct drm_device *dev, int index) 653 { 654 struct radeon_device *rdev = dev->dev_private; 655 struct radeon_crtc *radeon_crtc; 656 int i; 657 658 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 659 if (radeon_crtc == NULL) 660 return; 661 662 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 663 664 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 665 radeon_crtc->crtc_id = index; 666 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc"); 667 rdev->mode_info.crtcs[index] = radeon_crtc; 668 669 if (rdev->family >= CHIP_BONAIRE) { 670 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 671 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 672 } else { 673 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 674 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 675 } 676 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 677 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 678 679 #if 0 680 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 681 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 682 radeon_crtc->mode_set.num_connectors = 0; 683 #endif 684 685 for (i = 0; i < 256; i++) { 686 radeon_crtc->lut_r[i] = i << 2; 687 radeon_crtc->lut_g[i] = i << 2; 688 radeon_crtc->lut_b[i] = i << 2; 689 } 690 691 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 692 radeon_atombios_init_crtc(dev, radeon_crtc); 693 else 694 radeon_legacy_init_crtc(dev, radeon_crtc); 695 } 696 697 static const char *encoder_names[38] = { 698 "NONE", 699 "INTERNAL_LVDS", 700 "INTERNAL_TMDS1", 701 "INTERNAL_TMDS2", 702 "INTERNAL_DAC1", 703 "INTERNAL_DAC2", 704 "INTERNAL_SDVOA", 705 "INTERNAL_SDVOB", 706 "SI170B", 707 "CH7303", 708 "CH7301", 709 "INTERNAL_DVO1", 710 "EXTERNAL_SDVOA", 711 "EXTERNAL_SDVOB", 712 "TITFP513", 713 "INTERNAL_LVTM1", 714 "VT1623", 715 "HDMI_SI1930", 716 "HDMI_INTERNAL", 717 "INTERNAL_KLDSCP_TMDS1", 718 "INTERNAL_KLDSCP_DVO1", 719 "INTERNAL_KLDSCP_DAC1", 720 "INTERNAL_KLDSCP_DAC2", 721 "SI178", 722 "MVPU_FPGA", 723 "INTERNAL_DDI", 724 "VT1625", 725 "HDMI_SI1932", 726 "DP_AN9801", 727 "DP_DP501", 728 "INTERNAL_UNIPHY", 729 "INTERNAL_KLDSCP_LVTMA", 730 "INTERNAL_UNIPHY1", 731 "INTERNAL_UNIPHY2", 732 "NUTMEG", 733 "TRAVIS", 734 "INTERNAL_VCE", 735 "INTERNAL_UNIPHY3", 736 }; 737 738 static const char *hpd_names[6] = { 739 "HPD1", 740 "HPD2", 741 "HPD3", 742 "HPD4", 743 "HPD5", 744 "HPD6", 745 }; 746 747 static void radeon_print_display_setup(struct drm_device *dev) 748 { 749 struct drm_connector *connector; 750 struct radeon_connector *radeon_connector; 751 struct drm_encoder *encoder; 752 struct radeon_encoder *radeon_encoder; 753 uint32_t devices; 754 int i = 0; 755 756 DRM_INFO("Radeon Display Connectors\n"); 757 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 758 radeon_connector = to_radeon_connector(connector); 759 DRM_INFO("Connector %d:\n", i); 760 DRM_INFO(" %s\n", connector->name); 761 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 762 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 763 if (radeon_connector->ddc_bus) { 764 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 765 radeon_connector->ddc_bus->rec.mask_clk_reg, 766 radeon_connector->ddc_bus->rec.mask_data_reg, 767 radeon_connector->ddc_bus->rec.a_clk_reg, 768 radeon_connector->ddc_bus->rec.a_data_reg, 769 radeon_connector->ddc_bus->rec.en_clk_reg, 770 radeon_connector->ddc_bus->rec.en_data_reg, 771 radeon_connector->ddc_bus->rec.y_clk_reg, 772 radeon_connector->ddc_bus->rec.y_data_reg); 773 if (radeon_connector->router.ddc_valid) 774 DRM_INFO(" DDC Router 0x%x/0x%x\n", 775 radeon_connector->router.ddc_mux_control_pin, 776 radeon_connector->router.ddc_mux_state); 777 if (radeon_connector->router.cd_valid) 778 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 779 radeon_connector->router.cd_mux_control_pin, 780 radeon_connector->router.cd_mux_state); 781 } else { 782 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 783 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 784 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 785 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 786 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 787 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 788 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 789 } 790 DRM_INFO(" Encoders:\n"); 791 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 792 radeon_encoder = to_radeon_encoder(encoder); 793 devices = radeon_encoder->devices & radeon_connector->devices; 794 if (devices) { 795 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 796 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 797 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 798 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 799 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 800 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 801 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 802 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 803 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 804 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 805 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 806 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 807 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 808 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 809 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 810 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 811 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 812 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 813 if (devices & ATOM_DEVICE_TV1_SUPPORT) 814 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 815 if (devices & ATOM_DEVICE_CV_SUPPORT) 816 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 817 } 818 } 819 i++; 820 } 821 } 822 823 static bool radeon_setup_enc_conn(struct drm_device *dev) 824 { 825 struct radeon_device *rdev = dev->dev_private; 826 bool ret = false; 827 828 if (rdev->bios) { 829 if (rdev->is_atom_bios) { 830 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 831 if (ret == false) 832 ret = radeon_get_atom_connector_info_from_object_table(dev); 833 } else { 834 ret = radeon_get_legacy_connector_info_from_bios(dev); 835 if (ret == false) 836 ret = radeon_get_legacy_connector_info_from_table(dev); 837 } 838 } else { 839 if (!ASIC_IS_AVIVO(rdev)) 840 ret = radeon_get_legacy_connector_info_from_table(dev); 841 } 842 if (ret) { 843 radeon_setup_encoder_clones(dev); 844 radeon_print_display_setup(dev); 845 } 846 847 return ret; 848 } 849 850 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) 851 { 852 struct drm_device *dev = radeon_connector->base.dev; 853 struct radeon_device *rdev = dev->dev_private; 854 int ret = 0; 855 856 /* don't leak the edid if we already fetched it in detect() */ 857 if (radeon_connector->edid) 858 goto got_edid; 859 860 /* on hw with routers, select right port */ 861 if (radeon_connector->router.ddc_valid) 862 radeon_router_select_ddc_port(radeon_connector); 863 864 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) != 865 ENCODER_OBJECT_ID_NONE) { 866 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 867 868 if (dig->dp_i2c_bus) 869 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 870 dig->dp_i2c_bus->adapter); 871 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 872 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { 873 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 874 875 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 876 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) 877 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 878 dig->dp_i2c_bus->adapter); 879 else if (radeon_connector->ddc_bus && !radeon_connector->edid) 880 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 881 radeon_connector->ddc_bus->adapter); 882 } else { 883 if (radeon_connector->ddc_bus && !radeon_connector->edid) 884 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 885 radeon_connector->ddc_bus->adapter); 886 } 887 888 if (!radeon_connector->edid) { 889 if (rdev->is_atom_bios) { 890 /* some laptops provide a hardcoded edid in rom for LCDs */ 891 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || 892 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) 893 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); 894 } else 895 /* some servers provide a hardcoded edid in rom for KVMs */ 896 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); 897 } 898 if (radeon_connector->edid) { 899 got_edid: 900 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); 901 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); 902 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid); 903 #if 0 904 /* XXX Dragonfly does not support HDMI deep colors safely for now */ 905 if (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 906 radeon_connector->base.display_info.bpc = 8; 907 } 908 #endif 909 return ret; 910 } 911 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); 912 return 0; 913 } 914 915 /* avivo */ 916 917 /** 918 * avivo_reduce_ratio - fractional number reduction 919 * 920 * @nom: nominator 921 * @den: denominator 922 * @nom_min: minimum value for nominator 923 * @den_min: minimum value for denominator 924 * 925 * Find the greatest common divisor and apply it on both nominator and 926 * denominator, but make nominator and denominator are at least as large 927 * as their minimum values. 928 */ 929 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 930 unsigned nom_min, unsigned den_min) 931 { 932 unsigned tmp; 933 934 /* reduce the numbers to a simpler ratio */ 935 tmp = gcd64(*nom, *den); 936 *nom /= tmp; 937 *den /= tmp; 938 939 /* make sure nominator is large enough */ 940 if (*nom < nom_min) { 941 tmp = DIV_ROUND_UP(nom_min, *nom); 942 *nom *= tmp; 943 *den *= tmp; 944 } 945 946 /* make sure the denominator is large enough */ 947 if (*den < den_min) { 948 tmp = DIV_ROUND_UP(den_min, *den); 949 *nom *= tmp; 950 *den *= tmp; 951 } 952 } 953 954 /** 955 * avivo_get_fb_ref_div - feedback and ref divider calculation 956 * 957 * @nom: nominator 958 * @den: denominator 959 * @post_div: post divider 960 * @fb_div_max: feedback divider maximum 961 * @ref_div_max: reference divider maximum 962 * @fb_div: resulting feedback divider 963 * @ref_div: resulting reference divider 964 * 965 * Calculate feedback and reference divider for a given post divider. Makes 966 * sure we stay within the limits. 967 */ 968 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 969 unsigned fb_div_max, unsigned ref_div_max, 970 unsigned *fb_div, unsigned *ref_div) 971 { 972 /* limit reference * post divider to a maximum */ 973 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 974 975 /* get matching reference and feedback divider */ 976 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 977 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 978 979 /* limit fb divider to its maximum */ 980 if (*fb_div > fb_div_max) { 981 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 982 *fb_div = fb_div_max; 983 } 984 } 985 986 /** 987 * radeon_compute_pll_avivo - compute PLL paramaters 988 * 989 * @pll: information about the PLL 990 * @dot_clock_p: resulting pixel clock 991 * fb_div_p: resulting feedback divider 992 * frac_fb_div_p: fractional part of the feedback divider 993 * ref_div_p: resulting reference divider 994 * post_div_p: resulting reference divider 995 * 996 * Try to calculate the PLL parameters to generate the given frequency: 997 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 998 */ 999 void radeon_compute_pll_avivo(struct radeon_pll *pll, 1000 u32 freq, 1001 u32 *dot_clock_p, 1002 u32 *fb_div_p, 1003 u32 *frac_fb_div_p, 1004 u32 *ref_div_p, 1005 u32 *post_div_p) 1006 { 1007 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 1008 freq : freq / 10; 1009 1010 unsigned fb_div_min, fb_div_max, fb_div; 1011 unsigned post_div_min, post_div_max, post_div; 1012 unsigned ref_div_min, ref_div_max, ref_div; 1013 unsigned post_div_best, diff_best; 1014 unsigned nom, den; 1015 1016 /* determine allowed feedback divider range */ 1017 fb_div_min = pll->min_feedback_div; 1018 fb_div_max = pll->max_feedback_div; 1019 1020 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1021 fb_div_min *= 10; 1022 fb_div_max *= 10; 1023 } 1024 1025 /* determine allowed ref divider range */ 1026 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1027 ref_div_min = pll->reference_div; 1028 else 1029 ref_div_min = pll->min_ref_div; 1030 1031 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 1032 pll->flags & RADEON_PLL_USE_REF_DIV) 1033 ref_div_max = pll->reference_div; 1034 else 1035 ref_div_max = pll->max_ref_div; 1036 1037 /* determine allowed post divider range */ 1038 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 1039 post_div_min = pll->post_div; 1040 post_div_max = pll->post_div; 1041 } else { 1042 unsigned vco_min, vco_max; 1043 1044 if (pll->flags & RADEON_PLL_IS_LCD) { 1045 vco_min = pll->lcd_pll_out_min; 1046 vco_max = pll->lcd_pll_out_max; 1047 } else { 1048 vco_min = pll->pll_out_min; 1049 vco_max = pll->pll_out_max; 1050 } 1051 1052 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1053 vco_min *= 10; 1054 vco_max *= 10; 1055 } 1056 1057 post_div_min = vco_min / target_clock; 1058 if ((target_clock * post_div_min) < vco_min) 1059 ++post_div_min; 1060 if (post_div_min < pll->min_post_div) 1061 post_div_min = pll->min_post_div; 1062 1063 post_div_max = vco_max / target_clock; 1064 if ((target_clock * post_div_max) > vco_max) 1065 --post_div_max; 1066 if (post_div_max > pll->max_post_div) 1067 post_div_max = pll->max_post_div; 1068 } 1069 1070 /* represent the searched ratio as fractional number */ 1071 nom = target_clock; 1072 den = pll->reference_freq; 1073 1074 /* reduce the numbers to a simpler ratio */ 1075 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1076 1077 /* now search for a post divider */ 1078 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1079 post_div_best = post_div_min; 1080 else 1081 post_div_best = post_div_max; 1082 diff_best = ~0; 1083 1084 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1085 unsigned diff; 1086 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1087 ref_div_max, &fb_div, &ref_div); 1088 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1089 (ref_div * post_div)); 1090 1091 if (diff < diff_best || (diff == diff_best && 1092 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1093 1094 post_div_best = post_div; 1095 diff_best = diff; 1096 } 1097 } 1098 post_div = post_div_best; 1099 1100 /* get the feedback and reference divider for the optimal value */ 1101 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1102 &fb_div, &ref_div); 1103 1104 /* reduce the numbers to a simpler ratio once more */ 1105 /* this also makes sure that the reference divider is large enough */ 1106 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1107 1108 /* avoid high jitter with small fractional dividers */ 1109 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1110 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1111 if (fb_div < fb_div_min) { 1112 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1113 fb_div *= tmp; 1114 ref_div *= tmp; 1115 } 1116 } 1117 1118 /* and finally save the result */ 1119 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1120 *fb_div_p = fb_div / 10; 1121 *frac_fb_div_p = fb_div % 10; 1122 } else { 1123 *fb_div_p = fb_div; 1124 *frac_fb_div_p = 0; 1125 } 1126 1127 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1128 (pll->reference_freq * *frac_fb_div_p)) / 1129 (ref_div * post_div * 10); 1130 *ref_div_p = ref_div; 1131 *post_div_p = post_div; 1132 1133 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1134 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1135 ref_div, post_div); 1136 } 1137 1138 /* pre-avivo */ 1139 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1140 { 1141 uint64_t mod; 1142 1143 n += d / 2; 1144 1145 mod = do_div(n, d); 1146 return n; 1147 } 1148 1149 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1150 uint64_t freq, 1151 uint32_t *dot_clock_p, 1152 uint32_t *fb_div_p, 1153 uint32_t *frac_fb_div_p, 1154 uint32_t *ref_div_p, 1155 uint32_t *post_div_p) 1156 { 1157 uint32_t min_ref_div = pll->min_ref_div; 1158 uint32_t max_ref_div = pll->max_ref_div; 1159 uint32_t min_post_div = pll->min_post_div; 1160 uint32_t max_post_div = pll->max_post_div; 1161 uint32_t min_fractional_feed_div = 0; 1162 uint32_t max_fractional_feed_div = 0; 1163 uint32_t best_vco = pll->best_vco; 1164 uint32_t best_post_div = 1; 1165 uint32_t best_ref_div = 1; 1166 uint32_t best_feedback_div = 1; 1167 uint32_t best_frac_feedback_div = 0; 1168 uint32_t best_freq = -1; 1169 uint32_t best_error = 0xffffffff; 1170 uint32_t best_vco_diff = 1; 1171 uint32_t post_div; 1172 u32 pll_out_min, pll_out_max; 1173 1174 DRM_DEBUG_KMS("PLL freq %ju %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1175 freq = freq * 1000; 1176 1177 if (pll->flags & RADEON_PLL_IS_LCD) { 1178 pll_out_min = pll->lcd_pll_out_min; 1179 pll_out_max = pll->lcd_pll_out_max; 1180 } else { 1181 pll_out_min = pll->pll_out_min; 1182 pll_out_max = pll->pll_out_max; 1183 } 1184 1185 if (pll_out_min > 64800) 1186 pll_out_min = 64800; 1187 1188 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1189 min_ref_div = max_ref_div = pll->reference_div; 1190 else { 1191 while (min_ref_div < max_ref_div-1) { 1192 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1193 uint32_t pll_in = pll->reference_freq / mid; 1194 if (pll_in < pll->pll_in_min) 1195 max_ref_div = mid; 1196 else if (pll_in > pll->pll_in_max) 1197 min_ref_div = mid; 1198 else 1199 break; 1200 } 1201 } 1202 1203 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1204 min_post_div = max_post_div = pll->post_div; 1205 1206 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1207 min_fractional_feed_div = pll->min_frac_feedback_div; 1208 max_fractional_feed_div = pll->max_frac_feedback_div; 1209 } 1210 1211 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1212 uint32_t ref_div; 1213 1214 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1215 continue; 1216 1217 /* legacy radeons only have a few post_divs */ 1218 if (pll->flags & RADEON_PLL_LEGACY) { 1219 if ((post_div == 5) || 1220 (post_div == 7) || 1221 (post_div == 9) || 1222 (post_div == 10) || 1223 (post_div == 11) || 1224 (post_div == 13) || 1225 (post_div == 14) || 1226 (post_div == 15)) 1227 continue; 1228 } 1229 1230 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1231 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1232 uint32_t pll_in = pll->reference_freq / ref_div; 1233 uint32_t min_feed_div = pll->min_feedback_div; 1234 uint32_t max_feed_div = pll->max_feedback_div + 1; 1235 1236 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1237 continue; 1238 1239 while (min_feed_div < max_feed_div) { 1240 uint32_t vco; 1241 uint32_t min_frac_feed_div = min_fractional_feed_div; 1242 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1243 uint32_t frac_feedback_div; 1244 uint64_t tmp; 1245 1246 feedback_div = (min_feed_div + max_feed_div) / 2; 1247 1248 tmp = (uint64_t)pll->reference_freq * feedback_div; 1249 vco = radeon_div(tmp, ref_div); 1250 1251 if (vco < pll_out_min) { 1252 min_feed_div = feedback_div + 1; 1253 continue; 1254 } else if (vco > pll_out_max) { 1255 max_feed_div = feedback_div; 1256 continue; 1257 } 1258 1259 while (min_frac_feed_div < max_frac_feed_div) { 1260 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1261 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1262 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1263 current_freq = radeon_div(tmp, ref_div * post_div); 1264 1265 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1266 if (freq < current_freq) 1267 error = 0xffffffff; 1268 else 1269 error = freq - current_freq; 1270 } else 1271 error = abs(current_freq - freq); 1272 vco_diff = abs(vco - best_vco); 1273 1274 if ((best_vco == 0 && error < best_error) || 1275 (best_vco != 0 && 1276 ((best_error > 100 && error < best_error - 100) || 1277 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1278 best_post_div = post_div; 1279 best_ref_div = ref_div; 1280 best_feedback_div = feedback_div; 1281 best_frac_feedback_div = frac_feedback_div; 1282 best_freq = current_freq; 1283 best_error = error; 1284 best_vco_diff = vco_diff; 1285 } else if (current_freq == freq) { 1286 if (best_freq == -1) { 1287 best_post_div = post_div; 1288 best_ref_div = ref_div; 1289 best_feedback_div = feedback_div; 1290 best_frac_feedback_div = frac_feedback_div; 1291 best_freq = current_freq; 1292 best_error = error; 1293 best_vco_diff = vco_diff; 1294 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1295 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1296 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1297 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1298 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1299 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1300 best_post_div = post_div; 1301 best_ref_div = ref_div; 1302 best_feedback_div = feedback_div; 1303 best_frac_feedback_div = frac_feedback_div; 1304 best_freq = current_freq; 1305 best_error = error; 1306 best_vco_diff = vco_diff; 1307 } 1308 } 1309 if (current_freq < freq) 1310 min_frac_feed_div = frac_feedback_div + 1; 1311 else 1312 max_frac_feed_div = frac_feedback_div; 1313 } 1314 if (current_freq < freq) 1315 min_feed_div = feedback_div + 1; 1316 else 1317 max_feed_div = feedback_div; 1318 } 1319 } 1320 } 1321 1322 *dot_clock_p = best_freq / 10000; 1323 *fb_div_p = best_feedback_div; 1324 *frac_fb_div_p = best_frac_feedback_div; 1325 *ref_div_p = best_ref_div; 1326 *post_div_p = best_post_div; 1327 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1328 (long long)freq, 1329 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1330 best_ref_div, best_post_div); 1331 1332 } 1333 1334 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1335 { 1336 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1337 1338 if (radeon_fb->obj) { 1339 drm_gem_object_unreference_unlocked(radeon_fb->obj); 1340 } 1341 drm_framebuffer_cleanup(fb); 1342 kfree(radeon_fb); 1343 } 1344 1345 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1346 struct drm_file *file_priv, 1347 unsigned int *handle) 1348 { 1349 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1350 1351 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1352 } 1353 1354 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1355 .destroy = radeon_user_framebuffer_destroy, 1356 .create_handle = radeon_user_framebuffer_create_handle, 1357 }; 1358 1359 int 1360 radeon_framebuffer_init(struct drm_device *dev, 1361 struct radeon_framebuffer *rfb, 1362 struct drm_mode_fb_cmd2 *mode_cmd, 1363 struct drm_gem_object *obj) 1364 { 1365 int ret; 1366 rfb->obj = obj; 1367 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1368 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1369 if (ret) { 1370 rfb->obj = NULL; 1371 return ret; 1372 } 1373 return 0; 1374 } 1375 1376 static struct drm_framebuffer * 1377 radeon_user_framebuffer_create(struct drm_device *dev, 1378 struct drm_file *file_priv, 1379 struct drm_mode_fb_cmd2 *mode_cmd) 1380 { 1381 struct drm_gem_object *obj; 1382 struct radeon_framebuffer *radeon_fb; 1383 int ret; 1384 1385 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); 1386 if (obj == NULL) { 1387 dev_err(dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1388 "can't create framebuffer\n", mode_cmd->handles[0]); 1389 return ERR_PTR(-ENOENT); 1390 } 1391 1392 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1393 if (radeon_fb == NULL) { 1394 drm_gem_object_unreference_unlocked(obj); 1395 return ERR_PTR(-ENOMEM); 1396 } 1397 1398 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1399 if (ret) { 1400 kfree(radeon_fb); 1401 drm_gem_object_unreference_unlocked(obj); 1402 return ERR_PTR(ret); 1403 } 1404 1405 return &radeon_fb->base; 1406 } 1407 1408 static void radeon_output_poll_changed(struct drm_device *dev) 1409 { 1410 struct radeon_device *rdev = dev->dev_private; 1411 radeon_fb_output_poll_changed(rdev); 1412 } 1413 1414 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1415 .fb_create = radeon_user_framebuffer_create, 1416 .output_poll_changed = radeon_output_poll_changed 1417 }; 1418 1419 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1420 { { 0, "driver" }, 1421 { 1, "bios" }, 1422 }; 1423 1424 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1425 { { TV_STD_NTSC, "ntsc" }, 1426 { TV_STD_PAL, "pal" }, 1427 { TV_STD_PAL_M, "pal-m" }, 1428 { TV_STD_PAL_60, "pal-60" }, 1429 { TV_STD_NTSC_J, "ntsc-j" }, 1430 { TV_STD_SCART_PAL, "scart-pal" }, 1431 { TV_STD_PAL_CN, "pal-cn" }, 1432 { TV_STD_SECAM, "secam" }, 1433 }; 1434 1435 static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1436 { { UNDERSCAN_OFF, "off" }, 1437 { UNDERSCAN_ON, "on" }, 1438 { UNDERSCAN_AUTO, "auto" }, 1439 }; 1440 1441 static struct drm_prop_enum_list radeon_audio_enum_list[] = 1442 { { RADEON_AUDIO_DISABLE, "off" }, 1443 { RADEON_AUDIO_ENABLE, "on" }, 1444 { RADEON_AUDIO_AUTO, "auto" }, 1445 }; 1446 1447 /* XXX support different dither options? spatial, temporal, both, etc. */ 1448 static struct drm_prop_enum_list radeon_dither_enum_list[] = 1449 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1450 { RADEON_FMT_DITHER_ENABLE, "on" }, 1451 }; 1452 1453 static int radeon_modeset_create_props(struct radeon_device *rdev) 1454 { 1455 int sz; 1456 1457 if (rdev->is_atom_bios) { 1458 rdev->mode_info.coherent_mode_property = 1459 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1460 if (!rdev->mode_info.coherent_mode_property) 1461 return -ENOMEM; 1462 } 1463 1464 if (!ASIC_IS_AVIVO(rdev)) { 1465 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1466 rdev->mode_info.tmds_pll_property = 1467 drm_property_create_enum(rdev->ddev, 0, 1468 "tmds_pll", 1469 radeon_tmds_pll_enum_list, sz); 1470 } 1471 1472 rdev->mode_info.load_detect_property = 1473 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1474 if (!rdev->mode_info.load_detect_property) 1475 return -ENOMEM; 1476 1477 drm_mode_create_scaling_mode_property(rdev->ddev); 1478 1479 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1480 rdev->mode_info.tv_std_property = 1481 drm_property_create_enum(rdev->ddev, 0, 1482 "tv standard", 1483 radeon_tv_std_enum_list, sz); 1484 1485 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1486 rdev->mode_info.underscan_property = 1487 drm_property_create_enum(rdev->ddev, 0, 1488 "underscan", 1489 radeon_underscan_enum_list, sz); 1490 1491 rdev->mode_info.underscan_hborder_property = 1492 drm_property_create_range(rdev->ddev, 0, 1493 "underscan hborder", 0, 128); 1494 if (!rdev->mode_info.underscan_hborder_property) 1495 return -ENOMEM; 1496 1497 rdev->mode_info.underscan_vborder_property = 1498 drm_property_create_range(rdev->ddev, 0, 1499 "underscan vborder", 0, 128); 1500 if (!rdev->mode_info.underscan_vborder_property) 1501 return -ENOMEM; 1502 1503 sz = ARRAY_SIZE(radeon_audio_enum_list); 1504 rdev->mode_info.audio_property = 1505 drm_property_create_enum(rdev->ddev, 0, 1506 "audio", 1507 radeon_audio_enum_list, sz); 1508 1509 sz = ARRAY_SIZE(radeon_dither_enum_list); 1510 rdev->mode_info.dither_property = 1511 drm_property_create_enum(rdev->ddev, 0, 1512 "dither", 1513 radeon_dither_enum_list, sz); 1514 1515 return 0; 1516 } 1517 1518 void radeon_update_display_priority(struct radeon_device *rdev) 1519 { 1520 /* adjustment options for the display watermarks */ 1521 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1522 /* set display priority to high for r3xx, rv515 chips 1523 * this avoids flickering due to underflow to the 1524 * display controllers during heavy acceleration. 1525 * Don't force high on rs4xx igp chips as it seems to 1526 * affect the sound card. See kernel bug 15982. 1527 */ 1528 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1529 !(rdev->flags & RADEON_IS_IGP)) 1530 rdev->disp_priority = 2; 1531 else 1532 rdev->disp_priority = 0; 1533 } else 1534 rdev->disp_priority = radeon_disp_priority; 1535 1536 } 1537 1538 /* 1539 * Allocate hdmi structs and determine register offsets 1540 */ 1541 static void radeon_afmt_init(struct radeon_device *rdev) 1542 { 1543 int i; 1544 1545 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1546 rdev->mode_info.afmt[i] = NULL; 1547 1548 if (ASIC_IS_NODCE(rdev)) { 1549 /* nothing to do */ 1550 } else if (ASIC_IS_DCE4(rdev)) { 1551 static uint32_t eg_offsets[] = { 1552 EVERGREEN_CRTC0_REGISTER_OFFSET, 1553 EVERGREEN_CRTC1_REGISTER_OFFSET, 1554 EVERGREEN_CRTC2_REGISTER_OFFSET, 1555 EVERGREEN_CRTC3_REGISTER_OFFSET, 1556 EVERGREEN_CRTC4_REGISTER_OFFSET, 1557 EVERGREEN_CRTC5_REGISTER_OFFSET, 1558 0x13830 - 0x7030, 1559 }; 1560 int num_afmt; 1561 1562 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1563 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1564 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1565 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1566 if (ASIC_IS_DCE8(rdev)) 1567 num_afmt = 7; 1568 else if (ASIC_IS_DCE6(rdev)) 1569 num_afmt = 6; 1570 else if (ASIC_IS_DCE5(rdev)) 1571 num_afmt = 6; 1572 else if (ASIC_IS_DCE41(rdev)) 1573 num_afmt = 2; 1574 else /* DCE4 */ 1575 num_afmt = 6; 1576 1577 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1578 for (i = 0; i < num_afmt; i++) { 1579 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1580 if (rdev->mode_info.afmt[i]) { 1581 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1582 rdev->mode_info.afmt[i]->id = i; 1583 } 1584 } 1585 } else if (ASIC_IS_DCE3(rdev)) { 1586 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1587 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1588 if (rdev->mode_info.afmt[0]) { 1589 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1590 rdev->mode_info.afmt[0]->id = 0; 1591 } 1592 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1593 if (rdev->mode_info.afmt[1]) { 1594 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1595 rdev->mode_info.afmt[1]->id = 1; 1596 } 1597 } else if (ASIC_IS_DCE2(rdev)) { 1598 /* DCE2 has at least 1 routable audio block */ 1599 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1600 if (rdev->mode_info.afmt[0]) { 1601 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1602 rdev->mode_info.afmt[0]->id = 0; 1603 } 1604 /* r6xx has 2 routable audio blocks */ 1605 if (rdev->family >= CHIP_R600) { 1606 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1607 if (rdev->mode_info.afmt[1]) { 1608 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1609 rdev->mode_info.afmt[1]->id = 1; 1610 } 1611 } 1612 } 1613 } 1614 1615 static void radeon_afmt_fini(struct radeon_device *rdev) 1616 { 1617 int i; 1618 1619 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1620 kfree(rdev->mode_info.afmt[i]); 1621 rdev->mode_info.afmt[i] = NULL; 1622 } 1623 } 1624 1625 int radeon_modeset_init(struct radeon_device *rdev) 1626 { 1627 int i; 1628 int ret; 1629 1630 drm_mode_config_init(rdev->ddev); 1631 rdev->mode_info.mode_config_initialized = true; 1632 1633 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1634 1635 if (ASIC_IS_DCE5(rdev)) { 1636 rdev->ddev->mode_config.max_width = 16384; 1637 rdev->ddev->mode_config.max_height = 16384; 1638 } else if (ASIC_IS_AVIVO(rdev)) { 1639 rdev->ddev->mode_config.max_width = 8192; 1640 rdev->ddev->mode_config.max_height = 8192; 1641 } else { 1642 rdev->ddev->mode_config.max_width = 4096; 1643 rdev->ddev->mode_config.max_height = 4096; 1644 } 1645 1646 rdev->ddev->mode_config.preferred_depth = 24; 1647 rdev->ddev->mode_config.prefer_shadow = 1; 1648 1649 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1650 1651 ret = radeon_modeset_create_props(rdev); 1652 if (ret) { 1653 return ret; 1654 } 1655 1656 /* init i2c buses */ 1657 radeon_i2c_init(rdev); 1658 1659 /* check combios for a valid hardcoded EDID - Sun servers */ 1660 if (!rdev->is_atom_bios) { 1661 /* check for hardcoded EDID in BIOS */ 1662 radeon_combios_check_hardcoded_edid(rdev); 1663 } 1664 1665 /* allocate crtcs */ 1666 for (i = 0; i < rdev->num_crtc; i++) { 1667 radeon_crtc_init(rdev->ddev, i); 1668 } 1669 1670 /* okay we should have all the bios connectors */ 1671 ret = radeon_setup_enc_conn(rdev->ddev); 1672 if (!ret) { 1673 return ret; 1674 } 1675 1676 /* init dig PHYs, disp eng pll */ 1677 if (rdev->is_atom_bios) { 1678 radeon_atom_encoder_init(rdev); 1679 radeon_atom_disp_eng_pll_init(rdev); 1680 } 1681 1682 /* initialize hpd */ 1683 radeon_hpd_init(rdev); 1684 1685 /* setup afmt */ 1686 radeon_afmt_init(rdev); 1687 1688 radeon_fbdev_init(rdev); 1689 drm_kms_helper_poll_init(rdev->ddev); 1690 1691 if (rdev->pm.dpm_enabled) { 1692 /* do dpm late init */ 1693 ret = radeon_pm_late_init(rdev); 1694 if (ret) { 1695 rdev->pm.dpm_enabled = false; 1696 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1697 } 1698 /* set the dpm state for PX since there won't be 1699 * a modeset to call this. 1700 */ 1701 radeon_pm_compute_clocks(rdev); 1702 } 1703 1704 return 0; 1705 } 1706 1707 void radeon_modeset_fini(struct radeon_device *rdev) 1708 { 1709 radeon_fbdev_fini(rdev); 1710 kfree(rdev->mode_info.bios_hardcoded_edid); 1711 1712 if (rdev->mode_info.mode_config_initialized) { 1713 radeon_afmt_fini(rdev); 1714 drm_kms_helper_poll_fini(rdev->ddev); 1715 radeon_hpd_fini(rdev); 1716 DRM_UNLOCK(rdev->ddev); /* Work around lock recursion. dumbbell@ */ 1717 drm_mode_config_cleanup(rdev->ddev); 1718 DRM_LOCK(rdev->ddev); 1719 rdev->mode_info.mode_config_initialized = false; 1720 } 1721 /* free i2c buses */ 1722 radeon_i2c_fini(rdev); 1723 } 1724 1725 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1726 { 1727 /* try and guess if this is a tv or a monitor */ 1728 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1729 (mode->vdisplay == 576) || /* 576p */ 1730 (mode->vdisplay == 720) || /* 720p */ 1731 (mode->vdisplay == 1080)) /* 1080p */ 1732 return true; 1733 else 1734 return false; 1735 } 1736 1737 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1738 const struct drm_display_mode *mode, 1739 struct drm_display_mode *adjusted_mode) 1740 { 1741 struct drm_device *dev = crtc->dev; 1742 struct radeon_device *rdev = dev->dev_private; 1743 struct drm_encoder *encoder; 1744 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1745 struct radeon_encoder *radeon_encoder; 1746 struct drm_connector *connector; 1747 struct radeon_connector *radeon_connector; 1748 bool first = true; 1749 u32 src_v = 1, dst_v = 1; 1750 u32 src_h = 1, dst_h = 1; 1751 1752 radeon_crtc->h_border = 0; 1753 radeon_crtc->v_border = 0; 1754 1755 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1756 if (encoder->crtc != crtc) 1757 continue; 1758 radeon_encoder = to_radeon_encoder(encoder); 1759 connector = radeon_get_connector_for_encoder(encoder); 1760 radeon_connector = to_radeon_connector(connector); 1761 1762 if (first) { 1763 /* set scaling */ 1764 if (radeon_encoder->rmx_type == RMX_OFF) 1765 radeon_crtc->rmx_type = RMX_OFF; 1766 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1767 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1768 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1769 else 1770 radeon_crtc->rmx_type = RMX_OFF; 1771 /* copy native mode */ 1772 memcpy(&radeon_crtc->native_mode, 1773 &radeon_encoder->native_mode, 1774 sizeof(struct drm_display_mode)); 1775 src_v = crtc->mode.vdisplay; 1776 dst_v = radeon_crtc->native_mode.vdisplay; 1777 src_h = crtc->mode.hdisplay; 1778 dst_h = radeon_crtc->native_mode.hdisplay; 1779 1780 /* fix up for overscan on hdmi */ 1781 if (ASIC_IS_AVIVO(rdev) && 1782 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1783 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1784 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1785 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1786 is_hdtv_mode(mode)))) { 1787 if (radeon_encoder->underscan_hborder != 0) 1788 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1789 else 1790 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1791 if (radeon_encoder->underscan_vborder != 0) 1792 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1793 else 1794 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1795 radeon_crtc->rmx_type = RMX_FULL; 1796 src_v = crtc->mode.vdisplay; 1797 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1798 src_h = crtc->mode.hdisplay; 1799 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1800 } 1801 first = false; 1802 } else { 1803 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1804 /* WARNING: Right now this can't happen but 1805 * in the future we need to check that scaling 1806 * are consistent across different encoder 1807 * (ie all encoder can work with the same 1808 * scaling). 1809 */ 1810 DRM_ERROR("Scaling not consistent across encoder.\n"); 1811 return false; 1812 } 1813 } 1814 } 1815 if (radeon_crtc->rmx_type != RMX_OFF) { 1816 fixed20_12 a, b; 1817 a.full = dfixed_const(src_v); 1818 b.full = dfixed_const(dst_v); 1819 radeon_crtc->vsc.full = dfixed_div(a, b); 1820 a.full = dfixed_const(src_h); 1821 b.full = dfixed_const(dst_h); 1822 radeon_crtc->hsc.full = dfixed_div(a, b); 1823 } else { 1824 radeon_crtc->vsc.full = dfixed_const(1); 1825 radeon_crtc->hsc.full = dfixed_const(1); 1826 } 1827 return true; 1828 } 1829 1830 /* 1831 * Retrieve current video scanout position of crtc on a given gpu, and 1832 * an optional accurate timestamp of when query happened. 1833 * 1834 * \param dev Device to query. 1835 * \param crtc Crtc to query. 1836 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1837 * \param *vpos Location where vertical scanout position should be stored. 1838 * \param *hpos Location where horizontal scanout position should go. 1839 * \param *stime Target location for timestamp taken immediately before 1840 * scanout position query. Can be NULL to skip timestamp. 1841 * \param *etime Target location for timestamp taken immediately after 1842 * scanout position query. Can be NULL to skip timestamp. 1843 * 1844 * Returns vpos as a positive number while in active scanout area. 1845 * Returns vpos as a negative number inside vblank, counting the number 1846 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1847 * until start of active scanout / end of vblank." 1848 * 1849 * \return Flags, or'ed together as follows: 1850 * 1851 * DRM_SCANOUTPOS_VALID = Query successful. 1852 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1853 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1854 * this flag means that returned position may be offset by a constant but 1855 * unknown small number of scanlines wrt. real scanout position. 1856 * 1857 */ 1858 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags, 1859 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime) 1860 { 1861 u32 stat_crtc = 0, vbl = 0, position = 0; 1862 int vbl_start, vbl_end, vtotal, ret = 0; 1863 bool in_vbl = true; 1864 1865 struct radeon_device *rdev = dev->dev_private; 1866 1867 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1868 1869 /* Get optional system timestamp before query. */ 1870 if (stime) 1871 *stime = ktime_get(); 1872 1873 if (ASIC_IS_DCE4(rdev)) { 1874 if (crtc == 0) { 1875 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1876 EVERGREEN_CRTC0_REGISTER_OFFSET); 1877 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1878 EVERGREEN_CRTC0_REGISTER_OFFSET); 1879 ret |= DRM_SCANOUTPOS_VALID; 1880 } 1881 if (crtc == 1) { 1882 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1883 EVERGREEN_CRTC1_REGISTER_OFFSET); 1884 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1885 EVERGREEN_CRTC1_REGISTER_OFFSET); 1886 ret |= DRM_SCANOUTPOS_VALID; 1887 } 1888 if (crtc == 2) { 1889 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1890 EVERGREEN_CRTC2_REGISTER_OFFSET); 1891 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1892 EVERGREEN_CRTC2_REGISTER_OFFSET); 1893 ret |= DRM_SCANOUTPOS_VALID; 1894 } 1895 if (crtc == 3) { 1896 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1897 EVERGREEN_CRTC3_REGISTER_OFFSET); 1898 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1899 EVERGREEN_CRTC3_REGISTER_OFFSET); 1900 ret |= DRM_SCANOUTPOS_VALID; 1901 } 1902 if (crtc == 4) { 1903 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1904 EVERGREEN_CRTC4_REGISTER_OFFSET); 1905 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1906 EVERGREEN_CRTC4_REGISTER_OFFSET); 1907 ret |= DRM_SCANOUTPOS_VALID; 1908 } 1909 if (crtc == 5) { 1910 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1911 EVERGREEN_CRTC5_REGISTER_OFFSET); 1912 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1913 EVERGREEN_CRTC5_REGISTER_OFFSET); 1914 ret |= DRM_SCANOUTPOS_VALID; 1915 } 1916 } else if (ASIC_IS_AVIVO(rdev)) { 1917 if (crtc == 0) { 1918 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1919 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1920 ret |= DRM_SCANOUTPOS_VALID; 1921 } 1922 if (crtc == 1) { 1923 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1924 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1925 ret |= DRM_SCANOUTPOS_VALID; 1926 } 1927 } else { 1928 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1929 if (crtc == 0) { 1930 /* Assume vbl_end == 0, get vbl_start from 1931 * upper 16 bits. 1932 */ 1933 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1934 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1935 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1936 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1937 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1938 if (!(stat_crtc & 1)) 1939 in_vbl = false; 1940 1941 ret |= DRM_SCANOUTPOS_VALID; 1942 } 1943 if (crtc == 1) { 1944 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1945 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1946 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1947 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1948 if (!(stat_crtc & 1)) 1949 in_vbl = false; 1950 1951 ret |= DRM_SCANOUTPOS_VALID; 1952 } 1953 } 1954 1955 /* Get optional system timestamp after query. */ 1956 if (etime) 1957 *etime = ktime_get(); 1958 1959 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1960 1961 /* Decode into vertical and horizontal scanout position. */ 1962 *vpos = position & 0x1fff; 1963 *hpos = (position >> 16) & 0x1fff; 1964 1965 /* Valid vblank area boundaries from gpu retrieved? */ 1966 if (vbl > 0) { 1967 /* Yes: Decode. */ 1968 ret |= DRM_SCANOUTPOS_ACCURATE; 1969 vbl_start = vbl & 0x1fff; 1970 vbl_end = (vbl >> 16) & 0x1fff; 1971 } 1972 else { 1973 /* No: Fake something reasonable which gives at least ok results. */ 1974 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; 1975 vbl_end = 0; 1976 } 1977 1978 /* Test scanout position against vblank region. */ 1979 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1980 in_vbl = false; 1981 1982 /* Check if inside vblank area and apply corrective offsets: 1983 * vpos will then be >=0 in video scanout area, but negative 1984 * within vblank area, counting down the number of lines until 1985 * start of scanout. 1986 */ 1987 1988 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1989 if (in_vbl && (*vpos >= vbl_start)) { 1990 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; 1991 *vpos = *vpos - vtotal; 1992 } 1993 1994 /* Correct for shifted end of vbl at vbl_end. */ 1995 *vpos = *vpos - vbl_end; 1996 1997 /* In vblank? */ 1998 if (in_vbl) 1999 ret |= DRM_SCANOUTPOS_IN_VBLANK; 2000 2001 /* Is vpos outside nominal vblank area, but less than 2002 * 1/100 of a frame height away from start of vblank? 2003 * If so, assume this isn't a massively delayed vblank 2004 * interrupt, but a vblank interrupt that fired a few 2005 * microseconds before true start of vblank. Compensate 2006 * by adding a full frame duration to the final timestamp. 2007 * Happens, e.g., on ATI R500, R600. 2008 * 2009 * We only do this if DRM_CALLED_FROM_VBLIRQ. 2010 */ 2011 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) { 2012 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; 2013 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; 2014 2015 if (vbl_start - *vpos < vtotal / 100) { 2016 *vpos -= vtotal; 2017 2018 /* Signal this correction as "applied". */ 2019 ret |= 0x8; 2020 } 2021 } 2022 2023 return ret; 2024 } 2025