1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon.h" 30 #include <uapi_drm/radeon_drm.h> 31 #include "radeon_asic.h" 32 #include "radeon_kms.h" 33 34 #include <linux/slab.h> 35 #ifdef PM_TODO 36 #include <linux/pm_runtime.h> 37 #endif 38 39 #ifdef PM_TODO 40 #if defined(CONFIG_VGA_SWITCHEROO) 41 bool radeon_has_atpx(void); 42 #else 43 static inline bool radeon_has_atpx(void) { return false; } 44 #endif 45 #endif 46 47 /** 48 * radeon_driver_unload_kms - Main unload function for KMS. 49 * 50 * @dev: drm dev pointer 51 * 52 * This is the main unload function for KMS (all asics). 53 * It calls radeon_modeset_fini() to tear down the 54 * displays, and radeon_device_fini() to tear down 55 * the rest of the device (CP, writeback, etc.). 56 * Returns 0 on success. 57 */ 58 int radeon_driver_unload_kms(struct drm_device *dev) 59 { 60 struct radeon_device *rdev = dev->dev_private; 61 62 /* XXX pending drm update */ 63 drm_fini_pdev(&dev->pdev); 64 65 if (rdev == NULL) 66 return 0; 67 68 if (rdev->rmmio == NULL) 69 goto done_free; 70 71 #ifdef PM_TODO 72 pm_runtime_get_sync(dev->dev); 73 #endif 74 75 radeon_acpi_fini(rdev); 76 radeon_modeset_fini(rdev); 77 radeon_device_fini(rdev); 78 79 done_free: 80 kfree(rdev); 81 dev->dev_private = NULL; 82 return 0; 83 } 84 85 /** 86 * radeon_driver_load_kms - Main load function for KMS. 87 * 88 * @dev: drm dev pointer 89 * @flags: device flags 90 * 91 * This is the main load function for KMS (all asics). 92 * It calls radeon_device_init() to set up the non-display 93 * parts of the chip (asic init, CP, writeback, etc.), and 94 * radeon_modeset_init() to set up the display parts 95 * (crtcs, encoders, hotplug detect, etc.). 96 * Returns 0 on success, error on failure. 97 */ 98 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 99 { 100 struct radeon_device *rdev; 101 int r, acpi_status; 102 103 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 104 if (rdev == NULL) { 105 return -ENOMEM; 106 } 107 dev->dev_private = (void *)rdev; 108 109 /* update BUS flag */ 110 if (drm_device_is_agp(dev)) { 111 DRM_INFO("RADEON_IS_AGP\n"); 112 flags |= RADEON_IS_AGP; 113 } else if (drm_device_is_pcie(dev)) { 114 DRM_INFO("RADEON_IS_PCIE\n"); 115 flags |= RADEON_IS_PCIE; 116 } else { 117 DRM_INFO("RADEON_IS_PCI\n"); 118 flags |= RADEON_IS_PCI; 119 } 120 121 #ifdef PM_TODO 122 if ((radeon_runtime_pm != 0) && 123 radeon_has_atpx() && 124 ((flags & RADEON_IS_IGP) == 0)) 125 #endif 126 127 /* radeon_device_init should report only fatal error 128 * like memory allocation failure or iomapping failure, 129 * or memory manager initialization failure, it must 130 * properly initialize the GPU MC controller and permit 131 * VRAM allocation 132 */ 133 r = radeon_device_init(rdev, dev, dev->pdev, flags); 134 if (r) { 135 dev_err(dev->pdev->dev, "Fatal error during GPU init\n"); 136 goto out; 137 } 138 139 /* Again modeset_init should fail only on fatal error 140 * otherwise it should provide enough functionalities 141 * for shadowfb to run 142 */ 143 r = radeon_modeset_init(rdev); 144 if (r) 145 dev_err(dev->pdev->dev, "Fatal error during modeset init\n"); 146 147 /* Call ACPI methods: require modeset init 148 * but failure is not fatal 149 */ 150 if (!r) { 151 acpi_status = radeon_acpi_init(rdev); 152 if (acpi_status) 153 dev_dbg(dev->pdev->dev, 154 "Error during ACPI methods call\n"); 155 } 156 157 #ifdef PM_TODO 158 if (radeon_is_px(dev)) { 159 pm_runtime_use_autosuspend(dev->dev); 160 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 161 pm_runtime_set_active(dev->dev); 162 pm_runtime_allow(dev->dev); 163 pm_runtime_mark_last_busy(dev->dev); 164 pm_runtime_put_autosuspend(dev->dev); 165 } 166 #endif 167 168 out: 169 if (r) 170 radeon_driver_unload_kms(dev); 171 return r; 172 } 173 174 /** 175 * radeon_set_filp_rights - Set filp right. 176 * 177 * @dev: drm dev pointer 178 * @owner: drm file 179 * @applier: drm file 180 * @value: value 181 * 182 * Sets the filp rights for the device (all asics). 183 */ 184 static void radeon_set_filp_rights(struct drm_device *dev, 185 struct drm_file **owner, 186 struct drm_file *applier, 187 uint32_t *value) 188 { 189 DRM_LOCK(dev); 190 if (*value == 1) { 191 /* wants rights */ 192 if (!*owner) 193 *owner = applier; 194 } else if (*value == 0) { 195 /* revokes rights */ 196 if (*owner == applier) 197 *owner = NULL; 198 } 199 *value = *owner == applier ? 1 : 0; 200 DRM_UNLOCK(dev); 201 } 202 203 /* 204 * Userspace get information ioctl 205 */ 206 /** 207 * radeon_info_ioctl - answer a device specific request. 208 * 209 * @rdev: radeon device pointer 210 * @data: request object 211 * @filp: drm filp 212 * 213 * This function is used to pass device specific parameters to the userspace 214 * drivers. Examples include: pci device id, pipeline parms, tiling params, 215 * etc. (all asics). 216 * Returns 0 on success, -EINVAL on failure. 217 */ 218 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 219 { 220 struct radeon_device *rdev = dev->dev_private; 221 struct drm_radeon_info *info = data; 222 struct radeon_mode_info *minfo = &rdev->mode_info; 223 uint32_t *value, value_tmp, *value_ptr, value_size; 224 uint64_t value64; 225 struct drm_crtc *crtc; 226 int i, found; 227 228 value_ptr = (uint32_t *)((unsigned long)info->value); 229 value = &value_tmp; 230 value_size = sizeof(uint32_t); 231 232 switch (info->request) { 233 case RADEON_INFO_DEVICE_ID: 234 *value = dev->pdev->device; 235 break; 236 case RADEON_INFO_NUM_GB_PIPES: 237 *value = rdev->num_gb_pipes; 238 break; 239 case RADEON_INFO_NUM_Z_PIPES: 240 *value = rdev->num_z_pipes; 241 break; 242 case RADEON_INFO_ACCEL_WORKING: 243 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 244 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 245 *value = false; 246 else 247 *value = rdev->accel_working; 248 break; 249 case RADEON_INFO_CRTC_FROM_ID: 250 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 251 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 252 return -EFAULT; 253 } 254 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 255 crtc = (struct drm_crtc *)minfo->crtcs[i]; 256 if (crtc && crtc->base.id == *value) { 257 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 258 *value = radeon_crtc->crtc_id; 259 found = 1; 260 break; 261 } 262 } 263 if (!found) { 264 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 265 return -EINVAL; 266 } 267 break; 268 case RADEON_INFO_ACCEL_WORKING2: 269 if (rdev->family == CHIP_HAWAII) { 270 if (rdev->accel_working) 271 *value = 2; 272 else 273 *value = 0; 274 } else { 275 *value = rdev->accel_working; 276 } 277 break; 278 case RADEON_INFO_TILING_CONFIG: 279 if (rdev->family >= CHIP_BONAIRE) 280 *value = rdev->config.cik.tile_config; 281 else if (rdev->family >= CHIP_TAHITI) 282 *value = rdev->config.si.tile_config; 283 else if (rdev->family >= CHIP_CAYMAN) 284 *value = rdev->config.cayman.tile_config; 285 else if (rdev->family >= CHIP_CEDAR) 286 *value = rdev->config.evergreen.tile_config; 287 else if (rdev->family >= CHIP_RV770) 288 *value = rdev->config.rv770.tile_config; 289 else if (rdev->family >= CHIP_R600) 290 *value = rdev->config.r600.tile_config; 291 else { 292 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 293 return -EINVAL; 294 } 295 break; 296 case RADEON_INFO_WANT_HYPERZ: 297 /* The "value" here is both an input and output parameter. 298 * If the input value is 1, filp requests hyper-z access. 299 * If the input value is 0, filp revokes its hyper-z access. 300 * 301 * When returning, the value is 1 if filp owns hyper-z access, 302 * 0 otherwise. */ 303 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 304 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 305 return -EFAULT; 306 } 307 if (*value >= 2) { 308 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 309 return -EINVAL; 310 } 311 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 312 break; 313 case RADEON_INFO_WANT_CMASK: 314 /* The same logic as Hyper-Z. */ 315 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 316 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 317 return -EFAULT; 318 } 319 if (*value >= 2) { 320 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 321 return -EINVAL; 322 } 323 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 324 break; 325 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 326 /* return clock value in KHz */ 327 if (rdev->asic->get_xclk) 328 *value = radeon_get_xclk(rdev) * 10; 329 else 330 *value = rdev->clock.spll.reference_freq * 10; 331 break; 332 case RADEON_INFO_NUM_BACKENDS: 333 if (rdev->family >= CHIP_BONAIRE) 334 *value = rdev->config.cik.max_backends_per_se * 335 rdev->config.cik.max_shader_engines; 336 else if (rdev->family >= CHIP_TAHITI) 337 *value = rdev->config.si.max_backends_per_se * 338 rdev->config.si.max_shader_engines; 339 else if (rdev->family >= CHIP_CAYMAN) 340 *value = rdev->config.cayman.max_backends_per_se * 341 rdev->config.cayman.max_shader_engines; 342 else if (rdev->family >= CHIP_CEDAR) 343 *value = rdev->config.evergreen.max_backends; 344 else if (rdev->family >= CHIP_RV770) 345 *value = rdev->config.rv770.max_backends; 346 else if (rdev->family >= CHIP_R600) 347 *value = rdev->config.r600.max_backends; 348 else { 349 return -EINVAL; 350 } 351 break; 352 case RADEON_INFO_NUM_TILE_PIPES: 353 if (rdev->family >= CHIP_BONAIRE) 354 *value = rdev->config.cik.max_tile_pipes; 355 else if (rdev->family >= CHIP_TAHITI) 356 *value = rdev->config.si.max_tile_pipes; 357 else if (rdev->family >= CHIP_CAYMAN) 358 *value = rdev->config.cayman.max_tile_pipes; 359 else if (rdev->family >= CHIP_CEDAR) 360 *value = rdev->config.evergreen.max_tile_pipes; 361 else if (rdev->family >= CHIP_RV770) 362 *value = rdev->config.rv770.max_tile_pipes; 363 else if (rdev->family >= CHIP_R600) 364 *value = rdev->config.r600.max_tile_pipes; 365 else { 366 return -EINVAL; 367 } 368 break; 369 case RADEON_INFO_FUSION_GART_WORKING: 370 *value = 1; 371 break; 372 case RADEON_INFO_BACKEND_MAP: 373 if (rdev->family >= CHIP_BONAIRE) 374 *value = rdev->config.cik.backend_map; 375 else if (rdev->family >= CHIP_TAHITI) 376 *value = rdev->config.si.backend_map; 377 else if (rdev->family >= CHIP_CAYMAN) 378 *value = rdev->config.cayman.backend_map; 379 else if (rdev->family >= CHIP_CEDAR) 380 *value = rdev->config.evergreen.backend_map; 381 else if (rdev->family >= CHIP_RV770) 382 *value = rdev->config.rv770.backend_map; 383 else if (rdev->family >= CHIP_R600) 384 *value = rdev->config.r600.backend_map; 385 else { 386 return -EINVAL; 387 } 388 break; 389 case RADEON_INFO_VA_START: 390 /* this is where we report if vm is supported or not */ 391 if (rdev->family < CHIP_CAYMAN) 392 return -EINVAL; 393 *value = RADEON_VA_RESERVED_SIZE; 394 break; 395 case RADEON_INFO_IB_VM_MAX_SIZE: 396 /* this is where we report if vm is supported or not */ 397 if (rdev->family < CHIP_CAYMAN) 398 return -EINVAL; 399 *value = RADEON_IB_VM_MAX_SIZE; 400 break; 401 case RADEON_INFO_MAX_PIPES: 402 if (rdev->family >= CHIP_BONAIRE) 403 *value = rdev->config.cik.max_cu_per_sh; 404 else if (rdev->family >= CHIP_TAHITI) 405 *value = rdev->config.si.max_cu_per_sh; 406 else if (rdev->family >= CHIP_CAYMAN) 407 *value = rdev->config.cayman.max_pipes_per_simd; 408 else if (rdev->family >= CHIP_CEDAR) 409 *value = rdev->config.evergreen.max_pipes; 410 else if (rdev->family >= CHIP_RV770) 411 *value = rdev->config.rv770.max_pipes; 412 else if (rdev->family >= CHIP_R600) 413 *value = rdev->config.r600.max_pipes; 414 else { 415 return -EINVAL; 416 } 417 break; 418 case RADEON_INFO_TIMESTAMP: 419 if (rdev->family < CHIP_R600) { 420 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 421 return -EINVAL; 422 } 423 value = (uint32_t*)&value64; 424 value_size = sizeof(uint64_t); 425 value64 = radeon_get_gpu_clock_counter(rdev); 426 break; 427 case RADEON_INFO_MAX_SE: 428 if (rdev->family >= CHIP_BONAIRE) 429 *value = rdev->config.cik.max_shader_engines; 430 else if (rdev->family >= CHIP_TAHITI) 431 *value = rdev->config.si.max_shader_engines; 432 else if (rdev->family >= CHIP_CAYMAN) 433 *value = rdev->config.cayman.max_shader_engines; 434 else if (rdev->family >= CHIP_CEDAR) 435 *value = rdev->config.evergreen.num_ses; 436 else 437 *value = 1; 438 break; 439 case RADEON_INFO_MAX_SH_PER_SE: 440 if (rdev->family >= CHIP_BONAIRE) 441 *value = rdev->config.cik.max_sh_per_se; 442 else if (rdev->family >= CHIP_TAHITI) 443 *value = rdev->config.si.max_sh_per_se; 444 else 445 return -EINVAL; 446 break; 447 case RADEON_INFO_FASTFB_WORKING: 448 *value = rdev->fastfb_working; 449 break; 450 case RADEON_INFO_RING_WORKING: 451 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 452 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 453 return -EFAULT; 454 } 455 switch (*value) { 456 case RADEON_CS_RING_GFX: 457 case RADEON_CS_RING_COMPUTE: 458 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 459 break; 460 case RADEON_CS_RING_DMA: 461 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 462 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 463 break; 464 case RADEON_CS_RING_UVD: 465 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 466 break; 467 case RADEON_CS_RING_VCE: 468 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 469 break; 470 default: 471 return -EINVAL; 472 } 473 break; 474 case RADEON_INFO_SI_TILE_MODE_ARRAY: 475 if (rdev->family >= CHIP_BONAIRE) { 476 value = rdev->config.cik.tile_mode_array; 477 value_size = sizeof(uint32_t)*32; 478 } else if (rdev->family >= CHIP_TAHITI) { 479 value = rdev->config.si.tile_mode_array; 480 value_size = sizeof(uint32_t)*32; 481 } else { 482 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 483 return -EINVAL; 484 } 485 break; 486 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 487 if (rdev->family >= CHIP_BONAIRE) { 488 value = rdev->config.cik.macrotile_mode_array; 489 value_size = sizeof(uint32_t)*16; 490 } else { 491 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 492 return -EINVAL; 493 } 494 break; 495 case RADEON_INFO_SI_CP_DMA_COMPUTE: 496 *value = 1; 497 break; 498 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 499 if (rdev->family >= CHIP_BONAIRE) { 500 *value = rdev->config.cik.backend_enable_mask; 501 } else if (rdev->family >= CHIP_TAHITI) { 502 *value = rdev->config.si.backend_enable_mask; 503 } else { 504 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 505 } 506 break; 507 case RADEON_INFO_MAX_SCLK: 508 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 509 rdev->pm.dpm_enabled) 510 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 511 else 512 *value = rdev->pm.default_sclk * 10; 513 break; 514 case RADEON_INFO_VCE_FW_VERSION: 515 *value = rdev->vce.fw_version; 516 break; 517 case RADEON_INFO_VCE_FB_VERSION: 518 *value = rdev->vce.fb_version; 519 break; 520 case RADEON_INFO_NUM_BYTES_MOVED: 521 value = (uint32_t*)&value64; 522 value_size = sizeof(uint64_t); 523 value64 = atomic64_read(&rdev->num_bytes_moved); 524 break; 525 case RADEON_INFO_VRAM_USAGE: 526 value = (uint32_t*)&value64; 527 value_size = sizeof(uint64_t); 528 value64 = atomic64_read(&rdev->vram_usage); 529 break; 530 case RADEON_INFO_GTT_USAGE: 531 value = (uint32_t*)&value64; 532 value_size = sizeof(uint64_t); 533 value64 = atomic64_read(&rdev->gtt_usage); 534 break; 535 case RADEON_INFO_ACTIVE_CU_COUNT: 536 if (rdev->family >= CHIP_BONAIRE) 537 *value = rdev->config.cik.active_cus; 538 else if (rdev->family >= CHIP_TAHITI) 539 *value = rdev->config.si.active_cus; 540 else if (rdev->family >= CHIP_CAYMAN) 541 *value = rdev->config.cayman.active_simds; 542 else if (rdev->family >= CHIP_CEDAR) 543 *value = rdev->config.evergreen.active_simds; 544 else if (rdev->family >= CHIP_RV770) 545 *value = rdev->config.rv770.active_simds; 546 else if (rdev->family >= CHIP_R600) 547 *value = rdev->config.r600.active_simds; 548 else 549 *value = 1; 550 break; 551 default: 552 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 553 return -EINVAL; 554 } 555 if (copy_to_user(value_ptr, (char*)value, value_size)) { 556 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 557 return -EFAULT; 558 } 559 return 0; 560 } 561 562 563 /* 564 * Outdated mess for old drm with Xorg being in charge (void function now). 565 */ 566 /** 567 * radeon_driver_firstopen_kms - drm callback for last close 568 * 569 * @dev: drm dev pointer 570 * 571 * Switch vga switcheroo state after last close (all asics). 572 */ 573 void radeon_driver_lastclose_kms(struct drm_device *dev) 574 { 575 #ifdef DUMBBELL_WIP 576 vga_switcheroo_process_delayed_switch(); 577 #endif /* DUMBBELL_WIP */ 578 } 579 580 /** 581 * radeon_driver_open_kms - drm callback for open 582 * 583 * @dev: drm dev pointer 584 * @file_priv: drm file 585 * 586 * On device open, init vm on cayman+ (all asics). 587 * Returns 0 on success, error on failure. 588 */ 589 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 590 { 591 struct radeon_device *rdev = dev->dev_private; 592 593 file_priv->driver_priv = NULL; 594 595 #ifdef PM_TODO 596 r = pm_runtime_get_sync(dev->dev); 597 if (r < 0) 598 return r; 599 #endif 600 601 /* new gpu have virtual address space support */ 602 if (rdev->family >= CHIP_CAYMAN) { 603 struct radeon_fpriv *fpriv; 604 struct radeon_vm *vm; 605 int r; 606 607 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 608 if (unlikely(!fpriv)) { 609 return -ENOMEM; 610 } 611 612 vm = &fpriv->vm; 613 r = radeon_vm_init(rdev, vm); 614 if (r) { 615 kfree(fpriv); 616 return r; 617 } 618 619 if (rdev->accel_working) { 620 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 621 if (r) { 622 radeon_vm_fini(rdev, vm); 623 kfree(fpriv); 624 return r; 625 } 626 627 /* map the ib pool buffer read only into 628 * virtual address space */ 629 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 630 rdev->ring_tmp_bo.bo); 631 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 632 RADEON_VA_IB_OFFSET, 633 RADEON_VM_PAGE_READABLE | 634 RADEON_VM_PAGE_SNOOPED); 635 636 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 637 if (r) { 638 radeon_vm_fini(rdev, vm); 639 kfree(fpriv); 640 return r; 641 } 642 } 643 file_priv->driver_priv = fpriv; 644 } 645 646 #ifdef PM_TODO 647 pm_runtime_mark_last_busy(dev->dev); 648 pm_runtime_put_autosuspend(dev->dev); 649 #endif 650 return 0; 651 } 652 653 /** 654 * radeon_driver_postclose_kms - drm callback for post close 655 * 656 * @dev: drm dev pointer 657 * @file_priv: drm file 658 * 659 * On device post close, tear down vm on cayman+ (all asics). 660 */ 661 void radeon_driver_postclose_kms(struct drm_device *dev, 662 struct drm_file *file_priv) 663 { 664 struct radeon_device *rdev = dev->dev_private; 665 666 /* new gpu have virtual address space support */ 667 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 668 struct radeon_fpriv *fpriv = file_priv->driver_priv; 669 struct radeon_vm *vm = &fpriv->vm; 670 int r; 671 672 if (rdev->accel_working) { 673 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 674 if (!r) { 675 if (vm->ib_bo_va) 676 radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 677 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 678 } 679 } 680 681 radeon_vm_fini(rdev, vm); 682 kfree(fpriv); 683 file_priv->driver_priv = NULL; 684 } 685 } 686 687 /** 688 * radeon_driver_preclose_kms - drm callback for pre close 689 * 690 * @dev: drm dev pointer 691 * @file_priv: drm file 692 * 693 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 694 * (all asics). 695 */ 696 void radeon_driver_preclose_kms(struct drm_device *dev, 697 struct drm_file *file_priv) 698 { 699 struct radeon_device *rdev = dev->dev_private; 700 if (rdev->hyperz_filp == file_priv) 701 rdev->hyperz_filp = NULL; 702 if (rdev->cmask_filp == file_priv) 703 rdev->cmask_filp = NULL; 704 radeon_uvd_free_handles(rdev, file_priv); 705 radeon_vce_free_handles(rdev, file_priv); 706 } 707 708 /* 709 * VBlank related functions. 710 */ 711 /** 712 * radeon_get_vblank_counter_kms - get frame count 713 * 714 * @dev: drm dev pointer 715 * @crtc: crtc to get the frame count from 716 * 717 * Gets the frame count on the requested crtc (all asics). 718 * Returns frame count on success, -EINVAL on failure. 719 */ 720 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 721 { 722 struct radeon_device *rdev = dev->dev_private; 723 724 if (crtc < 0 || crtc >= rdev->num_crtc) { 725 DRM_ERROR("Invalid crtc %d\n", crtc); 726 return -EINVAL; 727 } 728 729 return radeon_get_vblank_counter(rdev, crtc); 730 } 731 732 /** 733 * radeon_enable_vblank_kms - enable vblank interrupt 734 * 735 * @dev: drm dev pointer 736 * @crtc: crtc to enable vblank interrupt for 737 * 738 * Enable the interrupt on the requested crtc (all asics). 739 * Returns 0 on success, -EINVAL on failure. 740 */ 741 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 742 { 743 struct radeon_device *rdev = dev->dev_private; 744 int r; 745 746 if (crtc < 0 || crtc >= rdev->num_crtc) { 747 DRM_ERROR("Invalid crtc %d\n", crtc); 748 return -EINVAL; 749 } 750 751 lockmgr(&rdev->irq.lock, LK_EXCLUSIVE); 752 rdev->irq.crtc_vblank_int[crtc] = true; 753 r = radeon_irq_set(rdev); 754 lockmgr(&rdev->irq.lock, LK_RELEASE); 755 return r; 756 } 757 758 /** 759 * radeon_disable_vblank_kms - disable vblank interrupt 760 * 761 * @dev: drm dev pointer 762 * @crtc: crtc to disable vblank interrupt for 763 * 764 * Disable the interrupt on the requested crtc (all asics). 765 */ 766 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 767 { 768 struct radeon_device *rdev = dev->dev_private; 769 770 if (crtc < 0 || crtc >= rdev->num_crtc) { 771 DRM_ERROR("Invalid crtc %d\n", crtc); 772 return; 773 } 774 775 lockmgr(&rdev->irq.lock, LK_EXCLUSIVE); 776 rdev->irq.crtc_vblank_int[crtc] = false; 777 radeon_irq_set(rdev); 778 lockmgr(&rdev->irq.lock, LK_RELEASE); 779 } 780 781 /** 782 * radeon_get_vblank_timestamp_kms - get vblank timestamp 783 * 784 * @dev: drm dev pointer 785 * @crtc: crtc to get the timestamp for 786 * @max_error: max error 787 * @vblank_time: time value 788 * @flags: flags passed to the driver 789 * 790 * Gets the timestamp on the requested crtc based on the 791 * scanout position. (all asics). 792 * Returns postive status flags on success, negative error on failure. 793 */ 794 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 795 int *max_error, 796 struct timeval *vblank_time, 797 unsigned flags) 798 { 799 struct drm_crtc *drmcrtc; 800 struct radeon_device *rdev = dev->dev_private; 801 802 if (crtc < 0 || crtc >= dev->num_crtcs) { 803 DRM_ERROR("Invalid crtc %d\n", crtc); 804 return -EINVAL; 805 } 806 807 /* Get associated drm_crtc: */ 808 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 809 if (!drmcrtc) 810 return -EINVAL; 811 812 /* Helper routine in DRM core does all the work: */ 813 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 814 vblank_time, flags, 815 drmcrtc, &drmcrtc->hwmode); 816 } 817 818 #define KMS_INVALID_IOCTL(name) \ 819 static int name(struct drm_device *dev, void *data, struct drm_file \ 820 *file_priv) \ 821 { \ 822 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ 823 return -EINVAL; \ 824 } 825 826 /* 827 * All these ioctls are invalid in kms world. 828 */ 829 KMS_INVALID_IOCTL(radeon_cp_init_kms) 830 KMS_INVALID_IOCTL(radeon_cp_start_kms) 831 KMS_INVALID_IOCTL(radeon_cp_stop_kms) 832 KMS_INVALID_IOCTL(radeon_cp_reset_kms) 833 KMS_INVALID_IOCTL(radeon_cp_idle_kms) 834 KMS_INVALID_IOCTL(radeon_cp_resume_kms) 835 KMS_INVALID_IOCTL(radeon_engine_reset_kms) 836 KMS_INVALID_IOCTL(radeon_fullscreen_kms) 837 KMS_INVALID_IOCTL(radeon_cp_swap_kms) 838 KMS_INVALID_IOCTL(radeon_cp_clear_kms) 839 KMS_INVALID_IOCTL(radeon_cp_vertex_kms) 840 KMS_INVALID_IOCTL(radeon_cp_indices_kms) 841 KMS_INVALID_IOCTL(radeon_cp_texture_kms) 842 KMS_INVALID_IOCTL(radeon_cp_stipple_kms) 843 KMS_INVALID_IOCTL(radeon_cp_indirect_kms) 844 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) 845 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) 846 KMS_INVALID_IOCTL(radeon_cp_getparam_kms) 847 KMS_INVALID_IOCTL(radeon_cp_flip_kms) 848 KMS_INVALID_IOCTL(radeon_mem_alloc_kms) 849 KMS_INVALID_IOCTL(radeon_mem_free_kms) 850 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) 851 KMS_INVALID_IOCTL(radeon_irq_emit_kms) 852 KMS_INVALID_IOCTL(radeon_irq_wait_kms) 853 KMS_INVALID_IOCTL(radeon_cp_setparam_kms) 854 KMS_INVALID_IOCTL(radeon_surface_alloc_kms) 855 KMS_INVALID_IOCTL(radeon_surface_free_kms) 856 857 858 const struct drm_ioctl_desc radeon_ioctls_kms[] = { 859 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 860 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 861 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 862 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 863 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), 864 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), 865 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), 866 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), 867 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), 868 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), 869 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), 870 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), 871 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), 872 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), 873 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 874 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), 875 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), 876 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), 877 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), 878 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), 879 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), 880 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 881 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), 882 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), 883 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), 884 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), 885 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), 886 /* KMS */ 887 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 888 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 889 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 890 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 891 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), 892 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), 893 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 894 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 895 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 896 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 897 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 898 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 899 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 900 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 901 }; 902 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); 903