1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a 3 * copy of this software and associated documentation files (the "Software"), 4 * to deal in the Software without restriction, including without limitation 5 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 6 * and/or sell copies of the Software, and to permit persons to whom the 7 * Software is furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 18 * OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Authors: Rafał Miłecki <zajec5@gmail.com> 21 * Alex Deucher <alexdeucher@gmail.com> 22 */ 23 #include <drm/drmP.h> 24 #include "radeon.h" 25 #include "avivod.h" 26 #include "atom.h" 27 #include "r600_dpm.h" 28 #include <linux/power_supply.h> 29 #include <linux/hwmon.h> 30 31 #include <sys/power.h> 32 #include <sys/sensors.h> 33 34 #define RADEON_IDLE_LOOP_MS 100 35 #define RADEON_RECLOCK_DELAY_MS 200 36 #define RADEON_WAIT_VBLANK_TIMEOUT 200 37 38 static const char *radeon_pm_state_type_name[5] = { 39 "", 40 "Powersave", 41 "Battery", 42 "Balanced", 43 "Performance", 44 }; 45 46 static void radeon_dynpm_idle_work_handler(struct work_struct *work); 47 static int radeon_debugfs_pm_init(struct radeon_device *rdev); 48 static bool radeon_pm_in_vbl(struct radeon_device *rdev); 49 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 50 static void radeon_pm_update_profile(struct radeon_device *rdev); 51 static void radeon_pm_set_clocks(struct radeon_device *rdev); 52 53 int radeon_pm_get_type_index(struct radeon_device *rdev, 54 enum radeon_pm_state_type ps_type, 55 int instance) 56 { 57 int i; 58 int found_instance = -1; 59 60 for (i = 0; i < rdev->pm.num_power_states; i++) { 61 if (rdev->pm.power_state[i].type == ps_type) { 62 found_instance++; 63 if (found_instance == instance) 64 return i; 65 } 66 } 67 /* return default if no match */ 68 return rdev->pm.default_power_state_index; 69 } 70 71 void radeon_pm_acpi_event_handler(struct radeon_device *rdev) 72 { 73 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 74 mutex_lock(&rdev->pm.mutex); 75 if (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) 76 rdev->pm.dpm.ac_power = true; 77 else 78 rdev->pm.dpm.ac_power = false; 79 if (rdev->family == CHIP_ARUBA) { 80 if (rdev->asic->dpm.enable_bapm) 81 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); 82 } 83 mutex_unlock(&rdev->pm.mutex); 84 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 85 if (rdev->pm.profile == PM_PROFILE_AUTO) { 86 mutex_lock(&rdev->pm.mutex); 87 radeon_pm_update_profile(rdev); 88 radeon_pm_set_clocks(rdev); 89 mutex_unlock(&rdev->pm.mutex); 90 } 91 } 92 } 93 94 static void radeon_pm_update_profile(struct radeon_device *rdev) 95 { 96 switch (rdev->pm.profile) { 97 case PM_PROFILE_DEFAULT: 98 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 99 break; 100 case PM_PROFILE_AUTO: 101 if (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) { 102 if (rdev->pm.active_crtc_count > 1) 103 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 104 else 105 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 106 } else { 107 if (rdev->pm.active_crtc_count > 1) 108 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 109 else 110 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 111 } 112 break; 113 case PM_PROFILE_LOW: 114 if (rdev->pm.active_crtc_count > 1) 115 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 116 else 117 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 118 break; 119 case PM_PROFILE_MID: 120 if (rdev->pm.active_crtc_count > 1) 121 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 122 else 123 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 124 break; 125 case PM_PROFILE_HIGH: 126 if (rdev->pm.active_crtc_count > 1) 127 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 128 else 129 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 130 break; 131 } 132 133 if (rdev->pm.active_crtc_count == 0) { 134 rdev->pm.requested_power_state_index = 135 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 136 rdev->pm.requested_clock_mode_index = 137 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 138 } else { 139 rdev->pm.requested_power_state_index = 140 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 141 rdev->pm.requested_clock_mode_index = 142 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 143 } 144 } 145 146 static void radeon_unmap_vram_bos(struct radeon_device *rdev) 147 { 148 struct radeon_bo *bo, *n; 149 150 if (list_empty(&rdev->gem.objects)) 151 return; 152 153 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 154 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 155 ttm_bo_unmap_virtual(&bo->tbo); 156 } 157 } 158 159 static void radeon_sync_with_vblank(struct radeon_device *rdev) 160 { 161 if (rdev->pm.active_crtcs) { 162 rdev->pm.vblank_sync = false; 163 #ifdef DUMBBELL_WIP 164 wait_event_timeout( 165 rdev->irq.vblank_queue, rdev->pm.vblank_sync, 166 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 167 #endif /* DUMBBELL_WIP */ 168 } 169 } 170 171 static void radeon_set_power_state(struct radeon_device *rdev) 172 { 173 u32 sclk, mclk; 174 bool misc_after = false; 175 176 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 177 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 178 return; 179 180 if (radeon_gui_idle(rdev)) { 181 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 182 clock_info[rdev->pm.requested_clock_mode_index].sclk; 183 if (sclk > rdev->pm.default_sclk) 184 sclk = rdev->pm.default_sclk; 185 186 /* starting with BTC, there is one state that is used for both 187 * MH and SH. Difference is that we always use the high clock index for 188 * mclk and vddci. 189 */ 190 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 191 (rdev->family >= CHIP_BARTS) && 192 rdev->pm.active_crtc_count && 193 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 194 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 195 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 196 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 197 else 198 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 199 clock_info[rdev->pm.requested_clock_mode_index].mclk; 200 201 if (mclk > rdev->pm.default_mclk) 202 mclk = rdev->pm.default_mclk; 203 204 /* upvolt before raising clocks, downvolt after lowering clocks */ 205 if (sclk < rdev->pm.current_sclk) 206 misc_after = true; 207 208 radeon_sync_with_vblank(rdev); 209 210 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 211 if (!radeon_pm_in_vbl(rdev)) 212 return; 213 } 214 215 radeon_pm_prepare(rdev); 216 217 if (!misc_after) 218 /* voltage, pcie lanes, etc.*/ 219 radeon_pm_misc(rdev); 220 221 /* set engine clock */ 222 if (sclk != rdev->pm.current_sclk) { 223 radeon_pm_debug_check_in_vbl(rdev, false); 224 radeon_set_engine_clock(rdev, sclk); 225 radeon_pm_debug_check_in_vbl(rdev, true); 226 rdev->pm.current_sclk = sclk; 227 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 228 } 229 230 /* set memory clock */ 231 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 232 radeon_pm_debug_check_in_vbl(rdev, false); 233 radeon_set_memory_clock(rdev, mclk); 234 radeon_pm_debug_check_in_vbl(rdev, true); 235 rdev->pm.current_mclk = mclk; 236 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 237 } 238 239 if (misc_after) 240 /* voltage, pcie lanes, etc.*/ 241 radeon_pm_misc(rdev); 242 243 radeon_pm_finish(rdev); 244 245 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 246 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 247 } else 248 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 249 } 250 251 static void radeon_pm_set_clocks(struct radeon_device *rdev) 252 { 253 struct drm_crtc *crtc; 254 int i, r; 255 256 /* no need to take locks, etc. if nothing's going to change */ 257 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 258 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 259 return; 260 261 down_write(&rdev->pm.mclk_lock); 262 mutex_lock(&rdev->ring_lock); 263 264 /* wait for the rings to drain */ 265 for (i = 0; i < RADEON_NUM_RINGS; i++) { 266 struct radeon_ring *ring = &rdev->ring[i]; 267 if (!ring->ready) { 268 continue; 269 } 270 r = radeon_fence_wait_empty(rdev, i); 271 if (r) { 272 /* needs a GPU reset dont reset here */ 273 mutex_unlock(&rdev->ring_lock); 274 up_write(&rdev->pm.mclk_lock); 275 return; 276 } 277 } 278 279 radeon_unmap_vram_bos(rdev); 280 281 if (rdev->irq.installed) { 282 i = 0; 283 drm_for_each_crtc(crtc, rdev->ddev) { 284 if (rdev->pm.active_crtcs & (1 << i)) { 285 /* This can fail if a modeset is in progress */ 286 if (drm_crtc_vblank_get(crtc) == 0) 287 rdev->pm.req_vblank |= (1 << i); 288 else 289 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n", 290 i); 291 } 292 i++; 293 } 294 } 295 296 radeon_set_power_state(rdev); 297 298 if (rdev->irq.installed) { 299 i = 0; 300 drm_for_each_crtc(crtc, rdev->ddev) { 301 if (rdev->pm.req_vblank & (1 << i)) { 302 rdev->pm.req_vblank &= ~(1 << i); 303 drm_crtc_vblank_put(crtc); 304 } 305 i++; 306 } 307 } 308 309 /* update display watermarks based on new power state */ 310 radeon_update_bandwidth_info(rdev); 311 if (rdev->pm.active_crtc_count) 312 radeon_bandwidth_update(rdev); 313 314 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 315 316 mutex_unlock(&rdev->ring_lock); 317 up_write(&rdev->pm.mclk_lock); 318 } 319 320 static void radeon_pm_print_states(struct radeon_device *rdev) 321 { 322 int i, j; 323 struct radeon_power_state *power_state; 324 struct radeon_pm_clock_info *clock_info; 325 326 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 327 for (i = 0; i < rdev->pm.num_power_states; i++) { 328 power_state = &rdev->pm.power_state[i]; 329 DRM_DEBUG_DRIVER("State %d: %s\n", i, 330 radeon_pm_state_type_name[power_state->type]); 331 if (i == rdev->pm.default_power_state_index) 332 DRM_DEBUG_DRIVER("\tDefault"); 333 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 334 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 335 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 336 DRM_DEBUG_DRIVER("\tSingle display only\n"); 337 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 338 for (j = 0; j < power_state->num_clock_modes; j++) { 339 clock_info = &(power_state->clock_info[j]); 340 if (rdev->flags & RADEON_IS_IGP) 341 DRM_DEBUG_DRIVER("\t\t%d e: %d\n", 342 j, 343 clock_info->sclk * 10); 344 else 345 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", 346 j, 347 clock_info->sclk * 10, 348 clock_info->mclk * 10, 349 clock_info->voltage.voltage); 350 } 351 } 352 } 353 354 #ifdef DUMBBELL_WIP 355 static ssize_t radeon_get_pm_profile(struct device *dev, 356 struct device_attribute *attr, 357 char *buf) 358 { 359 struct drm_device *ddev = dev_get_drvdata(dev); 360 struct radeon_device *rdev = ddev->dev_private; 361 int cp = rdev->pm.profile; 362 363 return ksnprintf(buf, PAGE_SIZE, "%s\n", 364 (cp == PM_PROFILE_AUTO) ? "auto" : 365 (cp == PM_PROFILE_LOW) ? "low" : 366 (cp == PM_PROFILE_MID) ? "mid" : 367 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 368 } 369 370 static ssize_t radeon_set_pm_profile(struct device *dev, 371 struct device_attribute *attr, 372 const char *buf, 373 size_t count) 374 { 375 struct drm_device *ddev = dev_get_drvdata(dev); 376 struct radeon_device *rdev = ddev->dev_private; 377 378 /* Can't set profile when the card is off */ 379 if ((rdev->flags & RADEON_IS_PX) && 380 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 381 return -EINVAL; 382 383 mutex_lock(&rdev->pm.mutex); 384 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 385 if (strncmp("default", buf, strlen("default")) == 0) 386 rdev->pm.profile = PM_PROFILE_DEFAULT; 387 else if (strncmp("auto", buf, strlen("auto")) == 0) 388 rdev->pm.profile = PM_PROFILE_AUTO; 389 else if (strncmp("low", buf, strlen("low")) == 0) 390 rdev->pm.profile = PM_PROFILE_LOW; 391 else if (strncmp("mid", buf, strlen("mid")) == 0) 392 rdev->pm.profile = PM_PROFILE_MID; 393 else if (strncmp("high", buf, strlen("high")) == 0) 394 rdev->pm.profile = PM_PROFILE_HIGH; 395 else { 396 count = -EINVAL; 397 goto fail; 398 } 399 radeon_pm_update_profile(rdev); 400 radeon_pm_set_clocks(rdev); 401 } else 402 count = -EINVAL; 403 404 fail: 405 mutex_unlock(&rdev->pm.mutex); 406 407 return count; 408 } 409 410 static ssize_t radeon_get_pm_method(struct device *dev, 411 struct device_attribute *attr, 412 char *buf) 413 { 414 struct drm_device *ddev = dev_get_drvdata(dev); 415 struct radeon_device *rdev = ddev->dev_private; 416 int pm = rdev->pm.pm_method; 417 418 return ksnprintf(buf, PAGE_SIZE, "%s\n", 419 (pm == PM_METHOD_DYNPM) ? "dynpm" : 420 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); 421 } 422 423 static ssize_t radeon_set_pm_method(struct device *dev, 424 struct device_attribute *attr, 425 const char *buf, 426 size_t count) 427 { 428 struct drm_device *ddev = dev_get_drvdata(dev); 429 struct radeon_device *rdev = ddev->dev_private; 430 431 /* Can't set method when the card is off */ 432 if ((rdev->flags & RADEON_IS_PX) && 433 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 434 count = -EINVAL; 435 goto fail; 436 } 437 438 /* we don't support the legacy modes with dpm */ 439 if (rdev->pm.pm_method == PM_METHOD_DPM) { 440 count = -EINVAL; 441 goto fail; 442 } 443 444 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 445 mutex_lock(&rdev->pm.mutex); 446 rdev->pm.pm_method = PM_METHOD_DYNPM; 447 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 448 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 449 mutex_unlock(&rdev->pm.mutex); 450 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 451 mutex_lock(&rdev->pm.mutex); 452 /* disable dynpm */ 453 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 454 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 455 rdev->pm.pm_method = PM_METHOD_PROFILE; 456 mutex_unlock(&rdev->pm.mutex); 457 #ifdef DUMBBELL_WIP 458 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 459 #endif /* DUMBBELL_WIP */ 460 } else { 461 count = -EINVAL; 462 goto fail; 463 } 464 radeon_pm_compute_clocks(rdev); 465 fail: 466 return count; 467 } 468 469 static ssize_t radeon_get_dpm_state(struct device *dev, 470 struct device_attribute *attr, 471 char *buf) 472 { 473 struct drm_device *ddev = dev_get_drvdata(dev); 474 struct radeon_device *rdev = ddev->dev_private; 475 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; 476 477 return snprintf(buf, PAGE_SIZE, "%s\n", 478 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 479 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 480 } 481 482 static ssize_t radeon_set_dpm_state(struct device *dev, 483 struct device_attribute *attr, 484 const char *buf, 485 size_t count) 486 { 487 struct drm_device *ddev = dev_get_drvdata(dev); 488 struct radeon_device *rdev = ddev->dev_private; 489 490 mutex_lock(&rdev->pm.mutex); 491 if (strncmp("battery", buf, strlen("battery")) == 0) 492 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; 493 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 494 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 495 else if (strncmp("performance", buf, strlen("performance")) == 0) 496 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; 497 else { 498 mutex_unlock(&rdev->pm.mutex); 499 count = -EINVAL; 500 goto fail; 501 } 502 mutex_unlock(&rdev->pm.mutex); 503 504 /* Can't set dpm state when the card is off */ 505 if (!(rdev->flags & RADEON_IS_PX) || 506 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) 507 radeon_pm_compute_clocks(rdev); 508 509 fail: 510 return count; 511 } 512 513 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, 514 struct device_attribute *attr, 515 char *buf) 516 { 517 struct drm_device *ddev = dev_get_drvdata(dev); 518 struct radeon_device *rdev = ddev->dev_private; 519 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 520 521 if ((rdev->flags & RADEON_IS_PX) && 522 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 523 return ksnprintf(buf, PAGE_SIZE, "off\n"); 524 525 return snprintf(buf, PAGE_SIZE, "%s\n", 526 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : 527 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); 528 } 529 530 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, 531 struct device_attribute *attr, 532 const char *buf, 533 size_t count) 534 { 535 struct drm_device *ddev = dev_get_drvdata(dev); 536 struct radeon_device *rdev = ddev->dev_private; 537 enum radeon_dpm_forced_level level; 538 int ret = 0; 539 540 /* Can't force performance level when the card is off */ 541 if ((rdev->flags & RADEON_IS_PX) && 542 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 543 return -EINVAL; 544 545 mutex_lock(&rdev->pm.mutex); 546 if (strncmp("low", buf, strlen("low")) == 0) { 547 level = RADEON_DPM_FORCED_LEVEL_LOW; 548 } else if (strncmp("high", buf, strlen("high")) == 0) { 549 level = RADEON_DPM_FORCED_LEVEL_HIGH; 550 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 551 level = RADEON_DPM_FORCED_LEVEL_AUTO; 552 } else { 553 count = -EINVAL; 554 goto fail; 555 } 556 if (rdev->asic->dpm.force_performance_level) { 557 if (rdev->pm.dpm.thermal_active) { 558 count = -EINVAL; 559 goto fail; 560 } 561 ret = radeon_dpm_force_performance_level(rdev, level); 562 if (ret) 563 count = -EINVAL; 564 } 565 fail: 566 mutex_unlock(&rdev->pm.mutex); 567 568 return count; 569 } 570 571 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev, 572 struct device_attribute *attr, 573 char *buf) 574 { 575 struct radeon_device *rdev = dev_get_drvdata(dev); 576 u32 pwm_mode = 0; 577 578 if (rdev->asic->dpm.fan_ctrl_get_mode) 579 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev); 580 581 /* never 0 (full-speed), fuse or smc-controlled always */ 582 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); 583 } 584 585 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev, 586 struct device_attribute *attr, 587 const char *buf, 588 size_t count) 589 { 590 struct radeon_device *rdev = dev_get_drvdata(dev); 591 int err; 592 int value; 593 594 if(!rdev->asic->dpm.fan_ctrl_set_mode) 595 return -EINVAL; 596 597 err = kstrtoint(buf, 10, &value); 598 if (err) 599 return err; 600 601 switch (value) { 602 case 1: /* manual, percent-based */ 603 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC); 604 break; 605 default: /* disable */ 606 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0); 607 break; 608 } 609 610 return count; 611 } 612 613 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev, 614 struct device_attribute *attr, 615 char *buf) 616 { 617 return sprintf(buf, "%i\n", 0); 618 } 619 620 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev, 621 struct device_attribute *attr, 622 char *buf) 623 { 624 return sprintf(buf, "%i\n", 255); 625 } 626 627 static ssize_t radeon_hwmon_set_pwm1(struct device *dev, 628 struct device_attribute *attr, 629 const char *buf, size_t count) 630 { 631 struct radeon_device *rdev = dev_get_drvdata(dev); 632 int err; 633 u32 value; 634 635 err = kstrtou32(buf, 10, &value); 636 if (err) 637 return err; 638 639 value = (value * 100) / 255; 640 641 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value); 642 if (err) 643 return err; 644 645 return count; 646 } 647 648 static ssize_t radeon_hwmon_get_pwm1(struct device *dev, 649 struct device_attribute *attr, 650 char *buf) 651 { 652 struct radeon_device *rdev = dev_get_drvdata(dev); 653 int err; 654 u32 speed; 655 656 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed); 657 if (err) 658 return err; 659 660 speed = (speed * 255) / 100; 661 662 return sprintf(buf, "%i\n", speed); 663 } 664 665 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 666 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 667 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state); 668 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, 669 radeon_get_dpm_forced_performance_level, 670 radeon_set_dpm_forced_performance_level); 671 672 static ssize_t radeon_hwmon_show_temp(struct device *dev, 673 struct device_attribute *attr, 674 char *buf) 675 { 676 struct radeon_device *rdev = dev_get_drvdata(dev); 677 struct drm_device *ddev = rdev->ddev; 678 int temp; 679 680 /* Can't get temperature when the card is off */ 681 if ((rdev->flags & RADEON_IS_PX) && 682 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 683 return -EINVAL; 684 685 if (rdev->asic->pm.get_temperature) 686 temp = radeon_get_temperature(rdev); 687 else 688 temp = 0; 689 690 return ksnprintf(buf, PAGE_SIZE, "%d\n", temp); 691 } 692 693 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, 694 struct device_attribute *attr, 695 char *buf) 696 { 697 struct radeon_device *rdev = dev_get_drvdata(dev); 698 int hyst = to_sensor_dev_attr(attr)->index; 699 int temp; 700 701 if (hyst) 702 temp = rdev->pm.dpm.thermal.min_temp; 703 else 704 temp = rdev->pm.dpm.thermal.max_temp; 705 706 return ksnprintf(buf, PAGE_SIZE, "%d\n", temp); 707 } 708 709 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 710 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); 711 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); 712 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0); 713 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0); 714 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0); 715 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0); 716 717 718 static struct attribute *hwmon_attributes[] = { 719 &sensor_dev_attr_temp1_input.dev_attr.attr, 720 &sensor_dev_attr_temp1_crit.dev_attr.attr, 721 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 722 &sensor_dev_attr_pwm1.dev_attr.attr, 723 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 724 &sensor_dev_attr_pwm1_min.dev_attr.attr, 725 &sensor_dev_attr_pwm1_max.dev_attr.attr, 726 NULL 727 }; 728 729 static umode_t hwmon_attributes_visible(struct kobject *kobj, 730 struct attribute *attr, int index) 731 { 732 struct device *dev = kobj_to_dev(kobj); 733 struct radeon_device *rdev = dev_get_drvdata(dev); 734 umode_t effective_mode = attr->mode; 735 736 /* Skip attributes if DPM is not enabled */ 737 if (rdev->pm.pm_method != PM_METHOD_DPM && 738 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 739 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 740 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 741 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 742 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 743 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 744 return 0; 745 746 /* Skip fan attributes if fan is not present */ 747 if (rdev->pm.no_fan && 748 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 749 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 750 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 751 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 752 return 0; 753 754 /* mask fan attributes if we have no bindings for this asic to expose */ 755 if ((!rdev->asic->dpm.get_fan_speed_percent && 756 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 757 (!rdev->asic->dpm.fan_ctrl_get_mode && 758 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 759 effective_mode &= ~S_IRUGO; 760 761 if ((!rdev->asic->dpm.set_fan_speed_percent && 762 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 763 (!rdev->asic->dpm.fan_ctrl_set_mode && 764 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 765 effective_mode &= ~S_IWUSR; 766 767 /* hide max/min values if we can't both query and manage the fan */ 768 if ((!rdev->asic->dpm.set_fan_speed_percent && 769 !rdev->asic->dpm.get_fan_speed_percent) && 770 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 771 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 772 return 0; 773 774 return effective_mode; 775 } 776 777 static const struct attribute_group hwmon_attrgroup = { 778 .attrs = hwmon_attributes, 779 .is_visible = hwmon_attributes_visible, 780 }; 781 782 static const struct attribute_group *hwmon_groups[] = { 783 &hwmon_attrgroup, 784 NULL 785 }; 786 #endif /* DUMBBELL_WIP */ 787 788 static void 789 radeon_hwmon_refresh(void *arg) 790 { 791 struct radeon_device *rdev = (struct radeon_device *)arg; 792 struct drm_device *ddev = rdev->ddev; 793 struct ksensor *s = rdev->pm.int_sensor; 794 int temp; 795 enum sensor_status stat; 796 797 /* Can't get temperature when the card is off */ 798 if ((rdev->flags & RADEON_IS_PX) && 799 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 800 sensor_set_unknown(s); 801 s->status = SENSOR_S_OK; 802 return; 803 } 804 805 if (rdev->asic->pm.get_temperature == NULL) { 806 sensor_set_invalid(s); 807 return; 808 } 809 810 temp = radeon_get_temperature(rdev); 811 if (temp >= rdev->pm.dpm.thermal.max_temp) 812 stat = SENSOR_S_CRIT; 813 else if (temp >= rdev->pm.dpm.thermal.min_temp) 814 stat = SENSOR_S_WARN; 815 else 816 stat = SENSOR_S_OK; 817 818 sensor_set(s, temp * 1000 + 273150000, stat); 819 } 820 821 static int radeon_hwmon_init(struct radeon_device *rdev) 822 { 823 int err = 0; 824 825 rdev->pm.int_sensor = NULL; 826 rdev->pm.int_sensordev = NULL; 827 828 switch (rdev->pm.int_thermal_type) { 829 case THERMAL_TYPE_RV6XX: 830 case THERMAL_TYPE_RV770: 831 case THERMAL_TYPE_EVERGREEN: 832 case THERMAL_TYPE_NI: 833 case THERMAL_TYPE_SUMO: 834 case THERMAL_TYPE_SI: 835 case THERMAL_TYPE_CI: 836 case THERMAL_TYPE_KV: 837 if (rdev->asic->pm.get_temperature == NULL) 838 return err; 839 840 rdev->pm.int_sensor = kmalloc(sizeof(*rdev->pm.int_sensor), 841 M_DRM, M_ZERO | M_WAITOK); 842 rdev->pm.int_sensordev = kmalloc( 843 sizeof(*rdev->pm.int_sensordev), M_DRM, 844 M_ZERO | M_WAITOK); 845 strlcpy(rdev->pm.int_sensordev->xname, 846 device_get_nameunit(rdev->dev->bsddev), 847 sizeof(rdev->pm.int_sensordev->xname)); 848 rdev->pm.int_sensor->type = SENSOR_TEMP; 849 rdev->pm.int_sensor->flags |= SENSOR_FINVALID; 850 sensor_attach(rdev->pm.int_sensordev, rdev->pm.int_sensor); 851 sensor_task_register(rdev, radeon_hwmon_refresh, 5); 852 sensordev_install(rdev->pm.int_sensordev); 853 break; 854 default: 855 break; 856 } 857 858 return err; 859 } 860 861 static void radeon_hwmon_fini(struct radeon_device *rdev) 862 { 863 if (rdev->pm.int_sensor != NULL && rdev->pm.int_sensordev != NULL) { 864 sensordev_deinstall(rdev->pm.int_sensordev); 865 sensor_task_unregister(rdev); 866 kfree(rdev->pm.int_sensor); 867 kfree(rdev->pm.int_sensordev); 868 rdev->pm.int_sensor = NULL; 869 rdev->pm.int_sensordev = NULL; 870 } 871 } 872 873 static void radeon_dpm_thermal_work_handler(struct work_struct *work) 874 { 875 struct radeon_device *rdev = 876 container_of(work, struct radeon_device, 877 pm.dpm.thermal.work); 878 /* switch to the thermal state */ 879 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; 880 881 if (!rdev->pm.dpm_enabled) 882 return; 883 884 if (rdev->asic->pm.get_temperature) { 885 int temp = radeon_get_temperature(rdev); 886 887 if (temp < rdev->pm.dpm.thermal.min_temp) 888 /* switch back the user state */ 889 dpm_state = rdev->pm.dpm.user_state; 890 } else { 891 if (rdev->pm.dpm.thermal.high_to_low) 892 /* switch back the user state */ 893 dpm_state = rdev->pm.dpm.user_state; 894 } 895 mutex_lock(&rdev->pm.mutex); 896 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) 897 rdev->pm.dpm.thermal_active = true; 898 else 899 rdev->pm.dpm.thermal_active = false; 900 rdev->pm.dpm.state = dpm_state; 901 mutex_unlock(&rdev->pm.mutex); 902 903 radeon_pm_compute_clocks(rdev); 904 } 905 906 static bool radeon_dpm_single_display(struct radeon_device *rdev) 907 { 908 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? 909 true : false; 910 911 /* check if the vblank period is too short to adjust the mclk */ 912 if (single_display && rdev->asic->dpm.vblank_too_short) { 913 if (radeon_dpm_vblank_too_short(rdev)) 914 single_display = false; 915 } 916 917 return single_display; 918 } 919 920 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, 921 enum radeon_pm_state_type dpm_state) 922 { 923 int i; 924 struct radeon_ps *ps; 925 u32 ui_class; 926 bool single_display = radeon_dpm_single_display(rdev); 927 928 /* 120hz tends to be problematic even if they are under the 929 * vblank limit. 930 */ 931 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) 932 single_display = false; 933 934 /* certain older asics have a separare 3D performance state, 935 * so try that first if the user selected performance 936 */ 937 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) 938 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; 939 /* balanced states don't exist at the moment */ 940 if (dpm_state == POWER_STATE_TYPE_BALANCED) 941 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 942 943 restart_search: 944 /* Pick the best power state based on current conditions */ 945 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 946 ps = &rdev->pm.dpm.ps[i]; 947 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; 948 switch (dpm_state) { 949 /* user states */ 950 case POWER_STATE_TYPE_BATTERY: 951 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { 952 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 953 if (single_display) 954 return ps; 955 } else 956 return ps; 957 } 958 break; 959 case POWER_STATE_TYPE_BALANCED: 960 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { 961 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 962 if (single_display) 963 return ps; 964 } else 965 return ps; 966 } 967 break; 968 case POWER_STATE_TYPE_PERFORMANCE: 969 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 970 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 971 if (single_display) 972 return ps; 973 } else 974 return ps; 975 } 976 break; 977 /* internal states */ 978 case POWER_STATE_TYPE_INTERNAL_UVD: 979 if (rdev->pm.dpm.uvd_ps) 980 return rdev->pm.dpm.uvd_ps; 981 else 982 break; 983 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 984 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 985 return ps; 986 break; 987 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 988 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 989 return ps; 990 break; 991 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 992 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 993 return ps; 994 break; 995 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 996 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 997 return ps; 998 break; 999 case POWER_STATE_TYPE_INTERNAL_BOOT: 1000 return rdev->pm.dpm.boot_ps; 1001 case POWER_STATE_TYPE_INTERNAL_THERMAL: 1002 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 1003 return ps; 1004 break; 1005 case POWER_STATE_TYPE_INTERNAL_ACPI: 1006 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) 1007 return ps; 1008 break; 1009 case POWER_STATE_TYPE_INTERNAL_ULV: 1010 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) 1011 return ps; 1012 break; 1013 case POWER_STATE_TYPE_INTERNAL_3DPERF: 1014 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 1015 return ps; 1016 break; 1017 default: 1018 break; 1019 } 1020 } 1021 /* use a fallback state if we didn't match */ 1022 switch (dpm_state) { 1023 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 1024 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1025 goto restart_search; 1026 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 1027 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 1028 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 1029 if (rdev->pm.dpm.uvd_ps) { 1030 return rdev->pm.dpm.uvd_ps; 1031 } else { 1032 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1033 goto restart_search; 1034 } 1035 case POWER_STATE_TYPE_INTERNAL_THERMAL: 1036 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; 1037 goto restart_search; 1038 case POWER_STATE_TYPE_INTERNAL_ACPI: 1039 dpm_state = POWER_STATE_TYPE_BATTERY; 1040 goto restart_search; 1041 case POWER_STATE_TYPE_BATTERY: 1042 case POWER_STATE_TYPE_BALANCED: 1043 case POWER_STATE_TYPE_INTERNAL_3DPERF: 1044 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1045 goto restart_search; 1046 default: 1047 break; 1048 } 1049 1050 return NULL; 1051 } 1052 1053 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) 1054 { 1055 int i; 1056 struct radeon_ps *ps; 1057 enum radeon_pm_state_type dpm_state; 1058 int ret; 1059 bool single_display = radeon_dpm_single_display(rdev); 1060 1061 /* if dpm init failed */ 1062 if (!rdev->pm.dpm_enabled) 1063 return; 1064 1065 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { 1066 /* add other state override checks here */ 1067 if ((!rdev->pm.dpm.thermal_active) && 1068 (!rdev->pm.dpm.uvd_active)) 1069 rdev->pm.dpm.state = rdev->pm.dpm.user_state; 1070 } 1071 dpm_state = rdev->pm.dpm.state; 1072 1073 ps = radeon_dpm_pick_power_state(rdev, dpm_state); 1074 if (ps) 1075 rdev->pm.dpm.requested_ps = ps; 1076 else 1077 return; 1078 1079 /* no need to reprogram if nothing changed unless we are on BTC+ */ 1080 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { 1081 /* vce just modifies an existing state so force a change */ 1082 if (ps->vce_active != rdev->pm.dpm.vce_active) 1083 goto force; 1084 /* user has made a display change (such as timing) */ 1085 if (rdev->pm.dpm.single_display != single_display) 1086 goto force; 1087 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { 1088 /* for pre-BTC and APUs if the num crtcs changed but state is the same, 1089 * all we need to do is update the display configuration. 1090 */ 1091 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { 1092 /* update display watermarks based on new power state */ 1093 radeon_bandwidth_update(rdev); 1094 /* update displays */ 1095 radeon_dpm_display_configuration_changed(rdev); 1096 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1097 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1098 } 1099 return; 1100 } else { 1101 /* for BTC+ if the num crtcs hasn't changed and state is the same, 1102 * nothing to do, if the num crtcs is > 1 and state is the same, 1103 * update display configuration. 1104 */ 1105 if (rdev->pm.dpm.new_active_crtcs == 1106 rdev->pm.dpm.current_active_crtcs) { 1107 return; 1108 } else { 1109 if ((rdev->pm.dpm.current_active_crtc_count > 1) && 1110 (rdev->pm.dpm.new_active_crtc_count > 1)) { 1111 /* update display watermarks based on new power state */ 1112 radeon_bandwidth_update(rdev); 1113 /* update displays */ 1114 radeon_dpm_display_configuration_changed(rdev); 1115 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1116 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1117 return; 1118 } 1119 } 1120 } 1121 } 1122 1123 force: 1124 if (radeon_dpm == 1) { 1125 printk("switching from power state:\n"); 1126 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); 1127 printk("switching to power state:\n"); 1128 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); 1129 } 1130 1131 down_write(&rdev->pm.mclk_lock); 1132 mutex_lock(&rdev->ring_lock); 1133 1134 /* update whether vce is active */ 1135 ps->vce_active = rdev->pm.dpm.vce_active; 1136 1137 ret = radeon_dpm_pre_set_power_state(rdev); 1138 if (ret) 1139 goto done; 1140 1141 /* update display watermarks based on new power state */ 1142 radeon_bandwidth_update(rdev); 1143 1144 /* wait for the rings to drain */ 1145 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1146 struct radeon_ring *ring = &rdev->ring[i]; 1147 if (ring->ready) 1148 radeon_fence_wait_empty(rdev, i); 1149 } 1150 1151 /* program the new power state */ 1152 radeon_dpm_set_power_state(rdev); 1153 1154 /* update current power state */ 1155 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; 1156 1157 radeon_dpm_post_set_power_state(rdev); 1158 1159 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1160 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1161 rdev->pm.dpm.single_display = single_display; 1162 1163 /* update displays */ 1164 radeon_dpm_display_configuration_changed(rdev); 1165 1166 if (rdev->asic->dpm.force_performance_level) { 1167 if (rdev->pm.dpm.thermal_active) { 1168 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 1169 /* force low perf level for thermal */ 1170 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); 1171 /* save the user's level */ 1172 rdev->pm.dpm.forced_level = level; 1173 } else { 1174 /* otherwise, user selected level */ 1175 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); 1176 } 1177 } 1178 1179 done: 1180 mutex_unlock(&rdev->ring_lock); 1181 up_write(&rdev->pm.mclk_lock); 1182 } 1183 1184 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) 1185 { 1186 enum radeon_pm_state_type dpm_state; 1187 1188 if (rdev->asic->dpm.powergate_uvd) { 1189 mutex_lock(&rdev->pm.mutex); 1190 /* don't powergate anything if we 1191 have active but pause streams */ 1192 enable |= rdev->pm.dpm.sd > 0; 1193 enable |= rdev->pm.dpm.hd > 0; 1194 /* enable/disable UVD */ 1195 radeon_dpm_powergate_uvd(rdev, !enable); 1196 mutex_unlock(&rdev->pm.mutex); 1197 } else { 1198 if (enable) { 1199 mutex_lock(&rdev->pm.mutex); 1200 rdev->pm.dpm.uvd_active = true; 1201 /* disable this for now */ 1202 #if 0 1203 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 1204 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 1205 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) 1206 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1207 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) 1208 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1209 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 1210 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 1211 else 1212 #endif 1213 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 1214 rdev->pm.dpm.state = dpm_state; 1215 mutex_unlock(&rdev->pm.mutex); 1216 } else { 1217 mutex_lock(&rdev->pm.mutex); 1218 rdev->pm.dpm.uvd_active = false; 1219 mutex_unlock(&rdev->pm.mutex); 1220 } 1221 1222 radeon_pm_compute_clocks(rdev); 1223 } 1224 } 1225 1226 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable) 1227 { 1228 if (enable) { 1229 mutex_lock(&rdev->pm.mutex); 1230 rdev->pm.dpm.vce_active = true; 1231 /* XXX select vce level based on ring/task */ 1232 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; 1233 mutex_unlock(&rdev->pm.mutex); 1234 } else { 1235 mutex_lock(&rdev->pm.mutex); 1236 rdev->pm.dpm.vce_active = false; 1237 mutex_unlock(&rdev->pm.mutex); 1238 } 1239 1240 radeon_pm_compute_clocks(rdev); 1241 } 1242 1243 static void radeon_pm_suspend_old(struct radeon_device *rdev) 1244 { 1245 mutex_lock(&rdev->pm.mutex); 1246 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1247 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 1248 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 1249 } 1250 mutex_unlock(&rdev->pm.mutex); 1251 1252 #ifdef DUMBBELL_WIP 1253 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1254 #endif /* DUMBBELL_WIP */ 1255 } 1256 1257 static void radeon_pm_suspend_dpm(struct radeon_device *rdev) 1258 { 1259 mutex_lock(&rdev->pm.mutex); 1260 /* disable dpm */ 1261 radeon_dpm_disable(rdev); 1262 /* reset the power state */ 1263 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1264 rdev->pm.dpm_enabled = false; 1265 mutex_unlock(&rdev->pm.mutex); 1266 } 1267 1268 void radeon_pm_suspend(struct radeon_device *rdev) 1269 { 1270 if (rdev->pm.pm_method == PM_METHOD_DPM) 1271 radeon_pm_suspend_dpm(rdev); 1272 else 1273 radeon_pm_suspend_old(rdev); 1274 } 1275 1276 static void radeon_pm_resume_old(struct radeon_device *rdev) 1277 { 1278 /* set up the default clocks if the MC ucode is loaded */ 1279 if ((rdev->family >= CHIP_BARTS) && 1280 (rdev->family <= CHIP_CAYMAN) && 1281 rdev->mc_fw) { 1282 if (rdev->pm.default_vddc) 1283 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1284 SET_VOLTAGE_TYPE_ASIC_VDDC); 1285 if (rdev->pm.default_vddci) 1286 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1287 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1288 if (rdev->pm.default_sclk) 1289 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1290 if (rdev->pm.default_mclk) 1291 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1292 } 1293 /* asic init will reset the default power state */ 1294 mutex_lock(&rdev->pm.mutex); 1295 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 1296 rdev->pm.current_clock_mode_index = 0; 1297 rdev->pm.current_sclk = rdev->pm.default_sclk; 1298 rdev->pm.current_mclk = rdev->pm.default_mclk; 1299 if (rdev->pm.power_state) { 1300 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 1301 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 1302 } 1303 if (rdev->pm.pm_method == PM_METHOD_DYNPM 1304 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 1305 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1306 #ifdef DUMBBELL_WIP 1307 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1308 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1309 #endif /* DUMBBELL_WIP */ 1310 } 1311 mutex_unlock(&rdev->pm.mutex); 1312 radeon_pm_compute_clocks(rdev); 1313 } 1314 1315 static void radeon_pm_resume_dpm(struct radeon_device *rdev) 1316 { 1317 int ret; 1318 1319 /* asic init will reset to the boot state */ 1320 mutex_lock(&rdev->pm.mutex); 1321 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1322 radeon_dpm_setup_asic(rdev); 1323 ret = radeon_dpm_enable(rdev); 1324 mutex_unlock(&rdev->pm.mutex); 1325 if (ret) 1326 goto dpm_resume_fail; 1327 rdev->pm.dpm_enabled = true; 1328 return; 1329 1330 dpm_resume_fail: 1331 DRM_ERROR("radeon: dpm resume failed\n"); 1332 if ((rdev->family >= CHIP_BARTS) && 1333 (rdev->family <= CHIP_CAYMAN) && 1334 rdev->mc_fw) { 1335 if (rdev->pm.default_vddc) 1336 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1337 SET_VOLTAGE_TYPE_ASIC_VDDC); 1338 if (rdev->pm.default_vddci) 1339 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1340 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1341 if (rdev->pm.default_sclk) 1342 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1343 if (rdev->pm.default_mclk) 1344 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1345 } 1346 } 1347 1348 void radeon_pm_resume(struct radeon_device *rdev) 1349 { 1350 if (rdev->pm.pm_method == PM_METHOD_DPM) 1351 radeon_pm_resume_dpm(rdev); 1352 else 1353 radeon_pm_resume_old(rdev); 1354 } 1355 1356 static int radeon_pm_init_old(struct radeon_device *rdev) 1357 { 1358 int ret; 1359 1360 rdev->pm.profile = PM_PROFILE_DEFAULT; 1361 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1362 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1363 rdev->pm.dynpm_can_upclock = true; 1364 rdev->pm.dynpm_can_downclock = true; 1365 rdev->pm.default_sclk = rdev->clock.default_sclk; 1366 rdev->pm.default_mclk = rdev->clock.default_mclk; 1367 rdev->pm.current_sclk = rdev->clock.default_sclk; 1368 rdev->pm.current_mclk = rdev->clock.default_mclk; 1369 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1370 1371 if (rdev->bios) { 1372 if (rdev->is_atom_bios) 1373 radeon_atombios_get_power_modes(rdev); 1374 else 1375 radeon_combios_get_power_modes(rdev); 1376 radeon_pm_print_states(rdev); 1377 radeon_pm_init_profile(rdev); 1378 /* set up the default clocks if the MC ucode is loaded */ 1379 if ((rdev->family >= CHIP_BARTS) && 1380 (rdev->family <= CHIP_CAYMAN) && 1381 rdev->mc_fw) { 1382 if (rdev->pm.default_vddc) 1383 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1384 SET_VOLTAGE_TYPE_ASIC_VDDC); 1385 if (rdev->pm.default_vddci) 1386 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1387 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1388 if (rdev->pm.default_sclk) 1389 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1390 if (rdev->pm.default_mclk) 1391 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1392 } 1393 } 1394 1395 /* set up the internal thermal sensor if applicable */ 1396 ret = radeon_hwmon_init(rdev); 1397 if (ret) 1398 return ret; 1399 1400 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 1401 1402 if (rdev->pm.num_power_states > 1) { 1403 if (radeon_debugfs_pm_init(rdev)) { 1404 DRM_ERROR("Failed to register debugfs file for PM!\n"); 1405 } 1406 1407 DRM_INFO("radeon: power management initialized\n"); 1408 } 1409 1410 return 0; 1411 } 1412 1413 static void radeon_dpm_print_power_states(struct radeon_device *rdev) 1414 { 1415 int i; 1416 1417 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 1418 printk("== power state %d ==\n", i); 1419 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); 1420 } 1421 } 1422 1423 static int radeon_pm_init_dpm(struct radeon_device *rdev) 1424 { 1425 int ret; 1426 1427 /* default to balanced state */ 1428 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 1429 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 1430 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 1431 rdev->pm.default_sclk = rdev->clock.default_sclk; 1432 rdev->pm.default_mclk = rdev->clock.default_mclk; 1433 rdev->pm.current_sclk = rdev->clock.default_sclk; 1434 rdev->pm.current_mclk = rdev->clock.default_mclk; 1435 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1436 1437 if (rdev->bios && rdev->is_atom_bios) 1438 radeon_atombios_get_power_modes(rdev); 1439 else 1440 return -EINVAL; 1441 1442 /* set up the internal thermal sensor if applicable */ 1443 ret = radeon_hwmon_init(rdev); 1444 if (ret) 1445 return ret; 1446 1447 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); 1448 mutex_lock(&rdev->pm.mutex); 1449 radeon_dpm_init(rdev); 1450 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1451 if (radeon_dpm == 1) 1452 radeon_dpm_print_power_states(rdev); 1453 radeon_dpm_setup_asic(rdev); 1454 ret = radeon_dpm_enable(rdev); 1455 mutex_unlock(&rdev->pm.mutex); 1456 if (ret) 1457 goto dpm_failed; 1458 rdev->pm.dpm_enabled = true; 1459 1460 #ifdef TODO_DEVICE_FILE 1461 if (radeon_debugfs_pm_init(rdev)) { 1462 DRM_ERROR("Failed to register debugfs file for dpm!\n"); 1463 } 1464 #endif 1465 1466 DRM_INFO("radeon: dpm initialized\n"); 1467 1468 return 0; 1469 1470 dpm_failed: 1471 rdev->pm.dpm_enabled = false; 1472 if ((rdev->family >= CHIP_BARTS) && 1473 (rdev->family <= CHIP_CAYMAN) && 1474 rdev->mc_fw) { 1475 if (rdev->pm.default_vddc) 1476 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1477 SET_VOLTAGE_TYPE_ASIC_VDDC); 1478 if (rdev->pm.default_vddci) 1479 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1480 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1481 if (rdev->pm.default_sclk) 1482 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1483 if (rdev->pm.default_mclk) 1484 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1485 } 1486 DRM_ERROR("radeon: dpm initialization failed\n"); 1487 return ret; 1488 } 1489 1490 struct radeon_dpm_quirk { 1491 u32 chip_vendor; 1492 u32 chip_device; 1493 u32 subsys_vendor; 1494 u32 subsys_device; 1495 }; 1496 1497 /* cards with dpm stability problems */ 1498 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = { 1499 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */ 1500 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 }, 1501 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */ 1502 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 }, 1503 { 0, 0, 0, 0 }, 1504 }; 1505 1506 int radeon_pm_init(struct radeon_device *rdev) 1507 { 1508 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list; 1509 bool disable_dpm = false; 1510 1511 /* Apply dpm quirks */ 1512 while (p && p->chip_device != 0) { 1513 if (rdev->pdev->vendor == p->chip_vendor && 1514 rdev->pdev->device == p->chip_device && 1515 rdev->pdev->subsystem_vendor == p->subsys_vendor && 1516 rdev->pdev->subsystem_device == p->subsys_device) { 1517 disable_dpm = true; 1518 break; 1519 } 1520 ++p; 1521 } 1522 1523 /* enable dpm on rv6xx+ */ 1524 switch (rdev->family) { 1525 case CHIP_RV610: 1526 case CHIP_RV630: 1527 case CHIP_RV620: 1528 case CHIP_RV635: 1529 case CHIP_RV670: 1530 case CHIP_RS780: 1531 case CHIP_RS880: 1532 case CHIP_RV770: 1533 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1534 if (!rdev->rlc_fw) 1535 rdev->pm.pm_method = PM_METHOD_PROFILE; 1536 else if ((rdev->family >= CHIP_RV770) && 1537 (!(rdev->flags & RADEON_IS_IGP)) && 1538 (!rdev->smc_fw)) 1539 rdev->pm.pm_method = PM_METHOD_PROFILE; 1540 else if (radeon_dpm == 1) 1541 rdev->pm.pm_method = PM_METHOD_DPM; 1542 else 1543 rdev->pm.pm_method = PM_METHOD_PROFILE; 1544 break; 1545 case CHIP_RV730: 1546 case CHIP_RV710: 1547 case CHIP_RV740: 1548 case CHIP_CEDAR: 1549 case CHIP_REDWOOD: 1550 case CHIP_JUNIPER: 1551 case CHIP_CYPRESS: 1552 case CHIP_HEMLOCK: 1553 case CHIP_PALM: 1554 case CHIP_SUMO: 1555 case CHIP_SUMO2: 1556 case CHIP_BARTS: 1557 case CHIP_TURKS: 1558 case CHIP_CAICOS: 1559 case CHIP_CAYMAN: 1560 case CHIP_ARUBA: 1561 case CHIP_TAHITI: 1562 case CHIP_PITCAIRN: 1563 case CHIP_VERDE: 1564 case CHIP_OLAND: 1565 case CHIP_HAINAN: 1566 case CHIP_BONAIRE: 1567 case CHIP_KABINI: 1568 case CHIP_KAVERI: 1569 case CHIP_HAWAII: 1570 case CHIP_MULLINS: 1571 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1572 if (!rdev->rlc_fw) 1573 rdev->pm.pm_method = PM_METHOD_PROFILE; 1574 else if ((rdev->family >= CHIP_RV770) && 1575 (!(rdev->flags & RADEON_IS_IGP)) && 1576 (!rdev->smc_fw)) 1577 rdev->pm.pm_method = PM_METHOD_PROFILE; 1578 else if (disable_dpm && (radeon_dpm == -1)) 1579 rdev->pm.pm_method = PM_METHOD_PROFILE; 1580 else if (radeon_dpm == 0) 1581 rdev->pm.pm_method = PM_METHOD_PROFILE; 1582 else 1583 rdev->pm.pm_method = PM_METHOD_DPM; 1584 break; 1585 default: 1586 /* default to profile method */ 1587 rdev->pm.pm_method = PM_METHOD_PROFILE; 1588 break; 1589 } 1590 1591 if (rdev->pm.pm_method == PM_METHOD_DPM) 1592 return radeon_pm_init_dpm(rdev); 1593 else 1594 return radeon_pm_init_old(rdev); 1595 } 1596 1597 int radeon_pm_late_init(struct radeon_device *rdev) 1598 { 1599 int ret = 0; 1600 1601 if (rdev->pm.pm_method == PM_METHOD_DPM) { 1602 if (rdev->pm.dpm_enabled) { 1603 if (!rdev->pm.sysfs_initialized) { 1604 #if 0 1605 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); 1606 if (ret) 1607 DRM_ERROR("failed to create device file for dpm state\n"); 1608 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1609 if (ret) 1610 DRM_ERROR("failed to create device file for dpm state\n"); 1611 /* XXX: these are noops for dpm but are here for backwards compat */ 1612 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1613 if (ret) 1614 DRM_ERROR("failed to create device file for power profile\n"); 1615 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1616 if (ret) 1617 DRM_ERROR("failed to create device file for power method\n"); 1618 #endif 1619 rdev->pm.sysfs_initialized = true; 1620 } 1621 1622 mutex_lock(&rdev->pm.mutex); 1623 ret = radeon_dpm_late_enable(rdev); 1624 mutex_unlock(&rdev->pm.mutex); 1625 if (ret) { 1626 rdev->pm.dpm_enabled = false; 1627 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1628 } else { 1629 /* set the dpm state for PX since there won't be 1630 * a modeset to call this. 1631 */ 1632 radeon_pm_compute_clocks(rdev); 1633 } 1634 } 1635 } else { 1636 if ((rdev->pm.num_power_states > 1) && 1637 (!rdev->pm.sysfs_initialized)) { 1638 /* where's the best place to put these? */ 1639 #if 0 1640 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1641 if (ret) 1642 DRM_ERROR("failed to create device file for power profile\n"); 1643 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1644 if (ret) 1645 DRM_ERROR("failed to create device file for power method\n"); 1646 if (!ret) 1647 rdev->pm.sysfs_initialized = true; 1648 #endif 1649 } 1650 } 1651 return ret; 1652 } 1653 1654 static void radeon_pm_fini_old(struct radeon_device *rdev) 1655 { 1656 if (rdev->pm.num_power_states > 1) { 1657 mutex_lock(&rdev->pm.mutex); 1658 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1659 rdev->pm.profile = PM_PROFILE_DEFAULT; 1660 radeon_pm_update_profile(rdev); 1661 radeon_pm_set_clocks(rdev); 1662 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1663 /* reset default clocks */ 1664 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1665 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1666 radeon_pm_set_clocks(rdev); 1667 } 1668 mutex_unlock(&rdev->pm.mutex); 1669 1670 #ifdef DUMBBELL_WIP 1671 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1672 1673 device_remove_file(rdev->dev, &dev_attr_power_profile); 1674 device_remove_file(rdev->dev, &dev_attr_power_method); 1675 #endif /* DUMBBELL_WIP */ 1676 } 1677 1678 if (rdev->pm.power_state) { 1679 int i; 1680 for (i = 0; i < rdev->pm.num_power_states; ++i) { 1681 kfree(rdev->pm.power_state[i].clock_info); 1682 } 1683 kfree(rdev->pm.power_state); 1684 rdev->pm.power_state = NULL; 1685 rdev->pm.num_power_states = 0; 1686 } 1687 1688 radeon_hwmon_fini(rdev); 1689 } 1690 1691 static void radeon_pm_fini_dpm(struct radeon_device *rdev) 1692 { 1693 if (rdev->pm.num_power_states > 1) { 1694 mutex_lock(&rdev->pm.mutex); 1695 radeon_dpm_disable(rdev); 1696 mutex_unlock(&rdev->pm.mutex); 1697 1698 #ifdef TODO_DEVICE_FILE 1699 device_remove_file(rdev->dev, &dev_attr_power_dpm_state); 1700 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1701 /* XXX backwards compat */ 1702 device_remove_file(rdev->dev, &dev_attr_power_profile); 1703 device_remove_file(rdev->dev, &dev_attr_power_method); 1704 #endif 1705 } 1706 radeon_dpm_fini(rdev); 1707 1708 /* prevents leaking 440 bytes on OLAND */ 1709 if (rdev->pm.power_state) { 1710 int i; 1711 for (i = 0; i < rdev->pm.num_power_states; ++i) { 1712 kfree(rdev->pm.power_state[i].clock_info); 1713 } 1714 kfree(rdev->pm.power_state); 1715 rdev->pm.power_state = NULL; 1716 rdev->pm.num_power_states = 0; 1717 } 1718 1719 radeon_hwmon_fini(rdev); 1720 } 1721 1722 void radeon_pm_fini(struct radeon_device *rdev) 1723 { 1724 if (rdev->pm.pm_method == PM_METHOD_DPM) 1725 radeon_pm_fini_dpm(rdev); 1726 else 1727 radeon_pm_fini_old(rdev); 1728 } 1729 1730 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) 1731 { 1732 struct drm_device *ddev = rdev->ddev; 1733 struct drm_crtc *crtc; 1734 struct radeon_crtc *radeon_crtc; 1735 1736 if (rdev->pm.num_power_states < 2) 1737 return; 1738 1739 mutex_lock(&rdev->pm.mutex); 1740 1741 rdev->pm.active_crtcs = 0; 1742 rdev->pm.active_crtc_count = 0; 1743 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1744 list_for_each_entry(crtc, 1745 &ddev->mode_config.crtc_list, head) { 1746 radeon_crtc = to_radeon_crtc(crtc); 1747 if (radeon_crtc->enabled) { 1748 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 1749 rdev->pm.active_crtc_count++; 1750 } 1751 } 1752 } 1753 1754 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1755 radeon_pm_update_profile(rdev); 1756 radeon_pm_set_clocks(rdev); 1757 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1758 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 1759 if (rdev->pm.active_crtc_count > 1) { 1760 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1761 #ifdef DUMBBELL_WIP 1762 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1763 #endif /* DUMBBELL_WIP */ 1764 1765 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 1766 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1767 radeon_pm_get_dynpm_state(rdev); 1768 radeon_pm_set_clocks(rdev); 1769 1770 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 1771 } 1772 } else if (rdev->pm.active_crtc_count == 1) { 1773 /* TODO: Increase clocks if needed for current mode */ 1774 1775 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 1776 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1777 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 1778 radeon_pm_get_dynpm_state(rdev); 1779 radeon_pm_set_clocks(rdev); 1780 1781 #ifdef DUMBBELL_WIP 1782 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1783 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1784 #endif /* DUMBBELL_WIP */ 1785 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 1786 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1787 #ifdef DUMBBELL_WIP 1788 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1789 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1790 #endif /* DUMBBELL_WIP */ 1791 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 1792 } 1793 } else { /* count == 0 */ 1794 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 1795 #ifdef DUMBBELL_WIP 1796 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1797 #endif /* DUMBBELL_WIP */ 1798 1799 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 1800 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 1801 radeon_pm_get_dynpm_state(rdev); 1802 radeon_pm_set_clocks(rdev); 1803 } 1804 } 1805 } 1806 } 1807 1808 mutex_unlock(&rdev->pm.mutex); 1809 } 1810 1811 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) 1812 { 1813 struct drm_device *ddev = rdev->ddev; 1814 struct drm_crtc *crtc; 1815 struct radeon_crtc *radeon_crtc; 1816 1817 if (!rdev->pm.dpm_enabled) 1818 return; 1819 1820 mutex_lock(&rdev->pm.mutex); 1821 1822 /* update active crtc counts */ 1823 rdev->pm.dpm.new_active_crtcs = 0; 1824 rdev->pm.dpm.new_active_crtc_count = 0; 1825 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1826 list_for_each_entry(crtc, 1827 &ddev->mode_config.crtc_list, head) { 1828 radeon_crtc = to_radeon_crtc(crtc); 1829 if (crtc->enabled) { 1830 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); 1831 rdev->pm.dpm.new_active_crtc_count++; 1832 } 1833 } 1834 } 1835 1836 /* update battery/ac status */ 1837 if (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) 1838 rdev->pm.dpm.ac_power = true; 1839 else 1840 rdev->pm.dpm.ac_power = false; 1841 1842 radeon_dpm_change_power_state_locked(rdev); 1843 1844 mutex_unlock(&rdev->pm.mutex); 1845 1846 } 1847 1848 void radeon_pm_compute_clocks(struct radeon_device *rdev) 1849 { 1850 if (rdev->pm.pm_method == PM_METHOD_DPM) 1851 radeon_pm_compute_clocks_dpm(rdev); 1852 else 1853 radeon_pm_compute_clocks_old(rdev); 1854 } 1855 1856 static bool radeon_pm_in_vbl(struct radeon_device *rdev) 1857 { 1858 int crtc, vpos, hpos, vbl_status; 1859 bool in_vbl = true; 1860 1861 /* Iterate over all active crtc's. All crtc's must be in vblank, 1862 * otherwise return in_vbl == false. 1863 */ 1864 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 1865 if (rdev->pm.active_crtcs & (1 << crtc)) { 1866 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, 1867 crtc, 1868 USE_REAL_VBLANKSTART, 1869 &vpos, &hpos, NULL, NULL, 1870 &rdev->mode_info.crtcs[crtc]->base.hwmode); 1871 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 1872 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK)) 1873 in_vbl = false; 1874 } 1875 } 1876 1877 return in_vbl; 1878 } 1879 1880 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 1881 { 1882 u32 stat_crtc = 0; 1883 bool in_vbl = radeon_pm_in_vbl(rdev); 1884 1885 if (in_vbl == false) 1886 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 1887 finish ? "exit" : "entry"); 1888 return in_vbl; 1889 } 1890 1891 static void radeon_dynpm_idle_work_handler(struct work_struct *work) 1892 { 1893 struct radeon_device *rdev; 1894 int resched; 1895 rdev = container_of(work, struct radeon_device, 1896 pm.dynpm_idle_work.work); 1897 1898 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1899 mutex_lock(&rdev->pm.mutex); 1900 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1901 int not_processed = 0; 1902 int i; 1903 1904 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1905 struct radeon_ring *ring = &rdev->ring[i]; 1906 1907 if (ring->ready) { 1908 not_processed += radeon_fence_count_emitted(rdev, i); 1909 if (not_processed >= 3) 1910 break; 1911 } 1912 } 1913 1914 if (not_processed >= 3) { /* should upclock */ 1915 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 1916 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1917 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1918 rdev->pm.dynpm_can_upclock) { 1919 rdev->pm.dynpm_planned_action = 1920 DYNPM_ACTION_UPCLOCK; 1921 rdev->pm.dynpm_action_timeout = jiffies + 1922 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1923 } 1924 } else if (not_processed == 0) { /* should downclock */ 1925 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 1926 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1927 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1928 rdev->pm.dynpm_can_downclock) { 1929 rdev->pm.dynpm_planned_action = 1930 DYNPM_ACTION_DOWNCLOCK; 1931 rdev->pm.dynpm_action_timeout = jiffies + 1932 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1933 } 1934 } 1935 1936 /* Note, radeon_pm_set_clocks is called with static_switch set 1937 * to false since we want to wait for vbl to avoid flicker. 1938 */ 1939 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 1940 jiffies > rdev->pm.dynpm_action_timeout) { 1941 radeon_pm_get_dynpm_state(rdev); 1942 radeon_pm_set_clocks(rdev); 1943 } 1944 1945 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1946 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1947 } 1948 mutex_unlock(&rdev->pm.mutex); 1949 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1950 } 1951 1952 /* 1953 * Debugfs info 1954 */ 1955 #if defined(CONFIG_DEBUG_FS) 1956 1957 static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 1958 { 1959 struct drm_info_node *node = (struct drm_info_node *) m->private; 1960 struct drm_device *dev = node->minor->dev; 1961 struct radeon_device *rdev = dev->dev_private; 1962 struct drm_device *ddev = rdev->ddev; 1963 1964 if ((rdev->flags & RADEON_IS_PX) && 1965 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 1966 seq_printf(m, "PX asic powered off\n"); 1967 } else if (rdev->pm.dpm_enabled) { 1968 mutex_lock(&rdev->pm.mutex); 1969 if (rdev->asic->dpm.debugfs_print_current_performance_level) 1970 radeon_dpm_debugfs_print_current_performance_level(rdev, m); 1971 else 1972 seq_printf(m, "Debugfs support not implemented for this asic\n"); 1973 mutex_unlock(&rdev->pm.mutex); 1974 } else { 1975 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 1976 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ 1977 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) 1978 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); 1979 else 1980 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 1981 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 1982 if (rdev->asic->pm.get_memory_clock) 1983 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 1984 if (rdev->pm.current_vddc) 1985 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 1986 if (rdev->asic->pm.get_pcie_lanes) 1987 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 1988 } 1989 1990 return 0; 1991 } 1992 1993 static struct drm_info_list radeon_pm_info_list[] = { 1994 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, 1995 }; 1996 #endif 1997 1998 static int radeon_debugfs_pm_init(struct radeon_device *rdev) 1999 { 2000 #if defined(CONFIG_DEBUG_FS) 2001 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); 2002 #else 2003 return 0; 2004 #endif 2005 } 2006