1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 * 32 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_ttm.c 254885 2013-08-25 19:37:15Z dumbbell $ 33 */ 34 35 #include <drm/ttm/ttm_bo_api.h> 36 #include <drm/ttm/ttm_bo_driver.h> 37 #include <drm/ttm/ttm_placement.h> 38 #include <drm/ttm/ttm_module.h> 39 #include <drm/ttm/ttm_page_alloc.h> 40 #include <drm/drmP.h> 41 #include <drm/radeon_drm.h> 42 #include <linux/seq_file.h> 43 #include <linux/slab.h> 44 #include "radeon_reg.h" 45 #include "radeon.h" 46 47 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 48 49 static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 50 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); 51 52 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 53 { 54 struct radeon_mman *mman; 55 struct radeon_device *rdev; 56 57 mman = container_of(bdev, struct radeon_mman, bdev); 58 rdev = container_of(mman, struct radeon_device, mman); 59 return rdev; 60 } 61 62 63 /* 64 * Global memory. 65 */ 66 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) 67 { 68 return ttm_mem_global_init(ref->object); 69 } 70 71 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) 72 { 73 ttm_mem_global_release(ref->object); 74 } 75 76 static int radeon_ttm_global_init(struct radeon_device *rdev) 77 { 78 struct drm_global_reference *global_ref; 79 int r; 80 81 rdev->mman.mem_global_referenced = false; 82 global_ref = &rdev->mman.mem_global_ref; 83 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 84 global_ref->size = sizeof(struct ttm_mem_global); 85 global_ref->init = &radeon_ttm_mem_global_init; 86 global_ref->release = &radeon_ttm_mem_global_release; 87 r = drm_global_item_ref(global_ref); 88 if (r != 0) { 89 DRM_ERROR("Failed setting up TTM memory accounting " 90 "subsystem.\n"); 91 return r; 92 } 93 94 rdev->mman.bo_global_ref.mem_glob = 95 rdev->mman.mem_global_ref.object; 96 global_ref = &rdev->mman.bo_global_ref.ref; 97 global_ref->global_type = DRM_GLOBAL_TTM_BO; 98 global_ref->size = sizeof(struct ttm_bo_global); 99 global_ref->init = &ttm_bo_global_init; 100 global_ref->release = &ttm_bo_global_release; 101 r = drm_global_item_ref(global_ref); 102 if (r != 0) { 103 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 104 drm_global_item_unref(&rdev->mman.mem_global_ref); 105 return r; 106 } 107 108 rdev->mman.mem_global_referenced = true; 109 return 0; 110 } 111 112 static void radeon_ttm_global_fini(struct radeon_device *rdev) 113 { 114 if (rdev->mman.mem_global_referenced) { 115 drm_global_item_unref(&rdev->mman.bo_global_ref.ref); 116 drm_global_item_unref(&rdev->mman.mem_global_ref); 117 rdev->mman.mem_global_referenced = false; 118 } 119 } 120 121 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 122 { 123 return 0; 124 } 125 126 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 127 struct ttm_mem_type_manager *man) 128 { 129 struct radeon_device *rdev; 130 131 rdev = radeon_get_rdev(bdev); 132 133 switch (type) { 134 case TTM_PL_SYSTEM: 135 /* System memory */ 136 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 137 man->available_caching = TTM_PL_MASK_CACHING; 138 man->default_caching = TTM_PL_FLAG_CACHED; 139 break; 140 case TTM_PL_TT: 141 man->func = &ttm_bo_manager_func; 142 man->gpu_offset = rdev->mc.gtt_start; 143 man->available_caching = TTM_PL_MASK_CACHING; 144 man->default_caching = TTM_PL_FLAG_CACHED; 145 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 146 #if __OS_HAS_AGP 147 if (rdev->flags & RADEON_IS_AGP) { 148 if (!rdev->ddev->agp) { 149 DRM_ERROR("AGP is not enabled for memory type %u\n", 150 (unsigned)type); 151 return -EINVAL; 152 } 153 if (!rdev->ddev->agp->cant_use_aperture) 154 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 155 man->available_caching = TTM_PL_FLAG_UNCACHED | 156 TTM_PL_FLAG_WC; 157 man->default_caching = TTM_PL_FLAG_WC; 158 } 159 #endif 160 break; 161 case TTM_PL_VRAM: 162 /* "On-card" video ram */ 163 man->func = &ttm_bo_manager_func; 164 man->gpu_offset = rdev->mc.vram_start; 165 man->flags = TTM_MEMTYPE_FLAG_FIXED | 166 TTM_MEMTYPE_FLAG_MAPPABLE; 167 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 168 man->default_caching = TTM_PL_FLAG_WC; 169 break; 170 default: 171 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 172 return -EINVAL; 173 } 174 return 0; 175 } 176 177 static void radeon_evict_flags(struct ttm_buffer_object *bo, 178 struct ttm_placement *placement) 179 { 180 static struct ttm_place placements = { 181 .fpfn = 0, 182 .lpfn = 0, 183 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 184 }; 185 186 struct radeon_bo *rbo; 187 188 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 189 placement->placement = &placements; 190 placement->busy_placement = &placements; 191 placement->num_placement = 1; 192 placement->num_busy_placement = 1; 193 return; 194 } 195 rbo = container_of(bo, struct radeon_bo, tbo); 196 switch (bo->mem.mem_type) { 197 case TTM_PL_VRAM: 198 if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) 199 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 200 else 201 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 202 break; 203 case TTM_PL_TT: 204 default: 205 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 206 } 207 *placement = rbo->placement; 208 } 209 210 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *fp) 211 { 212 #if 0 213 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 214 #endif 215 216 return 0; 217 218 #if 0 219 /* XXX needs radeon_gem_userptr_ioctl() and related infrastructure */ 220 if (radeon_ttm_tt_has_userptr(bo->ttm)) 221 return -EPERM; 222 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, 223 fp->private_data); 224 #endif 225 } 226 227 static void radeon_move_null(struct ttm_buffer_object *bo, 228 struct ttm_mem_reg *new_mem) 229 { 230 struct ttm_mem_reg *old_mem = &bo->mem; 231 232 BUG_ON(old_mem->mm_node != NULL); 233 *old_mem = *new_mem; 234 new_mem->mm_node = NULL; 235 } 236 237 static int radeon_move_blit(struct ttm_buffer_object *bo, 238 bool evict, bool no_wait_gpu, 239 struct ttm_mem_reg *new_mem, 240 struct ttm_mem_reg *old_mem) 241 { 242 struct radeon_device *rdev; 243 uint64_t old_start, new_start; 244 struct radeon_fence *fence; 245 int r, ridx; 246 247 rdev = radeon_get_rdev(bo->bdev); 248 ridx = radeon_copy_ring_index(rdev); 249 old_start = old_mem->start << PAGE_SHIFT; 250 new_start = new_mem->start << PAGE_SHIFT; 251 252 switch (old_mem->mem_type) { 253 case TTM_PL_VRAM: 254 old_start += rdev->mc.vram_start; 255 break; 256 case TTM_PL_TT: 257 old_start += rdev->mc.gtt_start; 258 break; 259 default: 260 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 261 return -EINVAL; 262 } 263 switch (new_mem->mem_type) { 264 case TTM_PL_VRAM: 265 new_start += rdev->mc.vram_start; 266 break; 267 case TTM_PL_TT: 268 new_start += rdev->mc.gtt_start; 269 break; 270 default: 271 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 272 return -EINVAL; 273 } 274 if (!rdev->ring[ridx].ready) { 275 DRM_ERROR("Trying to move memory with ring turned off.\n"); 276 return -EINVAL; 277 } 278 279 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 280 281 /* sync other rings */ 282 fence = bo->sync_obj; 283 r = radeon_copy(rdev, old_start, new_start, 284 new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ 285 &fence); 286 /* FIXME: handle copy error */ 287 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, 288 evict, no_wait_gpu, new_mem); 289 radeon_fence_unref(&fence); 290 return r; 291 } 292 293 static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 294 bool evict, bool interruptible, 295 bool no_wait_gpu, 296 struct ttm_mem_reg *new_mem) 297 { 298 struct radeon_device *rdev; 299 struct ttm_mem_reg *old_mem = &bo->mem; 300 struct ttm_mem_reg tmp_mem; 301 struct ttm_place placements; 302 struct ttm_placement placement; 303 int r; 304 305 rdev = radeon_get_rdev(bo->bdev); 306 tmp_mem = *new_mem; 307 tmp_mem.mm_node = NULL; 308 placement.num_placement = 1; 309 placement.placement = &placements; 310 placement.num_busy_placement = 1; 311 placement.busy_placement = &placements; 312 placements.fpfn = 0; 313 placements.lpfn = 0; 314 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 315 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 316 interruptible, no_wait_gpu); 317 if (unlikely(r)) { 318 return r; 319 } 320 321 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 322 if (unlikely(r)) { 323 goto out_cleanup; 324 } 325 326 r = ttm_tt_bind(bo->ttm, &tmp_mem); 327 if (unlikely(r)) { 328 goto out_cleanup; 329 } 330 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 331 if (unlikely(r)) { 332 goto out_cleanup; 333 } 334 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); 335 out_cleanup: 336 ttm_bo_mem_put(bo, &tmp_mem); 337 return r; 338 } 339 340 static int radeon_move_ram_vram(struct ttm_buffer_object *bo, 341 bool evict, bool interruptible, 342 bool no_wait_gpu, 343 struct ttm_mem_reg *new_mem) 344 { 345 struct radeon_device *rdev; 346 struct ttm_mem_reg *old_mem = &bo->mem; 347 struct ttm_mem_reg tmp_mem; 348 struct ttm_placement placement; 349 struct ttm_place placements; 350 int r; 351 352 rdev = radeon_get_rdev(bo->bdev); 353 tmp_mem = *new_mem; 354 tmp_mem.mm_node = NULL; 355 placement.num_placement = 1; 356 placement.placement = &placements; 357 placement.num_busy_placement = 1; 358 placement.busy_placement = &placements; 359 placements.fpfn = 0; 360 placements.lpfn = 0; 361 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 362 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 363 interruptible, no_wait_gpu); 364 if (unlikely(r)) { 365 return r; 366 } 367 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); 368 if (unlikely(r)) { 369 goto out_cleanup; 370 } 371 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 372 if (unlikely(r)) { 373 goto out_cleanup; 374 } 375 out_cleanup: 376 ttm_bo_mem_put(bo, &tmp_mem); 377 return r; 378 } 379 380 static int radeon_bo_move(struct ttm_buffer_object *bo, 381 bool evict, bool interruptible, 382 bool no_wait_gpu, 383 struct ttm_mem_reg *new_mem) 384 { 385 struct radeon_device *rdev; 386 struct ttm_mem_reg *old_mem = &bo->mem; 387 int r; 388 389 rdev = radeon_get_rdev(bo->bdev); 390 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 391 radeon_move_null(bo, new_mem); 392 return 0; 393 } 394 if ((old_mem->mem_type == TTM_PL_TT && 395 new_mem->mem_type == TTM_PL_SYSTEM) || 396 (old_mem->mem_type == TTM_PL_SYSTEM && 397 new_mem->mem_type == TTM_PL_TT)) { 398 /* bind is enough */ 399 radeon_move_null(bo, new_mem); 400 return 0; 401 } 402 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || 403 rdev->asic->copy.copy == NULL) { 404 /* use memcpy */ 405 goto memcpy; 406 } 407 408 if (old_mem->mem_type == TTM_PL_VRAM && 409 new_mem->mem_type == TTM_PL_SYSTEM) { 410 r = radeon_move_vram_ram(bo, evict, interruptible, 411 no_wait_gpu, new_mem); 412 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 413 new_mem->mem_type == TTM_PL_VRAM) { 414 r = radeon_move_ram_vram(bo, evict, interruptible, 415 no_wait_gpu, new_mem); 416 } else { 417 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 418 } 419 420 if (r) { 421 memcpy: 422 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); 423 if (r) { 424 return r; 425 } 426 } 427 428 /* update statistics */ 429 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); 430 return 0; 431 } 432 433 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 434 { 435 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 436 struct radeon_device *rdev = radeon_get_rdev(bdev); 437 438 mem->bus.addr = NULL; 439 mem->bus.offset = 0; 440 mem->bus.size = mem->num_pages << PAGE_SHIFT; 441 mem->bus.base = 0; 442 mem->bus.is_iomem = false; 443 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 444 return -EINVAL; 445 switch (mem->mem_type) { 446 case TTM_PL_SYSTEM: 447 /* system memory */ 448 return 0; 449 case TTM_PL_TT: 450 #if __OS_HAS_AGP 451 if (rdev->flags & RADEON_IS_AGP) { 452 /* RADEON_IS_AGP is set only if AGP is active */ 453 mem->bus.offset = mem->start << PAGE_SHIFT; 454 mem->bus.base = rdev->mc.agp_base; 455 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; 456 } 457 #endif 458 break; 459 case TTM_PL_VRAM: 460 mem->bus.offset = mem->start << PAGE_SHIFT; 461 /* check if it's visible */ 462 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) 463 return -EINVAL; 464 mem->bus.base = rdev->mc.aper_base; 465 mem->bus.is_iomem = true; 466 #ifdef __alpha__ 467 /* 468 * Alpha: use bus.addr to hold the ioremap() return, 469 * so we can modify bus.base below. 470 */ 471 if (mem->placement & TTM_PL_FLAG_WC) 472 mem->bus.addr = 473 ioremap_wc(mem->bus.base + mem->bus.offset, 474 mem->bus.size); 475 else 476 mem->bus.addr = 477 ioremap_nocache(mem->bus.base + mem->bus.offset, 478 mem->bus.size); 479 480 /* 481 * Alpha: Use just the bus offset plus 482 * the hose/domain memory base for bus.base. 483 * It then can be used to build PTEs for VRAM 484 * access, as done in ttm_bo_vm_fault(). 485 */ 486 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 487 rdev->ddev->hose->dense_mem_base; 488 #endif 489 break; 490 default: 491 return -EINVAL; 492 } 493 return 0; 494 } 495 496 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 497 { 498 } 499 500 static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible) 501 { 502 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); 503 } 504 505 static int radeon_sync_obj_flush(void *sync_obj) 506 { 507 return 0; 508 } 509 510 static void radeon_sync_obj_unref(void **sync_obj) 511 { 512 radeon_fence_unref((struct radeon_fence **)sync_obj); 513 } 514 515 static void *radeon_sync_obj_ref(void *sync_obj) 516 { 517 return radeon_fence_ref((struct radeon_fence *)sync_obj); 518 } 519 520 static bool radeon_sync_obj_signaled(void *sync_obj) 521 { 522 return radeon_fence_signaled((struct radeon_fence *)sync_obj); 523 } 524 525 /* 526 * TTM backend functions. 527 */ 528 struct radeon_ttm_tt { 529 struct ttm_dma_tt ttm; 530 struct radeon_device *rdev; 531 u64 offset; 532 }; 533 534 static int radeon_ttm_backend_bind(struct ttm_tt *ttm, 535 struct ttm_mem_reg *bo_mem) 536 { 537 struct radeon_ttm_tt *gtt = (void*)ttm; 538 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | 539 RADEON_GART_PAGE_WRITE; 540 int r; 541 542 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 543 if (!ttm->num_pages) { 544 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 545 ttm->num_pages, bo_mem, ttm); 546 } 547 if (ttm->caching_state == tt_cached) 548 flags |= RADEON_GART_PAGE_SNOOP; 549 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, 550 ttm->pages, gtt->ttm.dma_address, flags); 551 if (r) { 552 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 553 ttm->num_pages, (unsigned)gtt->offset); 554 return r; 555 } 556 return 0; 557 } 558 559 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) 560 { 561 struct radeon_ttm_tt *gtt = (void *)ttm; 562 563 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); 564 return 0; 565 } 566 567 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) 568 { 569 struct radeon_ttm_tt *gtt = (void *)ttm; 570 571 ttm_dma_tt_fini(>t->ttm); 572 kfree(gtt); 573 } 574 575 static struct ttm_backend_func radeon_backend_func = { 576 .bind = &radeon_ttm_backend_bind, 577 .unbind = &radeon_ttm_backend_unbind, 578 .destroy = &radeon_ttm_backend_destroy, 579 }; 580 581 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, 582 unsigned long size, uint32_t page_flags, 583 struct page *dummy_read_page) 584 { 585 struct radeon_device *rdev; 586 struct radeon_ttm_tt *gtt; 587 588 rdev = radeon_get_rdev(bdev); 589 #if __OS_HAS_AGP 590 #ifdef DUMBBELL_WIP 591 if (rdev->flags & RADEON_IS_AGP) { 592 return ttm_agp_tt_create(bdev, rdev->ddev->agp->agpdev, 593 size, page_flags, dummy_read_page); 594 } 595 #endif /* DUMBBELL_WIP */ 596 #endif 597 598 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 599 if (gtt == NULL) { 600 return NULL; 601 } 602 gtt->ttm.ttm.func = &radeon_backend_func; 603 gtt->rdev = rdev; 604 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 605 kfree(gtt); 606 return NULL; 607 } 608 return >t->ttm.ttm; 609 } 610 611 static int radeon_ttm_tt_populate(struct ttm_tt *ttm) 612 { 613 struct radeon_device *rdev; 614 struct radeon_ttm_tt *gtt = (void *)ttm; 615 unsigned i; 616 int r; 617 #ifdef DUMBBELL_WIP 618 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 619 #endif /* DUMBBELL_WIP */ 620 621 if (ttm->state != tt_unpopulated) 622 return 0; 623 624 #ifdef DUMBBELL_WIP 625 /* 626 * Maybe unneeded on FreeBSD. 627 * -- dumbbell@ 628 */ 629 if (slave && ttm->sg) { 630 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 631 gtt->ttm.dma_address, ttm->num_pages); 632 ttm->state = tt_unbound; 633 return 0; 634 } 635 #endif /* DUMBBELL_WIP */ 636 637 rdev = radeon_get_rdev(ttm->bdev); 638 #if __OS_HAS_AGP 639 #ifdef DUMBBELL_WIP 640 if (rdev->flags & RADEON_IS_AGP) { 641 return ttm_agp_tt_populate(ttm); 642 } 643 #endif /* DUMBBELL_WIP */ 644 #endif 645 646 #ifdef CONFIG_SWIOTLB 647 if (swiotlb_nr_tbl()) { 648 return ttm_dma_populate(>t->ttm, rdev->dev); 649 } 650 #endif 651 652 r = ttm_pool_populate(ttm); 653 if (r) { 654 return r; 655 } 656 657 for (i = 0; i < ttm->num_pages; i++) { 658 gtt->ttm.dma_address[i] = VM_PAGE_TO_PHYS((struct vm_page *)ttm->pages[i]); 659 #ifdef DUMBBELL_WIP 660 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], 661 0, PAGE_SIZE, 662 PCI_DMA_BIDIRECTIONAL); 663 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { 664 while (--i) { 665 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 666 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 667 gtt->ttm.dma_address[i] = 0; 668 } 669 ttm_pool_unpopulate(ttm); 670 return -EFAULT; 671 } 672 #endif /* DUMBBELL_WIP */ 673 } 674 return 0; 675 } 676 677 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) 678 { 679 struct radeon_device *rdev; 680 struct radeon_ttm_tt *gtt = (void *)ttm; 681 unsigned i; 682 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 683 684 if (slave) 685 return; 686 687 rdev = radeon_get_rdev(ttm->bdev); 688 #if __OS_HAS_AGP 689 #ifdef DUMBBELL_WIP 690 if (rdev->flags & RADEON_IS_AGP) { 691 ttm_agp_tt_unpopulate(ttm); 692 return; 693 } 694 #endif /* DUMBBELL_WIP */ 695 #endif 696 697 #ifdef CONFIG_SWIOTLB 698 if (swiotlb_nr_tbl()) { 699 ttm_dma_unpopulate(>t->ttm, rdev->dev); 700 return; 701 } 702 #endif 703 704 for (i = 0; i < ttm->num_pages; i++) { 705 if (gtt->ttm.dma_address[i]) { 706 gtt->ttm.dma_address[i] = 0; 707 #ifdef DUMBBELL_WIP 708 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 709 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 710 #endif /* DUMBBELL_WIP */ 711 } 712 } 713 714 ttm_pool_unpopulate(ttm); 715 } 716 717 static struct ttm_bo_driver radeon_bo_driver = { 718 .ttm_tt_create = &radeon_ttm_tt_create, 719 .ttm_tt_populate = &radeon_ttm_tt_populate, 720 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 721 .invalidate_caches = &radeon_invalidate_caches, 722 .init_mem_type = &radeon_init_mem_type, 723 .evict_flags = &radeon_evict_flags, 724 .move = &radeon_bo_move, 725 .verify_access = &radeon_verify_access, 726 .sync_obj_signaled = &radeon_sync_obj_signaled, 727 .sync_obj_wait = &radeon_sync_obj_wait, 728 .sync_obj_flush = &radeon_sync_obj_flush, 729 .sync_obj_unref = &radeon_sync_obj_unref, 730 .sync_obj_ref = &radeon_sync_obj_ref, 731 .move_notify = &radeon_bo_move_notify, 732 .fault_reserve_notify = &radeon_bo_fault_reserve_notify, 733 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 734 .io_mem_free = &radeon_ttm_io_mem_free, 735 }; 736 737 int radeon_ttm_init(struct radeon_device *rdev) 738 { 739 int r, r2; 740 741 r = radeon_ttm_global_init(rdev); 742 if (r) { 743 return r; 744 } 745 /* No others user of address space so set it to 0 */ 746 r = ttm_bo_device_init(&rdev->mman.bdev, 747 rdev->mman.bo_global_ref.ref.object, 748 &radeon_bo_driver, 749 #ifdef __DragonFly__ 750 NULL, 751 #else 752 rdev->ddev->anon_inode->i_mapping, 753 #endif 754 DRM_FILE_PAGE_OFFSET, 755 rdev->need_dma32); 756 if (r) { 757 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 758 return r; 759 } 760 rdev->mman.initialized = true; 761 rdev->ddev->drm_ttm_bdev = &rdev->mman.bdev; 762 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 763 rdev->mc.real_vram_size >> PAGE_SHIFT); 764 if (r) { 765 DRM_ERROR("Failed initializing VRAM heap.\n"); 766 return r; 767 } 768 /* Change the size here instead of the init above so only lpfn is affected */ 769 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 770 771 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 772 RADEON_GEM_DOMAIN_VRAM, 0, 773 NULL, &rdev->stollen_vga_memory); 774 if (r) { 775 return r; 776 } 777 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 778 if (r) { 779 radeon_bo_unref(&rdev->stollen_vga_memory); 780 return r; 781 } 782 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 783 radeon_bo_unreserve(rdev->stollen_vga_memory); 784 if (r) { 785 radeon_bo_unref(&rdev->stollen_vga_memory); 786 return r; 787 } 788 DRM_INFO("radeon: %uM of VRAM memory ready\n", 789 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 790 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 791 rdev->mc.gtt_size >> PAGE_SHIFT); 792 if (r) { 793 DRM_ERROR("Failed initializing GTT heap.\n"); 794 r2 = radeon_bo_reserve(rdev->stollen_vga_memory, false); 795 if (likely(r2 == 0)) { 796 radeon_bo_unpin(rdev->stollen_vga_memory); 797 radeon_bo_unreserve(rdev->stollen_vga_memory); 798 } 799 radeon_bo_unref(&rdev->stollen_vga_memory); 800 return r; 801 } 802 DRM_INFO("radeon: %uM of GTT memory ready.\n", 803 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 804 805 r = radeon_ttm_debugfs_init(rdev); 806 if (r) { 807 DRM_ERROR("Failed to init debugfs\n"); 808 r2 = radeon_bo_reserve(rdev->stollen_vga_memory, false); 809 if (likely(r2 == 0)) { 810 radeon_bo_unpin(rdev->stollen_vga_memory); 811 radeon_bo_unreserve(rdev->stollen_vga_memory); 812 } 813 radeon_bo_unref(&rdev->stollen_vga_memory); 814 return r; 815 } 816 return 0; 817 } 818 819 void radeon_ttm_fini(struct radeon_device *rdev) 820 { 821 int r; 822 823 if (!rdev->mman.initialized) 824 return; 825 radeon_ttm_debugfs_fini(rdev); 826 if (rdev->stollen_vga_memory) { 827 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 828 if (r == 0) { 829 radeon_bo_unpin(rdev->stollen_vga_memory); 830 radeon_bo_unreserve(rdev->stollen_vga_memory); 831 } 832 radeon_bo_unref(&rdev->stollen_vga_memory); 833 } 834 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); 835 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); 836 ttm_bo_device_release(&rdev->mman.bdev); 837 radeon_gart_fini(rdev); 838 radeon_ttm_global_fini(rdev); 839 rdev->mman.initialized = false; 840 DRM_INFO("radeon: ttm finalized\n"); 841 } 842 843 /* this should only be called at bootup or when userspace 844 * isn't running */ 845 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 846 { 847 struct ttm_mem_type_manager *man; 848 849 if (!rdev->mman.initialized) 850 return; 851 852 man = &rdev->mman.bdev.man[TTM_PL_VRAM]; 853 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 854 man->size = size >> PAGE_SHIFT; 855 } 856 857 #ifdef DUMBBELL_WIP 858 static struct vm_operations_struct radeon_ttm_vm_ops; 859 static const struct vm_operations_struct *ttm_vm_ops = NULL; 860 861 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) 862 { 863 struct ttm_buffer_object *bo; 864 struct radeon_device *rdev; 865 int r; 866 867 bo = (struct ttm_buffer_object *)vma->vm_private_data; 868 if (bo == NULL) { 869 return VM_FAULT_NOPAGE; 870 } 871 rdev = radeon_get_rdev(bo->bdev); 872 lockmgr(&rdev->pm.mclk_lock, LK_SHARED); 873 r = ttm_vm_ops->fault(vma, vmf); 874 lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); 875 return r; 876 } 877 878 int radeon_mmap(struct file *filp, struct vm_area_struct *vma) 879 { 880 struct drm_file *file_priv; 881 struct radeon_device *rdev; 882 int r; 883 884 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { 885 return -EINVAL; 886 } 887 888 file_priv = filp->private_data; 889 rdev = file_priv->minor->dev->dev_private; 890 if (rdev == NULL) { 891 return -EINVAL; 892 } 893 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); 894 if (unlikely(r != 0)) { 895 return r; 896 } 897 if (unlikely(ttm_vm_ops == NULL)) { 898 ttm_vm_ops = vma->vm_ops; 899 radeon_ttm_vm_ops = *ttm_vm_ops; 900 radeon_ttm_vm_ops.fault = &radeon_ttm_fault; 901 } 902 vma->vm_ops = &radeon_ttm_vm_ops; 903 return 0; 904 } 905 #endif /* DUMBBELL_WIP */ 906 907 #if defined(CONFIG_DEBUG_FS) 908 909 static int radeon_mm_dump_table(struct seq_file *m, void *data) 910 { 911 struct drm_info_node *node = (struct drm_info_node *)m->private; 912 unsigned ttm_pl = *(int *)node->info_ent->data; 913 struct drm_device *dev = node->minor->dev; 914 struct radeon_device *rdev = dev->dev_private; 915 struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv; 916 int ret; 917 struct ttm_bo_global *glob = rdev->mman.bdev.glob; 918 919 spin_lock(&glob->lru_lock); 920 ret = drm_mm_dump_table(m, mm); 921 spin_unlock(&glob->lru_lock); 922 return ret; 923 } 924 925 static int ttm_pl_vram = TTM_PL_VRAM; 926 static int ttm_pl_tt = TTM_PL_TT; 927 928 static struct drm_info_list radeon_ttm_debugfs_list[] = { 929 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, 930 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, 931 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 932 #ifdef CONFIG_SWIOTLB 933 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 934 #endif 935 }; 936 937 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) 938 { 939 struct radeon_device *rdev = inode->i_private; 940 i_size_write(inode, rdev->mc.mc_vram_size); 941 filep->private_data = inode->i_private; 942 return 0; 943 } 944 945 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, 946 size_t size, loff_t *pos) 947 { 948 struct radeon_device *rdev = f->private_data; 949 ssize_t result = 0; 950 int r; 951 952 if (size & 0x3 || *pos & 0x3) 953 return -EINVAL; 954 955 while (size) { 956 unsigned long flags; 957 uint32_t value; 958 959 if (*pos >= rdev->mc.mc_vram_size) 960 return result; 961 962 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 963 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); 964 if (rdev->family >= CHIP_CEDAR) 965 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); 966 value = RREG32(RADEON_MM_DATA); 967 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 968 969 r = put_user(value, (uint32_t *)buf); 970 if (r) 971 return r; 972 973 result += 4; 974 buf += 4; 975 *pos += 4; 976 size -= 4; 977 } 978 979 return result; 980 } 981 982 static const struct file_operations radeon_ttm_vram_fops = { 983 .owner = THIS_MODULE, 984 .open = radeon_ttm_vram_open, 985 .read = radeon_ttm_vram_read, 986 .llseek = default_llseek 987 }; 988 989 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) 990 { 991 struct radeon_device *rdev = inode->i_private; 992 i_size_write(inode, rdev->mc.gtt_size); 993 filep->private_data = inode->i_private; 994 return 0; 995 } 996 997 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, 998 size_t size, loff_t *pos) 999 { 1000 struct radeon_device *rdev = f->private_data; 1001 ssize_t result = 0; 1002 int r; 1003 1004 while (size) { 1005 loff_t p = *pos / PAGE_SIZE; 1006 unsigned off = *pos & ~LINUX_PAGE_MASK; 1007 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 1008 struct page *page; 1009 void *ptr; 1010 1011 if (p >= rdev->gart.num_cpu_pages) 1012 return result; 1013 1014 page = rdev->gart.pages[p]; 1015 if (page) { 1016 ptr = kmap(page); 1017 ptr += off; 1018 1019 r = copy_to_user(buf, ptr, cur_size); 1020 kunmap(rdev->gart.pages[p]); 1021 } else 1022 r = clear_user(buf, cur_size); 1023 1024 if (r) 1025 return -EFAULT; 1026 1027 result += cur_size; 1028 buf += cur_size; 1029 *pos += cur_size; 1030 size -= cur_size; 1031 } 1032 1033 return result; 1034 } 1035 1036 static const struct file_operations radeon_ttm_gtt_fops = { 1037 .owner = THIS_MODULE, 1038 .open = radeon_ttm_gtt_open, 1039 .read = radeon_ttm_gtt_read, 1040 .llseek = default_llseek 1041 }; 1042 1043 #endif 1044 1045 static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 1046 { 1047 #if defined(CONFIG_DEBUG_FS) 1048 unsigned count; 1049 1050 struct drm_minor *minor = rdev->ddev->primary; 1051 struct dentry *ent, *root = minor->debugfs_root; 1052 1053 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root, 1054 rdev, &radeon_ttm_vram_fops); 1055 if (IS_ERR(ent)) 1056 return PTR_ERR(ent); 1057 rdev->mman.vram = ent; 1058 1059 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root, 1060 rdev, &radeon_ttm_gtt_fops); 1061 if (IS_ERR(ent)) 1062 return PTR_ERR(ent); 1063 rdev->mman.gtt = ent; 1064 1065 count = ARRAY_SIZE(radeon_ttm_debugfs_list); 1066 1067 #ifdef CONFIG_SWIOTLB 1068 if (!swiotlb_nr_tbl()) 1069 --count; 1070 #endif 1071 1072 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); 1073 #else 1074 1075 return 0; 1076 #endif 1077 } 1078 1079 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) 1080 { 1081 #if defined(CONFIG_DEBUG_FS) 1082 1083 debugfs_remove(rdev->mman.vram); 1084 rdev->mman.vram = NULL; 1085 1086 debugfs_remove(rdev->mman.gtt); 1087 rdev->mman.gtt = NULL; 1088 #endif 1089 } 1090