1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 /* RS600 / Radeon X1250/X1270 integrated GPU 29 * 30 * This file gather function specific to RS600 which is the IGP of 31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740 32 * is the X1250/X1270 supporting AMD CPU). The display engine are 33 * the avivo one, bios is an atombios, 3D block are the one of the 34 * R4XX family. The GART is different from the RS400 one and is very 35 * close to the one of the R600 family (R600 likely being an evolution 36 * of the RS600 GART block). 37 */ 38 #include <drm/drmP.h> 39 #include "radeon.h" 40 #include "radeon_asic.h" 41 #include "radeon_audio.h" 42 #include "atom.h" 43 #include "rs600d.h" 44 45 #include "rs600_reg_safe.h" 46 47 static void rs600_gpu_init(struct radeon_device *rdev); 48 49 static const u32 crtc_offsets[2] = 50 { 51 0, 52 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 53 }; 54 55 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) 56 { 57 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) 58 return true; 59 else 60 return false; 61 } 62 63 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) 64 { 65 u32 pos1, pos2; 66 67 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 68 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 69 70 if (pos1 != pos2) 71 return true; 72 else 73 return false; 74 } 75 76 /** 77 * avivo_wait_for_vblank - vblank wait asic callback. 78 * 79 * @rdev: radeon_device pointer 80 * @crtc: crtc to wait for vblank on 81 * 82 * Wait for vblank on the requested crtc (r5xx-r7xx). 83 */ 84 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) 85 { 86 unsigned i = 0; 87 88 if (crtc >= rdev->num_crtc) 89 return; 90 91 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) 92 return; 93 94 /* depending on when we hit vblank, we may be close to active; if so, 95 * wait for another frame. 96 */ 97 while (avivo_is_in_vblank(rdev, crtc)) { 98 if (i++ % 100 == 0) { 99 if (!avivo_is_counter_moving(rdev, crtc)) 100 break; 101 } 102 } 103 104 while (!avivo_is_in_vblank(rdev, crtc)) { 105 if (i++ % 100 == 0) { 106 if (!avivo_is_counter_moving(rdev, crtc)) 107 break; 108 } 109 } 110 } 111 112 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) 113 { 114 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 115 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 116 int i; 117 118 /* Lock the graphics update lock */ 119 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 120 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 121 122 /* update the scanout addresses */ 123 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 124 async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0); 125 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 126 (u32)crtc_base); 127 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 128 (u32)crtc_base); 129 130 /* Wait for update_pending to go high. */ 131 for (i = 0; i < rdev->usec_timeout; i++) { 132 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 133 break; 134 udelay(1); 135 } 136 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 137 138 /* Unlock the lock, so double-buffering can take place inside vblank */ 139 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 140 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 141 } 142 143 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id) 144 { 145 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 146 147 /* Return current update_pending status: */ 148 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & 149 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING); 150 } 151 152 void avivo_program_fmt(struct drm_encoder *encoder) 153 { 154 struct drm_device *dev = encoder->dev; 155 struct radeon_device *rdev = dev->dev_private; 156 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 157 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 158 int bpc = 0; 159 u32 tmp = 0; 160 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 161 162 if (connector) { 163 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 164 bpc = radeon_get_monitor_bpc(connector); 165 dither = radeon_connector->dither; 166 } 167 168 /* LVDS FMT is set up by atom */ 169 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 170 return; 171 172 if (bpc == 0) 173 return; 174 175 switch (bpc) { 176 case 6: 177 if (dither == RADEON_FMT_DITHER_ENABLE) 178 /* XXX sort out optimal dither settings */ 179 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 180 else 181 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN; 182 break; 183 case 8: 184 if (dither == RADEON_FMT_DITHER_ENABLE) 185 /* XXX sort out optimal dither settings */ 186 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN | 187 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH); 188 else 189 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN | 190 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH); 191 break; 192 case 10: 193 default: 194 /* not needed */ 195 break; 196 } 197 198 switch (radeon_encoder->encoder_id) { 199 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 200 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); 201 break; 202 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 203 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); 204 break; 205 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 206 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); 207 break; 208 case ENCODER_OBJECT_ID_INTERNAL_DDI: 209 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); 210 break; 211 default: 212 break; 213 } 214 } 215 216 void rs600_pm_misc(struct radeon_device *rdev) 217 { 218 int requested_index = rdev->pm.requested_power_state_index; 219 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 220 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 221 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; 222 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; 223 224 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 225 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 226 tmp = RREG32(voltage->gpio.reg); 227 if (voltage->active_high) 228 tmp |= voltage->gpio.mask; 229 else 230 tmp &= ~(voltage->gpio.mask); 231 WREG32(voltage->gpio.reg, tmp); 232 if (voltage->delay) 233 udelay(voltage->delay); 234 } else { 235 tmp = RREG32(voltage->gpio.reg); 236 if (voltage->active_high) 237 tmp &= ~voltage->gpio.mask; 238 else 239 tmp |= voltage->gpio.mask; 240 WREG32(voltage->gpio.reg, tmp); 241 if (voltage->delay) 242 udelay(voltage->delay); 243 } 244 } else if (voltage->type == VOLTAGE_VDDC) 245 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); 246 247 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); 248 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); 249 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); 250 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 251 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { 252 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); 253 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); 254 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { 255 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); 256 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); 257 } 258 } else { 259 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); 260 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); 261 } 262 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); 263 264 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); 265 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 266 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; 267 if (voltage->delay) { 268 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; 269 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); 270 } else 271 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; 272 } else 273 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; 274 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); 275 276 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); 277 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 278 hdp_dyn_cntl &= ~HDP_FORCEON; 279 else 280 hdp_dyn_cntl |= HDP_FORCEON; 281 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); 282 #if 0 283 /* mc_host_dyn seems to cause hangs from time to time */ 284 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); 285 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) 286 mc_host_dyn_cntl &= ~MC_HOST_FORCEON; 287 else 288 mc_host_dyn_cntl |= MC_HOST_FORCEON; 289 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); 290 #endif 291 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); 292 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) 293 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; 294 else 295 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; 296 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); 297 298 /* set pcie lanes */ 299 if ((rdev->flags & RADEON_IS_PCIE) && 300 !(rdev->flags & RADEON_IS_IGP) && 301 rdev->asic->pm.set_pcie_lanes && 302 (ps->pcie_lanes != 303 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 304 radeon_set_pcie_lanes(rdev, 305 ps->pcie_lanes); 306 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); 307 } 308 } 309 310 void rs600_pm_prepare(struct radeon_device *rdev) 311 { 312 struct drm_device *ddev = rdev->ddev; 313 struct drm_crtc *crtc; 314 struct radeon_crtc *radeon_crtc; 315 u32 tmp; 316 317 /* disable any active CRTCs */ 318 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 319 radeon_crtc = to_radeon_crtc(crtc); 320 if (radeon_crtc->enabled) { 321 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 322 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 323 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 324 } 325 } 326 } 327 328 void rs600_pm_finish(struct radeon_device *rdev) 329 { 330 struct drm_device *ddev = rdev->ddev; 331 struct drm_crtc *crtc; 332 struct radeon_crtc *radeon_crtc; 333 u32 tmp; 334 335 /* enable any active CRTCs */ 336 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 337 radeon_crtc = to_radeon_crtc(crtc); 338 if (radeon_crtc->enabled) { 339 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 340 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 341 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 342 } 343 } 344 } 345 346 /* hpd for digital panel detect/disconnect */ 347 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 348 { 349 u32 tmp; 350 bool connected = false; 351 352 switch (hpd) { 353 case RADEON_HPD_1: 354 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); 355 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) 356 connected = true; 357 break; 358 case RADEON_HPD_2: 359 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); 360 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) 361 connected = true; 362 break; 363 default: 364 break; 365 } 366 return connected; 367 } 368 369 void rs600_hpd_set_polarity(struct radeon_device *rdev, 370 enum radeon_hpd_id hpd) 371 { 372 u32 tmp; 373 bool connected = rs600_hpd_sense(rdev, hpd); 374 375 switch (hpd) { 376 case RADEON_HPD_1: 377 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 378 if (connected) 379 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 380 else 381 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 382 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 383 break; 384 case RADEON_HPD_2: 385 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 386 if (connected) 387 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 388 else 389 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 390 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 391 break; 392 default: 393 break; 394 } 395 } 396 397 void rs600_hpd_init(struct radeon_device *rdev) 398 { 399 struct drm_device *dev = rdev->ddev; 400 struct drm_connector *connector; 401 unsigned enable = 0; 402 403 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 404 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 405 switch (radeon_connector->hpd.hpd) { 406 case RADEON_HPD_1: 407 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 408 S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); 409 break; 410 case RADEON_HPD_2: 411 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 412 S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); 413 break; 414 default: 415 break; 416 } 417 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 418 enable |= 1 << radeon_connector->hpd.hpd; 419 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 420 } 421 radeon_irq_kms_enable_hpd(rdev, enable); 422 } 423 424 void rs600_hpd_fini(struct radeon_device *rdev) 425 { 426 struct drm_device *dev = rdev->ddev; 427 struct drm_connector *connector; 428 unsigned disable = 0; 429 430 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 431 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 432 switch (radeon_connector->hpd.hpd) { 433 case RADEON_HPD_1: 434 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 435 S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); 436 break; 437 case RADEON_HPD_2: 438 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 439 S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); 440 break; 441 default: 442 break; 443 } 444 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 445 disable |= 1 << radeon_connector->hpd.hpd; 446 } 447 radeon_irq_kms_disable_hpd(rdev, disable); 448 } 449 450 int rs600_asic_reset(struct radeon_device *rdev, bool hard) 451 { 452 struct rv515_mc_save save; 453 u32 status, tmp; 454 int ret = 0; 455 456 status = RREG32(R_000E40_RBBM_STATUS); 457 if (!G_000E40_GUI_ACTIVE(status)) { 458 return 0; 459 } 460 /* Stops all mc clients */ 461 rv515_mc_stop(rdev, &save); 462 status = RREG32(R_000E40_RBBM_STATUS); 463 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 464 /* stop CP */ 465 WREG32(RADEON_CP_CSQ_CNTL, 0); 466 tmp = RREG32(RADEON_CP_RB_CNTL); 467 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 468 WREG32(RADEON_CP_RB_RPTR_WR, 0); 469 WREG32(RADEON_CP_RB_WPTR, 0); 470 WREG32(RADEON_CP_RB_CNTL, tmp); 471 pci_save_state(device_get_parent(rdev->dev->bsddev)); 472 /* disable bus mastering */ 473 pci_disable_busmaster(rdev->dev->bsddev); 474 mdelay(1); 475 /* reset GA+VAP */ 476 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 477 S_0000F0_SOFT_RESET_GA(1)); 478 RREG32(R_0000F0_RBBM_SOFT_RESET); 479 mdelay(500); 480 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 481 mdelay(1); 482 status = RREG32(R_000E40_RBBM_STATUS); 483 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 484 /* reset CP */ 485 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 486 RREG32(R_0000F0_RBBM_SOFT_RESET); 487 mdelay(500); 488 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 489 mdelay(1); 490 status = RREG32(R_000E40_RBBM_STATUS); 491 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 492 /* reset MC */ 493 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); 494 RREG32(R_0000F0_RBBM_SOFT_RESET); 495 mdelay(500); 496 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 497 mdelay(1); 498 status = RREG32(R_000E40_RBBM_STATUS); 499 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 500 /* restore PCI & busmastering */ 501 pci_restore_state(device_get_parent(rdev->dev->bsddev)); 502 /* Check if GPU is idle */ 503 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 504 dev_err(rdev->dev, "failed to reset GPU\n"); 505 ret = -1; 506 } else 507 dev_info(rdev->dev, "GPU reset succeed\n"); 508 rv515_mc_resume(rdev, &save); 509 return ret; 510 } 511 512 /* 513 * GART. 514 */ 515 void rs600_gart_tlb_flush(struct radeon_device *rdev) 516 { 517 uint32_t tmp; 518 519 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 520 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 521 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 522 523 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 524 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); 525 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 526 527 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 528 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 529 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 530 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 531 } 532 533 static int rs600_gart_init(struct radeon_device *rdev) 534 { 535 int r; 536 537 if (rdev->gart.robj) { 538 WARN(1, "RS600 GART already initialized\n"); 539 return 0; 540 } 541 /* Initialize common gart structure */ 542 r = radeon_gart_init(rdev); 543 if (r) { 544 return r; 545 } 546 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 547 return radeon_gart_table_vram_alloc(rdev); 548 } 549 550 static int rs600_gart_enable(struct radeon_device *rdev) 551 { 552 u32 tmp; 553 int r, i; 554 555 if (rdev->gart.robj == NULL) { 556 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 557 return -EINVAL; 558 } 559 r = radeon_gart_table_vram_pin(rdev); 560 if (r) 561 return r; 562 /* Enable bus master */ 563 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 564 WREG32(RADEON_BUS_CNTL, tmp); 565 /* FIXME: setup default page */ 566 WREG32_MC(R_000100_MC_PT0_CNTL, 567 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 568 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); 569 570 for (i = 0; i < 19; i++) { 571 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 572 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | 573 S_00016C_SYSTEM_ACCESS_MODE_MASK( 574 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | 575 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( 576 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | 577 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | 578 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | 579 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); 580 } 581 /* enable first context */ 582 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 583 S_000102_ENABLE_PAGE_TABLE(1) | 584 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); 585 586 /* disable all other contexts */ 587 for (i = 1; i < 8; i++) 588 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 589 590 /* setup the page table */ 591 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 592 rdev->gart.table_addr); 593 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 594 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); 595 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 596 597 /* System context maps to VRAM space */ 598 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); 599 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); 600 601 /* enable page tables */ 602 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 603 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); 604 tmp = RREG32_MC(R_000009_MC_CNTL1); 605 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); 606 rs600_gart_tlb_flush(rdev); 607 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 608 (unsigned)(rdev->mc.gtt_size >> 20), 609 (unsigned long long)rdev->gart.table_addr); 610 rdev->gart.ready = true; 611 return 0; 612 } 613 614 static void rs600_gart_disable(struct radeon_device *rdev) 615 { 616 u32 tmp; 617 618 /* FIXME: disable out of gart access */ 619 WREG32_MC(R_000100_MC_PT0_CNTL, 0); 620 tmp = RREG32_MC(R_000009_MC_CNTL1); 621 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); 622 radeon_gart_table_vram_unpin(rdev); 623 } 624 625 static void rs600_gart_fini(struct radeon_device *rdev) 626 { 627 radeon_gart_fini(rdev); 628 rs600_gart_disable(rdev); 629 radeon_gart_table_vram_free(rdev); 630 } 631 632 uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags) 633 { 634 addr = addr & 0xFFFFFFFFFFFFF000ULL; 635 addr |= R600_PTE_SYSTEM; 636 if (flags & RADEON_GART_PAGE_VALID) 637 addr |= R600_PTE_VALID; 638 if (flags & RADEON_GART_PAGE_READ) 639 addr |= R600_PTE_READABLE; 640 if (flags & RADEON_GART_PAGE_WRITE) 641 addr |= R600_PTE_WRITEABLE; 642 if (flags & RADEON_GART_PAGE_SNOOP) 643 addr |= R600_PTE_SNOOPED; 644 return addr; 645 } 646 647 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, 648 uint64_t entry) 649 { 650 void __iomem *ptr = (void *)rdev->gart.ptr; 651 writeq(entry, (uint8_t *)ptr + (i * 8)); 652 } 653 654 int rs600_irq_set(struct radeon_device *rdev) 655 { 656 uint32_t tmp = 0; 657 uint32_t mode_int = 0; 658 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & 659 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 660 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & 661 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 662 u32 hdmi0; 663 if (ASIC_IS_DCE2(rdev)) 664 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 665 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 666 else 667 hdmi0 = 0; 668 669 if (!rdev->irq.installed) { 670 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 671 WREG32(R_000040_GEN_INT_CNTL, 0); 672 return -EINVAL; 673 } 674 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 675 tmp |= S_000040_SW_INT_EN(1); 676 } 677 if (rdev->irq.crtc_vblank_int[0] || 678 atomic_read(&rdev->irq.pflip[0])) { 679 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); 680 } 681 if (rdev->irq.crtc_vblank_int[1] || 682 atomic_read(&rdev->irq.pflip[1])) { 683 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); 684 } 685 if (rdev->irq.hpd[0]) { 686 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 687 } 688 if (rdev->irq.hpd[1]) { 689 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 690 } 691 if (rdev->irq.afmt[0]) { 692 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 693 } 694 WREG32(R_000040_GEN_INT_CNTL, tmp); 695 WREG32(R_006540_DxMODE_INT_MASK, mode_int); 696 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 697 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 698 if (ASIC_IS_DCE2(rdev)) 699 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 700 701 /* posting read */ 702 RREG32(R_000040_GEN_INT_CNTL); 703 704 return 0; 705 } 706 707 static inline u32 rs600_irq_ack(struct radeon_device *rdev) 708 { 709 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); 710 uint32_t irq_mask = S_000044_SW_INT(1); 711 u32 tmp; 712 713 if (G_000044_DISPLAY_INT_STAT(irqs)) { 714 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); 715 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 716 WREG32(R_006534_D1MODE_VBLANK_STATUS, 717 S_006534_D1MODE_VBLANK_ACK(1)); 718 } 719 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 720 WREG32(R_006D34_D2MODE_VBLANK_STATUS, 721 S_006D34_D2MODE_VBLANK_ACK(1)); 722 } 723 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 724 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 725 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); 726 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 727 } 728 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 729 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 730 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); 731 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 732 } 733 } else { 734 rdev->irq.stat_regs.r500.disp_int = 0; 735 } 736 737 if (ASIC_IS_DCE2(rdev)) { 738 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & 739 S_007404_HDMI0_AZ_FORMAT_WTRIG(1); 740 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 741 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); 742 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); 743 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); 744 } 745 } else 746 rdev->irq.stat_regs.r500.hdmi0_status = 0; 747 748 if (irqs) { 749 WREG32(R_000044_GEN_INT_STATUS, irqs); 750 } 751 return irqs & irq_mask; 752 } 753 754 void rs600_irq_disable(struct radeon_device *rdev) 755 { 756 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 757 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 758 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 759 WREG32(R_000040_GEN_INT_CNTL, 0); 760 WREG32(R_006540_DxMODE_INT_MASK, 0); 761 /* Wait and acknowledge irq */ 762 mdelay(1); 763 rs600_irq_ack(rdev); 764 } 765 766 irqreturn_t rs600_irq_process(struct radeon_device *rdev) 767 { 768 u32 status, msi_rearm; 769 bool queue_hotplug = false; 770 bool queue_hdmi = false; 771 772 status = rs600_irq_ack(rdev); 773 if (!status && 774 !rdev->irq.stat_regs.r500.disp_int && 775 !rdev->irq.stat_regs.r500.hdmi0_status) { 776 return IRQ_NONE; 777 } 778 while (status || 779 rdev->irq.stat_regs.r500.disp_int || 780 rdev->irq.stat_regs.r500.hdmi0_status) { 781 /* SW interrupt */ 782 if (G_000044_SW_INT(status)) { 783 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 784 } 785 /* Vertical blank interrupts */ 786 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 787 if (rdev->irq.crtc_vblank_int[0]) { 788 drm_handle_vblank(rdev->ddev, 0); 789 rdev->pm.vblank_sync = true; 790 wake_up(&rdev->irq.vblank_queue); 791 } 792 if (atomic_read(&rdev->irq.pflip[0])) 793 radeon_crtc_handle_vblank(rdev, 0); 794 } 795 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 796 if (rdev->irq.crtc_vblank_int[1]) { 797 drm_handle_vblank(rdev->ddev, 1); 798 rdev->pm.vblank_sync = true; 799 wake_up(&rdev->irq.vblank_queue); 800 } 801 if (atomic_read(&rdev->irq.pflip[1])) 802 radeon_crtc_handle_vblank(rdev, 1); 803 } 804 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 805 queue_hotplug = true; 806 DRM_DEBUG("HPD1\n"); 807 } 808 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 809 queue_hotplug = true; 810 DRM_DEBUG("HPD2\n"); 811 } 812 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 813 queue_hdmi = true; 814 DRM_DEBUG("HDMI0\n"); 815 } 816 status = rs600_irq_ack(rdev); 817 } 818 if (queue_hotplug) 819 schedule_delayed_work(&rdev->hotplug_work, 0); 820 if (queue_hdmi) 821 schedule_work(&rdev->audio_work); 822 if (rdev->msi_enabled) { 823 switch (rdev->family) { 824 case CHIP_RS600: 825 case CHIP_RS690: 826 case CHIP_RS740: 827 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; 828 WREG32(RADEON_BUS_CNTL, msi_rearm); 829 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 830 break; 831 default: 832 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 833 break; 834 } 835 } 836 return IRQ_HANDLED; 837 } 838 839 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) 840 { 841 if (crtc == 0) 842 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); 843 else 844 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); 845 } 846 847 int rs600_mc_wait_for_idle(struct radeon_device *rdev) 848 { 849 unsigned i; 850 851 for (i = 0; i < rdev->usec_timeout; i++) { 852 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) 853 return 0; 854 udelay(1); 855 } 856 return -1; 857 } 858 859 static void rs600_gpu_init(struct radeon_device *rdev) 860 { 861 r420_pipes_init(rdev); 862 /* Wait for mc idle */ 863 if (rs600_mc_wait_for_idle(rdev)) 864 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 865 } 866 867 static void rs600_mc_init(struct radeon_device *rdev) 868 { 869 u64 base; 870 871 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 872 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 873 rdev->mc.vram_is_ddr = true; 874 rdev->mc.vram_width = 128; 875 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 876 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 877 rdev->mc.visible_vram_size = rdev->mc.aper_size; 878 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 879 base = RREG32_MC(R_000004_MC_FB_LOCATION); 880 base = G_000004_MC_FB_START(base) << 16; 881 radeon_vram_location(rdev, &rdev->mc, base); 882 rdev->mc.gtt_base_align = 0; 883 radeon_gtt_location(rdev, &rdev->mc); 884 radeon_update_bandwidth_info(rdev); 885 } 886 887 void rs600_bandwidth_update(struct radeon_device *rdev) 888 { 889 struct drm_display_mode *mode0 = NULL; 890 struct drm_display_mode *mode1 = NULL; 891 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; 892 /* FIXME: implement full support */ 893 894 if (!rdev->mode_info.mode_config_initialized) 895 return; 896 897 radeon_update_display_priority(rdev); 898 899 if (rdev->mode_info.crtcs[0]->base.enabled) 900 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 901 if (rdev->mode_info.crtcs[1]->base.enabled) 902 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 903 904 rs690_line_buffer_adjust(rdev, mode0, mode1); 905 906 if (rdev->disp_priority == 2) { 907 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); 908 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); 909 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 910 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 911 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 912 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 913 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 914 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 915 } 916 } 917 918 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 919 { 920 u32 r; 921 922 lockmgr(&rdev->mc_idx_lock, LK_EXCLUSIVE); 923 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 924 S_000070_MC_IND_CITF_ARB0(1)); 925 r = RREG32(R_000074_MC_IND_DATA); 926 lockmgr(&rdev->mc_idx_lock, LK_RELEASE); 927 return r; 928 } 929 930 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 931 { 932 lockmgr(&rdev->mc_idx_lock, LK_EXCLUSIVE); 933 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 934 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); 935 WREG32(R_000074_MC_IND_DATA, v); 936 lockmgr(&rdev->mc_idx_lock, LK_RELEASE); 937 } 938 939 static void rs600_debugfs(struct radeon_device *rdev) 940 { 941 if (r100_debugfs_rbbm_init(rdev)) 942 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 943 } 944 945 void rs600_set_safe_registers(struct radeon_device *rdev) 946 { 947 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 948 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); 949 } 950 951 static void rs600_mc_program(struct radeon_device *rdev) 952 { 953 struct rv515_mc_save save; 954 955 /* Stops all mc clients */ 956 rv515_mc_stop(rdev, &save); 957 958 /* Wait for mc idle */ 959 if (rs600_mc_wait_for_idle(rdev)) 960 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 961 962 /* FIXME: What does AGP means for such chipset ? */ 963 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); 964 WREG32_MC(R_000006_AGP_BASE, 0); 965 WREG32_MC(R_000007_AGP_BASE_2, 0); 966 /* Program MC */ 967 WREG32_MC(R_000004_MC_FB_LOCATION, 968 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 969 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 970 WREG32(R_000134_HDP_FB_LOCATION, 971 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 972 973 rv515_mc_resume(rdev, &save); 974 } 975 976 static int rs600_startup(struct radeon_device *rdev) 977 { 978 int r; 979 980 rs600_mc_program(rdev); 981 /* Resume clock */ 982 rv515_clock_startup(rdev); 983 /* Initialize GPU configuration (# pipes, ...) */ 984 rs600_gpu_init(rdev); 985 /* Initialize GART (initialize after TTM so we can allocate 986 * memory through TTM but finalize after TTM) */ 987 r = rs600_gart_enable(rdev); 988 if (r) 989 return r; 990 991 /* allocate wb buffer */ 992 r = radeon_wb_init(rdev); 993 if (r) 994 return r; 995 996 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 997 if (r) { 998 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 999 return r; 1000 } 1001 1002 /* Enable IRQ */ 1003 if (!rdev->irq.installed) { 1004 r = radeon_irq_kms_init(rdev); 1005 if (r) 1006 return r; 1007 } 1008 1009 rs600_irq_set(rdev); 1010 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1011 /* 1M ring buffer */ 1012 r = r100_cp_init(rdev, 1024 * 1024); 1013 if (r) { 1014 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1015 return r; 1016 } 1017 1018 r = radeon_ib_pool_init(rdev); 1019 if (r) { 1020 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1021 return r; 1022 } 1023 1024 r = radeon_audio_init(rdev); 1025 if (r) { 1026 dev_err(rdev->dev, "failed initializing audio\n"); 1027 return r; 1028 } 1029 1030 return 0; 1031 } 1032 1033 int rs600_resume(struct radeon_device *rdev) 1034 { 1035 int r; 1036 1037 /* Make sur GART are not working */ 1038 rs600_gart_disable(rdev); 1039 /* Resume clock before doing reset */ 1040 rv515_clock_startup(rdev); 1041 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1042 if (radeon_asic_reset(rdev)) { 1043 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1044 RREG32(R_000E40_RBBM_STATUS), 1045 RREG32(R_0007C0_CP_STAT)); 1046 } 1047 /* post */ 1048 atom_asic_init(rdev->mode_info.atom_context); 1049 /* Resume clock after posting */ 1050 rv515_clock_startup(rdev); 1051 /* Initialize surface registers */ 1052 radeon_surface_init(rdev); 1053 1054 rdev->accel_working = true; 1055 r = rs600_startup(rdev); 1056 if (r) { 1057 rdev->accel_working = false; 1058 } 1059 return r; 1060 } 1061 1062 int rs600_suspend(struct radeon_device *rdev) 1063 { 1064 radeon_pm_suspend(rdev); 1065 radeon_audio_fini(rdev); 1066 r100_cp_disable(rdev); 1067 radeon_wb_disable(rdev); 1068 rs600_irq_disable(rdev); 1069 rs600_gart_disable(rdev); 1070 return 0; 1071 } 1072 1073 void rs600_fini(struct radeon_device *rdev) 1074 { 1075 radeon_pm_fini(rdev); 1076 radeon_audio_fini(rdev); 1077 r100_cp_fini(rdev); 1078 radeon_wb_fini(rdev); 1079 radeon_ib_pool_fini(rdev); 1080 radeon_gem_fini(rdev); 1081 rs600_gart_fini(rdev); 1082 radeon_irq_kms_fini(rdev); 1083 radeon_fence_driver_fini(rdev); 1084 radeon_bo_fini(rdev); 1085 radeon_atombios_fini(rdev); 1086 kfree(rdev->bios); 1087 rdev->bios = NULL; 1088 } 1089 1090 int rs600_init(struct radeon_device *rdev) 1091 { 1092 int r; 1093 1094 /* Disable VGA */ 1095 rv515_vga_render_disable(rdev); 1096 /* Initialize scratch registers */ 1097 radeon_scratch_init(rdev); 1098 /* Initialize surface registers */ 1099 radeon_surface_init(rdev); 1100 /* restore some register to sane defaults */ 1101 r100_restore_sanity(rdev); 1102 /* BIOS */ 1103 if (!radeon_get_bios(rdev)) { 1104 if (ASIC_IS_AVIVO(rdev)) 1105 return -EINVAL; 1106 } 1107 if (rdev->is_atom_bios) { 1108 r = radeon_atombios_init(rdev); 1109 if (r) 1110 return r; 1111 } else { 1112 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); 1113 return -EINVAL; 1114 } 1115 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1116 if (radeon_asic_reset(rdev)) { 1117 dev_warn(rdev->dev, 1118 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1119 RREG32(R_000E40_RBBM_STATUS), 1120 RREG32(R_0007C0_CP_STAT)); 1121 } 1122 /* check if cards are posted or not */ 1123 if (radeon_boot_test_post_card(rdev) == false) 1124 return -EINVAL; 1125 1126 /* Initialize clocks */ 1127 radeon_get_clock_info(rdev->ddev); 1128 /* initialize memory controller */ 1129 rs600_mc_init(rdev); 1130 rs600_debugfs(rdev); 1131 /* Fence driver */ 1132 r = radeon_fence_driver_init(rdev); 1133 if (r) 1134 return r; 1135 /* Memory manager */ 1136 r = radeon_bo_init(rdev); 1137 if (r) 1138 return r; 1139 r = rs600_gart_init(rdev); 1140 if (r) 1141 return r; 1142 rs600_set_safe_registers(rdev); 1143 1144 /* Initialize power management */ 1145 radeon_pm_init(rdev); 1146 1147 rdev->accel_working = true; 1148 r = rs600_startup(rdev); 1149 if (r) { 1150 /* Somethings want wront with the accel init stop accel */ 1151 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1152 r100_cp_fini(rdev); 1153 radeon_wb_fini(rdev); 1154 radeon_ib_pool_fini(rdev); 1155 rs600_gart_fini(rdev); 1156 radeon_irq_kms_fini(rdev); 1157 rdev->accel_working = false; 1158 } 1159 return 0; 1160 } 1161