1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 #include "r600_dpm.h" 29 #include "si_dpm.h" 30 #include "atom.h" 31 #include <linux/math64.h> 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x20000 40 41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43 static const struct si_cac_config_reg cac_weights_tahiti[] = 44 { 45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 105 { 0xFFFFFFFF } 106 }; 107 108 static const struct si_cac_config_reg lcac_tahiti[] = 109 { 110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0xFFFFFFFF } 197 198 }; 199 200 static const struct si_cac_config_reg cac_override_tahiti[] = 201 { 202 { 0xFFFFFFFF } 203 }; 204 205 static const struct si_powertune_data powertune_data_tahiti = 206 { 207 ((1 << 16) | 27027), 208 6, 209 0, 210 4, 211 95, 212 { 213 0UL, 214 0UL, 215 4521550UL, 216 309631529UL, 217 -1270850L, 218 4513710L, 219 40 220 }, 221 595000000UL, 222 12, 223 { 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0 232 }, 233 true 234 }; 235 236 static const struct si_dte_data dte_data_tahiti = 237 { 238 { 1159409, 0, 0, 0, 0 }, 239 { 777, 0, 0, 0, 0 }, 240 2, 241 54000, 242 127000, 243 25, 244 2, 245 10, 246 13, 247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 250 85, 251 false 252 }; 253 254 #if 0 /* unused */ 255 static const struct si_dte_data dte_data_tahiti_le = 256 { 257 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 258 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 259 0x5, 260 0xAFC8, 261 0x64, 262 0x32, 263 1, 264 0, 265 0x10, 266 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 267 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 268 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 269 85, 270 true 271 }; 272 #endif 273 274 static const struct si_dte_data dte_data_tahiti_pro = 275 { 276 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 277 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 278 5, 279 45000, 280 100, 281 0xA, 282 1, 283 0, 284 0x10, 285 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 286 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 287 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 288 90, 289 true 290 }; 291 292 static const struct si_dte_data dte_data_new_zealand = 293 { 294 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 295 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 296 0x5, 297 0xAFC8, 298 0x69, 299 0x32, 300 1, 301 0, 302 0x10, 303 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 304 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 305 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 306 85, 307 true 308 }; 309 310 static const struct si_dte_data dte_data_aruba_pro = 311 { 312 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 313 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 314 5, 315 45000, 316 100, 317 0xA, 318 1, 319 0, 320 0x10, 321 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 322 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 323 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 324 90, 325 true 326 }; 327 328 static const struct si_dte_data dte_data_malta = 329 { 330 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 331 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 332 5, 333 45000, 334 100, 335 0xA, 336 1, 337 0, 338 0x10, 339 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 340 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 341 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 342 90, 343 true 344 }; 345 346 struct si_cac_config_reg cac_weights_pitcairn[] = 347 { 348 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 349 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 350 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 351 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 352 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 353 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 354 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 356 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 357 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 358 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 359 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 360 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 361 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 362 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 365 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 366 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 367 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 368 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 369 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 370 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 371 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 374 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 375 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 379 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 381 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 383 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 384 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 385 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 387 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 407 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 408 { 0xFFFFFFFF } 409 }; 410 411 static const struct si_cac_config_reg lcac_pitcairn[] = 412 { 413 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 416 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 422 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 428 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 434 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 440 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 446 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 452 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 458 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 472 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 486 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 498 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 499 { 0xFFFFFFFF } 500 }; 501 502 static const struct si_cac_config_reg cac_override_pitcairn[] = 503 { 504 { 0xFFFFFFFF } 505 }; 506 507 static const struct si_powertune_data powertune_data_pitcairn = 508 { 509 ((1 << 16) | 27027), 510 5, 511 0, 512 6, 513 100, 514 { 515 51600000UL, 516 1800000UL, 517 7194395UL, 518 309631529UL, 519 -1270850L, 520 4513710L, 521 100 522 }, 523 117830498UL, 524 12, 525 { 526 0, 527 0, 528 0, 529 0, 530 0, 531 0, 532 0, 533 0 534 }, 535 true 536 }; 537 538 static const struct si_dte_data dte_data_pitcairn = 539 { 540 { 0, 0, 0, 0, 0 }, 541 { 0, 0, 0, 0, 0 }, 542 0, 543 0, 544 0, 545 0, 546 0, 547 0, 548 0, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 551 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 552 0, 553 false 554 }; 555 556 static const struct si_dte_data dte_data_curacao_xt = 557 { 558 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 559 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 560 5, 561 45000, 562 100, 563 0xA, 564 1, 565 0, 566 0x10, 567 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 568 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 569 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 570 90, 571 true 572 }; 573 574 static const struct si_dte_data dte_data_curacao_pro = 575 { 576 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 577 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 578 5, 579 45000, 580 100, 581 0xA, 582 1, 583 0, 584 0x10, 585 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 586 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 587 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 588 90, 589 true 590 }; 591 592 static const struct si_dte_data dte_data_neptune_xt = 593 { 594 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 595 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 596 5, 597 45000, 598 100, 599 0xA, 600 1, 601 0, 602 0x10, 603 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 604 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 605 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 606 90, 607 true 608 }; 609 610 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 611 { 612 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 613 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 614 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 615 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 616 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 617 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 619 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 620 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 621 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 622 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 623 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 624 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 625 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 626 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 627 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 628 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 629 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 630 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 631 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 632 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 633 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 634 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 635 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 636 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 637 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 638 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 639 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 640 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 641 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 642 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 643 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 644 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 645 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 646 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 647 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 648 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 650 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 652 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 653 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 671 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 672 { 0xFFFFFFFF } 673 }; 674 675 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 676 { 677 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 678 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 679 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 680 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 681 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 682 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 684 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 685 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 686 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 687 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 688 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 689 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 690 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 691 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 692 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 693 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 694 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 695 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 696 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 697 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 698 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 699 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 700 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 701 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 702 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 703 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 704 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 705 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 706 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 707 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 708 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 709 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 710 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 711 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 712 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 713 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 715 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 717 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 718 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 736 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 737 { 0xFFFFFFFF } 738 }; 739 740 static const struct si_cac_config_reg cac_weights_heathrow[] = 741 { 742 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 743 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 744 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 745 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 746 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 747 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 749 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 750 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 751 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 752 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 753 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 754 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 755 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 756 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 757 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 758 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 759 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 760 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 761 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 762 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 763 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 764 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 765 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 766 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 767 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 768 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 769 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 771 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 772 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 773 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 774 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 775 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 776 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 777 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 778 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 780 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 782 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 783 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 801 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 802 { 0xFFFFFFFF } 803 }; 804 805 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 806 { 807 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 808 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 809 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 810 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 811 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 812 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 814 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 815 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 816 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 817 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 818 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 819 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 820 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 821 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 822 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 823 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 824 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 825 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 826 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 827 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 828 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 829 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 830 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 831 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 832 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 833 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 834 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 836 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 837 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 838 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 839 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 840 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 841 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 842 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 843 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 845 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 847 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 848 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 866 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 867 { 0xFFFFFFFF } 868 }; 869 870 static const struct si_cac_config_reg cac_weights_cape_verde[] = 871 { 872 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 873 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 874 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 875 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 876 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 877 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 879 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 880 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 881 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 882 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 883 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 884 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 885 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 886 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 887 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 888 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 889 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 890 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 891 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 892 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 893 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 894 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 895 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 896 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 897 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 898 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 899 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 901 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 902 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 903 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 904 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 905 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 906 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 907 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 908 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 910 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 912 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 913 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 931 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 932 { 0xFFFFFFFF } 933 }; 934 935 static const struct si_cac_config_reg lcac_cape_verde[] = 936 { 937 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 940 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 946 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 952 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 956 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 978 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 982 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 991 { 0xFFFFFFFF } 992 }; 993 994 static const struct si_cac_config_reg cac_override_cape_verde[] = 995 { 996 { 0xFFFFFFFF } 997 }; 998 999 static const struct si_powertune_data powertune_data_cape_verde = 1000 { 1001 ((1 << 16) | 0x6993), 1002 5, 1003 0, 1004 7, 1005 105, 1006 { 1007 0UL, 1008 0UL, 1009 7194395UL, 1010 309631529UL, 1011 -1270850L, 1012 4513710L, 1013 100 1014 }, 1015 117830498UL, 1016 12, 1017 { 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0, 1024 0, 1025 0 1026 }, 1027 true 1028 }; 1029 1030 static const struct si_dte_data dte_data_cape_verde = 1031 { 1032 { 0, 0, 0, 0, 0 }, 1033 { 0, 0, 0, 0, 0 }, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 0, 1040 0, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1043 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1044 0, 1045 false 1046 }; 1047 1048 static const struct si_dte_data dte_data_venus_xtx = 1049 { 1050 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1051 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1052 5, 1053 55000, 1054 0x69, 1055 0xA, 1056 1, 1057 0, 1058 0x3, 1059 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1061 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1062 90, 1063 true 1064 }; 1065 1066 static const struct si_dte_data dte_data_venus_xt = 1067 { 1068 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1069 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1070 5, 1071 55000, 1072 0x69, 1073 0xA, 1074 1, 1075 0, 1076 0x3, 1077 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1079 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1080 90, 1081 true 1082 }; 1083 1084 static const struct si_dte_data dte_data_venus_pro = 1085 { 1086 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1087 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1088 5, 1089 55000, 1090 0x69, 1091 0xA, 1092 1, 1093 0, 1094 0x3, 1095 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1097 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1098 90, 1099 true 1100 }; 1101 1102 struct si_cac_config_reg cac_weights_oland[] = 1103 { 1104 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1131 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1164 { 0xFFFFFFFF } 1165 }; 1166 1167 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1168 { 1169 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1196 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xFFFFFFFF } 1230 }; 1231 1232 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1233 { 1234 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1261 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xFFFFFFFF } 1295 }; 1296 1297 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1298 { 1299 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1326 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xFFFFFFFF } 1360 }; 1361 1362 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1363 { 1364 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1391 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xFFFFFFFF } 1425 }; 1426 1427 static const struct si_cac_config_reg lcac_oland[] = 1428 { 1429 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1471 { 0xFFFFFFFF } 1472 }; 1473 1474 static const struct si_cac_config_reg lcac_mars_pro[] = 1475 { 1476 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1518 { 0xFFFFFFFF } 1519 }; 1520 1521 static const struct si_cac_config_reg cac_override_oland[] = 1522 { 1523 { 0xFFFFFFFF } 1524 }; 1525 1526 static const struct si_powertune_data powertune_data_oland = 1527 { 1528 ((1 << 16) | 0x6993), 1529 5, 1530 0, 1531 7, 1532 105, 1533 { 1534 0UL, 1535 0UL, 1536 7194395UL, 1537 309631529UL, 1538 -1270850L, 1539 4513710L, 1540 100 1541 }, 1542 117830498UL, 1543 12, 1544 { 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0, 1551 0, 1552 0 1553 }, 1554 true 1555 }; 1556 1557 static const struct si_powertune_data powertune_data_mars_pro = 1558 { 1559 ((1 << 16) | 0x6993), 1560 5, 1561 0, 1562 7, 1563 105, 1564 { 1565 0UL, 1566 0UL, 1567 7194395UL, 1568 309631529UL, 1569 -1270850L, 1570 4513710L, 1571 100 1572 }, 1573 117830498UL, 1574 12, 1575 { 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0, 1582 0, 1583 0 1584 }, 1585 true 1586 }; 1587 1588 static const struct si_dte_data dte_data_oland = 1589 { 1590 { 0, 0, 0, 0, 0 }, 1591 { 0, 0, 0, 0, 0 }, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 0, 1598 0, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1601 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1602 0, 1603 false 1604 }; 1605 1606 static const struct si_dte_data dte_data_mars_pro = 1607 { 1608 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1609 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1610 5, 1611 55000, 1612 105, 1613 0xA, 1614 1, 1615 0, 1616 0x10, 1617 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1618 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1619 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1620 90, 1621 true 1622 }; 1623 1624 static const struct si_dte_data dte_data_sun_xt = 1625 { 1626 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1627 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1628 5, 1629 55000, 1630 105, 1631 0xA, 1632 1, 1633 0, 1634 0x10, 1635 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1636 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1637 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1638 90, 1639 true 1640 }; 1641 1642 1643 static const struct si_cac_config_reg cac_weights_hainan[] = 1644 { 1645 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1672 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1704 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1705 { 0xFFFFFFFF } 1706 }; 1707 1708 static const struct si_powertune_data powertune_data_hainan = 1709 { 1710 ((1 << 16) | 0x6993), 1711 5, 1712 0, 1713 9, 1714 105, 1715 { 1716 0UL, 1717 0UL, 1718 7194395UL, 1719 309631529UL, 1720 -1270850L, 1721 4513710L, 1722 100 1723 }, 1724 117830498UL, 1725 12, 1726 { 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0, 1733 0, 1734 0 1735 }, 1736 true 1737 }; 1738 1739 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1740 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1741 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1742 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1743 1744 static int si_populate_voltage_value(struct radeon_device *rdev, 1745 const struct atom_voltage_table *table, 1746 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1747 static int si_get_std_voltage_value(struct radeon_device *rdev, 1748 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1749 u16 *std_voltage); 1750 static int si_write_smc_soft_register(struct radeon_device *rdev, 1751 u16 reg_offset, u32 value); 1752 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1753 struct rv7xx_pl *pl, 1754 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1755 static int si_calculate_sclk_params(struct radeon_device *rdev, 1756 u32 engine_clock, 1757 SISLANDS_SMC_SCLK_VALUE *sclk); 1758 1759 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1760 { 1761 struct si_power_info *pi = rdev->pm.dpm.priv; 1762 1763 return pi; 1764 } 1765 1766 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1767 u16 v, s32 t, u32 ileakage, u32 *leakage) 1768 { 1769 s64 kt, kv, leakage_w, i_leakage, vddc; 1770 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1771 s64 tmp; 1772 1773 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1774 vddc = div64_s64(drm_int2fixp(v), 1000); 1775 temperature = div64_s64(drm_int2fixp(t), 1000); 1776 1777 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1778 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1779 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1780 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1781 t_ref = drm_int2fixp(coeff->t_ref); 1782 1783 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1784 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1785 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1786 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1787 1788 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1789 1790 *leakage = drm_fixp2int(leakage_w * 1000); 1791 } 1792 1793 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1794 const struct ni_leakage_coeffients *coeff, 1795 u16 v, 1796 s32 t, 1797 u32 i_leakage, 1798 u32 *leakage) 1799 { 1800 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1801 } 1802 1803 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1804 const u32 fixed_kt, u16 v, 1805 u32 ileakage, u32 *leakage) 1806 { 1807 s64 kt, kv, leakage_w, i_leakage, vddc; 1808 1809 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1810 vddc = div64_s64(drm_int2fixp(v), 1000); 1811 1812 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1813 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1814 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1815 1816 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1817 1818 *leakage = drm_fixp2int(leakage_w * 1000); 1819 } 1820 1821 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1822 const struct ni_leakage_coeffients *coeff, 1823 const u32 fixed_kt, 1824 u16 v, 1825 u32 i_leakage, 1826 u32 *leakage) 1827 { 1828 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1829 } 1830 1831 1832 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1833 struct si_dte_data *dte_data) 1834 { 1835 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1836 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1837 u32 k = dte_data->k; 1838 u32 t_max = dte_data->max_t; 1839 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1840 u32 t_0 = dte_data->t0; 1841 u32 i; 1842 1843 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1844 dte_data->tdep_count = 3; 1845 1846 for (i = 0; i < k; i++) { 1847 dte_data->r[i] = 1848 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1849 (p_limit2 * (u32)100); 1850 } 1851 1852 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1853 1854 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1855 dte_data->tdep_r[i] = dte_data->r[4]; 1856 } 1857 } else { 1858 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1859 } 1860 } 1861 1862 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1863 { 1864 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1865 struct si_power_info *si_pi = si_get_pi(rdev); 1866 bool update_dte_from_pl2 = false; 1867 1868 if (rdev->family == CHIP_TAHITI) { 1869 si_pi->cac_weights = cac_weights_tahiti; 1870 si_pi->lcac_config = lcac_tahiti; 1871 si_pi->cac_override = cac_override_tahiti; 1872 si_pi->powertune_data = &powertune_data_tahiti; 1873 si_pi->dte_data = dte_data_tahiti; 1874 1875 switch (rdev->pdev->device) { 1876 case 0x6798: 1877 si_pi->dte_data.enable_dte_by_default = true; 1878 break; 1879 case 0x6799: 1880 si_pi->dte_data = dte_data_new_zealand; 1881 break; 1882 case 0x6790: 1883 case 0x6791: 1884 case 0x6792: 1885 case 0x679E: 1886 si_pi->dte_data = dte_data_aruba_pro; 1887 update_dte_from_pl2 = true; 1888 break; 1889 case 0x679B: 1890 si_pi->dte_data = dte_data_malta; 1891 update_dte_from_pl2 = true; 1892 break; 1893 case 0x679A: 1894 si_pi->dte_data = dte_data_tahiti_pro; 1895 update_dte_from_pl2 = true; 1896 break; 1897 default: 1898 if (si_pi->dte_data.enable_dte_by_default == true) 1899 DRM_ERROR("DTE is not enabled!\n"); 1900 break; 1901 } 1902 } else if (rdev->family == CHIP_PITCAIRN) { 1903 switch (rdev->pdev->device) { 1904 case 0x6810: 1905 case 0x6818: 1906 si_pi->cac_weights = cac_weights_pitcairn; 1907 si_pi->lcac_config = lcac_pitcairn; 1908 si_pi->cac_override = cac_override_pitcairn; 1909 si_pi->powertune_data = &powertune_data_pitcairn; 1910 si_pi->dte_data = dte_data_curacao_xt; 1911 update_dte_from_pl2 = true; 1912 break; 1913 case 0x6819: 1914 case 0x6811: 1915 si_pi->cac_weights = cac_weights_pitcairn; 1916 si_pi->lcac_config = lcac_pitcairn; 1917 si_pi->cac_override = cac_override_pitcairn; 1918 si_pi->powertune_data = &powertune_data_pitcairn; 1919 si_pi->dte_data = dte_data_curacao_pro; 1920 update_dte_from_pl2 = true; 1921 break; 1922 case 0x6800: 1923 case 0x6806: 1924 si_pi->cac_weights = cac_weights_pitcairn; 1925 si_pi->lcac_config = lcac_pitcairn; 1926 si_pi->cac_override = cac_override_pitcairn; 1927 si_pi->powertune_data = &powertune_data_pitcairn; 1928 si_pi->dte_data = dte_data_neptune_xt; 1929 update_dte_from_pl2 = true; 1930 break; 1931 default: 1932 si_pi->cac_weights = cac_weights_pitcairn; 1933 si_pi->lcac_config = lcac_pitcairn; 1934 si_pi->cac_override = cac_override_pitcairn; 1935 si_pi->powertune_data = &powertune_data_pitcairn; 1936 si_pi->dte_data = dte_data_pitcairn; 1937 break; 1938 } 1939 } else if (rdev->family == CHIP_VERDE) { 1940 si_pi->lcac_config = lcac_cape_verde; 1941 si_pi->cac_override = cac_override_cape_verde; 1942 si_pi->powertune_data = &powertune_data_cape_verde; 1943 1944 switch (rdev->pdev->device) { 1945 case 0x683B: 1946 case 0x683F: 1947 case 0x6829: 1948 case 0x6835: 1949 si_pi->cac_weights = cac_weights_cape_verde_pro; 1950 si_pi->dte_data = dte_data_cape_verde; 1951 break; 1952 case 0x682C: 1953 si_pi->cac_weights = cac_weights_cape_verde_pro; 1954 si_pi->dte_data = dte_data_sun_xt; 1955 break; 1956 case 0x6825: 1957 case 0x6827: 1958 si_pi->cac_weights = cac_weights_heathrow; 1959 si_pi->dte_data = dte_data_cape_verde; 1960 break; 1961 case 0x6824: 1962 case 0x682D: 1963 si_pi->cac_weights = cac_weights_chelsea_xt; 1964 si_pi->dte_data = dte_data_cape_verde; 1965 break; 1966 case 0x682F: 1967 si_pi->cac_weights = cac_weights_chelsea_pro; 1968 si_pi->dte_data = dte_data_cape_verde; 1969 break; 1970 case 0x6820: 1971 si_pi->cac_weights = cac_weights_heathrow; 1972 si_pi->dte_data = dte_data_venus_xtx; 1973 break; 1974 case 0x6821: 1975 si_pi->cac_weights = cac_weights_heathrow; 1976 si_pi->dte_data = dte_data_venus_xt; 1977 break; 1978 case 0x6823: 1979 case 0x682B: 1980 case 0x6822: 1981 case 0x682A: 1982 si_pi->cac_weights = cac_weights_chelsea_pro; 1983 si_pi->dte_data = dte_data_venus_pro; 1984 break; 1985 default: 1986 si_pi->cac_weights = cac_weights_cape_verde; 1987 si_pi->dte_data = dte_data_cape_verde; 1988 break; 1989 } 1990 } else if (rdev->family == CHIP_OLAND) { 1991 switch (rdev->pdev->device) { 1992 case 0x6601: 1993 case 0x6621: 1994 case 0x6603: 1995 case 0x6605: 1996 si_pi->cac_weights = cac_weights_mars_pro; 1997 si_pi->lcac_config = lcac_mars_pro; 1998 si_pi->cac_override = cac_override_oland; 1999 si_pi->powertune_data = &powertune_data_mars_pro; 2000 si_pi->dte_data = dte_data_mars_pro; 2001 update_dte_from_pl2 = true; 2002 break; 2003 case 0x6600: 2004 case 0x6606: 2005 case 0x6620: 2006 case 0x6604: 2007 si_pi->cac_weights = cac_weights_mars_xt; 2008 si_pi->lcac_config = lcac_mars_pro; 2009 si_pi->cac_override = cac_override_oland; 2010 si_pi->powertune_data = &powertune_data_mars_pro; 2011 si_pi->dte_data = dte_data_mars_pro; 2012 update_dte_from_pl2 = true; 2013 break; 2014 case 0x6611: 2015 case 0x6613: 2016 case 0x6608: 2017 si_pi->cac_weights = cac_weights_oland_pro; 2018 si_pi->lcac_config = lcac_mars_pro; 2019 si_pi->cac_override = cac_override_oland; 2020 si_pi->powertune_data = &powertune_data_mars_pro; 2021 si_pi->dte_data = dte_data_mars_pro; 2022 update_dte_from_pl2 = true; 2023 break; 2024 case 0x6610: 2025 si_pi->cac_weights = cac_weights_oland_xt; 2026 si_pi->lcac_config = lcac_mars_pro; 2027 si_pi->cac_override = cac_override_oland; 2028 si_pi->powertune_data = &powertune_data_mars_pro; 2029 si_pi->dte_data = dte_data_mars_pro; 2030 update_dte_from_pl2 = true; 2031 break; 2032 default: 2033 si_pi->cac_weights = cac_weights_oland; 2034 si_pi->lcac_config = lcac_oland; 2035 si_pi->cac_override = cac_override_oland; 2036 si_pi->powertune_data = &powertune_data_oland; 2037 si_pi->dte_data = dte_data_oland; 2038 break; 2039 } 2040 } else if (rdev->family == CHIP_HAINAN) { 2041 si_pi->cac_weights = cac_weights_hainan; 2042 si_pi->lcac_config = lcac_oland; 2043 si_pi->cac_override = cac_override_oland; 2044 si_pi->powertune_data = &powertune_data_hainan; 2045 si_pi->dte_data = dte_data_sun_xt; 2046 update_dte_from_pl2 = true; 2047 } else { 2048 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2049 return; 2050 } 2051 2052 ni_pi->enable_power_containment = false; 2053 ni_pi->enable_cac = false; 2054 ni_pi->enable_sq_ramping = false; 2055 si_pi->enable_dte = false; 2056 2057 if (si_pi->powertune_data->enable_powertune_by_default) { 2058 ni_pi->enable_power_containment= true; 2059 ni_pi->enable_cac = true; 2060 if (si_pi->dte_data.enable_dte_by_default) { 2061 si_pi->enable_dte = true; 2062 if (update_dte_from_pl2) 2063 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2064 2065 } 2066 ni_pi->enable_sq_ramping = true; 2067 } 2068 2069 ni_pi->driver_calculate_cac_leakage = true; 2070 ni_pi->cac_configuration_required = true; 2071 2072 if (ni_pi->cac_configuration_required) { 2073 ni_pi->support_cac_long_term_average = true; 2074 si_pi->dyn_powertune_data.l2_lta_window_size = 2075 si_pi->powertune_data->l2_lta_window_size_default; 2076 si_pi->dyn_powertune_data.lts_truncate = 2077 si_pi->powertune_data->lts_truncate_default; 2078 } else { 2079 ni_pi->support_cac_long_term_average = false; 2080 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2081 si_pi->dyn_powertune_data.lts_truncate = 0; 2082 } 2083 2084 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2085 } 2086 2087 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2088 { 2089 return 1; 2090 } 2091 2092 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2093 { 2094 u32 xclk; 2095 u32 wintime; 2096 u32 cac_window; 2097 u32 cac_window_size; 2098 2099 xclk = radeon_get_xclk(rdev); 2100 2101 if (xclk == 0) 2102 return 0; 2103 2104 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2105 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2106 2107 wintime = (cac_window_size * 100) / xclk; 2108 2109 return wintime; 2110 } 2111 2112 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2113 { 2114 return power_in_watts; 2115 } 2116 2117 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2118 bool adjust_polarity, 2119 u32 tdp_adjustment, 2120 u32 *tdp_limit, 2121 u32 *near_tdp_limit) 2122 { 2123 u32 adjustment_delta, max_tdp_limit; 2124 2125 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2126 return -EINVAL; 2127 2128 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2129 2130 if (adjust_polarity) { 2131 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2132 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2133 } else { 2134 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2135 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2136 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2137 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2138 else 2139 *near_tdp_limit = 0; 2140 } 2141 2142 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2143 return -EINVAL; 2144 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2145 return -EINVAL; 2146 2147 return 0; 2148 } 2149 2150 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2151 struct radeon_ps *radeon_state) 2152 { 2153 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2154 struct si_power_info *si_pi = si_get_pi(rdev); 2155 2156 if (ni_pi->enable_power_containment) { 2157 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2158 PP_SIslands_PAPMParameters *papm_parm; 2159 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2160 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2161 u32 tdp_limit; 2162 u32 near_tdp_limit; 2163 int ret; 2164 2165 if (scaling_factor == 0) 2166 return -EINVAL; 2167 2168 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2169 2170 ret = si_calculate_adjusted_tdp_limits(rdev, 2171 false, /* ??? */ 2172 rdev->pm.dpm.tdp_adjustment, 2173 &tdp_limit, 2174 &near_tdp_limit); 2175 if (ret) 2176 return ret; 2177 2178 smc_table->dpm2Params.TDPLimit = 2179 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2180 smc_table->dpm2Params.NearTDPLimit = 2181 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2182 smc_table->dpm2Params.SafePowerLimit = 2183 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2184 2185 ret = si_copy_bytes_to_smc(rdev, 2186 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2187 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2188 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2189 sizeof(u32) * 3, 2190 si_pi->sram_end); 2191 if (ret) 2192 return ret; 2193 2194 if (si_pi->enable_ppm) { 2195 papm_parm = &si_pi->papm_parm; 2196 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2197 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2198 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2199 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2200 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2201 papm_parm->PlatformPowerLimit = 0xffffffff; 2202 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2203 2204 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2205 (u8 *)papm_parm, 2206 sizeof(PP_SIslands_PAPMParameters), 2207 si_pi->sram_end); 2208 if (ret) 2209 return ret; 2210 } 2211 } 2212 return 0; 2213 } 2214 2215 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2216 struct radeon_ps *radeon_state) 2217 { 2218 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2219 struct si_power_info *si_pi = si_get_pi(rdev); 2220 2221 if (ni_pi->enable_power_containment) { 2222 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2223 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2224 int ret; 2225 2226 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2227 2228 smc_table->dpm2Params.NearTDPLimit = 2229 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2230 smc_table->dpm2Params.SafePowerLimit = 2231 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2232 2233 ret = si_copy_bytes_to_smc(rdev, 2234 (si_pi->state_table_start + 2235 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2236 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2237 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2238 sizeof(u32) * 2, 2239 si_pi->sram_end); 2240 if (ret) 2241 return ret; 2242 } 2243 2244 return 0; 2245 } 2246 2247 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2248 const u16 prev_std_vddc, 2249 const u16 curr_std_vddc) 2250 { 2251 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2252 u64 prev_vddc = (u64)prev_std_vddc; 2253 u64 curr_vddc = (u64)curr_std_vddc; 2254 u64 pwr_efficiency_ratio, n, d; 2255 2256 if ((prev_vddc == 0) || (curr_vddc == 0)) 2257 return 0; 2258 2259 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2260 d = prev_vddc * prev_vddc; 2261 pwr_efficiency_ratio = div64_u64(n, d); 2262 2263 if (pwr_efficiency_ratio > (u64)0xFFFF) 2264 return 0; 2265 2266 return (u16)pwr_efficiency_ratio; 2267 } 2268 2269 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2270 struct radeon_ps *radeon_state) 2271 { 2272 struct si_power_info *si_pi = si_get_pi(rdev); 2273 2274 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2275 radeon_state->vclk && radeon_state->dclk) 2276 return true; 2277 2278 return false; 2279 } 2280 2281 static int si_populate_power_containment_values(struct radeon_device *rdev, 2282 struct radeon_ps *radeon_state, 2283 SISLANDS_SMC_SWSTATE *smc_state) 2284 { 2285 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2286 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2287 struct ni_ps *state = ni_get_ps(radeon_state); 2288 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2289 u32 prev_sclk; 2290 u32 max_sclk; 2291 u32 min_sclk; 2292 u16 prev_std_vddc; 2293 u16 curr_std_vddc; 2294 int i; 2295 u16 pwr_efficiency_ratio; 2296 u8 max_ps_percent; 2297 bool disable_uvd_power_tune; 2298 int ret; 2299 2300 if (ni_pi->enable_power_containment == false) 2301 return 0; 2302 2303 if (state->performance_level_count == 0) 2304 return -EINVAL; 2305 2306 if (smc_state->levelCount != state->performance_level_count) 2307 return -EINVAL; 2308 2309 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2310 2311 smc_state->levels[0].dpm2.MaxPS = 0; 2312 smc_state->levels[0].dpm2.NearTDPDec = 0; 2313 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2314 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2315 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2316 2317 for (i = 1; i < state->performance_level_count; i++) { 2318 prev_sclk = state->performance_levels[i-1].sclk; 2319 max_sclk = state->performance_levels[i].sclk; 2320 if (i == 1) 2321 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2322 else 2323 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2324 2325 if (prev_sclk > max_sclk) 2326 return -EINVAL; 2327 2328 if ((max_ps_percent == 0) || 2329 (prev_sclk == max_sclk) || 2330 disable_uvd_power_tune) { 2331 min_sclk = max_sclk; 2332 } else if (i == 1) { 2333 min_sclk = prev_sclk; 2334 } else { 2335 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2336 } 2337 2338 if (min_sclk < state->performance_levels[0].sclk) 2339 min_sclk = state->performance_levels[0].sclk; 2340 2341 if (min_sclk == 0) 2342 return -EINVAL; 2343 2344 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2345 state->performance_levels[i-1].vddc, &vddc); 2346 if (ret) 2347 return ret; 2348 2349 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2350 if (ret) 2351 return ret; 2352 2353 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2354 state->performance_levels[i].vddc, &vddc); 2355 if (ret) 2356 return ret; 2357 2358 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2359 if (ret) 2360 return ret; 2361 2362 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2363 prev_std_vddc, curr_std_vddc); 2364 2365 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2366 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2367 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2368 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2369 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2370 } 2371 2372 return 0; 2373 } 2374 2375 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2376 struct radeon_ps *radeon_state, 2377 SISLANDS_SMC_SWSTATE *smc_state) 2378 { 2379 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2380 struct ni_ps *state = ni_get_ps(radeon_state); 2381 u32 sq_power_throttle, sq_power_throttle2; 2382 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2383 int i; 2384 2385 if (state->performance_level_count == 0) 2386 return -EINVAL; 2387 2388 if (smc_state->levelCount != state->performance_level_count) 2389 return -EINVAL; 2390 2391 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2392 return -EINVAL; 2393 2394 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2395 enable_sq_ramping = false; 2396 2397 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2398 enable_sq_ramping = false; 2399 2400 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2401 enable_sq_ramping = false; 2402 2403 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2404 enable_sq_ramping = false; 2405 2406 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2407 enable_sq_ramping = false; 2408 2409 for (i = 0; i < state->performance_level_count; i++) { 2410 sq_power_throttle = 0; 2411 sq_power_throttle2 = 0; 2412 2413 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2414 enable_sq_ramping) { 2415 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2416 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2417 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2418 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2419 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2420 } else { 2421 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2422 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2423 } 2424 2425 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2426 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2427 } 2428 2429 return 0; 2430 } 2431 2432 static int si_enable_power_containment(struct radeon_device *rdev, 2433 struct radeon_ps *radeon_new_state, 2434 bool enable) 2435 { 2436 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2437 PPSMC_Result smc_result; 2438 int ret = 0; 2439 2440 if (ni_pi->enable_power_containment) { 2441 if (enable) { 2442 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2443 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2444 if (smc_result != PPSMC_Result_OK) { 2445 ret = -EINVAL; 2446 ni_pi->pc_enabled = false; 2447 } else { 2448 ni_pi->pc_enabled = true; 2449 } 2450 } 2451 } else { 2452 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2453 if (smc_result != PPSMC_Result_OK) 2454 ret = -EINVAL; 2455 ni_pi->pc_enabled = false; 2456 } 2457 } 2458 2459 return ret; 2460 } 2461 2462 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2463 { 2464 struct si_power_info *si_pi = si_get_pi(rdev); 2465 int ret = 0; 2466 struct si_dte_data *dte_data = &si_pi->dte_data; 2467 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2468 u32 table_size; 2469 u8 tdep_count; 2470 u32 i; 2471 2472 if (dte_data == NULL) 2473 si_pi->enable_dte = false; 2474 2475 if (si_pi->enable_dte == false) 2476 return 0; 2477 2478 if (dte_data->k <= 0) 2479 return -EINVAL; 2480 2481 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2482 if (dte_tables == NULL) { 2483 si_pi->enable_dte = false; 2484 return -ENOMEM; 2485 } 2486 2487 table_size = dte_data->k; 2488 2489 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2490 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2491 2492 tdep_count = dte_data->tdep_count; 2493 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2494 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2495 2496 dte_tables->K = cpu_to_be32(table_size); 2497 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2498 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2499 dte_tables->WindowSize = dte_data->window_size; 2500 dte_tables->temp_select = dte_data->temp_select; 2501 dte_tables->DTE_mode = dte_data->dte_mode; 2502 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2503 2504 if (tdep_count > 0) 2505 table_size--; 2506 2507 for (i = 0; i < table_size; i++) { 2508 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2509 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2510 } 2511 2512 dte_tables->Tdep_count = tdep_count; 2513 2514 for (i = 0; i < (u32)tdep_count; i++) { 2515 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2516 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2517 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2518 } 2519 2520 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2521 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2522 kfree(dte_tables); 2523 2524 return ret; 2525 } 2526 2527 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2528 u16 *max, u16 *min) 2529 { 2530 struct si_power_info *si_pi = si_get_pi(rdev); 2531 struct radeon_cac_leakage_table *table = 2532 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2533 u32 i; 2534 u32 v0_loadline; 2535 2536 2537 if (table == NULL) 2538 return -EINVAL; 2539 2540 *max = 0; 2541 *min = 0xFFFF; 2542 2543 for (i = 0; i < table->count; i++) { 2544 if (table->entries[i].vddc > *max) 2545 *max = table->entries[i].vddc; 2546 if (table->entries[i].vddc < *min) 2547 *min = table->entries[i].vddc; 2548 } 2549 2550 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2551 return -EINVAL; 2552 2553 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2554 2555 if (v0_loadline > 0xFFFFUL) 2556 return -EINVAL; 2557 2558 *min = (u16)v0_loadline; 2559 2560 if ((*min > *max) || (*max == 0) || (*min == 0)) 2561 return -EINVAL; 2562 2563 return 0; 2564 } 2565 2566 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2567 { 2568 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2569 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2570 } 2571 2572 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2573 PP_SIslands_CacConfig *cac_tables, 2574 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2575 u16 t0, u16 t_step) 2576 { 2577 struct si_power_info *si_pi = si_get_pi(rdev); 2578 u32 leakage; 2579 unsigned int i, j; 2580 s32 t; 2581 u32 smc_leakage; 2582 u32 scaling_factor; 2583 u16 voltage; 2584 2585 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2586 2587 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2588 t = (1000 * (i * t_step + t0)); 2589 2590 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2591 voltage = vddc_max - (vddc_step * j); 2592 2593 si_calculate_leakage_for_v_and_t(rdev, 2594 &si_pi->powertune_data->leakage_coefficients, 2595 voltage, 2596 t, 2597 si_pi->dyn_powertune_data.cac_leakage, 2598 &leakage); 2599 2600 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2601 2602 if (smc_leakage > 0xFFFF) 2603 smc_leakage = 0xFFFF; 2604 2605 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2606 cpu_to_be16((u16)smc_leakage); 2607 } 2608 } 2609 return 0; 2610 } 2611 2612 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2613 PP_SIslands_CacConfig *cac_tables, 2614 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2615 { 2616 struct si_power_info *si_pi = si_get_pi(rdev); 2617 u32 leakage; 2618 unsigned int i, j; 2619 u32 smc_leakage; 2620 u32 scaling_factor; 2621 u16 voltage; 2622 2623 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2624 2625 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2626 voltage = vddc_max - (vddc_step * j); 2627 2628 si_calculate_leakage_for_v(rdev, 2629 &si_pi->powertune_data->leakage_coefficients, 2630 si_pi->powertune_data->fixed_kt, 2631 voltage, 2632 si_pi->dyn_powertune_data.cac_leakage, 2633 &leakage); 2634 2635 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2636 2637 if (smc_leakage > 0xFFFF) 2638 smc_leakage = 0xFFFF; 2639 2640 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2641 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2642 cpu_to_be16((u16)smc_leakage); 2643 } 2644 return 0; 2645 } 2646 2647 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2648 { 2649 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2650 struct si_power_info *si_pi = si_get_pi(rdev); 2651 PP_SIslands_CacConfig *cac_tables = NULL; 2652 u16 vddc_max, vddc_min, vddc_step; 2653 u16 t0, t_step; 2654 u32 load_line_slope, reg; 2655 int ret = 0; 2656 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2657 2658 if (ni_pi->enable_cac == false) 2659 return 0; 2660 2661 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2662 if (!cac_tables) 2663 return -ENOMEM; 2664 2665 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2666 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2667 WREG32(CG_CAC_CTRL, reg); 2668 2669 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2670 si_pi->dyn_powertune_data.dc_pwr_value = 2671 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2672 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2673 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2674 2675 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2676 2677 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2678 if (ret) 2679 goto done_free; 2680 2681 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2682 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2683 t_step = 4; 2684 t0 = 60; 2685 2686 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2687 ret = si_init_dte_leakage_table(rdev, cac_tables, 2688 vddc_max, vddc_min, vddc_step, 2689 t0, t_step); 2690 else 2691 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2692 vddc_max, vddc_min, vddc_step); 2693 if (ret) 2694 goto done_free; 2695 2696 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2697 2698 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2699 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2700 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2701 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2702 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2703 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2704 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2705 cac_tables->calculation_repeats = cpu_to_be32(2); 2706 cac_tables->dc_cac = cpu_to_be32(0); 2707 cac_tables->log2_PG_LKG_SCALE = 12; 2708 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2709 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2710 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2711 2712 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2713 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2714 2715 if (ret) 2716 goto done_free; 2717 2718 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2719 2720 done_free: 2721 if (ret) { 2722 ni_pi->enable_cac = false; 2723 ni_pi->enable_power_containment = false; 2724 } 2725 2726 kfree(cac_tables); 2727 2728 return 0; 2729 } 2730 2731 static int si_program_cac_config_registers(struct radeon_device *rdev, 2732 const struct si_cac_config_reg *cac_config_regs) 2733 { 2734 const struct si_cac_config_reg *config_regs = cac_config_regs; 2735 u32 data = 0, offset; 2736 2737 if (!config_regs) 2738 return -EINVAL; 2739 2740 while (config_regs->offset != 0xFFFFFFFF) { 2741 switch (config_regs->type) { 2742 case SISLANDS_CACCONFIG_CGIND: 2743 offset = SMC_CG_IND_START + config_regs->offset; 2744 if (offset < SMC_CG_IND_END) 2745 data = RREG32_SMC(offset); 2746 break; 2747 default: 2748 data = RREG32(config_regs->offset << 2); 2749 break; 2750 } 2751 2752 data &= ~config_regs->mask; 2753 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2754 2755 switch (config_regs->type) { 2756 case SISLANDS_CACCONFIG_CGIND: 2757 offset = SMC_CG_IND_START + config_regs->offset; 2758 if (offset < SMC_CG_IND_END) 2759 WREG32_SMC(offset, data); 2760 break; 2761 default: 2762 WREG32(config_regs->offset << 2, data); 2763 break; 2764 } 2765 config_regs++; 2766 } 2767 return 0; 2768 } 2769 2770 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2771 { 2772 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2773 struct si_power_info *si_pi = si_get_pi(rdev); 2774 int ret; 2775 2776 if ((ni_pi->enable_cac == false) || 2777 (ni_pi->cac_configuration_required == false)) 2778 return 0; 2779 2780 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2781 if (ret) 2782 return ret; 2783 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2784 if (ret) 2785 return ret; 2786 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2787 if (ret) 2788 return ret; 2789 2790 return 0; 2791 } 2792 2793 static int si_enable_smc_cac(struct radeon_device *rdev, 2794 struct radeon_ps *radeon_new_state, 2795 bool enable) 2796 { 2797 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2798 struct si_power_info *si_pi = si_get_pi(rdev); 2799 PPSMC_Result smc_result; 2800 int ret = 0; 2801 2802 if (ni_pi->enable_cac) { 2803 if (enable) { 2804 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2805 if (ni_pi->support_cac_long_term_average) { 2806 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2807 if (smc_result != PPSMC_Result_OK) 2808 ni_pi->support_cac_long_term_average = false; 2809 } 2810 2811 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2812 if (smc_result != PPSMC_Result_OK) { 2813 ret = -EINVAL; 2814 ni_pi->cac_enabled = false; 2815 } else { 2816 ni_pi->cac_enabled = true; 2817 } 2818 2819 if (si_pi->enable_dte) { 2820 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2821 if (smc_result != PPSMC_Result_OK) 2822 ret = -EINVAL; 2823 } 2824 } 2825 } else if (ni_pi->cac_enabled) { 2826 if (si_pi->enable_dte) 2827 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2828 2829 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2830 2831 ni_pi->cac_enabled = false; 2832 2833 if (ni_pi->support_cac_long_term_average) 2834 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2835 } 2836 } 2837 return ret; 2838 } 2839 2840 static int si_init_smc_spll_table(struct radeon_device *rdev) 2841 { 2842 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2843 struct si_power_info *si_pi = si_get_pi(rdev); 2844 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2845 SISLANDS_SMC_SCLK_VALUE sclk_params; 2846 u32 fb_div, p_div; 2847 u32 clk_s, clk_v; 2848 u32 sclk = 0; 2849 int ret = 0; 2850 u32 tmp; 2851 int i; 2852 2853 if (si_pi->spll_table_start == 0) 2854 return -EINVAL; 2855 2856 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2857 if (spll_table == NULL) 2858 return -ENOMEM; 2859 2860 for (i = 0; i < 256; i++) { 2861 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2862 if (ret) 2863 break; 2864 2865 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2866 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2867 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2868 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2869 2870 fb_div &= ~0x00001FFF; 2871 fb_div >>= 1; 2872 clk_v >>= 6; 2873 2874 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2875 ret = -EINVAL; 2876 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2877 ret = -EINVAL; 2878 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2879 ret = -EINVAL; 2880 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2881 ret = -EINVAL; 2882 2883 if (ret) 2884 break; 2885 2886 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2887 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2888 spll_table->freq[i] = cpu_to_be32(tmp); 2889 2890 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2891 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2892 spll_table->ss[i] = cpu_to_be32(tmp); 2893 2894 sclk += 512; 2895 } 2896 2897 2898 if (!ret) 2899 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2900 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2901 si_pi->sram_end); 2902 2903 if (ret) 2904 ni_pi->enable_power_containment = false; 2905 2906 kfree(spll_table); 2907 2908 return ret; 2909 } 2910 2911 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2912 struct radeon_ps *rps) 2913 { 2914 struct ni_ps *ps = ni_get_ps(rps); 2915 struct radeon_clock_and_voltage_limits *max_limits; 2916 bool disable_mclk_switching = false; 2917 bool disable_sclk_switching = false; 2918 u32 mclk, sclk; 2919 u16 vddc, vddci; 2920 int i; 2921 2922 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2923 ni_dpm_vblank_too_short(rdev)) 2924 disable_mclk_switching = true; 2925 2926 if (rps->vclk || rps->dclk) { 2927 disable_mclk_switching = true; 2928 disable_sclk_switching = true; 2929 } 2930 2931 if (rdev->pm.dpm.ac_power) 2932 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2933 else 2934 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2935 2936 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2937 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2938 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2939 } 2940 if (rdev->pm.dpm.ac_power == false) { 2941 for (i = 0; i < ps->performance_level_count; i++) { 2942 if (ps->performance_levels[i].mclk > max_limits->mclk) 2943 ps->performance_levels[i].mclk = max_limits->mclk; 2944 if (ps->performance_levels[i].sclk > max_limits->sclk) 2945 ps->performance_levels[i].sclk = max_limits->sclk; 2946 if (ps->performance_levels[i].vddc > max_limits->vddc) 2947 ps->performance_levels[i].vddc = max_limits->vddc; 2948 if (ps->performance_levels[i].vddci > max_limits->vddci) 2949 ps->performance_levels[i].vddci = max_limits->vddci; 2950 } 2951 } 2952 2953 /* XXX validate the min clocks required for display */ 2954 2955 if (disable_mclk_switching) { 2956 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2957 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2958 } else { 2959 mclk = ps->performance_levels[0].mclk; 2960 vddci = ps->performance_levels[0].vddci; 2961 } 2962 2963 if (disable_sclk_switching) { 2964 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 2965 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 2966 } else { 2967 sclk = ps->performance_levels[0].sclk; 2968 vddc = ps->performance_levels[0].vddc; 2969 } 2970 2971 /* adjusted low state */ 2972 ps->performance_levels[0].sclk = sclk; 2973 ps->performance_levels[0].mclk = mclk; 2974 ps->performance_levels[0].vddc = vddc; 2975 ps->performance_levels[0].vddci = vddci; 2976 2977 if (disable_sclk_switching) { 2978 sclk = ps->performance_levels[0].sclk; 2979 for (i = 1; i < ps->performance_level_count; i++) { 2980 if (sclk < ps->performance_levels[i].sclk) 2981 sclk = ps->performance_levels[i].sclk; 2982 } 2983 for (i = 0; i < ps->performance_level_count; i++) { 2984 ps->performance_levels[i].sclk = sclk; 2985 ps->performance_levels[i].vddc = vddc; 2986 } 2987 } else { 2988 for (i = 1; i < ps->performance_level_count; i++) { 2989 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 2990 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 2991 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 2992 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 2993 } 2994 } 2995 2996 if (disable_mclk_switching) { 2997 mclk = ps->performance_levels[0].mclk; 2998 for (i = 1; i < ps->performance_level_count; i++) { 2999 if (mclk < ps->performance_levels[i].mclk) 3000 mclk = ps->performance_levels[i].mclk; 3001 } 3002 for (i = 0; i < ps->performance_level_count; i++) { 3003 ps->performance_levels[i].mclk = mclk; 3004 ps->performance_levels[i].vddci = vddci; 3005 } 3006 } else { 3007 for (i = 1; i < ps->performance_level_count; i++) { 3008 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3009 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3010 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3011 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3012 } 3013 } 3014 3015 for (i = 0; i < ps->performance_level_count; i++) 3016 btc_adjust_clock_combinations(rdev, max_limits, 3017 &ps->performance_levels[i]); 3018 3019 for (i = 0; i < ps->performance_level_count; i++) { 3020 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3021 ps->performance_levels[i].sclk, 3022 max_limits->vddc, &ps->performance_levels[i].vddc); 3023 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3024 ps->performance_levels[i].mclk, 3025 max_limits->vddci, &ps->performance_levels[i].vddci); 3026 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3027 ps->performance_levels[i].mclk, 3028 max_limits->vddc, &ps->performance_levels[i].vddc); 3029 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3030 rdev->clock.current_dispclk, 3031 max_limits->vddc, &ps->performance_levels[i].vddc); 3032 } 3033 3034 for (i = 0; i < ps->performance_level_count; i++) { 3035 btc_apply_voltage_delta_rules(rdev, 3036 max_limits->vddc, max_limits->vddci, 3037 &ps->performance_levels[i].vddc, 3038 &ps->performance_levels[i].vddci); 3039 } 3040 3041 ps->dc_compatible = true; 3042 for (i = 0; i < ps->performance_level_count; i++) { 3043 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3044 ps->dc_compatible = false; 3045 } 3046 3047 } 3048 3049 #if 0 3050 static int si_read_smc_soft_register(struct radeon_device *rdev, 3051 u16 reg_offset, u32 *value) 3052 { 3053 struct si_power_info *si_pi = si_get_pi(rdev); 3054 3055 return si_read_smc_sram_dword(rdev, 3056 si_pi->soft_regs_start + reg_offset, value, 3057 si_pi->sram_end); 3058 } 3059 #endif 3060 3061 static int si_write_smc_soft_register(struct radeon_device *rdev, 3062 u16 reg_offset, u32 value) 3063 { 3064 struct si_power_info *si_pi = si_get_pi(rdev); 3065 3066 return si_write_smc_sram_dword(rdev, 3067 si_pi->soft_regs_start + reg_offset, 3068 value, si_pi->sram_end); 3069 } 3070 3071 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3072 { 3073 bool ret = false; 3074 u32 tmp, width, row, column, bank, density; 3075 bool is_memory_gddr5, is_special; 3076 3077 tmp = RREG32(MC_SEQ_MISC0); 3078 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3079 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3080 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3081 3082 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3083 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3084 3085 tmp = RREG32(MC_ARB_RAMCFG); 3086 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3087 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3088 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3089 3090 density = (1 << (row + column - 20 + bank)) * width; 3091 3092 if ((rdev->pdev->device == 0x6819) && 3093 is_memory_gddr5 && is_special && (density == 0x400)) 3094 ret = true; 3095 3096 return ret; 3097 } 3098 3099 static void si_get_leakage_vddc(struct radeon_device *rdev) 3100 { 3101 struct si_power_info *si_pi = si_get_pi(rdev); 3102 u16 vddc, count = 0; 3103 int i, ret; 3104 3105 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3106 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3107 3108 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3109 si_pi->leakage_voltage.entries[count].voltage = vddc; 3110 si_pi->leakage_voltage.entries[count].leakage_index = 3111 SISLANDS_LEAKAGE_INDEX0 + i; 3112 count++; 3113 } 3114 } 3115 si_pi->leakage_voltage.count = count; 3116 } 3117 3118 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3119 u32 index, u16 *leakage_voltage) 3120 { 3121 struct si_power_info *si_pi = si_get_pi(rdev); 3122 int i; 3123 3124 if (leakage_voltage == NULL) 3125 return -EINVAL; 3126 3127 if ((index & 0xff00) != 0xff00) 3128 return -EINVAL; 3129 3130 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3131 return -EINVAL; 3132 3133 if (index < SISLANDS_LEAKAGE_INDEX0) 3134 return -EINVAL; 3135 3136 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3137 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3138 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3139 return 0; 3140 } 3141 } 3142 return -EAGAIN; 3143 } 3144 3145 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3146 { 3147 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3148 bool want_thermal_protection; 3149 enum radeon_dpm_event_src dpm_event_src; 3150 3151 switch (sources) { 3152 case 0: 3153 default: 3154 want_thermal_protection = false; 3155 break; 3156 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3157 want_thermal_protection = true; 3158 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3159 break; 3160 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3161 want_thermal_protection = true; 3162 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3163 break; 3164 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3165 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3166 want_thermal_protection = true; 3167 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3168 break; 3169 } 3170 3171 if (want_thermal_protection) { 3172 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3173 if (pi->thermal_protection) 3174 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3175 } else { 3176 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3177 } 3178 } 3179 3180 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3181 enum radeon_dpm_auto_throttle_src source, 3182 bool enable) 3183 { 3184 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3185 3186 if (enable) { 3187 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3188 pi->active_auto_throttle_sources |= 1 << source; 3189 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3190 } 3191 } else { 3192 if (pi->active_auto_throttle_sources & (1 << source)) { 3193 pi->active_auto_throttle_sources &= ~(1 << source); 3194 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3195 } 3196 } 3197 } 3198 3199 static void si_start_dpm(struct radeon_device *rdev) 3200 { 3201 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3202 } 3203 3204 static void si_stop_dpm(struct radeon_device *rdev) 3205 { 3206 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3207 } 3208 3209 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3210 { 3211 if (enable) 3212 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3213 else 3214 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3215 3216 } 3217 3218 #if 0 3219 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3220 u32 thermal_level) 3221 { 3222 PPSMC_Result ret; 3223 3224 if (thermal_level == 0) { 3225 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3226 if (ret == PPSMC_Result_OK) 3227 return 0; 3228 else 3229 return -EINVAL; 3230 } 3231 return 0; 3232 } 3233 3234 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3235 { 3236 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3237 } 3238 #endif 3239 3240 #if 0 3241 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3242 { 3243 if (ac_power) 3244 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3245 0 : -EINVAL; 3246 3247 return 0; 3248 } 3249 #endif 3250 3251 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3252 PPSMC_Msg msg, u32 parameter) 3253 { 3254 WREG32(SMC_SCRATCH0, parameter); 3255 return si_send_msg_to_smc(rdev, msg); 3256 } 3257 3258 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3259 { 3260 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3261 return -EINVAL; 3262 3263 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3264 0 : -EINVAL; 3265 } 3266 3267 int si_dpm_force_performance_level(struct radeon_device *rdev, 3268 enum radeon_dpm_forced_level level) 3269 { 3270 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3271 struct ni_ps *ps = ni_get_ps(rps); 3272 u32 levels = ps->performance_level_count; 3273 3274 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3275 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3276 return -EINVAL; 3277 3278 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3279 return -EINVAL; 3280 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3281 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3282 return -EINVAL; 3283 3284 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3285 return -EINVAL; 3286 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3287 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3288 return -EINVAL; 3289 3290 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3291 return -EINVAL; 3292 } 3293 3294 rdev->pm.dpm.forced_level = level; 3295 3296 return 0; 3297 } 3298 3299 #if 0 3300 static int si_set_boot_state(struct radeon_device *rdev) 3301 { 3302 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3303 0 : -EINVAL; 3304 } 3305 #endif 3306 3307 static int si_set_sw_state(struct radeon_device *rdev) 3308 { 3309 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3310 0 : -EINVAL; 3311 } 3312 3313 static int si_halt_smc(struct radeon_device *rdev) 3314 { 3315 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3316 return -EINVAL; 3317 3318 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3319 0 : -EINVAL; 3320 } 3321 3322 static int si_resume_smc(struct radeon_device *rdev) 3323 { 3324 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3325 return -EINVAL; 3326 3327 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3328 0 : -EINVAL; 3329 } 3330 3331 static void si_dpm_start_smc(struct radeon_device *rdev) 3332 { 3333 si_program_jump_on_start(rdev); 3334 si_start_smc(rdev); 3335 si_start_smc_clock(rdev); 3336 } 3337 3338 static void si_dpm_stop_smc(struct radeon_device *rdev) 3339 { 3340 si_reset_smc(rdev); 3341 si_stop_smc_clock(rdev); 3342 } 3343 3344 static int si_process_firmware_header(struct radeon_device *rdev) 3345 { 3346 struct si_power_info *si_pi = si_get_pi(rdev); 3347 u32 tmp; 3348 int ret; 3349 3350 ret = si_read_smc_sram_dword(rdev, 3351 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3352 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3353 &tmp, si_pi->sram_end); 3354 if (ret) 3355 return ret; 3356 3357 si_pi->state_table_start = tmp; 3358 3359 ret = si_read_smc_sram_dword(rdev, 3360 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3361 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3362 &tmp, si_pi->sram_end); 3363 if (ret) 3364 return ret; 3365 3366 si_pi->soft_regs_start = tmp; 3367 3368 ret = si_read_smc_sram_dword(rdev, 3369 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3370 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3371 &tmp, si_pi->sram_end); 3372 if (ret) 3373 return ret; 3374 3375 si_pi->mc_reg_table_start = tmp; 3376 3377 ret = si_read_smc_sram_dword(rdev, 3378 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3379 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3380 &tmp, si_pi->sram_end); 3381 if (ret) 3382 return ret; 3383 3384 si_pi->arb_table_start = tmp; 3385 3386 ret = si_read_smc_sram_dword(rdev, 3387 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3388 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3389 &tmp, si_pi->sram_end); 3390 if (ret) 3391 return ret; 3392 3393 si_pi->cac_table_start = tmp; 3394 3395 ret = si_read_smc_sram_dword(rdev, 3396 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3397 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3398 &tmp, si_pi->sram_end); 3399 if (ret) 3400 return ret; 3401 3402 si_pi->dte_table_start = tmp; 3403 3404 ret = si_read_smc_sram_dword(rdev, 3405 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3406 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3407 &tmp, si_pi->sram_end); 3408 if (ret) 3409 return ret; 3410 3411 si_pi->spll_table_start = tmp; 3412 3413 ret = si_read_smc_sram_dword(rdev, 3414 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3415 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3416 &tmp, si_pi->sram_end); 3417 if (ret) 3418 return ret; 3419 3420 si_pi->papm_cfg_table_start = tmp; 3421 3422 return ret; 3423 } 3424 3425 static void si_read_clock_registers(struct radeon_device *rdev) 3426 { 3427 struct si_power_info *si_pi = si_get_pi(rdev); 3428 3429 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3430 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3431 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3432 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3433 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3434 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3435 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3436 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3437 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3438 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3439 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3440 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3441 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3442 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3443 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3444 } 3445 3446 static void si_enable_thermal_protection(struct radeon_device *rdev, 3447 bool enable) 3448 { 3449 if (enable) 3450 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3451 else 3452 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3453 } 3454 3455 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3456 { 3457 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3458 } 3459 3460 #if 0 3461 static int si_enter_ulp_state(struct radeon_device *rdev) 3462 { 3463 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3464 3465 udelay(25000); 3466 3467 return 0; 3468 } 3469 3470 static int si_exit_ulp_state(struct radeon_device *rdev) 3471 { 3472 int i; 3473 3474 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3475 3476 udelay(7000); 3477 3478 for (i = 0; i < rdev->usec_timeout; i++) { 3479 if (RREG32(SMC_RESP_0) == 1) 3480 break; 3481 udelay(1000); 3482 } 3483 3484 return 0; 3485 } 3486 #endif 3487 3488 static int si_notify_smc_display_change(struct radeon_device *rdev, 3489 bool has_display) 3490 { 3491 PPSMC_Msg msg = has_display ? 3492 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3493 3494 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3495 0 : -EINVAL; 3496 } 3497 3498 static void si_program_response_times(struct radeon_device *rdev) 3499 { 3500 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3501 u32 vddc_dly, acpi_dly, vbi_dly; 3502 u32 reference_clock; 3503 3504 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3505 3506 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3507 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3508 3509 if (voltage_response_time == 0) 3510 voltage_response_time = 1000; 3511 3512 acpi_delay_time = 15000; 3513 vbi_time_out = 100000; 3514 3515 reference_clock = radeon_get_xclk(rdev); 3516 3517 vddc_dly = (voltage_response_time * reference_clock) / 100; 3518 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3519 vbi_dly = (vbi_time_out * reference_clock) / 100; 3520 3521 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3522 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3523 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3524 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3525 } 3526 3527 static void si_program_ds_registers(struct radeon_device *rdev) 3528 { 3529 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3530 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3531 3532 if (eg_pi->sclk_deep_sleep) { 3533 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3534 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3535 ~AUTOSCALE_ON_SS_CLEAR); 3536 } 3537 } 3538 3539 static void si_program_display_gap(struct radeon_device *rdev) 3540 { 3541 u32 tmp, pipe; 3542 int i; 3543 3544 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3545 if (rdev->pm.dpm.new_active_crtc_count > 0) 3546 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3547 else 3548 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3549 3550 if (rdev->pm.dpm.new_active_crtc_count > 1) 3551 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3552 else 3553 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3554 3555 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3556 3557 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3558 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3559 3560 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3561 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3562 /* find the first active crtc */ 3563 for (i = 0; i < rdev->num_crtc; i++) { 3564 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3565 break; 3566 } 3567 if (i == rdev->num_crtc) 3568 pipe = 0; 3569 else 3570 pipe = i; 3571 3572 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3573 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3574 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3575 } 3576 3577 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3578 * This can be a problem on PowerXpress systems or if you want to use the card 3579 * for offscreen rendering or compute if there are no crtcs enabled. 3580 */ 3581 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3582 } 3583 3584 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3585 { 3586 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3587 3588 if (enable) { 3589 if (pi->sclk_ss) 3590 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3591 } else { 3592 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3593 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3594 } 3595 } 3596 3597 static void si_setup_bsp(struct radeon_device *rdev) 3598 { 3599 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3600 u32 xclk = radeon_get_xclk(rdev); 3601 3602 r600_calculate_u_and_p(pi->asi, 3603 xclk, 3604 16, 3605 &pi->bsp, 3606 &pi->bsu); 3607 3608 r600_calculate_u_and_p(pi->pasi, 3609 xclk, 3610 16, 3611 &pi->pbsp, 3612 &pi->pbsu); 3613 3614 3615 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3616 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3617 3618 WREG32(CG_BSP, pi->dsp); 3619 } 3620 3621 static void si_program_git(struct radeon_device *rdev) 3622 { 3623 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3624 } 3625 3626 static void si_program_tp(struct radeon_device *rdev) 3627 { 3628 int i; 3629 enum r600_td td = R600_TD_DFLT; 3630 3631 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3632 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3633 3634 if (td == R600_TD_AUTO) 3635 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3636 else 3637 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3638 3639 if (td == R600_TD_UP) 3640 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3641 3642 if (td == R600_TD_DOWN) 3643 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3644 } 3645 3646 static void si_program_tpp(struct radeon_device *rdev) 3647 { 3648 WREG32(CG_TPC, R600_TPC_DFLT); 3649 } 3650 3651 static void si_program_sstp(struct radeon_device *rdev) 3652 { 3653 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3654 } 3655 3656 static void si_enable_display_gap(struct radeon_device *rdev) 3657 { 3658 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3659 3660 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3661 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3662 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3663 3664 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3665 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3666 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3667 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3668 } 3669 3670 static void si_program_vc(struct radeon_device *rdev) 3671 { 3672 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3673 3674 WREG32(CG_FTV, pi->vrc); 3675 } 3676 3677 static void si_clear_vc(struct radeon_device *rdev) 3678 { 3679 WREG32(CG_FTV, 0); 3680 } 3681 3682 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3683 { 3684 u8 mc_para_index; 3685 3686 if (memory_clock < 10000) 3687 mc_para_index = 0; 3688 else if (memory_clock >= 80000) 3689 mc_para_index = 0x0f; 3690 else 3691 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3692 return mc_para_index; 3693 } 3694 3695 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3696 { 3697 u8 mc_para_index; 3698 3699 if (strobe_mode) { 3700 if (memory_clock < 12500) 3701 mc_para_index = 0x00; 3702 else if (memory_clock > 47500) 3703 mc_para_index = 0x0f; 3704 else 3705 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3706 } else { 3707 if (memory_clock < 65000) 3708 mc_para_index = 0x00; 3709 else if (memory_clock > 135000) 3710 mc_para_index = 0x0f; 3711 else 3712 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3713 } 3714 return mc_para_index; 3715 } 3716 3717 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3718 { 3719 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3720 bool strobe_mode = false; 3721 u8 result = 0; 3722 3723 if (mclk <= pi->mclk_strobe_mode_threshold) 3724 strobe_mode = true; 3725 3726 if (pi->mem_gddr5) 3727 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3728 else 3729 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3730 3731 if (strobe_mode) 3732 result |= SISLANDS_SMC_STROBE_ENABLE; 3733 3734 return result; 3735 } 3736 3737 static int si_upload_firmware(struct radeon_device *rdev) 3738 { 3739 struct si_power_info *si_pi = si_get_pi(rdev); 3740 int ret; 3741 3742 si_reset_smc(rdev); 3743 si_stop_smc_clock(rdev); 3744 3745 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3746 3747 return ret; 3748 } 3749 3750 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3751 const struct atom_voltage_table *table, 3752 const struct radeon_phase_shedding_limits_table *limits) 3753 { 3754 u32 data, num_bits, num_levels; 3755 3756 if ((table == NULL) || (limits == NULL)) 3757 return false; 3758 3759 data = table->mask_low; 3760 3761 num_bits = hweight32(data); 3762 3763 if (num_bits == 0) 3764 return false; 3765 3766 num_levels = (1 << num_bits); 3767 3768 if (table->count != num_levels) 3769 return false; 3770 3771 if (limits->count != (num_levels - 1)) 3772 return false; 3773 3774 return true; 3775 } 3776 3777 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3778 u32 max_voltage_steps, 3779 struct atom_voltage_table *voltage_table) 3780 { 3781 unsigned int i, diff; 3782 3783 if (voltage_table->count <= max_voltage_steps) 3784 return; 3785 3786 diff = voltage_table->count - max_voltage_steps; 3787 3788 for (i= 0; i < max_voltage_steps; i++) 3789 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3790 3791 voltage_table->count = max_voltage_steps; 3792 } 3793 3794 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3795 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3796 struct atom_voltage_table *voltage_table) 3797 { 3798 u32 i; 3799 3800 if (voltage_dependency_table == NULL) 3801 return -EINVAL; 3802 3803 voltage_table->mask_low = 0; 3804 voltage_table->phase_delay = 0; 3805 3806 voltage_table->count = voltage_dependency_table->count; 3807 for (i = 0; i < voltage_table->count; i++) { 3808 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3809 voltage_table->entries[i].smio_low = 0; 3810 } 3811 3812 return 0; 3813 } 3814 3815 static int si_construct_voltage_tables(struct radeon_device *rdev) 3816 { 3817 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3818 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3819 struct si_power_info *si_pi = si_get_pi(rdev); 3820 int ret; 3821 3822 if (pi->voltage_control) { 3823 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3824 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3825 if (ret) 3826 return ret; 3827 3828 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3829 si_trim_voltage_table_to_fit_state_table(rdev, 3830 SISLANDS_MAX_NO_VREG_STEPS, 3831 &eg_pi->vddc_voltage_table); 3832 } else if (si_pi->voltage_control_svi2) { 3833 ret = si_get_svi2_voltage_table(rdev, 3834 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3835 &eg_pi->vddc_voltage_table); 3836 if (ret) 3837 return ret; 3838 } else { 3839 return -EINVAL; 3840 } 3841 3842 if (eg_pi->vddci_control) { 3843 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3844 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3845 if (ret) 3846 return ret; 3847 3848 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3849 si_trim_voltage_table_to_fit_state_table(rdev, 3850 SISLANDS_MAX_NO_VREG_STEPS, 3851 &eg_pi->vddci_voltage_table); 3852 } 3853 if (si_pi->vddci_control_svi2) { 3854 ret = si_get_svi2_voltage_table(rdev, 3855 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3856 &eg_pi->vddci_voltage_table); 3857 if (ret) 3858 return ret; 3859 } 3860 3861 if (pi->mvdd_control) { 3862 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3863 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3864 3865 if (ret) { 3866 pi->mvdd_control = false; 3867 return ret; 3868 } 3869 3870 if (si_pi->mvdd_voltage_table.count == 0) { 3871 pi->mvdd_control = false; 3872 return -EINVAL; 3873 } 3874 3875 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3876 si_trim_voltage_table_to_fit_state_table(rdev, 3877 SISLANDS_MAX_NO_VREG_STEPS, 3878 &si_pi->mvdd_voltage_table); 3879 } 3880 3881 if (si_pi->vddc_phase_shed_control) { 3882 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3883 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3884 if (ret) 3885 si_pi->vddc_phase_shed_control = false; 3886 3887 if ((si_pi->vddc_phase_shed_table.count == 0) || 3888 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3889 si_pi->vddc_phase_shed_control = false; 3890 } 3891 3892 return 0; 3893 } 3894 3895 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3896 const struct atom_voltage_table *voltage_table, 3897 SISLANDS_SMC_STATETABLE *table) 3898 { 3899 unsigned int i; 3900 3901 for (i = 0; i < voltage_table->count; i++) 3902 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3903 } 3904 3905 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3906 SISLANDS_SMC_STATETABLE *table) 3907 { 3908 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3909 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3910 struct si_power_info *si_pi = si_get_pi(rdev); 3911 u8 i; 3912 3913 if (si_pi->voltage_control_svi2) { 3914 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 3915 si_pi->svc_gpio_id); 3916 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 3917 si_pi->svd_gpio_id); 3918 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 3919 2); 3920 } else { 3921 if (eg_pi->vddc_voltage_table.count) { 3922 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3923 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3924 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 3925 3926 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 3927 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 3928 table->maxVDDCIndexInPPTable = i; 3929 break; 3930 } 3931 } 3932 } 3933 3934 if (eg_pi->vddci_voltage_table.count) { 3935 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 3936 3937 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 3938 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 3939 } 3940 3941 3942 if (si_pi->mvdd_voltage_table.count) { 3943 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 3944 3945 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 3946 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 3947 } 3948 3949 if (si_pi->vddc_phase_shed_control) { 3950 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 3951 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 3952 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 3953 3954 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3955 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 3956 3957 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 3958 (u32)si_pi->vddc_phase_shed_table.phase_delay); 3959 } else { 3960 si_pi->vddc_phase_shed_control = false; 3961 } 3962 } 3963 } 3964 3965 return 0; 3966 } 3967 3968 static int si_populate_voltage_value(struct radeon_device *rdev, 3969 const struct atom_voltage_table *table, 3970 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3971 { 3972 unsigned int i; 3973 3974 for (i = 0; i < table->count; i++) { 3975 if (value <= table->entries[i].value) { 3976 voltage->index = (u8)i; 3977 voltage->value = cpu_to_be16(table->entries[i].value); 3978 break; 3979 } 3980 } 3981 3982 if (i >= table->count) 3983 return -EINVAL; 3984 3985 return 0; 3986 } 3987 3988 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 3989 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3990 { 3991 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3992 struct si_power_info *si_pi = si_get_pi(rdev); 3993 3994 if (pi->mvdd_control) { 3995 if (mclk <= pi->mvdd_split_frequency) 3996 voltage->index = 0; 3997 else 3998 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 3999 4000 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4001 } 4002 return 0; 4003 } 4004 4005 static int si_get_std_voltage_value(struct radeon_device *rdev, 4006 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4007 u16 *std_voltage) 4008 { 4009 u16 v_index; 4010 bool voltage_found = false; 4011 *std_voltage = be16_to_cpu(voltage->value); 4012 4013 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4014 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4015 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4016 return -EINVAL; 4017 4018 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4019 if (be16_to_cpu(voltage->value) == 4020 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4021 voltage_found = true; 4022 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4023 *std_voltage = 4024 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4025 else 4026 *std_voltage = 4027 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4028 break; 4029 } 4030 } 4031 4032 if (!voltage_found) { 4033 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4034 if (be16_to_cpu(voltage->value) <= 4035 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4036 voltage_found = true; 4037 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4038 *std_voltage = 4039 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4040 else 4041 *std_voltage = 4042 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4043 break; 4044 } 4045 } 4046 } 4047 } else { 4048 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4049 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4050 } 4051 } 4052 4053 return 0; 4054 } 4055 4056 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4057 u16 value, u8 index, 4058 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4059 { 4060 voltage->index = index; 4061 voltage->value = cpu_to_be16(value); 4062 4063 return 0; 4064 } 4065 4066 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4067 const struct radeon_phase_shedding_limits_table *limits, 4068 u16 voltage, u32 sclk, u32 mclk, 4069 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4070 { 4071 unsigned int i; 4072 4073 for (i = 0; i < limits->count; i++) { 4074 if ((voltage <= limits->entries[i].voltage) && 4075 (sclk <= limits->entries[i].sclk) && 4076 (mclk <= limits->entries[i].mclk)) 4077 break; 4078 } 4079 4080 smc_voltage->phase_settings = (u8)i; 4081 4082 return 0; 4083 } 4084 4085 static int si_init_arb_table_index(struct radeon_device *rdev) 4086 { 4087 struct si_power_info *si_pi = si_get_pi(rdev); 4088 u32 tmp; 4089 int ret; 4090 4091 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4092 if (ret) 4093 return ret; 4094 4095 tmp &= 0x00FFFFFF; 4096 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4097 4098 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4099 } 4100 4101 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4102 { 4103 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4104 } 4105 4106 static int si_reset_to_default(struct radeon_device *rdev) 4107 { 4108 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4109 0 : -EINVAL; 4110 } 4111 4112 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4113 { 4114 struct si_power_info *si_pi = si_get_pi(rdev); 4115 u32 tmp; 4116 int ret; 4117 4118 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4119 &tmp, si_pi->sram_end); 4120 if (ret) 4121 return ret; 4122 4123 tmp = (tmp >> 24) & 0xff; 4124 4125 if (tmp == MC_CG_ARB_FREQ_F0) 4126 return 0; 4127 4128 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4129 } 4130 4131 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4132 u32 engine_clock) 4133 { 4134 u32 dram_rows; 4135 u32 dram_refresh_rate; 4136 u32 mc_arb_rfsh_rate; 4137 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4138 4139 if (tmp >= 4) 4140 dram_rows = 16384; 4141 else 4142 dram_rows = 1 << (tmp + 10); 4143 4144 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4145 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4146 4147 return mc_arb_rfsh_rate; 4148 } 4149 4150 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4151 struct rv7xx_pl *pl, 4152 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4153 { 4154 u32 dram_timing; 4155 u32 dram_timing2; 4156 u32 burst_time; 4157 4158 arb_regs->mc_arb_rfsh_rate = 4159 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4160 4161 radeon_atom_set_engine_dram_timings(rdev, 4162 pl->sclk, 4163 pl->mclk); 4164 4165 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4166 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4167 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4168 4169 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4170 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4171 arb_regs->mc_arb_burst_time = (u8)burst_time; 4172 4173 return 0; 4174 } 4175 4176 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4177 struct radeon_ps *radeon_state, 4178 unsigned int first_arb_set) 4179 { 4180 struct si_power_info *si_pi = si_get_pi(rdev); 4181 struct ni_ps *state = ni_get_ps(radeon_state); 4182 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4183 int i, ret = 0; 4184 4185 for (i = 0; i < state->performance_level_count; i++) { 4186 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4187 if (ret) 4188 break; 4189 ret = si_copy_bytes_to_smc(rdev, 4190 si_pi->arb_table_start + 4191 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4192 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4193 (u8 *)&arb_regs, 4194 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4195 si_pi->sram_end); 4196 if (ret) 4197 break; 4198 } 4199 4200 return ret; 4201 } 4202 4203 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4204 struct radeon_ps *radeon_new_state) 4205 { 4206 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4207 SISLANDS_DRIVER_STATE_ARB_INDEX); 4208 } 4209 4210 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4211 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4212 { 4213 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4214 struct si_power_info *si_pi = si_get_pi(rdev); 4215 4216 if (pi->mvdd_control) 4217 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4218 si_pi->mvdd_bootup_value, voltage); 4219 4220 return 0; 4221 } 4222 4223 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4224 struct radeon_ps *radeon_initial_state, 4225 SISLANDS_SMC_STATETABLE *table) 4226 { 4227 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4228 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4229 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4230 struct si_power_info *si_pi = si_get_pi(rdev); 4231 u32 reg; 4232 int ret; 4233 4234 table->initialState.levels[0].mclk.vDLL_CNTL = 4235 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4236 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4237 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4238 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4239 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4240 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4241 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4242 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4243 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4244 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4245 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4246 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4247 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4248 table->initialState.levels[0].mclk.vMPLL_SS = 4249 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4250 table->initialState.levels[0].mclk.vMPLL_SS2 = 4251 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4252 4253 table->initialState.levels[0].mclk.mclk_value = 4254 cpu_to_be32(initial_state->performance_levels[0].mclk); 4255 4256 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4257 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4258 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4259 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4260 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4261 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4262 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4263 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4264 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4265 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4266 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4267 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4268 4269 table->initialState.levels[0].sclk.sclk_value = 4270 cpu_to_be32(initial_state->performance_levels[0].sclk); 4271 4272 table->initialState.levels[0].arbRefreshState = 4273 SISLANDS_INITIAL_STATE_ARB_INDEX; 4274 4275 table->initialState.levels[0].ACIndex = 0; 4276 4277 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4278 initial_state->performance_levels[0].vddc, 4279 &table->initialState.levels[0].vddc); 4280 4281 if (!ret) { 4282 u16 std_vddc; 4283 4284 ret = si_get_std_voltage_value(rdev, 4285 &table->initialState.levels[0].vddc, 4286 &std_vddc); 4287 if (!ret) 4288 si_populate_std_voltage_value(rdev, std_vddc, 4289 table->initialState.levels[0].vddc.index, 4290 &table->initialState.levels[0].std_vddc); 4291 } 4292 4293 if (eg_pi->vddci_control) 4294 si_populate_voltage_value(rdev, 4295 &eg_pi->vddci_voltage_table, 4296 initial_state->performance_levels[0].vddci, 4297 &table->initialState.levels[0].vddci); 4298 4299 if (si_pi->vddc_phase_shed_control) 4300 si_populate_phase_shedding_value(rdev, 4301 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4302 initial_state->performance_levels[0].vddc, 4303 initial_state->performance_levels[0].sclk, 4304 initial_state->performance_levels[0].mclk, 4305 &table->initialState.levels[0].vddc); 4306 4307 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4308 4309 reg = CG_R(0xffff) | CG_L(0); 4310 table->initialState.levels[0].aT = cpu_to_be32(reg); 4311 4312 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4313 4314 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4315 4316 if (pi->mem_gddr5) { 4317 table->initialState.levels[0].strobeMode = 4318 si_get_strobe_mode_settings(rdev, 4319 initial_state->performance_levels[0].mclk); 4320 4321 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4322 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4323 else 4324 table->initialState.levels[0].mcFlags = 0; 4325 } 4326 4327 table->initialState.levelCount = 1; 4328 4329 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4330 4331 table->initialState.levels[0].dpm2.MaxPS = 0; 4332 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4333 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4334 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4335 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4336 4337 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4338 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4339 4340 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4341 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4342 4343 return 0; 4344 } 4345 4346 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4347 SISLANDS_SMC_STATETABLE *table) 4348 { 4349 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4350 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4351 struct si_power_info *si_pi = si_get_pi(rdev); 4352 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4353 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4354 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4355 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4356 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4357 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4358 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4359 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4360 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4361 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4362 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4363 u32 reg; 4364 int ret; 4365 4366 table->ACPIState = table->initialState; 4367 4368 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4369 4370 if (pi->acpi_vddc) { 4371 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4372 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4373 if (!ret) { 4374 u16 std_vddc; 4375 4376 ret = si_get_std_voltage_value(rdev, 4377 &table->ACPIState.levels[0].vddc, &std_vddc); 4378 if (!ret) 4379 si_populate_std_voltage_value(rdev, std_vddc, 4380 table->ACPIState.levels[0].vddc.index, 4381 &table->ACPIState.levels[0].std_vddc); 4382 } 4383 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4384 4385 if (si_pi->vddc_phase_shed_control) { 4386 si_populate_phase_shedding_value(rdev, 4387 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4388 pi->acpi_vddc, 4389 0, 4390 0, 4391 &table->ACPIState.levels[0].vddc); 4392 } 4393 } else { 4394 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4395 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4396 if (!ret) { 4397 u16 std_vddc; 4398 4399 ret = si_get_std_voltage_value(rdev, 4400 &table->ACPIState.levels[0].vddc, &std_vddc); 4401 4402 if (!ret) 4403 si_populate_std_voltage_value(rdev, std_vddc, 4404 table->ACPIState.levels[0].vddc.index, 4405 &table->ACPIState.levels[0].std_vddc); 4406 } 4407 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4408 si_pi->sys_pcie_mask, 4409 si_pi->boot_pcie_gen, 4410 RADEON_PCIE_GEN1); 4411 4412 if (si_pi->vddc_phase_shed_control) 4413 si_populate_phase_shedding_value(rdev, 4414 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4415 pi->min_vddc_in_table, 4416 0, 4417 0, 4418 &table->ACPIState.levels[0].vddc); 4419 } 4420 4421 if (pi->acpi_vddc) { 4422 if (eg_pi->acpi_vddci) 4423 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4424 eg_pi->acpi_vddci, 4425 &table->ACPIState.levels[0].vddci); 4426 } 4427 4428 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4429 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4430 4431 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4432 4433 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4434 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4435 4436 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4437 cpu_to_be32(dll_cntl); 4438 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4439 cpu_to_be32(mclk_pwrmgt_cntl); 4440 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4441 cpu_to_be32(mpll_ad_func_cntl); 4442 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4443 cpu_to_be32(mpll_dq_func_cntl); 4444 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4445 cpu_to_be32(mpll_func_cntl); 4446 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4447 cpu_to_be32(mpll_func_cntl_1); 4448 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4449 cpu_to_be32(mpll_func_cntl_2); 4450 table->ACPIState.levels[0].mclk.vMPLL_SS = 4451 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4452 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4453 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4454 4455 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4456 cpu_to_be32(spll_func_cntl); 4457 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4458 cpu_to_be32(spll_func_cntl_2); 4459 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4460 cpu_to_be32(spll_func_cntl_3); 4461 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4462 cpu_to_be32(spll_func_cntl_4); 4463 4464 table->ACPIState.levels[0].mclk.mclk_value = 0; 4465 table->ACPIState.levels[0].sclk.sclk_value = 0; 4466 4467 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4468 4469 if (eg_pi->dynamic_ac_timing) 4470 table->ACPIState.levels[0].ACIndex = 0; 4471 4472 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4473 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4474 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4475 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4476 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4477 4478 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4479 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4480 4481 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4482 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4483 4484 return 0; 4485 } 4486 4487 static int si_populate_ulv_state(struct radeon_device *rdev, 4488 SISLANDS_SMC_SWSTATE *state) 4489 { 4490 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4491 struct si_power_info *si_pi = si_get_pi(rdev); 4492 struct si_ulv_param *ulv = &si_pi->ulv; 4493 u32 sclk_in_sr = 1350; /* ??? */ 4494 int ret; 4495 4496 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4497 &state->levels[0]); 4498 if (!ret) { 4499 if (eg_pi->sclk_deep_sleep) { 4500 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4501 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4502 else 4503 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4504 } 4505 if (ulv->one_pcie_lane_in_ulv) 4506 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4507 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4508 state->levels[0].ACIndex = 1; 4509 state->levels[0].std_vddc = state->levels[0].vddc; 4510 state->levelCount = 1; 4511 4512 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4513 } 4514 4515 return ret; 4516 } 4517 4518 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4519 { 4520 struct si_power_info *si_pi = si_get_pi(rdev); 4521 struct si_ulv_param *ulv = &si_pi->ulv; 4522 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4523 int ret; 4524 4525 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4526 &arb_regs); 4527 if (ret) 4528 return ret; 4529 4530 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4531 ulv->volt_change_delay); 4532 4533 ret = si_copy_bytes_to_smc(rdev, 4534 si_pi->arb_table_start + 4535 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4536 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4537 (u8 *)&arb_regs, 4538 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4539 si_pi->sram_end); 4540 4541 return ret; 4542 } 4543 4544 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4545 { 4546 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4547 4548 pi->mvdd_split_frequency = 30000; 4549 } 4550 4551 static int si_init_smc_table(struct radeon_device *rdev) 4552 { 4553 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4554 struct si_power_info *si_pi = si_get_pi(rdev); 4555 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4556 const struct si_ulv_param *ulv = &si_pi->ulv; 4557 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4558 int ret; 4559 u32 lane_width; 4560 u32 vr_hot_gpio; 4561 4562 si_populate_smc_voltage_tables(rdev, table); 4563 4564 switch (rdev->pm.int_thermal_type) { 4565 case THERMAL_TYPE_SI: 4566 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4567 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4568 break; 4569 case THERMAL_TYPE_NONE: 4570 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4571 break; 4572 default: 4573 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4574 break; 4575 } 4576 4577 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4578 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4579 4580 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4581 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4582 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4583 } 4584 4585 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4586 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4587 4588 if (pi->mem_gddr5) 4589 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4590 4591 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4592 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4593 4594 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4595 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4596 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4597 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4598 vr_hot_gpio); 4599 } 4600 4601 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4602 if (ret) 4603 return ret; 4604 4605 ret = si_populate_smc_acpi_state(rdev, table); 4606 if (ret) 4607 return ret; 4608 4609 table->driverState = table->initialState; 4610 4611 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4612 SISLANDS_INITIAL_STATE_ARB_INDEX); 4613 if (ret) 4614 return ret; 4615 4616 if (ulv->supported && ulv->pl.vddc) { 4617 ret = si_populate_ulv_state(rdev, &table->ULVState); 4618 if (ret) 4619 return ret; 4620 4621 ret = si_program_ulv_memory_timing_parameters(rdev); 4622 if (ret) 4623 return ret; 4624 4625 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4626 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4627 4628 lane_width = radeon_get_pcie_lanes(rdev); 4629 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4630 } else { 4631 table->ULVState = table->initialState; 4632 } 4633 4634 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4635 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4636 si_pi->sram_end); 4637 } 4638 4639 static int si_calculate_sclk_params(struct radeon_device *rdev, 4640 u32 engine_clock, 4641 SISLANDS_SMC_SCLK_VALUE *sclk) 4642 { 4643 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4644 struct si_power_info *si_pi = si_get_pi(rdev); 4645 struct atom_clock_dividers dividers; 4646 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4647 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4648 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4649 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4650 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4651 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4652 u64 tmp; 4653 u32 reference_clock = rdev->clock.spll.reference_freq; 4654 u32 reference_divider; 4655 u32 fbdiv; 4656 int ret; 4657 4658 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4659 engine_clock, false, ÷rs); 4660 if (ret) 4661 return ret; 4662 4663 reference_divider = 1 + dividers.ref_div; 4664 4665 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4666 do_div(tmp, reference_clock); 4667 fbdiv = (u32) tmp; 4668 4669 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4670 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4671 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4672 4673 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4674 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4675 4676 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4677 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4678 spll_func_cntl_3 |= SPLL_DITHEN; 4679 4680 if (pi->sclk_ss) { 4681 struct radeon_atom_ss ss; 4682 u32 vco_freq = engine_clock * dividers.post_div; 4683 4684 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4685 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4686 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4687 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4688 4689 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4690 cg_spll_spread_spectrum |= CLK_S(clk_s); 4691 cg_spll_spread_spectrum |= SSEN; 4692 4693 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4694 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4695 } 4696 } 4697 4698 sclk->sclk_value = engine_clock; 4699 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4700 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4701 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4702 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4703 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4704 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4705 4706 return 0; 4707 } 4708 4709 static int si_populate_sclk_value(struct radeon_device *rdev, 4710 u32 engine_clock, 4711 SISLANDS_SMC_SCLK_VALUE *sclk) 4712 { 4713 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4714 int ret; 4715 4716 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4717 if (!ret) { 4718 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4719 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4720 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4721 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4722 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4723 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4724 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4725 } 4726 4727 return ret; 4728 } 4729 4730 static int si_populate_mclk_value(struct radeon_device *rdev, 4731 u32 engine_clock, 4732 u32 memory_clock, 4733 SISLANDS_SMC_MCLK_VALUE *mclk, 4734 bool strobe_mode, 4735 bool dll_state_on) 4736 { 4737 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4738 struct si_power_info *si_pi = si_get_pi(rdev); 4739 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4740 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4741 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4742 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4743 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4744 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4745 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4746 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4747 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4748 struct atom_mpll_param mpll_param; 4749 int ret; 4750 4751 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4752 if (ret) 4753 return ret; 4754 4755 mpll_func_cntl &= ~BWCTRL_MASK; 4756 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4757 4758 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4759 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4760 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4761 4762 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4763 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4764 4765 if (pi->mem_gddr5) { 4766 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4767 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4768 YCLK_POST_DIV(mpll_param.post_div); 4769 } 4770 4771 if (pi->mclk_ss) { 4772 struct radeon_atom_ss ss; 4773 u32 freq_nom; 4774 u32 tmp; 4775 u32 reference_clock = rdev->clock.mpll.reference_freq; 4776 4777 if (pi->mem_gddr5) 4778 freq_nom = memory_clock * 4; 4779 else 4780 freq_nom = memory_clock * 2; 4781 4782 tmp = freq_nom / reference_clock; 4783 tmp = tmp * tmp; 4784 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4785 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4786 u32 clks = reference_clock * 5 / ss.rate; 4787 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4788 4789 mpll_ss1 &= ~CLKV_MASK; 4790 mpll_ss1 |= CLKV(clkv); 4791 4792 mpll_ss2 &= ~CLKS_MASK; 4793 mpll_ss2 |= CLKS(clks); 4794 } 4795 } 4796 4797 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4798 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4799 4800 if (dll_state_on) 4801 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4802 else 4803 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4804 4805 mclk->mclk_value = cpu_to_be32(memory_clock); 4806 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4807 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4808 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4809 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4810 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4811 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4812 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4813 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4814 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4815 4816 return 0; 4817 } 4818 4819 static void si_populate_smc_sp(struct radeon_device *rdev, 4820 struct radeon_ps *radeon_state, 4821 SISLANDS_SMC_SWSTATE *smc_state) 4822 { 4823 struct ni_ps *ps = ni_get_ps(radeon_state); 4824 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4825 int i; 4826 4827 for (i = 0; i < ps->performance_level_count - 1; i++) 4828 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4829 4830 smc_state->levels[ps->performance_level_count - 1].bSP = 4831 cpu_to_be32(pi->psp); 4832 } 4833 4834 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4835 struct rv7xx_pl *pl, 4836 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4837 { 4838 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4839 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4840 struct si_power_info *si_pi = si_get_pi(rdev); 4841 int ret; 4842 bool dll_state_on; 4843 u16 std_vddc; 4844 bool gmc_pg = false; 4845 4846 if (eg_pi->pcie_performance_request && 4847 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4848 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4849 else 4850 level->gen2PCIE = (u8)pl->pcie_gen; 4851 4852 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4853 if (ret) 4854 return ret; 4855 4856 level->mcFlags = 0; 4857 4858 if (pi->mclk_stutter_mode_threshold && 4859 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4860 !eg_pi->uvd_enabled && 4861 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4862 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4863 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4864 4865 if (gmc_pg) 4866 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4867 } 4868 4869 if (pi->mem_gddr5) { 4870 if (pl->mclk > pi->mclk_edc_enable_threshold) 4871 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4872 4873 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4874 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4875 4876 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4877 4878 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4879 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4880 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4881 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4882 else 4883 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4884 } else { 4885 dll_state_on = false; 4886 } 4887 } else { 4888 level->strobeMode = si_get_strobe_mode_settings(rdev, 4889 pl->mclk); 4890 4891 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4892 } 4893 4894 ret = si_populate_mclk_value(rdev, 4895 pl->sclk, 4896 pl->mclk, 4897 &level->mclk, 4898 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4899 if (ret) 4900 return ret; 4901 4902 ret = si_populate_voltage_value(rdev, 4903 &eg_pi->vddc_voltage_table, 4904 pl->vddc, &level->vddc); 4905 if (ret) 4906 return ret; 4907 4908 4909 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4910 if (ret) 4911 return ret; 4912 4913 ret = si_populate_std_voltage_value(rdev, std_vddc, 4914 level->vddc.index, &level->std_vddc); 4915 if (ret) 4916 return ret; 4917 4918 if (eg_pi->vddci_control) { 4919 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4920 pl->vddci, &level->vddci); 4921 if (ret) 4922 return ret; 4923 } 4924 4925 if (si_pi->vddc_phase_shed_control) { 4926 ret = si_populate_phase_shedding_value(rdev, 4927 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4928 pl->vddc, 4929 pl->sclk, 4930 pl->mclk, 4931 &level->vddc); 4932 if (ret) 4933 return ret; 4934 } 4935 4936 level->MaxPoweredUpCU = si_pi->max_cu; 4937 4938 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 4939 4940 return ret; 4941 } 4942 4943 static int si_populate_smc_t(struct radeon_device *rdev, 4944 struct radeon_ps *radeon_state, 4945 SISLANDS_SMC_SWSTATE *smc_state) 4946 { 4947 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4948 struct ni_ps *state = ni_get_ps(radeon_state); 4949 u32 a_t; 4950 u32 t_l, t_h; 4951 u32 high_bsp; 4952 int i, ret; 4953 4954 if (state->performance_level_count >= 9) 4955 return -EINVAL; 4956 4957 if (state->performance_level_count < 2) { 4958 a_t = CG_R(0xffff) | CG_L(0); 4959 smc_state->levels[0].aT = cpu_to_be32(a_t); 4960 return 0; 4961 } 4962 4963 smc_state->levels[0].aT = cpu_to_be32(0); 4964 4965 for (i = 0; i <= state->performance_level_count - 2; i++) { 4966 ret = r600_calculate_at( 4967 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 4968 100 * R600_AH_DFLT, 4969 state->performance_levels[i + 1].sclk, 4970 state->performance_levels[i].sclk, 4971 &t_l, 4972 &t_h); 4973 4974 if (ret) { 4975 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 4976 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 4977 } 4978 4979 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 4980 a_t |= CG_R(t_l * pi->bsp / 20000); 4981 smc_state->levels[i].aT = cpu_to_be32(a_t); 4982 4983 high_bsp = (i == state->performance_level_count - 2) ? 4984 pi->pbsp : pi->bsp; 4985 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 4986 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 4987 } 4988 4989 return 0; 4990 } 4991 4992 static int si_disable_ulv(struct radeon_device *rdev) 4993 { 4994 struct si_power_info *si_pi = si_get_pi(rdev); 4995 struct si_ulv_param *ulv = &si_pi->ulv; 4996 4997 if (ulv->supported) 4998 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 4999 0 : -EINVAL; 5000 5001 return 0; 5002 } 5003 5004 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5005 struct radeon_ps *radeon_state) 5006 { 5007 const struct si_power_info *si_pi = si_get_pi(rdev); 5008 const struct si_ulv_param *ulv = &si_pi->ulv; 5009 const struct ni_ps *state = ni_get_ps(radeon_state); 5010 int i; 5011 5012 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5013 return false; 5014 5015 /* XXX validate against display requirements! */ 5016 5017 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5018 if (rdev->clock.current_dispclk <= 5019 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5020 if (ulv->pl.vddc < 5021 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5022 return false; 5023 } 5024 } 5025 5026 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5027 return false; 5028 5029 return true; 5030 } 5031 5032 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5033 struct radeon_ps *radeon_new_state) 5034 { 5035 const struct si_power_info *si_pi = si_get_pi(rdev); 5036 const struct si_ulv_param *ulv = &si_pi->ulv; 5037 5038 if (ulv->supported) { 5039 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5040 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5041 0 : -EINVAL; 5042 } 5043 return 0; 5044 } 5045 5046 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5047 struct radeon_ps *radeon_state, 5048 SISLANDS_SMC_SWSTATE *smc_state) 5049 { 5050 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5051 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5052 struct si_power_info *si_pi = si_get_pi(rdev); 5053 struct ni_ps *state = ni_get_ps(radeon_state); 5054 int i, ret; 5055 u32 threshold; 5056 u32 sclk_in_sr = 1350; /* ??? */ 5057 5058 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5059 return -EINVAL; 5060 5061 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5062 5063 if (radeon_state->vclk && radeon_state->dclk) { 5064 eg_pi->uvd_enabled = true; 5065 if (eg_pi->smu_uvd_hs) 5066 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5067 } else { 5068 eg_pi->uvd_enabled = false; 5069 } 5070 5071 if (state->dc_compatible) 5072 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5073 5074 smc_state->levelCount = 0; 5075 for (i = 0; i < state->performance_level_count; i++) { 5076 if (eg_pi->sclk_deep_sleep) { 5077 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5078 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5079 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5080 else 5081 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5082 } 5083 } 5084 5085 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5086 &smc_state->levels[i]); 5087 smc_state->levels[i].arbRefreshState = 5088 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5089 5090 if (ret) 5091 return ret; 5092 5093 if (ni_pi->enable_power_containment) 5094 smc_state->levels[i].displayWatermark = 5095 (state->performance_levels[i].sclk < threshold) ? 5096 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5097 else 5098 smc_state->levels[i].displayWatermark = (i < 2) ? 5099 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5100 5101 if (eg_pi->dynamic_ac_timing) 5102 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5103 else 5104 smc_state->levels[i].ACIndex = 0; 5105 5106 smc_state->levelCount++; 5107 } 5108 5109 si_write_smc_soft_register(rdev, 5110 SI_SMC_SOFT_REGISTER_watermark_threshold, 5111 threshold / 512); 5112 5113 si_populate_smc_sp(rdev, radeon_state, smc_state); 5114 5115 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5116 if (ret) 5117 ni_pi->enable_power_containment = false; 5118 5119 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5120 if (ret) 5121 ni_pi->enable_sq_ramping = false; 5122 5123 return si_populate_smc_t(rdev, radeon_state, smc_state); 5124 } 5125 5126 static int si_upload_sw_state(struct radeon_device *rdev, 5127 struct radeon_ps *radeon_new_state) 5128 { 5129 struct si_power_info *si_pi = si_get_pi(rdev); 5130 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5131 int ret; 5132 u32 address = si_pi->state_table_start + 5133 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5134 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5135 ((new_state->performance_level_count - 1) * 5136 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5137 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5138 5139 memset(smc_state, 0, state_size); 5140 5141 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5142 if (ret) 5143 return ret; 5144 5145 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5146 state_size, si_pi->sram_end); 5147 5148 return ret; 5149 } 5150 5151 static int si_upload_ulv_state(struct radeon_device *rdev) 5152 { 5153 struct si_power_info *si_pi = si_get_pi(rdev); 5154 struct si_ulv_param *ulv = &si_pi->ulv; 5155 int ret = 0; 5156 5157 if (ulv->supported && ulv->pl.vddc) { 5158 u32 address = si_pi->state_table_start + 5159 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5160 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5161 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5162 5163 memset(smc_state, 0, state_size); 5164 5165 ret = si_populate_ulv_state(rdev, smc_state); 5166 if (!ret) 5167 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5168 state_size, si_pi->sram_end); 5169 } 5170 5171 return ret; 5172 } 5173 5174 static int si_upload_smc_data(struct radeon_device *rdev) 5175 { 5176 struct radeon_crtc *radeon_crtc = NULL; 5177 int i; 5178 5179 if (rdev->pm.dpm.new_active_crtc_count == 0) 5180 return 0; 5181 5182 for (i = 0; i < rdev->num_crtc; i++) { 5183 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5184 radeon_crtc = rdev->mode_info.crtcs[i]; 5185 break; 5186 } 5187 } 5188 5189 if (radeon_crtc == NULL) 5190 return 0; 5191 5192 if (radeon_crtc->line_time <= 0) 5193 return 0; 5194 5195 if (si_write_smc_soft_register(rdev, 5196 SI_SMC_SOFT_REGISTER_crtc_index, 5197 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5198 return 0; 5199 5200 if (si_write_smc_soft_register(rdev, 5201 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5202 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5203 return 0; 5204 5205 if (si_write_smc_soft_register(rdev, 5206 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5207 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5208 return 0; 5209 5210 return 0; 5211 } 5212 5213 static int si_set_mc_special_registers(struct radeon_device *rdev, 5214 struct si_mc_reg_table *table) 5215 { 5216 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5217 u8 i, j, k; 5218 u32 temp_reg; 5219 5220 for (i = 0, j = table->last; i < table->last; i++) { 5221 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5222 return -EINVAL; 5223 switch (table->mc_reg_address[i].s1 << 2) { 5224 case MC_SEQ_MISC1: 5225 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5226 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5227 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5228 for (k = 0; k < table->num_entries; k++) 5229 table->mc_reg_table_entry[k].mc_data[j] = 5230 ((temp_reg & 0xffff0000)) | 5231 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5232 j++; 5233 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5234 return -EINVAL; 5235 5236 temp_reg = RREG32(MC_PMG_CMD_MRS); 5237 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5238 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5239 for (k = 0; k < table->num_entries; k++) { 5240 table->mc_reg_table_entry[k].mc_data[j] = 5241 (temp_reg & 0xffff0000) | 5242 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5243 if (!pi->mem_gddr5) 5244 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5245 } 5246 j++; 5247 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5248 return -EINVAL; 5249 5250 if (!pi->mem_gddr5) { 5251 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5252 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5253 for (k = 0; k < table->num_entries; k++) 5254 table->mc_reg_table_entry[k].mc_data[j] = 5255 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5256 j++; 5257 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5258 return -EINVAL; 5259 } 5260 break; 5261 case MC_SEQ_RESERVE_M: 5262 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5263 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5264 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5265 for(k = 0; k < table->num_entries; k++) 5266 table->mc_reg_table_entry[k].mc_data[j] = 5267 (temp_reg & 0xffff0000) | 5268 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5269 j++; 5270 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5271 return -EINVAL; 5272 break; 5273 default: 5274 break; 5275 } 5276 } 5277 5278 table->last = j; 5279 5280 return 0; 5281 } 5282 5283 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5284 { 5285 bool result = true; 5286 5287 switch (in_reg) { 5288 case MC_SEQ_RAS_TIMING >> 2: 5289 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5290 break; 5291 case MC_SEQ_CAS_TIMING >> 2: 5292 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5293 break; 5294 case MC_SEQ_MISC_TIMING >> 2: 5295 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5296 break; 5297 case MC_SEQ_MISC_TIMING2 >> 2: 5298 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5299 break; 5300 case MC_SEQ_RD_CTL_D0 >> 2: 5301 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5302 break; 5303 case MC_SEQ_RD_CTL_D1 >> 2: 5304 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5305 break; 5306 case MC_SEQ_WR_CTL_D0 >> 2: 5307 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5308 break; 5309 case MC_SEQ_WR_CTL_D1 >> 2: 5310 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5311 break; 5312 case MC_PMG_CMD_EMRS >> 2: 5313 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5314 break; 5315 case MC_PMG_CMD_MRS >> 2: 5316 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5317 break; 5318 case MC_PMG_CMD_MRS1 >> 2: 5319 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5320 break; 5321 case MC_SEQ_PMG_TIMING >> 2: 5322 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5323 break; 5324 case MC_PMG_CMD_MRS2 >> 2: 5325 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5326 break; 5327 case MC_SEQ_WR_CTL_2 >> 2: 5328 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5329 break; 5330 default: 5331 result = false; 5332 break; 5333 } 5334 5335 return result; 5336 } 5337 5338 static void si_set_valid_flag(struct si_mc_reg_table *table) 5339 { 5340 u8 i, j; 5341 5342 for (i = 0; i < table->last; i++) { 5343 for (j = 1; j < table->num_entries; j++) { 5344 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5345 table->valid_flag |= 1 << i; 5346 break; 5347 } 5348 } 5349 } 5350 } 5351 5352 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5353 { 5354 u32 i; 5355 u16 address; 5356 5357 for (i = 0; i < table->last; i++) 5358 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5359 address : table->mc_reg_address[i].s1; 5360 5361 } 5362 5363 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5364 struct si_mc_reg_table *si_table) 5365 { 5366 u8 i, j; 5367 5368 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5369 return -EINVAL; 5370 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5371 return -EINVAL; 5372 5373 for (i = 0; i < table->last; i++) 5374 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5375 si_table->last = table->last; 5376 5377 for (i = 0; i < table->num_entries; i++) { 5378 si_table->mc_reg_table_entry[i].mclk_max = 5379 table->mc_reg_table_entry[i].mclk_max; 5380 for (j = 0; j < table->last; j++) { 5381 si_table->mc_reg_table_entry[i].mc_data[j] = 5382 table->mc_reg_table_entry[i].mc_data[j]; 5383 } 5384 } 5385 si_table->num_entries = table->num_entries; 5386 5387 return 0; 5388 } 5389 5390 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5391 { 5392 struct si_power_info *si_pi = si_get_pi(rdev); 5393 struct atom_mc_reg_table *table; 5394 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5395 u8 module_index = rv770_get_memory_module_index(rdev); 5396 int ret; 5397 5398 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5399 if (!table) 5400 return -ENOMEM; 5401 5402 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5403 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5404 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5405 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5406 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5407 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5408 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5409 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5410 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5411 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5412 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5413 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5414 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5415 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5416 5417 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5418 if (ret) 5419 goto init_mc_done; 5420 5421 ret = si_copy_vbios_mc_reg_table(table, si_table); 5422 if (ret) 5423 goto init_mc_done; 5424 5425 si_set_s0_mc_reg_index(si_table); 5426 5427 ret = si_set_mc_special_registers(rdev, si_table); 5428 if (ret) 5429 goto init_mc_done; 5430 5431 si_set_valid_flag(si_table); 5432 5433 init_mc_done: 5434 kfree(table); 5435 5436 return ret; 5437 5438 } 5439 5440 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5441 SMC_SIslands_MCRegisters *mc_reg_table) 5442 { 5443 struct si_power_info *si_pi = si_get_pi(rdev); 5444 u32 i, j; 5445 5446 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5447 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5448 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5449 break; 5450 mc_reg_table->address[i].s0 = 5451 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5452 mc_reg_table->address[i].s1 = 5453 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5454 i++; 5455 } 5456 } 5457 mc_reg_table->last = (u8)i; 5458 } 5459 5460 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5461 SMC_SIslands_MCRegisterSet *data, 5462 u32 num_entries, u32 valid_flag) 5463 { 5464 u32 i, j; 5465 5466 for(i = 0, j = 0; j < num_entries; j++) { 5467 if (valid_flag & (1 << j)) { 5468 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5469 i++; 5470 } 5471 } 5472 } 5473 5474 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5475 struct rv7xx_pl *pl, 5476 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5477 { 5478 struct si_power_info *si_pi = si_get_pi(rdev); 5479 u32 i = 0; 5480 5481 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5482 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5483 break; 5484 } 5485 5486 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5487 --i; 5488 5489 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5490 mc_reg_table_data, si_pi->mc_reg_table.last, 5491 si_pi->mc_reg_table.valid_flag); 5492 } 5493 5494 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5495 struct radeon_ps *radeon_state, 5496 SMC_SIslands_MCRegisters *mc_reg_table) 5497 { 5498 struct ni_ps *state = ni_get_ps(radeon_state); 5499 int i; 5500 5501 for (i = 0; i < state->performance_level_count; i++) { 5502 si_convert_mc_reg_table_entry_to_smc(rdev, 5503 &state->performance_levels[i], 5504 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5505 } 5506 } 5507 5508 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5509 struct radeon_ps *radeon_boot_state) 5510 { 5511 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5512 struct si_power_info *si_pi = si_get_pi(rdev); 5513 struct si_ulv_param *ulv = &si_pi->ulv; 5514 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5515 5516 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5517 5518 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5519 5520 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5521 5522 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5523 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5524 5525 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5526 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5527 si_pi->mc_reg_table.last, 5528 si_pi->mc_reg_table.valid_flag); 5529 5530 if (ulv->supported && ulv->pl.vddc != 0) 5531 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5532 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5533 else 5534 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5535 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5536 si_pi->mc_reg_table.last, 5537 si_pi->mc_reg_table.valid_flag); 5538 5539 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5540 5541 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5542 (u8 *)smc_mc_reg_table, 5543 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5544 } 5545 5546 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5547 struct radeon_ps *radeon_new_state) 5548 { 5549 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5550 struct si_power_info *si_pi = si_get_pi(rdev); 5551 u32 address = si_pi->mc_reg_table_start + 5552 offsetof(SMC_SIslands_MCRegisters, 5553 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5554 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5555 5556 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5557 5558 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5559 5560 5561 return si_copy_bytes_to_smc(rdev, address, 5562 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5563 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5564 si_pi->sram_end); 5565 5566 } 5567 5568 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5569 { 5570 if (enable) 5571 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5572 else 5573 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5574 } 5575 5576 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5577 struct radeon_ps *radeon_state) 5578 { 5579 struct ni_ps *state = ni_get_ps(radeon_state); 5580 int i; 5581 u16 pcie_speed, max_speed = 0; 5582 5583 for (i = 0; i < state->performance_level_count; i++) { 5584 pcie_speed = state->performance_levels[i].pcie_gen; 5585 if (max_speed < pcie_speed) 5586 max_speed = pcie_speed; 5587 } 5588 return max_speed; 5589 } 5590 5591 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5592 { 5593 u32 speed_cntl; 5594 5595 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5596 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5597 5598 return (u16)speed_cntl; 5599 } 5600 5601 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5602 struct radeon_ps *radeon_new_state, 5603 struct radeon_ps *radeon_current_state) 5604 { 5605 struct si_power_info *si_pi = si_get_pi(rdev); 5606 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5607 enum radeon_pcie_gen current_link_speed; 5608 5609 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5610 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5611 else 5612 current_link_speed = si_pi->force_pcie_gen; 5613 5614 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5615 si_pi->pspp_notify_required = false; 5616 if (target_link_speed > current_link_speed) { 5617 switch (target_link_speed) { 5618 #if defined(CONFIG_ACPI) 5619 case RADEON_PCIE_GEN3: 5620 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5621 break; 5622 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5623 if (current_link_speed == RADEON_PCIE_GEN2) 5624 break; 5625 case RADEON_PCIE_GEN2: 5626 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5627 break; 5628 #endif 5629 default: 5630 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5631 break; 5632 } 5633 } else { 5634 if (target_link_speed < current_link_speed) 5635 si_pi->pspp_notify_required = true; 5636 } 5637 } 5638 5639 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5640 struct radeon_ps *radeon_new_state, 5641 struct radeon_ps *radeon_current_state) 5642 { 5643 struct si_power_info *si_pi = si_get_pi(rdev); 5644 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5645 u8 request; 5646 5647 if (si_pi->pspp_notify_required) { 5648 if (target_link_speed == RADEON_PCIE_GEN3) 5649 request = PCIE_PERF_REQ_PECI_GEN3; 5650 else if (target_link_speed == RADEON_PCIE_GEN2) 5651 request = PCIE_PERF_REQ_PECI_GEN2; 5652 else 5653 request = PCIE_PERF_REQ_PECI_GEN1; 5654 5655 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5656 (si_get_current_pcie_speed(rdev) > 0)) 5657 return; 5658 5659 #if defined(CONFIG_ACPI) 5660 radeon_acpi_pcie_performance_request(rdev, request, false); 5661 #endif 5662 } 5663 } 5664 5665 #if 0 5666 static int si_ds_request(struct radeon_device *rdev, 5667 bool ds_status_on, u32 count_write) 5668 { 5669 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5670 5671 if (eg_pi->sclk_deep_sleep) { 5672 if (ds_status_on) 5673 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5674 PPSMC_Result_OK) ? 5675 0 : -EINVAL; 5676 else 5677 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5678 PPSMC_Result_OK) ? 0 : -EINVAL; 5679 } 5680 return 0; 5681 } 5682 #endif 5683 5684 static void si_set_max_cu_value(struct radeon_device *rdev) 5685 { 5686 struct si_power_info *si_pi = si_get_pi(rdev); 5687 5688 if (rdev->family == CHIP_VERDE) { 5689 switch (rdev->pdev->device) { 5690 case 0x6820: 5691 case 0x6825: 5692 case 0x6821: 5693 case 0x6823: 5694 case 0x6827: 5695 si_pi->max_cu = 10; 5696 break; 5697 case 0x682D: 5698 case 0x6824: 5699 case 0x682F: 5700 case 0x6826: 5701 si_pi->max_cu = 8; 5702 break; 5703 case 0x6828: 5704 case 0x6830: 5705 case 0x6831: 5706 case 0x6838: 5707 case 0x6839: 5708 case 0x683D: 5709 si_pi->max_cu = 10; 5710 break; 5711 case 0x683B: 5712 case 0x683F: 5713 case 0x6829: 5714 si_pi->max_cu = 8; 5715 break; 5716 default: 5717 si_pi->max_cu = 0; 5718 break; 5719 } 5720 } else { 5721 si_pi->max_cu = 0; 5722 } 5723 } 5724 5725 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5726 struct radeon_clock_voltage_dependency_table *table) 5727 { 5728 u32 i; 5729 int j; 5730 u16 leakage_voltage; 5731 5732 if (table) { 5733 for (i = 0; i < table->count; i++) { 5734 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5735 table->entries[i].v, 5736 &leakage_voltage)) { 5737 case 0: 5738 table->entries[i].v = leakage_voltage; 5739 break; 5740 case -EAGAIN: 5741 return -EINVAL; 5742 case -EINVAL: 5743 default: 5744 break; 5745 } 5746 } 5747 5748 for (j = (table->count - 2); j >= 0; j--) { 5749 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5750 table->entries[j].v : table->entries[j + 1].v; 5751 } 5752 } 5753 return 0; 5754 } 5755 5756 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5757 { 5758 int ret = 0; 5759 5760 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5761 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5762 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5763 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5764 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5765 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5766 return ret; 5767 } 5768 5769 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5770 struct radeon_ps *radeon_new_state, 5771 struct radeon_ps *radeon_current_state) 5772 { 5773 u32 lane_width; 5774 u32 new_lane_width = 5775 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5776 u32 current_lane_width = 5777 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5778 5779 if (new_lane_width != current_lane_width) { 5780 radeon_set_pcie_lanes(rdev, new_lane_width); 5781 lane_width = radeon_get_pcie_lanes(rdev); 5782 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5783 } 5784 } 5785 5786 void si_dpm_setup_asic(struct radeon_device *rdev) 5787 { 5788 int r; 5789 5790 r = si_mc_load_microcode(rdev); 5791 if (r) 5792 DRM_ERROR("Failed to load MC firmware!\n"); 5793 rv770_get_memory_type(rdev); 5794 si_read_clock_registers(rdev); 5795 si_enable_acpi_power_management(rdev); 5796 } 5797 5798 static int si_set_thermal_temperature_range(struct radeon_device *rdev, 5799 int min_temp, int max_temp) 5800 { 5801 int low_temp = 0 * 1000; 5802 int high_temp = 255 * 1000; 5803 5804 if (low_temp < min_temp) 5805 low_temp = min_temp; 5806 if (high_temp > max_temp) 5807 high_temp = max_temp; 5808 if (high_temp < low_temp) { 5809 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5810 return -EINVAL; 5811 } 5812 5813 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5814 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5815 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5816 5817 rdev->pm.dpm.thermal.min_temp = low_temp; 5818 rdev->pm.dpm.thermal.max_temp = high_temp; 5819 5820 return 0; 5821 } 5822 5823 int si_dpm_enable(struct radeon_device *rdev) 5824 { 5825 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5826 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5827 struct si_power_info *si_pi = si_get_pi(rdev); 5828 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5829 int ret; 5830 5831 if (si_is_smc_running(rdev)) 5832 return -EINVAL; 5833 if (pi->voltage_control || si_pi->voltage_control_svi2) 5834 si_enable_voltage_control(rdev, true); 5835 if (pi->mvdd_control) 5836 si_get_mvdd_configuration(rdev); 5837 if (pi->voltage_control || si_pi->voltage_control_svi2) { 5838 ret = si_construct_voltage_tables(rdev); 5839 if (ret) { 5840 DRM_ERROR("si_construct_voltage_tables failed\n"); 5841 return ret; 5842 } 5843 } 5844 if (eg_pi->dynamic_ac_timing) { 5845 ret = si_initialize_mc_reg_table(rdev); 5846 if (ret) 5847 eg_pi->dynamic_ac_timing = false; 5848 } 5849 if (pi->dynamic_ss) 5850 si_enable_spread_spectrum(rdev, true); 5851 if (pi->thermal_protection) 5852 si_enable_thermal_protection(rdev, true); 5853 si_setup_bsp(rdev); 5854 si_program_git(rdev); 5855 si_program_tp(rdev); 5856 si_program_tpp(rdev); 5857 si_program_sstp(rdev); 5858 si_enable_display_gap(rdev); 5859 si_program_vc(rdev); 5860 ret = si_upload_firmware(rdev); 5861 if (ret) { 5862 DRM_ERROR("si_upload_firmware failed\n"); 5863 return ret; 5864 } 5865 ret = si_process_firmware_header(rdev); 5866 if (ret) { 5867 DRM_ERROR("si_process_firmware_header failed\n"); 5868 return ret; 5869 } 5870 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 5871 if (ret) { 5872 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 5873 return ret; 5874 } 5875 ret = si_init_smc_table(rdev); 5876 if (ret) { 5877 DRM_ERROR("si_init_smc_table failed\n"); 5878 return ret; 5879 } 5880 ret = si_init_smc_spll_table(rdev); 5881 if (ret) { 5882 DRM_ERROR("si_init_smc_spll_table failed\n"); 5883 return ret; 5884 } 5885 ret = si_init_arb_table_index(rdev); 5886 if (ret) { 5887 DRM_ERROR("si_init_arb_table_index failed\n"); 5888 return ret; 5889 } 5890 if (eg_pi->dynamic_ac_timing) { 5891 ret = si_populate_mc_reg_table(rdev, boot_ps); 5892 if (ret) { 5893 DRM_ERROR("si_populate_mc_reg_table failed\n"); 5894 return ret; 5895 } 5896 } 5897 ret = si_initialize_smc_cac_tables(rdev); 5898 if (ret) { 5899 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 5900 return ret; 5901 } 5902 ret = si_initialize_hardware_cac_manager(rdev); 5903 if (ret) { 5904 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 5905 return ret; 5906 } 5907 ret = si_initialize_smc_dte_tables(rdev); 5908 if (ret) { 5909 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 5910 return ret; 5911 } 5912 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 5913 if (ret) { 5914 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 5915 return ret; 5916 } 5917 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 5918 if (ret) { 5919 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 5920 return ret; 5921 } 5922 si_program_response_times(rdev); 5923 si_program_ds_registers(rdev); 5924 si_dpm_start_smc(rdev); 5925 ret = si_notify_smc_display_change(rdev, false); 5926 if (ret) { 5927 DRM_ERROR("si_notify_smc_display_change failed\n"); 5928 return ret; 5929 } 5930 si_enable_sclk_control(rdev, true); 5931 si_start_dpm(rdev); 5932 5933 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5934 5935 ni_update_current_ps(rdev, boot_ps); 5936 5937 return 0; 5938 } 5939 5940 int si_dpm_late_enable(struct radeon_device *rdev) 5941 { 5942 int ret; 5943 5944 if (rdev->irq.installed && 5945 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 5946 PPSMC_Result result; 5947 5948 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5949 if (ret) 5950 return ret; 5951 rdev->irq.dpm_thermal = true; 5952 radeon_irq_set(rdev); 5953 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5954 5955 if (result != PPSMC_Result_OK) 5956 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5957 } 5958 5959 return 0; 5960 } 5961 5962 void si_dpm_disable(struct radeon_device *rdev) 5963 { 5964 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5965 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5966 5967 if (!si_is_smc_running(rdev)) 5968 return; 5969 si_disable_ulv(rdev); 5970 si_clear_vc(rdev); 5971 if (pi->thermal_protection) 5972 si_enable_thermal_protection(rdev, false); 5973 si_enable_power_containment(rdev, boot_ps, false); 5974 si_enable_smc_cac(rdev, boot_ps, false); 5975 si_enable_spread_spectrum(rdev, false); 5976 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5977 si_stop_dpm(rdev); 5978 si_reset_to_default(rdev); 5979 si_dpm_stop_smc(rdev); 5980 si_force_switch_to_arb_f0(rdev); 5981 5982 ni_update_current_ps(rdev, boot_ps); 5983 } 5984 5985 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 5986 { 5987 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5988 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 5989 struct radeon_ps *new_ps = &requested_ps; 5990 5991 ni_update_requested_ps(rdev, new_ps); 5992 5993 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 5994 5995 return 0; 5996 } 5997 5998 static int si_power_control_set_level(struct radeon_device *rdev) 5999 { 6000 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6001 int ret; 6002 6003 ret = si_restrict_performance_levels_before_switch(rdev); 6004 if (ret) 6005 return ret; 6006 ret = si_halt_smc(rdev); 6007 if (ret) 6008 return ret; 6009 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6010 if (ret) 6011 return ret; 6012 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6013 if (ret) 6014 return ret; 6015 ret = si_resume_smc(rdev); 6016 if (ret) 6017 return ret; 6018 ret = si_set_sw_state(rdev); 6019 if (ret) 6020 return ret; 6021 return 0; 6022 } 6023 6024 int si_dpm_set_power_state(struct radeon_device *rdev) 6025 { 6026 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6027 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6028 struct radeon_ps *old_ps = &eg_pi->current_rps; 6029 int ret; 6030 6031 ret = si_disable_ulv(rdev); 6032 if (ret) { 6033 DRM_ERROR("si_disable_ulv failed\n"); 6034 return ret; 6035 } 6036 ret = si_restrict_performance_levels_before_switch(rdev); 6037 if (ret) { 6038 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6039 return ret; 6040 } 6041 if (eg_pi->pcie_performance_request) 6042 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6043 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6044 ret = si_enable_power_containment(rdev, new_ps, false); 6045 if (ret) { 6046 DRM_ERROR("si_enable_power_containment failed\n"); 6047 return ret; 6048 } 6049 ret = si_enable_smc_cac(rdev, new_ps, false); 6050 if (ret) { 6051 DRM_ERROR("si_enable_smc_cac failed\n"); 6052 return ret; 6053 } 6054 ret = si_halt_smc(rdev); 6055 if (ret) { 6056 DRM_ERROR("si_halt_smc failed\n"); 6057 return ret; 6058 } 6059 ret = si_upload_sw_state(rdev, new_ps); 6060 if (ret) { 6061 DRM_ERROR("si_upload_sw_state failed\n"); 6062 return ret; 6063 } 6064 ret = si_upload_smc_data(rdev); 6065 if (ret) { 6066 DRM_ERROR("si_upload_smc_data failed\n"); 6067 return ret; 6068 } 6069 ret = si_upload_ulv_state(rdev); 6070 if (ret) { 6071 DRM_ERROR("si_upload_ulv_state failed\n"); 6072 return ret; 6073 } 6074 if (eg_pi->dynamic_ac_timing) { 6075 ret = si_upload_mc_reg_table(rdev, new_ps); 6076 if (ret) { 6077 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6078 return ret; 6079 } 6080 } 6081 ret = si_program_memory_timing_parameters(rdev, new_ps); 6082 if (ret) { 6083 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6084 return ret; 6085 } 6086 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6087 6088 ret = si_resume_smc(rdev); 6089 if (ret) { 6090 DRM_ERROR("si_resume_smc failed\n"); 6091 return ret; 6092 } 6093 ret = si_set_sw_state(rdev); 6094 if (ret) { 6095 DRM_ERROR("si_set_sw_state failed\n"); 6096 return ret; 6097 } 6098 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6099 if (eg_pi->pcie_performance_request) 6100 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6101 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6102 if (ret) { 6103 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6104 return ret; 6105 } 6106 ret = si_enable_smc_cac(rdev, new_ps, true); 6107 if (ret) { 6108 DRM_ERROR("si_enable_smc_cac failed\n"); 6109 return ret; 6110 } 6111 ret = si_enable_power_containment(rdev, new_ps, true); 6112 if (ret) { 6113 DRM_ERROR("si_enable_power_containment failed\n"); 6114 return ret; 6115 } 6116 6117 ret = si_power_control_set_level(rdev); 6118 if (ret) { 6119 DRM_ERROR("si_power_control_set_level failed\n"); 6120 return ret; 6121 } 6122 6123 return 0; 6124 } 6125 6126 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6127 { 6128 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6129 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6130 6131 ni_update_current_ps(rdev, new_ps); 6132 } 6133 6134 #if 0 6135 void si_dpm_reset_asic(struct radeon_device *rdev) 6136 { 6137 si_restrict_performance_levels_before_switch(rdev); 6138 si_disable_ulv(rdev); 6139 si_set_boot_state(rdev); 6140 } 6141 #endif 6142 6143 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6144 { 6145 si_program_display_gap(rdev); 6146 } 6147 6148 union power_info { 6149 struct _ATOM_POWERPLAY_INFO info; 6150 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6151 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6152 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6153 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6154 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6155 }; 6156 6157 union pplib_clock_info { 6158 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6159 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6160 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6161 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6162 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6163 }; 6164 6165 union pplib_power_state { 6166 struct _ATOM_PPLIB_STATE v1; 6167 struct _ATOM_PPLIB_STATE_V2 v2; 6168 }; 6169 6170 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6171 struct radeon_ps *rps, 6172 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6173 u8 table_rev) 6174 { 6175 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6176 rps->class = le16_to_cpu(non_clock_info->usClassification); 6177 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6178 6179 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6180 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6181 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6182 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6183 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6184 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6185 } else { 6186 rps->vclk = 0; 6187 rps->dclk = 0; 6188 } 6189 6190 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6191 rdev->pm.dpm.boot_ps = rps; 6192 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6193 rdev->pm.dpm.uvd_ps = rps; 6194 } 6195 6196 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6197 struct radeon_ps *rps, int index, 6198 union pplib_clock_info *clock_info) 6199 { 6200 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6201 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6202 struct si_power_info *si_pi = si_get_pi(rdev); 6203 struct ni_ps *ps = ni_get_ps(rps); 6204 u16 leakage_voltage; 6205 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6206 int ret; 6207 6208 ps->performance_level_count = index + 1; 6209 6210 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6211 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6212 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6213 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6214 6215 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6216 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6217 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6218 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6219 si_pi->sys_pcie_mask, 6220 si_pi->boot_pcie_gen, 6221 clock_info->si.ucPCIEGen); 6222 6223 /* patch up vddc if necessary */ 6224 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6225 &leakage_voltage); 6226 if (ret == 0) 6227 pl->vddc = leakage_voltage; 6228 6229 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6230 pi->acpi_vddc = pl->vddc; 6231 eg_pi->acpi_vddci = pl->vddci; 6232 si_pi->acpi_pcie_gen = pl->pcie_gen; 6233 } 6234 6235 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6236 index == 0) { 6237 /* XXX disable for A0 tahiti */ 6238 si_pi->ulv.supported = false; 6239 si_pi->ulv.pl = *pl; 6240 si_pi->ulv.one_pcie_lane_in_ulv = false; 6241 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6242 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6243 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6244 } 6245 6246 if (pi->min_vddc_in_table > pl->vddc) 6247 pi->min_vddc_in_table = pl->vddc; 6248 6249 if (pi->max_vddc_in_table < pl->vddc) 6250 pi->max_vddc_in_table = pl->vddc; 6251 6252 /* patch up boot state */ 6253 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6254 u16 vddc, vddci, mvdd; 6255 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6256 pl->mclk = rdev->clock.default_mclk; 6257 pl->sclk = rdev->clock.default_sclk; 6258 pl->vddc = vddc; 6259 pl->vddci = vddci; 6260 si_pi->mvdd_bootup_value = mvdd; 6261 } 6262 6263 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6264 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6265 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6266 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6267 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6268 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6269 } 6270 } 6271 6272 static int si_parse_power_table(struct radeon_device *rdev) 6273 { 6274 struct radeon_mode_info *mode_info = &rdev->mode_info; 6275 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6276 union pplib_power_state *power_state; 6277 int i, j, k, non_clock_array_index, clock_array_index; 6278 union pplib_clock_info *clock_info; 6279 struct _StateArray *state_array; 6280 struct _ClockInfoArray *clock_info_array; 6281 struct _NonClockInfoArray *non_clock_info_array; 6282 union power_info *power_info; 6283 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6284 u16 data_offset; 6285 u8 frev, crev; 6286 u8 *power_state_offset; 6287 struct ni_ps *ps; 6288 6289 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6290 &frev, &crev, &data_offset)) 6291 return -EINVAL; 6292 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6293 6294 state_array = (struct _StateArray *) 6295 (mode_info->atom_context->bios + data_offset + 6296 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6297 clock_info_array = (struct _ClockInfoArray *) 6298 (mode_info->atom_context->bios + data_offset + 6299 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6300 non_clock_info_array = (struct _NonClockInfoArray *) 6301 (mode_info->atom_context->bios + data_offset + 6302 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6303 6304 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6305 state_array->ucNumEntries, GFP_KERNEL); 6306 if (!rdev->pm.dpm.ps) 6307 return -ENOMEM; 6308 power_state_offset = (u8 *)state_array->states; 6309 for (i = 0; i < state_array->ucNumEntries; i++) { 6310 u8 *idx; 6311 power_state = (union pplib_power_state *)power_state_offset; 6312 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6313 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6314 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6315 if (!rdev->pm.power_state[i].clock_info) 6316 return -EINVAL; 6317 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6318 if (ps == NULL) { 6319 kfree(rdev->pm.dpm.ps); 6320 return -ENOMEM; 6321 } 6322 rdev->pm.dpm.ps[i].ps_priv = ps; 6323 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6324 non_clock_info, 6325 non_clock_info_array->ucEntrySize); 6326 k = 0; 6327 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6328 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6329 clock_array_index = idx[j]; 6330 if (clock_array_index >= clock_info_array->ucNumEntries) 6331 continue; 6332 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6333 break; 6334 clock_info = (union pplib_clock_info *) 6335 ((u8 *)&clock_info_array->clockInfo[0] + 6336 (clock_array_index * clock_info_array->ucEntrySize)); 6337 si_parse_pplib_clock_info(rdev, 6338 &rdev->pm.dpm.ps[i], k, 6339 clock_info); 6340 k++; 6341 } 6342 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6343 } 6344 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6345 return 0; 6346 } 6347 6348 int si_dpm_init(struct radeon_device *rdev) 6349 { 6350 struct rv7xx_power_info *pi; 6351 struct evergreen_power_info *eg_pi; 6352 struct ni_power_info *ni_pi; 6353 struct si_power_info *si_pi; 6354 struct atom_clock_dividers dividers; 6355 int ret; 6356 u32 mask; 6357 6358 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6359 if (si_pi == NULL) 6360 return -ENOMEM; 6361 rdev->pm.dpm.priv = si_pi; 6362 ni_pi = &si_pi->ni; 6363 eg_pi = &ni_pi->eg; 6364 pi = &eg_pi->rv7xx; 6365 6366 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6367 if (ret) 6368 si_pi->sys_pcie_mask = 0; 6369 else 6370 si_pi->sys_pcie_mask = mask; 6371 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6372 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6373 6374 si_set_max_cu_value(rdev); 6375 6376 rv770_get_max_vddc(rdev); 6377 si_get_leakage_vddc(rdev); 6378 si_patch_dependency_tables_based_on_leakage(rdev); 6379 6380 pi->acpi_vddc = 0; 6381 eg_pi->acpi_vddci = 0; 6382 pi->min_vddc_in_table = 0; 6383 pi->max_vddc_in_table = 0; 6384 6385 ret = r600_get_platform_caps(rdev); 6386 if (ret) 6387 return ret; 6388 6389 ret = si_parse_power_table(rdev); 6390 if (ret) 6391 return ret; 6392 ret = r600_parse_extended_power_table(rdev); 6393 if (ret) 6394 return ret; 6395 6396 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6397 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6398 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6399 r600_free_extended_power_table(rdev); 6400 return -ENOMEM; 6401 } 6402 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6403 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6404 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6405 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6406 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6407 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6408 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6409 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6410 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6411 6412 if (rdev->pm.dpm.voltage_response_time == 0) 6413 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6414 if (rdev->pm.dpm.backbias_response_time == 0) 6415 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6416 6417 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6418 0, false, ÷rs); 6419 if (ret) 6420 pi->ref_div = dividers.ref_div + 1; 6421 else 6422 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6423 6424 eg_pi->smu_uvd_hs = false; 6425 6426 pi->mclk_strobe_mode_threshold = 40000; 6427 if (si_is_special_1gb_platform(rdev)) 6428 pi->mclk_stutter_mode_threshold = 0; 6429 else 6430 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6431 pi->mclk_edc_enable_threshold = 40000; 6432 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6433 6434 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6435 6436 pi->voltage_control = 6437 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6438 VOLTAGE_OBJ_GPIO_LUT); 6439 if (!pi->voltage_control) { 6440 si_pi->voltage_control_svi2 = 6441 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6442 VOLTAGE_OBJ_SVID2); 6443 if (si_pi->voltage_control_svi2) 6444 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6445 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 6446 } 6447 6448 pi->mvdd_control = 6449 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 6450 VOLTAGE_OBJ_GPIO_LUT); 6451 6452 eg_pi->vddci_control = 6453 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6454 VOLTAGE_OBJ_GPIO_LUT); 6455 if (!eg_pi->vddci_control) 6456 si_pi->vddci_control_svi2 = 6457 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6458 VOLTAGE_OBJ_SVID2); 6459 6460 si_pi->vddc_phase_shed_control = 6461 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6462 VOLTAGE_OBJ_PHASE_LUT); 6463 6464 rv770_get_engine_memory_ss(rdev); 6465 6466 pi->asi = RV770_ASI_DFLT; 6467 pi->pasi = CYPRESS_HASI_DFLT; 6468 pi->vrc = SISLANDS_VRC_DFLT; 6469 6470 pi->gfx_clock_gating = true; 6471 6472 eg_pi->sclk_deep_sleep = true; 6473 si_pi->sclk_deep_sleep_above_low = false; 6474 6475 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 6476 pi->thermal_protection = true; 6477 else 6478 pi->thermal_protection = false; 6479 6480 eg_pi->dynamic_ac_timing = true; 6481 6482 eg_pi->light_sleep = true; 6483 #if defined(CONFIG_ACPI) 6484 eg_pi->pcie_performance_request = 6485 radeon_acpi_is_pcie_performance_request_supported(rdev); 6486 #else 6487 eg_pi->pcie_performance_request = false; 6488 #endif 6489 6490 si_pi->sram_end = SMC_RAM_END; 6491 6492 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6493 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6494 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6495 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6496 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6497 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6498 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6499 6500 si_initialize_powertune_defaults(rdev); 6501 6502 /* make sure dc limits are valid */ 6503 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 6504 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 6505 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 6506 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 6507 6508 return 0; 6509 } 6510 6511 void si_dpm_fini(struct radeon_device *rdev) 6512 { 6513 int i; 6514 6515 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6516 kfree(rdev->pm.dpm.ps[i].ps_priv); 6517 } 6518 kfree(rdev->pm.dpm.ps); 6519 kfree(rdev->pm.dpm.priv); 6520 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6521 r600_free_extended_power_table(rdev); 6522 } 6523 6524 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6525 struct seq_file *m) 6526 { 6527 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6528 struct radeon_ps *rps = &eg_pi->current_rps; 6529 struct ni_ps *ps = ni_get_ps(rps); 6530 struct rv7xx_pl *pl; 6531 u32 current_index = 6532 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6533 CURRENT_STATE_INDEX_SHIFT; 6534 6535 if (current_index >= ps->performance_level_count) { 6536 seq_printf(m, "invalid dpm profile %d\n", current_index); 6537 } else { 6538 pl = &ps->performance_levels[current_index]; 6539 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6540 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6541 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6542 } 6543 } 6544