xref: /dragonfly/sys/dev/drm/radeon/si_smc.c (revision 78478697) 
1 /*
2  * Copyright 2011 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 
25 #include <linux/firmware.h>
26 #include <drm/drmP.h>
27 #include "radeon.h"
28 #include "sid.h"
29 #include "ppsmc.h"
30 #include "radeon_ucode.h"
31 #include "sislands_smc.h"
32 
33 static int si_set_smc_sram_address(struct radeon_device *rdev,
34 				   u32 smc_address, u32 limit)
35 {
36 	if (smc_address & 3)
37 		return -EINVAL;
38 	if ((smc_address + 3) > limit)
39 		return -EINVAL;
40 
41 	WREG32(SMC_IND_INDEX_0, smc_address);
42 	WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
43 
44 	return 0;
45 }
46 
47 int si_copy_bytes_to_smc(struct radeon_device *rdev,
48 			 u32 smc_start_address,
49 			 const u8 *src, u32 byte_count, u32 limit)
50 {
51 	int ret = 0;
52 	u32 data, original_data, addr, extra_shift;
53 
54 	if (smc_start_address & 3)
55 		return -EINVAL;
56 	if ((smc_start_address + byte_count) > limit)
57 		return -EINVAL;
58 
59 	addr = smc_start_address;
60 
61 	spin_lock(&rdev->smc_idx_lock);
62 	while (byte_count >= 4) {
63 		/* SMC address space is BE */
64 		data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
65 
66 		ret = si_set_smc_sram_address(rdev, addr, limit);
67 		if (ret)
68 			goto done;
69 
70 		WREG32(SMC_IND_DATA_0, data);
71 
72 		src += 4;
73 		byte_count -= 4;
74 		addr += 4;
75 	}
76 
77 	/* RMW for the final bytes */
78 	if (byte_count > 0) {
79 		data = 0;
80 
81 		ret = si_set_smc_sram_address(rdev, addr, limit);
82 		if (ret)
83 			goto done;
84 
85 		original_data = RREG32(SMC_IND_DATA_0);
86 
87 		extra_shift = 8 * (4 - byte_count);
88 
89 		while (byte_count > 0) {
90 			/* SMC address space is BE */
91 			data = (data << 8) + *src++;
92 			byte_count--;
93 		}
94 
95 		data <<= extra_shift;
96 
97 		data |= (original_data & ~((~0UL) << extra_shift));
98 
99 		ret = si_set_smc_sram_address(rdev, addr, limit);
100 		if (ret)
101 			goto done;
102 
103 		WREG32(SMC_IND_DATA_0, data);
104 	}
105 
106 done:
107 	spin_unlock(&rdev->smc_idx_lock);
108 
109 	return ret;
110 }
111 
112 void si_start_smc(struct radeon_device *rdev)
113 {
114 	u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
115 
116 	tmp &= ~RST_REG;
117 
118 	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
119 }
120 
121 void si_reset_smc(struct radeon_device *rdev)
122 {
123 	u32 tmp;
124 
125 	RREG32(CB_CGTT_SCLK_CTRL);
126 	RREG32(CB_CGTT_SCLK_CTRL);
127 	RREG32(CB_CGTT_SCLK_CTRL);
128 	RREG32(CB_CGTT_SCLK_CTRL);
129 
130 	tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
131 	tmp |= RST_REG;
132 	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
133 }
134 
135 int si_program_jump_on_start(struct radeon_device *rdev)
136 {
137 	static u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
138 
139 	return si_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1);
140 }
141 
142 void si_stop_smc_clock(struct radeon_device *rdev)
143 {
144 	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
145 
146 	tmp |= CK_DISABLE;
147 
148 	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
149 }
150 
151 void si_start_smc_clock(struct radeon_device *rdev)
152 {
153 	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
154 
155 	tmp &= ~CK_DISABLE;
156 
157 	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
158 }
159 
160 bool si_is_smc_running(struct radeon_device *rdev)
161 {
162 	u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
163 	u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
164 
165 	if (!(rst & RST_REG) && !(clk & CK_DISABLE))
166 		return true;
167 
168 	return false;
169 }
170 
171 PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
172 {
173 	u32 tmp;
174 	int i;
175 
176 	if (!si_is_smc_running(rdev))
177 		return PPSMC_Result_Failed;
178 
179 	WREG32(SMC_MESSAGE_0, msg);
180 
181 	for (i = 0; i < rdev->usec_timeout; i++) {
182 		tmp = RREG32(SMC_RESP_0);
183 		if (tmp != 0)
184 			break;
185 		udelay(1);
186 	}
187 	tmp = RREG32(SMC_RESP_0);
188 
189 	return (PPSMC_Result)tmp;
190 }
191 
192 PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev)
193 {
194 	u32 tmp;
195 	int i;
196 
197 	if (!si_is_smc_running(rdev))
198 		return PPSMC_Result_OK;
199 
200 	for (i = 0; i < rdev->usec_timeout; i++) {
201 		tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
202 		if ((tmp & CKEN) == 0)
203 			break;
204 		udelay(1);
205 	}
206 
207 	return PPSMC_Result_OK;
208 }
209 
210 int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)
211 {
212 	u32 ucode_start_address;
213 	u32 ucode_size;
214 	const u8 *src;
215 	u32 data;
216 
217 	if (!rdev->smc_fw)
218 		return -EINVAL;
219 
220 	switch (rdev->family) {
221 	case CHIP_TAHITI:
222 		ucode_start_address = TAHITI_SMC_UCODE_START;
223 		ucode_size = TAHITI_SMC_UCODE_SIZE;
224 		break;
225 	case CHIP_PITCAIRN:
226 		ucode_start_address = PITCAIRN_SMC_UCODE_START;
227 		ucode_size = PITCAIRN_SMC_UCODE_SIZE;
228 		break;
229 	case CHIP_VERDE:
230 		ucode_start_address = VERDE_SMC_UCODE_START;
231 		ucode_size = VERDE_SMC_UCODE_SIZE;
232 		break;
233 	case CHIP_OLAND:
234 		ucode_start_address = OLAND_SMC_UCODE_START;
235 		ucode_size = OLAND_SMC_UCODE_SIZE;
236 		break;
237 	case CHIP_HAINAN:
238 		ucode_start_address = HAINAN_SMC_UCODE_START;
239 		ucode_size = HAINAN_SMC_UCODE_SIZE;
240 		break;
241 	default:
242 		DRM_ERROR("unknown asic in smc ucode loader\n");
243 		BUG();
244 	}
245 
246 	if (ucode_size & 3)
247 		return -EINVAL;
248 
249 	src = (const u8 *)rdev->smc_fw->data;
250 	spin_lock(&rdev->smc_idx_lock);
251 	WREG32(SMC_IND_INDEX_0, ucode_start_address);
252 	WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
253 	while (ucode_size >= 4) {
254 		/* SMC address space is BE */
255 		data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
256 
257 		WREG32(SMC_IND_DATA_0, data);
258 
259 		src += 4;
260 		ucode_size -= 4;
261 	}
262 	WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
263 	spin_unlock(&rdev->smc_idx_lock);
264 
265 	return 0;
266 }
267 
268 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
269 			   u32 *value, u32 limit)
270 {
271 	int ret;
272 
273 	spin_lock(&rdev->smc_idx_lock);
274 	ret = si_set_smc_sram_address(rdev, smc_address, limit);
275 	if (ret == 0)
276 		*value = RREG32(SMC_IND_DATA_0);
277 	spin_unlock(&rdev->smc_idx_lock);
278 
279 	return ret;
280 }
281 
282 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
283 			    u32 value, u32 limit)
284 {
285 	int ret;
286 
287 	spin_lock(&rdev->smc_idx_lock);
288 	ret = si_set_smc_sram_address(rdev, smc_address, limit);
289 	if (ret == 0)
290 		WREG32(SMC_IND_DATA_0, value);
291 	spin_unlock(&rdev->smc_idx_lock);
292 
293 	return ret;
294 }
295