1 /*- 2 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx 29 * southbridges. 30 * Please see the following specifications for the descriptions of the 31 * registers and flags: 32 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG) 33 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf 34 * - AMD SB700/710/750 Register Reference Guide (RRG) 35 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf 36 * - AMD SB700/710/750 Register Programming Requirements (RPR) 37 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf 38 * - AMD SB800-Series Southbridges Register Reference Guide (RRG) 39 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf 40 * Please see the following for Watchdog Resource Table specification: 41 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT) 42 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx 43 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above 44 * specifications, but the table hasn't been spotted in the wild yet. 45 * 46 * $FreeBSD: src/sys/dev/amdsbwd/amdsbwd.c,v 1.3 2011/06/07 06:18:02 avg Exp $ 47 */ 48 49 #include <sys/param.h> 50 #include <sys/kernel.h> 51 #include <sys/module.h> 52 #include <sys/systm.h> 53 #include <sys/sysctl.h> 54 #include <sys/bus.h> 55 #include <sys/bus.h> 56 #include <sys/rman.h> 57 #include <sys/resource.h> 58 #include <sys/wdog.h> 59 60 #include <bus/isa/isavar.h> 61 #include <bus/pci/pcivar.h> 62 63 /* SB7xx RRG 2.3.3.1.1. */ 64 #define AMDSB_PMIO_INDEX 0xcd6 65 #define AMDSB_PMIO_DATA (PMIO_INDEX + 1) 66 #define AMDSB_PMIO_WIDTH 2 67 /* SB7xx RRG 2.3.3.2. */ 68 #define AMDSB_PM_RESET_STATUS0 0x44 69 #define AMDSB_PM_RESET_STATUS1 0x45 70 #define AMDSB_WD_RST_STS 0x02 71 /* SB7xx RRG 2.3.3.2, RPR 2.36. */ 72 #define AMDSB_PM_WDT_CTRL 0x69 73 #define AMDSB_WDT_DISABLE 0x01 74 #define AMDSB_WDT_RES_MASK (0x02 | 0x04) 75 #define AMDSB_WDT_RES_32US 0x00 76 #define AMDSB_WDT_RES_10MS 0x02 77 #define AMDSB_WDT_RES_100MS 0x04 78 #define AMDSB_WDT_RES_1S 0x06 79 #define AMDSB_PM_WDT_BASE_LSB 0x6c 80 #define AMDSB_PM_WDT_BASE_MSB 0x6f 81 /* SB8xx RRG 2.3.3. */ 82 #define AMDSB8_PM_WDT_EN 0x48 83 #define AMDSB8_WDT_DEC_EN 0x01 84 #define AMDSB8_WDT_DISABLE 0x02 85 #define AMDSB8_PM_WDT_CTRL 0x4c 86 #define AMDSB8_WDT_32KHZ 0x00 87 #define AMDSB8_WDT_1HZ 0x03 88 #define AMDSB8_WDT_RES_MASK 0x03 89 #define AMDSB8_PM_RESET_STATUS0 0xC0 90 #define AMDSB8_PM_RESET_STATUS1 0xC1 91 #define AMDSB8_WD_RST_STS 0x20 92 /* SB7xx RRG 2.3.4, WDRT. */ 93 #define AMDSB_WD_CTRL 0x00 94 #define AMDSB_WD_RUN 0x01 95 #define AMDSB_WD_FIRED 0x02 96 #define AMDSB_WD_SHUTDOWN 0x04 97 #define AMDSB_WD_DISABLE 0x08 98 #define AMDSB_WD_RESERVED 0x70 99 #define AMDSB_WD_RELOAD 0x80 100 #define AMDSB_WD_COUNT 0x04 101 #define AMDSB_WD_COUNT_MASK 0xffff 102 #define AMDSB_WDIO_REG_WIDTH 4 103 /* WDRT */ 104 #define MAXCOUNT_MIN_VALUE 511 105 /* SB7xx RRG 2.3.1.1, SB600 RRG 2.3.1.1, SB8xx RRG 2.3.1. */ 106 #define AMDSB_SMBUS_DEVID 0x43851002 107 #define AMDSB8_SMBUS_REVID 0x40 108 109 #define amdsbwd_verbose_printf(dev, ...) \ 110 do { \ 111 if (bootverbose) \ 112 device_printf(dev, __VA_ARGS__);\ 113 } while (0) 114 115 struct amdsbwd_softc { 116 device_t dev; 117 struct resource *res_ctrl; 118 struct resource *res_count; 119 int rid_ctrl; 120 int rid_count; 121 int ms_per_tick; 122 int max_ticks; 123 int active; 124 unsigned int timeout; 125 }; 126 static struct amdsbwd_softc amdsbwd_sc; 127 128 static void amdsbwd_identify(driver_t *driver, device_t parent); 129 static int amdsbwd_probe(device_t dev); 130 static int amdsbwd_attach(device_t dev); 131 static int amdsbwd_detach(device_t dev); 132 133 static device_method_t amdsbwd_methods[] = { 134 DEVMETHOD(device_identify, amdsbwd_identify), 135 DEVMETHOD(device_probe, amdsbwd_probe), 136 DEVMETHOD(device_attach, amdsbwd_attach), 137 DEVMETHOD(device_detach, amdsbwd_detach), 138 #if 0 139 DEVMETHOD(device_shutdown, amdsbwd_detach), 140 #endif 141 {0, 0} 142 }; 143 144 static devclass_t amdsbwd_devclass; 145 static driver_t amdsbwd_driver = { 146 "amdsbwd", 147 amdsbwd_methods, 148 0 149 }; 150 151 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL); 152 MODULE_VERSION(amdsbwd, 1); 153 154 155 static uint8_t 156 pmio_read(struct resource *res, uint8_t reg) 157 { 158 bus_write_1(res, 0, reg); /* Index */ 159 return (bus_read_1(res, 1)); /* Data */ 160 } 161 162 static void 163 pmio_write(struct resource *res, uint8_t reg, uint8_t val) 164 { 165 bus_write_1(res, 0, reg); /* Index */ 166 bus_write_1(res, 1, val); /* Data */ 167 } 168 169 static uint32_t 170 wdctrl_read(struct amdsbwd_softc *sc) 171 { 172 return (bus_read_4(sc->res_ctrl, 0)); 173 } 174 175 static void 176 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val) 177 { 178 bus_write_4(sc->res_ctrl, 0, val); 179 } 180 181 static __unused uint32_t 182 wdcount_read(struct amdsbwd_softc *sc) 183 { 184 return (bus_read_4(sc->res_count, 0)); 185 } 186 187 static void 188 wdcount_write(struct amdsbwd_softc *sc, uint32_t val) 189 { 190 bus_write_4(sc->res_count, 0, val); 191 } 192 193 static void 194 amdsbwd_tmr_enable(struct amdsbwd_softc *sc) 195 { 196 uint32_t val; 197 198 val = wdctrl_read(sc); 199 val |= AMDSB_WD_RUN; 200 wdctrl_write(sc, val); 201 sc->active = 1; 202 amdsbwd_verbose_printf(sc->dev, "timer enabled\n"); 203 } 204 205 static void 206 amdsbwd_tmr_disable(struct amdsbwd_softc *sc) 207 { 208 uint32_t val; 209 210 val = wdctrl_read(sc); 211 val &= ~AMDSB_WD_RUN; 212 wdctrl_write(sc, val); 213 sc->active = 0; 214 amdsbwd_verbose_printf(sc->dev, "timer disabled\n"); 215 } 216 217 static void 218 amdsbwd_tmr_reload(struct amdsbwd_softc *sc) 219 { 220 uint32_t val; 221 222 val = wdctrl_read(sc); 223 val |= AMDSB_WD_RELOAD; 224 wdctrl_write(sc, val); 225 } 226 227 static void 228 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout) 229 { 230 231 timeout &= AMDSB_WD_COUNT_MASK; 232 wdcount_write(sc, timeout); 233 sc->timeout = timeout; 234 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout); 235 } 236 237 static int 238 amdsb_watchdog(void *unused, int period) 239 { 240 unsigned int timeout; 241 struct amdsbwd_softc *sc; 242 243 sc = &amdsbwd_sc; 244 timeout = (period * 1000) / sc->ms_per_tick; 245 if (timeout > sc->max_ticks) 246 timeout = sc->max_ticks; 247 if (timeout != sc->timeout) { 248 amdsbwd_tmr_set(sc, timeout); 249 if (!sc->active) 250 amdsbwd_tmr_enable(sc); 251 } 252 amdsbwd_tmr_reload(sc); 253 254 return period; 255 } 256 257 static void 258 amdsbwd_identify(driver_t *driver, device_t parent) 259 { 260 device_t child; 261 device_t smb_dev; 262 263 if (resource_disabled("amdsbwd", 0)) 264 return; 265 if (device_find_child(parent, "amdsbwd", -1) != NULL) 266 return; 267 268 /* 269 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device 270 * that should be present at bus 0, device 20, function 0. 271 */ 272 smb_dev = pci_find_bsf(0, 20, 0); 273 if (smb_dev == NULL) 274 return; 275 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID) 276 return; 277 278 child = BUS_ADD_CHILD(parent, parent, 0, "amdsbwd", 0); 279 if (child == NULL) 280 device_printf(parent, "add amdsbwd child failed\n"); 281 } 282 283 284 static void 285 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr) 286 { 287 uint32_t val; 288 int i; 289 290 /* Report cause of previous reset for user's convenience. */ 291 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0); 292 if (val != 0) 293 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 294 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1); 295 if (val != 0) 296 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 297 if ((val & AMDSB_WD_RST_STS) != 0) 298 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 299 300 /* Find base address of memory mapped WDT registers. */ 301 for (*addr = 0, i = 0; i < 4; i++) { 302 *addr <<= 8; 303 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i); 304 } 305 /* Set watchdog timer tick to 1s. */ 306 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 307 val &= ~AMDSB_WDT_RES_MASK; 308 val |= AMDSB_WDT_RES_10MS; 309 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 310 311 /* Enable watchdog device (in stopped state). */ 312 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 313 val &= ~AMDSB_WDT_DISABLE; 314 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 315 316 /* 317 * XXX TODO: Ensure that watchdog decode is enabled 318 * (register 0x41, bit 3). 319 */ 320 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer"); 321 } 322 323 static void 324 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr) 325 { 326 uint32_t val; 327 int i; 328 329 /* Report cause of previous reset for user's convenience. */ 330 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS0); 331 if (val != 0) 332 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 333 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS1); 334 if (val != 0) 335 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 336 if ((val & AMDSB8_WD_RST_STS) != 0) 337 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 338 339 /* Find base address of memory mapped WDT registers. */ 340 for (*addr = 0, i = 0; i < 4; i++) { 341 *addr <<= 8; 342 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i); 343 } 344 *addr &= ~0x07u; 345 346 /* Set watchdog timer tick to 1s. */ 347 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 348 val &= ~AMDSB8_WDT_RES_MASK; 349 val |= AMDSB8_WDT_1HZ; 350 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val); 351 #ifdef AMDSBWD_DEBUG 352 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 353 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#02x\n", val); 354 #endif 355 356 /* 357 * Enable watchdog device (in stopped state) 358 * and decoding of its address. 359 */ 360 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 361 val &= ~AMDSB8_WDT_DISABLE; 362 val |= AMDSB8_WDT_DEC_EN; 363 pmio_write(pmres, AMDSB8_PM_WDT_EN, val); 364 #ifdef AMDSBWD_DEBUG 365 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 366 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#02x\n", val); 367 #endif 368 device_set_desc(dev, "AMD SB8xx Watchdog Timer"); 369 } 370 371 static int 372 amdsbwd_probe(device_t dev) 373 { 374 struct resource *res; 375 device_t smb_dev; 376 uint32_t addr; 377 int rid; 378 int rc; 379 380 /* Do not claim some ISA PnP device by accident. */ 381 if (isa_get_logicalid(dev) != 0) 382 return (ENXIO); 383 384 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX, 385 AMDSB_PMIO_WIDTH, -1); 386 if (rc != 0) { 387 device_printf(dev, "bus_set_resource for IO failed\n"); 388 return (ENXIO); 389 } 390 rid = 0; 391 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0ul, ~0ul, 392 AMDSB_PMIO_WIDTH, RF_ACTIVE | RF_SHAREABLE); 393 if (res == NULL) { 394 device_printf(dev, "bus_alloc_resource for IO failed\n"); 395 return (ENXIO); 396 } 397 398 smb_dev = pci_find_bsf(0, 20, 0); 399 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n")); 400 if (pci_get_revid(smb_dev) < AMDSB8_SMBUS_REVID) 401 amdsbwd_probe_sb7xx(dev, res, &addr); 402 else 403 amdsbwd_probe_sb8xx(dev, res, &addr); 404 405 bus_release_resource(dev, SYS_RES_IOPORT, rid, res); 406 bus_delete_resource(dev, SYS_RES_IOPORT, rid); 407 408 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr); 409 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL, 410 AMDSB_WDIO_REG_WIDTH, -1); 411 if (rc != 0) { 412 device_printf(dev, "bus_set_resource for control failed\n"); 413 return (ENXIO); 414 } 415 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT, 416 AMDSB_WDIO_REG_WIDTH, -1); 417 if (rc != 0) { 418 device_printf(dev, "bus_set_resource for count failed\n"); 419 return (ENXIO); 420 } 421 422 return (0); 423 } 424 425 static int 426 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc) 427 { 428 device_t smb_dev; 429 430 sc->max_ticks = UINT16_MAX; 431 sc->rid_ctrl = 0; 432 sc->rid_count = 1; 433 434 smb_dev = pci_find_bsf(0, 20, 0); 435 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n")); 436 if (pci_get_revid(smb_dev) < AMDSB8_SMBUS_REVID) 437 sc->ms_per_tick = 10; 438 else 439 sc->ms_per_tick = 1000; 440 441 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 442 &sc->rid_ctrl, RF_ACTIVE); 443 if (sc->res_ctrl == NULL) { 444 device_printf(dev, "bus_alloc_resource for ctrl failed\n"); 445 return (ENXIO); 446 } 447 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 448 &sc->rid_count, RF_ACTIVE); 449 if (sc->res_count == NULL) { 450 device_printf(dev, "bus_alloc_resource for count failed\n"); 451 return (ENXIO); 452 } 453 return (0); 454 } 455 456 static struct watchdog amdsb_wdog = { 457 .name = "AMD southbridge", 458 .wdog_fn = amdsb_watchdog, 459 .arg = NULL, 460 .period_max = (UINT16_MAX*1000) / 10, 461 }; 462 463 static int 464 amdsbwd_attach(device_t dev) 465 { 466 struct amdsbwd_softc *sc; 467 int rc; 468 469 sc = &amdsbwd_sc; 470 sc->dev = dev; 471 472 rc = amdsbwd_attach_sb(dev, sc); 473 if (rc != 0) 474 goto fail; 475 476 #ifdef AMDSBWD_DEBUG 477 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc)); 478 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc)); 479 #endif 480 481 /* Setup initial state of Watchdog Control. */ 482 wdctrl_write(sc, AMDSB_WD_FIRED); 483 484 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) { 485 device_printf(dev, "watchdog hardware is disabled\n"); 486 goto fail; 487 } 488 489 wdog_register(&amdsb_wdog); 490 491 return (0); 492 493 fail: 494 amdsbwd_detach(dev); 495 return (ENXIO); 496 } 497 498 static int 499 amdsbwd_detach(device_t dev) 500 { 501 struct amdsbwd_softc *sc; 502 503 sc = &amdsbwd_sc; 504 wdog_unregister(&amdsb_wdog); 505 506 if (sc->active) 507 amdsbwd_tmr_disable(sc); 508 509 if (sc->res_ctrl != NULL) 510 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl, 511 sc->res_ctrl); 512 513 if (sc->res_count != NULL) 514 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count, 515 sc->res_count); 516 517 return (0); 518 } 519