1 /*- 2 * Copyright (c) 2001 Alcove - Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp $ 27 * $DragonFly: src/sys/dev/misc/ppc/ppc.c,v 1.9 2005/07/17 02:41:10 swildner Exp $ 28 * 29 */ 30 31 #include "opt_ppc.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/malloc.h> 38 #include <sys/thread2.h> 39 40 #include <vm/vm.h> 41 #include <vm/pmap.h> 42 #include <machine/clock.h> 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/vmparam.h> 46 #include <sys/rman.h> 47 48 #include <bus/isa/isareg.h> 49 #include <bus/isa/isavar.h> 50 51 #include <bus/ppbus/ppbconf.h> 52 #include <bus/ppbus/ppb_msq.h> 53 54 #include "ppcreg.h" 55 56 #include "ppbus_if.h" 57 58 #define LOG_PPC(function, ppc, string) \ 59 if (bootverbose) printf("%s: %s\n", function, string) 60 61 62 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 63 64 devclass_t ppc_devclass; 65 66 static int ppc_probe(device_t dev); 67 static int ppc_attach(device_t dev); 68 static int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val); 69 70 static void ppc_reset_epp(device_t); 71 static void ppc_ecp_sync(device_t); 72 static void ppcintr(void *arg); 73 74 static int ppc_exec_microseq(device_t, struct ppb_microseq **); 75 static int ppc_setmode(device_t, int); 76 77 static int ppc_read(device_t, char *, int, int); 78 static int ppc_write(device_t, char *, int, int); 79 80 static u_char ppc_io(device_t, int, u_char *, int, u_char); 81 82 static int ppc_setup_intr(device_t, device_t, struct resource *, int, 83 void (*)(void *), void *, void **, lwkt_serialize_t); 84 static int ppc_teardown_intr(device_t, device_t, struct resource *, void *); 85 86 static device_method_t ppc_methods[] = { 87 /* device interface */ 88 DEVMETHOD(device_probe, ppc_probe), 89 DEVMETHOD(device_attach, ppc_attach), 90 91 /* bus interface */ 92 DEVMETHOD(bus_read_ivar, ppc_read_ivar), 93 DEVMETHOD(bus_setup_intr, ppc_setup_intr), 94 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr), 95 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 96 97 /* ppbus interface */ 98 DEVMETHOD(ppbus_io, ppc_io), 99 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq), 100 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp), 101 DEVMETHOD(ppbus_setmode, ppc_setmode), 102 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync), 103 DEVMETHOD(ppbus_read, ppc_read), 104 DEVMETHOD(ppbus_write, ppc_write), 105 106 { 0, 0 } 107 }; 108 109 static driver_t ppc_driver = { 110 "ppc", 111 ppc_methods, 112 sizeof(struct ppc_data), 113 }; 114 115 static char *ppc_models[] = { 116 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 117 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 118 "SMC FDC37C935", "PC87303", 0 119 }; 120 121 /* list of available modes */ 122 static char *ppc_avms[] = { 123 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 124 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 125 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 126 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 127 }; 128 129 /* list of current executing modes 130 * Note that few modes do not actually exist. 131 */ 132 static char *ppc_modes[] = { 133 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 134 "EPP", "EPP", "EPP", "ECP", 135 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 136 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 137 }; 138 139 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 140 141 #ifdef __i386__ 142 /* 143 * BIOS printer list - used by BIOS probe. 144 */ 145 #define BIOS_PPC_PORTS 0x408 146 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 147 #define BIOS_MAX_PPC 4 148 #endif 149 150 /* 151 * ppc_ecp_sync() XXX 152 */ 153 static void 154 ppc_ecp_sync(device_t dev) { 155 156 int i, r; 157 struct ppc_data *ppc = DEVTOSOFTC(dev); 158 159 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) 160 return; 161 162 r = r_ecr(ppc); 163 if ((r & 0xe0) != PPC_ECR_EPP) 164 return; 165 166 for (i = 0; i < 100; i++) { 167 r = r_ecr(ppc); 168 if (r & 0x1) 169 return; 170 DELAY(100); 171 } 172 173 printf("ppc%d: ECP sync failed as data still " \ 174 "present in FIFO.\n", ppc->ppc_unit); 175 176 return; 177 } 178 179 /* 180 * ppc_detect_fifo() 181 * 182 * Detect parallel port FIFO 183 */ 184 static int 185 ppc_detect_fifo(struct ppc_data *ppc) 186 { 187 char ecr_sav; 188 char ctr_sav, ctr, cc; 189 short i; 190 191 /* save registers */ 192 ecr_sav = r_ecr(ppc); 193 ctr_sav = r_ctr(ppc); 194 195 /* enter ECP configuration mode, no interrupt, no DMA */ 196 w_ecr(ppc, 0xf4); 197 198 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 199 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 200 201 /* XXX 16 and 32 bits implementations not supported */ 202 if (ppc->ppc_pword != PPC_PWORD_8) { 203 LOG_PPC(__func__, ppc, "PWord not supported"); 204 goto error; 205 } 206 207 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 208 ctr = r_ctr(ppc); 209 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 210 211 /* enter ECP test mode, no interrupt, no DMA */ 212 w_ecr(ppc, 0xd4); 213 214 /* flush the FIFO */ 215 for (i=0; i<1024; i++) { 216 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 217 break; 218 cc = r_fifo(ppc); 219 } 220 221 if (i >= 1024) { 222 LOG_PPC(__func__, ppc, "can't flush FIFO"); 223 goto error; 224 } 225 226 /* enable interrupts, no DMA */ 227 w_ecr(ppc, 0xd0); 228 229 /* determine readIntrThreshold 230 * fill the FIFO until serviceIntr is set 231 */ 232 for (i=0; i<1024; i++) { 233 w_fifo(ppc, (char)i); 234 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 235 /* readThreshold reached */ 236 ppc->ppc_rthr = i+1; 237 } 238 if (r_ecr(ppc) & PPC_FIFO_FULL) { 239 ppc->ppc_fifo = i+1; 240 break; 241 } 242 } 243 244 if (i >= 1024) { 245 LOG_PPC(__func__, ppc, "can't fill FIFO"); 246 goto error; 247 } 248 249 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 250 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 251 w_ecr(ppc, 0xd0); /* enable interrupts */ 252 253 /* determine writeIntrThreshold 254 * empty the FIFO until serviceIntr is set 255 */ 256 for (i=ppc->ppc_fifo; i>0; i--) { 257 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 258 LOG_PPC(__func__, ppc, "invalid data in FIFO"); 259 goto error; 260 } 261 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 262 /* writeIntrThreshold reached */ 263 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 264 } 265 /* if FIFO empty before the last byte, error */ 266 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 267 LOG_PPC(__func__, ppc, "data lost in FIFO"); 268 goto error; 269 } 270 } 271 272 /* FIFO must be empty after the last byte */ 273 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 274 LOG_PPC(__func__, ppc, "can't empty the FIFO"); 275 goto error; 276 } 277 278 w_ctr(ppc, ctr_sav); 279 w_ecr(ppc, ecr_sav); 280 281 return (0); 282 283 error: 284 w_ctr(ppc, ctr_sav); 285 w_ecr(ppc, ecr_sav); 286 287 return (EINVAL); 288 } 289 290 static int 291 ppc_detect_port(struct ppc_data *ppc) 292 { 293 294 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 295 w_dtr(ppc, 0xaa); 296 if (r_dtr(ppc) != 0xaa) 297 return (0); 298 299 return (1); 300 } 301 302 /* 303 * EPP timeout, according to the PC87332 manual 304 * Semantics of clearing EPP timeout bit. 305 * PC87332 - reading SPP_STR does it... 306 * SMC - write 1 to EPP timeout bit XXX 307 * Others - (?) write 0 to EPP timeout bit 308 */ 309 static void 310 ppc_reset_epp_timeout(struct ppc_data *ppc) 311 { 312 char r; 313 314 r = r_str(ppc); 315 w_str(ppc, r | 0x1); 316 w_str(ppc, r & 0xfe); 317 318 return; 319 } 320 321 static int 322 ppc_check_epp_timeout(struct ppc_data *ppc) 323 { 324 ppc_reset_epp_timeout(ppc); 325 326 return (!(r_str(ppc) & TIMEOUT)); 327 } 328 329 /* 330 * Configure current operating mode 331 */ 332 static int 333 ppc_generic_setmode(struct ppc_data *ppc, int mode) 334 { 335 u_char ecr = 0; 336 337 /* check if mode is available */ 338 if (mode && !(ppc->ppc_avm & mode)) 339 return (EINVAL); 340 341 /* if ECP mode, configure ecr register */ 342 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 343 /* return to byte mode (keeping direction bit), 344 * no interrupt, no DMA to be able to change to 345 * ECP 346 */ 347 w_ecr(ppc, PPC_ECR_RESET); 348 ecr = PPC_DISABLE_INTR; 349 350 if (mode & PPB_EPP) 351 return (EINVAL); 352 else if (mode & PPB_ECP) 353 /* select ECP mode */ 354 ecr |= PPC_ECR_ECP; 355 else if (mode & PPB_PS2) 356 /* select PS2 mode with ECP */ 357 ecr |= PPC_ECR_PS2; 358 else 359 /* select COMPATIBLE/NIBBLE mode */ 360 ecr |= PPC_ECR_STD; 361 362 w_ecr(ppc, ecr); 363 } 364 365 ppc->ppc_mode = mode; 366 367 return (0); 368 } 369 370 /* 371 * The ppc driver is free to choose options like FIFO or DMA 372 * if ECP mode is available. 373 * 374 * The 'RAW' option allows the upper drivers to force the ppc mode 375 * even with FIFO, DMA available. 376 */ 377 static int 378 ppc_smclike_setmode(struct ppc_data *ppc, int mode) 379 { 380 u_char ecr = 0; 381 382 /* check if mode is available */ 383 if (mode && !(ppc->ppc_avm & mode)) 384 return (EINVAL); 385 386 /* if ECP mode, configure ecr register */ 387 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 388 /* return to byte mode (keeping direction bit), 389 * no interrupt, no DMA to be able to change to 390 * ECP or EPP mode 391 */ 392 w_ecr(ppc, PPC_ECR_RESET); 393 ecr = PPC_DISABLE_INTR; 394 395 if (mode & PPB_EPP) 396 /* select EPP mode */ 397 ecr |= PPC_ECR_EPP; 398 else if (mode & PPB_ECP) 399 /* select ECP mode */ 400 ecr |= PPC_ECR_ECP; 401 else if (mode & PPB_PS2) 402 /* select PS2 mode with ECP */ 403 ecr |= PPC_ECR_PS2; 404 else 405 /* select COMPATIBLE/NIBBLE mode */ 406 ecr |= PPC_ECR_STD; 407 408 w_ecr(ppc, ecr); 409 } 410 411 ppc->ppc_mode = mode; 412 413 return (0); 414 } 415 416 #ifdef PPC_PROBE_CHIPSET 417 /* 418 * ppc_pc873xx_detect 419 * 420 * Probe for a Natsemi PC873xx-family part. 421 * 422 * References in this function are to the National Semiconductor 423 * PC87332 datasheet TL/C/11930, May 1995 revision. 424 */ 425 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 426 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 427 static int pc873xx_irqtab[] = {5, 7, 5, 0}; 428 429 static int pc873xx_regstab[] = { 430 PC873_FER, PC873_FAR, PC873_PTR, 431 PC873_FCR, PC873_PCR, PC873_PMC, 432 PC873_TUP, PC873_SID, PC873_PNP0, 433 PC873_PNP1, PC873_LPTBA, -1 434 }; 435 436 static char *pc873xx_rnametab[] = { 437 "FER", "FAR", "PTR", "FCR", "PCR", 438 "PMC", "TUP", "SID", "PNP0", "PNP1", 439 "LPTBA", NULL 440 }; 441 442 static int 443 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 444 { 445 static int index = 0; 446 int idport, irq; 447 int ptr, pcr, val, i; 448 449 while ((idport = pc873xx_basetab[index++])) { 450 451 /* XXX should check first to see if this location is already claimed */ 452 453 /* 454 * Pull the 873xx through the power-on ID cycle (2.2,1.). 455 * We can't use this to locate the chip as it may already have 456 * been used by the BIOS. 457 */ 458 (void)inb(idport); (void)inb(idport); 459 (void)inb(idport); (void)inb(idport); 460 461 /* 462 * Read the SID byte. Possible values are : 463 * 464 * 01010xxx PC87334 465 * 0001xxxx PC87332 466 * 01110xxx PC87306 467 * 00110xxx PC87303 468 */ 469 outb(idport, PC873_SID); 470 val = inb(idport + 1); 471 if ((val & 0xf0) == 0x10) { 472 ppc->ppc_model = NS_PC87332; 473 } else if ((val & 0xf8) == 0x70) { 474 ppc->ppc_model = NS_PC87306; 475 } else if ((val & 0xf8) == 0x50) { 476 ppc->ppc_model = NS_PC87334; 477 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the 478 documentation, but probing 479 yielded 0x40... */ 480 ppc->ppc_model = NS_PC87303; 481 } else { 482 if (bootverbose && (val != 0xff)) 483 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 484 continue ; /* not recognised */ 485 } 486 487 /* print registers */ 488 if (bootverbose) { 489 printf("PC873xx"); 490 for (i=0; pc873xx_regstab[i] != -1; i++) { 491 outb(idport, pc873xx_regstab[i]); 492 printf(" %s=0x%x", pc873xx_rnametab[i], 493 inb(idport + 1) & 0xff); 494 } 495 printf("\n"); 496 } 497 498 /* 499 * We think we have one. Is it enabled and where we want it to be? 500 */ 501 outb(idport, PC873_FER); 502 val = inb(idport + 1); 503 if (!(val & PC873_PPENABLE)) { 504 if (bootverbose) 505 printf("PC873xx parallel port disabled\n"); 506 continue; 507 } 508 outb(idport, PC873_FAR); 509 val = inb(idport + 1); 510 /* XXX we should create a driver instance for every port found */ 511 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { 512 513 /* First try to change the port address to that requested... */ 514 515 switch(ppc->ppc_base) { 516 case 0x378: 517 val &= 0xfc; 518 break; 519 520 case 0x3bc: 521 val &= 0xfd; 522 break; 523 524 case 0x278: 525 val &= 0xfe; 526 break; 527 528 default: 529 val &= 0xfd; 530 break; 531 } 532 533 outb(idport, PC873_FAR); 534 outb(idport + 1, val); 535 outb(idport + 1, val); 536 537 /* Check for success by reading back the value we supposedly 538 wrote and comparing...*/ 539 540 outb(idport, PC873_FAR); 541 val = inb(idport + 1) & 0x3; 542 543 /* If we fail, report the failure... */ 544 545 if (pc873xx_porttab[val] != ppc->ppc_base) { 546 if (bootverbose) 547 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 548 pc873xx_porttab[val], ppc->ppc_base); 549 } 550 continue; 551 } 552 553 outb(idport, PC873_PTR); 554 ptr = inb(idport + 1); 555 556 /* get irq settings */ 557 if (ppc->ppc_base == 0x378) 558 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 559 else 560 irq = pc873xx_irqtab[val]; 561 562 if (bootverbose) 563 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 564 565 /* 566 * Check if irq settings are correct 567 */ 568 if (irq != ppc->ppc_irq) { 569 /* 570 * If the chipset is not locked and base address is 0x378, 571 * we have another chance 572 */ 573 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 574 if (ppc->ppc_irq == 7) { 575 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 576 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 577 } else { 578 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 579 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 580 } 581 if (bootverbose) 582 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 583 } else { 584 if (bootverbose) 585 printf("PC873xx sorry, can't change irq setting\n"); 586 } 587 } else { 588 if (bootverbose) 589 printf("PC873xx irq settings are correct\n"); 590 } 591 592 outb(idport, PC873_PCR); 593 pcr = inb(idport + 1); 594 595 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 596 if (bootverbose) 597 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 598 599 ppc->ppc_avm |= PPB_NIBBLE; 600 if (bootverbose) 601 printf(", NIBBLE"); 602 603 if (pcr & PC873_EPPEN) { 604 ppc->ppc_avm |= PPB_EPP; 605 606 if (bootverbose) 607 printf(", EPP"); 608 609 if (pcr & PC873_EPP19) 610 ppc->ppc_epp = EPP_1_9; 611 else 612 ppc->ppc_epp = EPP_1_7; 613 614 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 615 outb(idport, PC873_PTR); 616 ptr = inb(idport + 1); 617 if (ptr & PC873_EPPRDIR) 618 printf(", Regular mode"); 619 else 620 printf(", Automatic mode"); 621 } 622 } else if (pcr & PC873_ECPEN) { 623 ppc->ppc_avm |= PPB_ECP; 624 if (bootverbose) 625 printf(", ECP"); 626 627 if (pcr & PC873_ECPCLK) { /* XXX */ 628 ppc->ppc_avm |= PPB_PS2; 629 if (bootverbose) 630 printf(", PS/2"); 631 } 632 } else { 633 outb(idport, PC873_PTR); 634 ptr = inb(idport + 1); 635 if (ptr & PC873_EXTENDED) { 636 ppc->ppc_avm |= PPB_SPP; 637 if (bootverbose) 638 printf(", SPP"); 639 } 640 } 641 } else { 642 if (bootverbose) 643 printf("PC873xx unlocked"); 644 645 if (chipset_mode & PPB_ECP) { 646 if ((chipset_mode & PPB_EPP) && bootverbose) 647 printf(", ECP+EPP not supported"); 648 649 pcr &= ~PC873_EPPEN; 650 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 651 outb(idport + 1, pcr); 652 outb(idport + 1, pcr); 653 654 if (bootverbose) 655 printf(", ECP"); 656 657 } else if (chipset_mode & PPB_EPP) { 658 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 659 pcr |= (PC873_EPPEN | PC873_EPP19); 660 outb(idport + 1, pcr); 661 outb(idport + 1, pcr); 662 663 ppc->ppc_epp = EPP_1_9; /* XXX */ 664 665 if (bootverbose) 666 printf(", EPP1.9"); 667 668 /* enable automatic direction turnover */ 669 if (ppc->ppc_model == NS_PC87332) { 670 outb(idport, PC873_PTR); 671 ptr = inb(idport + 1); 672 ptr &= ~PC873_EPPRDIR; 673 outb(idport + 1, ptr); 674 outb(idport + 1, ptr); 675 676 if (bootverbose) 677 printf(", Automatic mode"); 678 } 679 } else { 680 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 681 outb(idport + 1, pcr); 682 outb(idport + 1, pcr); 683 684 /* configure extended bit in PTR */ 685 outb(idport, PC873_PTR); 686 ptr = inb(idport + 1); 687 688 if (chipset_mode & PPB_PS2) { 689 ptr |= PC873_EXTENDED; 690 691 if (bootverbose) 692 printf(", PS/2"); 693 694 } else { 695 /* default to NIBBLE mode */ 696 ptr &= ~PC873_EXTENDED; 697 698 if (bootverbose) 699 printf(", NIBBLE"); 700 } 701 outb(idport + 1, ptr); 702 outb(idport + 1, ptr); 703 } 704 705 ppc->ppc_avm = chipset_mode; 706 } 707 708 if (bootverbose) 709 printf("\n"); 710 711 ppc->ppc_type = PPC_TYPE_GENERIC; 712 ppc_generic_setmode(ppc, chipset_mode); 713 714 return(chipset_mode); 715 } 716 return(-1); 717 } 718 719 /* 720 * ppc_smc37c66xgt_detect 721 * 722 * SMC FDC37C66xGT configuration. 723 */ 724 static int 725 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 726 { 727 int i; 728 u_char r; 729 int type = -1; 730 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 731 732 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 733 734 735 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 736 737 /* 738 * Detection: enter configuration mode and read CRD register. 739 */ 740 741 crit_enter(); 742 outb(csr, SMC665_iCODE); 743 outb(csr, SMC665_iCODE); 744 crit_exit(); 745 746 outb(csr, 0xd); 747 if (inb(cio) == 0x65) { 748 type = SMC_37C665GT; 749 goto config; 750 } 751 752 for (i = 0; i < 2; i++) { 753 crit_enter(); 754 outb(csr, SMC666_iCODE); 755 outb(csr, SMC666_iCODE); 756 crit_exit(); 757 758 outb(csr, 0xd); 759 if (inb(cio) == 0x66) { 760 type = SMC_37C666GT; 761 break; 762 } 763 764 /* Another chance, CSR may be hard-configured to be at 0x370 */ 765 csr = SMC666_CSR; 766 } 767 768 config: 769 /* 770 * If chipset not found, do not continue. 771 */ 772 if (type == -1) 773 return (-1); 774 775 /* select CR1 */ 776 outb(csr, 0x1); 777 778 /* read the port's address: bits 0 and 1 of CR1 */ 779 r = inb(cio) & SMC_CR1_ADDR; 780 if (port_address[(int)r] != ppc->ppc_base) 781 return (-1); 782 783 ppc->ppc_model = type; 784 785 /* 786 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 787 * If SPP mode is detected, try to set ECP+EPP mode 788 */ 789 790 if (bootverbose) { 791 outb(csr, 0x1); 792 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 793 inb(cio) & 0xff); 794 795 outb(csr, 0x4); 796 printf(" CR4=0x%x", inb(cio) & 0xff); 797 } 798 799 /* select CR1 */ 800 outb(csr, 0x1); 801 802 if (!chipset_mode) { 803 /* autodetect mode */ 804 805 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 806 if (type == SMC_37C666GT) { 807 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 808 if (bootverbose) 809 printf(" configuration hardwired, supposing " \ 810 "ECP+EPP SPP"); 811 812 } else 813 if ((inb(cio) & SMC_CR1_MODE) == 0) { 814 /* already in extended parallel port mode, read CR4 */ 815 outb(csr, 0x4); 816 r = (inb(cio) & SMC_CR4_EMODE); 817 818 switch (r) { 819 case SMC_SPP: 820 ppc->ppc_avm |= PPB_SPP; 821 if (bootverbose) 822 printf(" SPP"); 823 break; 824 825 case SMC_EPPSPP: 826 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 827 if (bootverbose) 828 printf(" EPP SPP"); 829 break; 830 831 case SMC_ECP: 832 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 833 if (bootverbose) 834 printf(" ECP SPP"); 835 break; 836 837 case SMC_ECPEPP: 838 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 839 if (bootverbose) 840 printf(" ECP+EPP SPP"); 841 break; 842 } 843 } else { 844 /* not an extended port mode */ 845 ppc->ppc_avm |= PPB_SPP; 846 if (bootverbose) 847 printf(" SPP"); 848 } 849 850 } else { 851 /* mode forced */ 852 ppc->ppc_avm = chipset_mode; 853 854 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 855 if (type == SMC_37C666GT) 856 goto end_detect; 857 858 r = inb(cio); 859 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 860 /* do not use ECP when the mode is not forced to */ 861 outb(cio, r | SMC_CR1_MODE); 862 if (bootverbose) 863 printf(" SPP"); 864 } else { 865 /* an extended mode is selected */ 866 outb(cio, r & ~SMC_CR1_MODE); 867 868 /* read CR4 register and reset mode field */ 869 outb(csr, 0x4); 870 r = inb(cio) & ~SMC_CR4_EMODE; 871 872 if (chipset_mode & PPB_ECP) { 873 if (chipset_mode & PPB_EPP) { 874 outb(cio, r | SMC_ECPEPP); 875 if (bootverbose) 876 printf(" ECP+EPP"); 877 } else { 878 outb(cio, r | SMC_ECP); 879 if (bootverbose) 880 printf(" ECP"); 881 } 882 } else { 883 /* PPB_EPP is set */ 884 outb(cio, r | SMC_EPPSPP); 885 if (bootverbose) 886 printf(" EPP SPP"); 887 } 888 } 889 ppc->ppc_avm = chipset_mode; 890 } 891 892 /* set FIFO threshold to 16 */ 893 if (ppc->ppc_avm & PPB_ECP) { 894 /* select CRA */ 895 outb(csr, 0xa); 896 outb(cio, 16); 897 } 898 899 end_detect: 900 901 if (bootverbose) 902 printf ("\n"); 903 904 if (ppc->ppc_avm & PPB_EPP) { 905 /* select CR4 */ 906 outb(csr, 0x4); 907 r = inb(cio); 908 909 /* 910 * Set the EPP protocol... 911 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 912 */ 913 if (ppc->ppc_epp == EPP_1_9) 914 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 915 else 916 outb(cio, (r | SMC_CR4_EPPTYPE)); 917 } 918 919 /* end config mode */ 920 outb(csr, 0xaa); 921 922 ppc->ppc_type = PPC_TYPE_SMCLIKE; 923 ppc_smclike_setmode(ppc, chipset_mode); 924 925 return (chipset_mode); 926 } 927 928 /* 929 * SMC FDC37C935 configuration 930 * Found on many Alpha machines 931 */ 932 static int 933 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) 934 { 935 int type = -1; 936 937 crit_enter(); 938 outb(SMC935_CFG, 0x55); /* enter config mode */ 939 outb(SMC935_CFG, 0x55); 940 crit_exit(); 941 942 outb(SMC935_IND, SMC935_ID); /* check device id */ 943 if (inb(SMC935_DAT) == 0x2) 944 type = SMC_37C935; 945 946 if (type == -1) { 947 outb(SMC935_CFG, 0xaa); /* exit config mode */ 948 return (-1); 949 } 950 951 ppc->ppc_model = type; 952 953 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ 954 outb(SMC935_DAT, 3); /* which is logical device 3 */ 955 956 /* set io port base */ 957 outb(SMC935_IND, SMC935_PORTHI); 958 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); 959 outb(SMC935_IND, SMC935_PORTLO); 960 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); 961 962 if (!chipset_mode) 963 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ 964 else { 965 ppc->ppc_avm = chipset_mode; 966 outb(SMC935_IND, SMC935_PPMODE); 967 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ 968 969 /* SPP + EPP or just plain SPP */ 970 if (chipset_mode & (PPB_SPP)) { 971 if (chipset_mode & PPB_EPP) { 972 if (ppc->ppc_epp == EPP_1_9) { 973 outb(SMC935_IND, SMC935_PPMODE); 974 outb(SMC935_DAT, SMC935_EPP19SPP); 975 } 976 if (ppc->ppc_epp == EPP_1_7) { 977 outb(SMC935_IND, SMC935_PPMODE); 978 outb(SMC935_DAT, SMC935_EPP17SPP); 979 } 980 } else { 981 outb(SMC935_IND, SMC935_PPMODE); 982 outb(SMC935_DAT, SMC935_SPP); 983 } 984 } 985 986 /* ECP + EPP or just plain ECP */ 987 if (chipset_mode & PPB_ECP) { 988 if (chipset_mode & PPB_EPP) { 989 if (ppc->ppc_epp == EPP_1_9) { 990 outb(SMC935_IND, SMC935_PPMODE); 991 outb(SMC935_DAT, SMC935_ECPEPP19); 992 } 993 if (ppc->ppc_epp == EPP_1_7) { 994 outb(SMC935_IND, SMC935_PPMODE); 995 outb(SMC935_DAT, SMC935_ECPEPP17); 996 } 997 } else { 998 outb(SMC935_IND, SMC935_PPMODE); 999 outb(SMC935_DAT, SMC935_ECP); 1000 } 1001 } 1002 } 1003 1004 outb(SMC935_CFG, 0xaa); /* exit config mode */ 1005 1006 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1007 ppc_smclike_setmode(ppc, chipset_mode); 1008 1009 return (chipset_mode); 1010 } 1011 1012 /* 1013 * Winbond W83877F stuff 1014 * 1015 * EFER: extended function enable register 1016 * EFIR: extended function index register 1017 * EFDR: extended function data register 1018 */ 1019 #define efir ((efer == 0x250) ? 0x251 : 0x3f0) 1020 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 1021 1022 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 1023 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 1024 static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 1025 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 1026 1027 static int 1028 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 1029 { 1030 int i, j, efer; 1031 unsigned char r, hefere, hefras; 1032 1033 for (i = 0; i < 4; i ++) { 1034 /* first try to enable configuration registers */ 1035 efer = w83877f_efers[i]; 1036 1037 /* write the key to the EFER */ 1038 for (j = 0; j < w83877f_keyiter[i]; j ++) 1039 outb (efer, w83877f_keys[i]); 1040 1041 /* then check HEFERE and HEFRAS bits */ 1042 outb (efir, 0x0c); 1043 hefere = inb(efdr) & WINB_HEFERE; 1044 1045 outb (efir, 0x16); 1046 hefras = inb(efdr) & WINB_HEFRAS; 1047 1048 /* 1049 * HEFRAS HEFERE 1050 * 0 1 write 89h to 250h (power-on default) 1051 * 1 0 write 86h twice to 3f0h 1052 * 1 1 write 87h twice to 3f0h 1053 * 0 0 write 88h to 250h 1054 */ 1055 if ((hefere | hefras) == w83877f_hefs[i]) 1056 goto found; 1057 } 1058 1059 return (-1); /* failed */ 1060 1061 found: 1062 /* check base port address - read from CR23 */ 1063 outb(efir, 0x23); 1064 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 1065 return (-1); 1066 1067 /* read CHIP ID from CR9/bits0-3 */ 1068 outb(efir, 0x9); 1069 1070 switch (inb(efdr) & WINB_CHIPID) { 1071 case WINB_W83877F_ID: 1072 ppc->ppc_model = WINB_W83877F; 1073 break; 1074 1075 case WINB_W83877AF_ID: 1076 ppc->ppc_model = WINB_W83877AF; 1077 break; 1078 1079 default: 1080 ppc->ppc_model = WINB_UNKNOWN; 1081 } 1082 1083 if (bootverbose) { 1084 /* dump of registers */ 1085 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 1086 for (i = 0; i <= 0xd; i ++) { 1087 outb(efir, i); 1088 printf("0x%x ", inb(efdr)); 1089 } 1090 for (i = 0x10; i <= 0x17; i ++) { 1091 outb(efir, i); 1092 printf("0x%x ", inb(efdr)); 1093 } 1094 outb(efir, 0x1e); 1095 printf("0x%x ", inb(efdr)); 1096 for (i = 0x20; i <= 0x29; i ++) { 1097 outb(efir, i); 1098 printf("0x%x ", inb(efdr)); 1099 } 1100 printf("\n"); 1101 printf("ppc%d:", ppc->ppc_unit); 1102 } 1103 1104 ppc->ppc_type = PPC_TYPE_GENERIC; 1105 1106 if (!chipset_mode) { 1107 /* autodetect mode */ 1108 1109 /* select CR0 */ 1110 outb(efir, 0x0); 1111 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 1112 1113 /* select CR9 */ 1114 outb(efir, 0x9); 1115 r |= (inb(efdr) & WINB_PRTMODS2); 1116 1117 switch (r) { 1118 case WINB_W83757: 1119 if (bootverbose) 1120 printf("ppc%d: W83757 compatible mode\n", 1121 ppc->ppc_unit); 1122 return (-1); /* generic or SMC-like */ 1123 1124 case WINB_EXTFDC: 1125 case WINB_EXTADP: 1126 case WINB_EXT2FDD: 1127 case WINB_JOYSTICK: 1128 if (bootverbose) 1129 printf(" not in parallel port mode\n"); 1130 return (-1); 1131 1132 case (WINB_PARALLEL | WINB_EPP_SPP): 1133 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1134 if (bootverbose) 1135 printf(" EPP SPP"); 1136 break; 1137 1138 case (WINB_PARALLEL | WINB_ECP): 1139 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1140 if (bootverbose) 1141 printf(" ECP SPP"); 1142 break; 1143 1144 case (WINB_PARALLEL | WINB_ECP_EPP): 1145 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1146 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1147 1148 if (bootverbose) 1149 printf(" ECP+EPP SPP"); 1150 break; 1151 default: 1152 printf("%s: unknown case (0x%x)!\n", __func__, r); 1153 } 1154 1155 } else { 1156 /* mode forced */ 1157 1158 /* select CR9 and set PRTMODS2 bit */ 1159 outb(efir, 0x9); 1160 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1161 1162 /* select CR0 and reset PRTMODSx bits */ 1163 outb(efir, 0x0); 1164 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1165 1166 if (chipset_mode & PPB_ECP) { 1167 if (chipset_mode & PPB_EPP) { 1168 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1169 if (bootverbose) 1170 printf(" ECP+EPP"); 1171 1172 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1173 1174 } else { 1175 outb(efdr, inb(efdr) | WINB_ECP); 1176 if (bootverbose) 1177 printf(" ECP"); 1178 } 1179 } else { 1180 /* select EPP_SPP otherwise */ 1181 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1182 if (bootverbose) 1183 printf(" EPP SPP"); 1184 } 1185 ppc->ppc_avm = chipset_mode; 1186 } 1187 1188 if (bootverbose) 1189 printf("\n"); 1190 1191 /* exit configuration mode */ 1192 outb(efer, 0xaa); 1193 1194 switch (ppc->ppc_type) { 1195 case PPC_TYPE_SMCLIKE: 1196 ppc_smclike_setmode(ppc, chipset_mode); 1197 break; 1198 default: 1199 ppc_generic_setmode(ppc, chipset_mode); 1200 break; 1201 } 1202 1203 return (chipset_mode); 1204 } 1205 #endif 1206 1207 /* 1208 * ppc_generic_detect 1209 */ 1210 static int 1211 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1212 { 1213 /* default to generic */ 1214 ppc->ppc_type = PPC_TYPE_GENERIC; 1215 1216 if (bootverbose) 1217 printf("ppc%d:", ppc->ppc_unit); 1218 1219 /* first, check for ECP */ 1220 w_ecr(ppc, PPC_ECR_PS2); 1221 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1222 ppc->ppc_dtm |= PPB_ECP | PPB_SPP; 1223 if (bootverbose) 1224 printf(" ECP SPP"); 1225 1226 /* search for SMC style ECP+EPP mode */ 1227 w_ecr(ppc, PPC_ECR_EPP); 1228 } 1229 1230 /* try to reset EPP timeout bit */ 1231 if (ppc_check_epp_timeout(ppc)) { 1232 ppc->ppc_dtm |= PPB_EPP; 1233 1234 if (ppc->ppc_dtm & PPB_ECP) { 1235 /* SMC like chipset found */ 1236 ppc->ppc_model = SMC_LIKE; 1237 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1238 1239 if (bootverbose) 1240 printf(" ECP+EPP"); 1241 } else { 1242 if (bootverbose) 1243 printf(" EPP"); 1244 } 1245 } else { 1246 /* restore to standard mode */ 1247 w_ecr(ppc, PPC_ECR_STD); 1248 } 1249 1250 /* XXX try to detect NIBBLE and PS2 modes */ 1251 ppc->ppc_dtm |= PPB_NIBBLE; 1252 1253 if (bootverbose) 1254 printf(" SPP"); 1255 1256 if (chipset_mode) 1257 ppc->ppc_avm = chipset_mode; 1258 else 1259 ppc->ppc_avm = ppc->ppc_dtm; 1260 1261 if (bootverbose) 1262 printf("\n"); 1263 1264 switch (ppc->ppc_type) { 1265 case PPC_TYPE_SMCLIKE: 1266 ppc_smclike_setmode(ppc, chipset_mode); 1267 break; 1268 default: 1269 ppc_generic_setmode(ppc, chipset_mode); 1270 break; 1271 } 1272 1273 return (chipset_mode); 1274 } 1275 1276 /* 1277 * ppc_detect() 1278 * 1279 * mode is the mode suggested at boot 1280 */ 1281 static int 1282 ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1283 1284 #ifdef PPC_PROBE_CHIPSET 1285 int i, mode; 1286 1287 /* list of supported chipsets */ 1288 int (*chipset_detect[])(struct ppc_data *, int) = { 1289 ppc_pc873xx_detect, 1290 ppc_smc37c66xgt_detect, 1291 ppc_w83877f_detect, 1292 ppc_smc37c935_detect, 1293 ppc_generic_detect, 1294 NULL 1295 }; 1296 #endif 1297 1298 /* if can't find the port and mode not forced return error */ 1299 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1300 return (EIO); /* failed, port not present */ 1301 1302 /* assume centronics compatible mode is supported */ 1303 ppc->ppc_avm = PPB_COMPATIBLE; 1304 1305 #ifdef PPC_PROBE_CHIPSET 1306 /* we have to differenciate available chipset modes, 1307 * chipset running modes and IEEE-1284 operating modes 1308 * 1309 * after detection, the port must support running in compatible mode 1310 */ 1311 if (ppc->ppc_flags & 0x40) { 1312 if (bootverbose) 1313 printf("ppc: chipset forced to generic\n"); 1314 #endif 1315 1316 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1317 1318 #ifdef PPC_PROBE_CHIPSET 1319 } else { 1320 for (i=0; chipset_detect[i] != NULL; i++) { 1321 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1322 ppc->ppc_mode = mode; 1323 break; 1324 } 1325 } 1326 } 1327 #endif 1328 1329 /* configure/detect ECP FIFO */ 1330 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1331 ppc_detect_fifo(ppc); 1332 1333 return (0); 1334 } 1335 1336 /* 1337 * ppc_exec_microseq() 1338 * 1339 * Execute a microsequence. 1340 * Microsequence mechanism is supposed to handle fast I/O operations. 1341 */ 1342 static int 1343 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1344 { 1345 struct ppc_data *ppc = DEVTOSOFTC(dev); 1346 struct ppb_microseq *mi; 1347 char cc, *p; 1348 int i, iter, len; 1349 int error; 1350 1351 int reg; 1352 char mask; 1353 int accum = 0; 1354 char *ptr = 0; 1355 1356 struct ppb_microseq *stack = 0; 1357 1358 /* microsequence registers are equivalent to PC-like port registers */ 1359 1360 #define r_reg(register,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, register)) 1361 #define w_reg(register, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, register, byte)) 1362 1363 #define INCR_PC (mi ++) /* increment program counter */ 1364 1365 mi = *p_msq; 1366 for (;;) { 1367 switch (mi->opcode) { 1368 case MS_OP_RSET: 1369 cc = r_reg(mi->arg[0].i, ppc); 1370 cc &= (char)mi->arg[2].i; /* clear mask */ 1371 cc |= (char)mi->arg[1].i; /* assert mask */ 1372 w_reg(mi->arg[0].i, ppc, cc); 1373 INCR_PC; 1374 break; 1375 1376 case MS_OP_RASSERT_P: 1377 reg = mi->arg[1].i; 1378 ptr = ppc->ppc_ptr; 1379 1380 if ((len = mi->arg[0].i) == MS_ACCUM) { 1381 accum = ppc->ppc_accum; 1382 for (; accum; accum--) 1383 w_reg(reg, ppc, *ptr++); 1384 ppc->ppc_accum = accum; 1385 } else 1386 for (i=0; i<len; i++) 1387 w_reg(reg, ppc, *ptr++); 1388 ppc->ppc_ptr = ptr; 1389 1390 INCR_PC; 1391 break; 1392 1393 case MS_OP_RFETCH_P: 1394 reg = mi->arg[1].i; 1395 mask = (char)mi->arg[2].i; 1396 ptr = ppc->ppc_ptr; 1397 1398 if ((len = mi->arg[0].i) == MS_ACCUM) { 1399 accum = ppc->ppc_accum; 1400 for (; accum; accum--) 1401 *ptr++ = r_reg(reg, ppc) & mask; 1402 ppc->ppc_accum = accum; 1403 } else 1404 for (i=0; i<len; i++) 1405 *ptr++ = r_reg(reg, ppc) & mask; 1406 ppc->ppc_ptr = ptr; 1407 1408 INCR_PC; 1409 break; 1410 1411 case MS_OP_RFETCH: 1412 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1413 (char)mi->arg[1].i; 1414 INCR_PC; 1415 break; 1416 1417 case MS_OP_RASSERT: 1418 case MS_OP_DELAY: 1419 1420 /* let's suppose the next instr. is the same */ 1421 prefetch: 1422 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1423 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1424 1425 if (mi->opcode == MS_OP_DELAY) { 1426 DELAY(mi->arg[0].i); 1427 INCR_PC; 1428 goto prefetch; 1429 } 1430 break; 1431 1432 case MS_OP_ADELAY: 1433 if (mi->arg[0].i) 1434 tsleep(NULL, 0, "ppbdelay", 1435 mi->arg[0].i * (hz/1000)); 1436 INCR_PC; 1437 break; 1438 1439 case MS_OP_TRIG: 1440 reg = mi->arg[0].i; 1441 iter = mi->arg[1].i; 1442 p = (char *)mi->arg[2].p; 1443 1444 /* XXX delay limited to 255 us */ 1445 for (i=0; i<iter; i++) { 1446 w_reg(reg, ppc, *p++); 1447 DELAY((unsigned char)*p++); 1448 } 1449 INCR_PC; 1450 break; 1451 1452 case MS_OP_SET: 1453 ppc->ppc_accum = mi->arg[0].i; 1454 INCR_PC; 1455 break; 1456 1457 case MS_OP_DBRA: 1458 if (--ppc->ppc_accum > 0) 1459 mi += mi->arg[0].i; 1460 INCR_PC; 1461 break; 1462 1463 case MS_OP_BRSET: 1464 cc = r_str(ppc); 1465 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1466 mi += mi->arg[1].i; 1467 INCR_PC; 1468 break; 1469 1470 case MS_OP_BRCLEAR: 1471 cc = r_str(ppc); 1472 if ((cc & (char)mi->arg[0].i) == 0) 1473 mi += mi->arg[1].i; 1474 INCR_PC; 1475 break; 1476 1477 case MS_OP_BRSTAT: 1478 cc = r_str(ppc); 1479 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1480 (char)mi->arg[0].i) 1481 mi += mi->arg[2].i; 1482 INCR_PC; 1483 break; 1484 1485 case MS_OP_C_CALL: 1486 /* 1487 * If the C call returns !0 then end the microseq. 1488 * The current state of ptr is passed to the C function 1489 */ 1490 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1491 return (error); 1492 1493 INCR_PC; 1494 break; 1495 1496 case MS_OP_PTR: 1497 ppc->ppc_ptr = (char *)mi->arg[0].p; 1498 INCR_PC; 1499 break; 1500 1501 case MS_OP_CALL: 1502 if (stack) 1503 panic("%s: too much calls", __func__); 1504 1505 if (mi->arg[0].p) { 1506 /* store the state of the actual 1507 * microsequence 1508 */ 1509 stack = mi; 1510 1511 /* jump to the new microsequence */ 1512 mi = (struct ppb_microseq *)mi->arg[0].p; 1513 } else 1514 INCR_PC; 1515 1516 break; 1517 1518 case MS_OP_SUBRET: 1519 /* retrieve microseq and pc state before the call */ 1520 mi = stack; 1521 1522 /* reset the stack */ 1523 stack = 0; 1524 1525 /* XXX return code */ 1526 1527 INCR_PC; 1528 break; 1529 1530 case MS_OP_PUT: 1531 case MS_OP_GET: 1532 case MS_OP_RET: 1533 /* can't return to ppb level during the execution 1534 * of a submicrosequence */ 1535 if (stack) 1536 panic("%s: can't return to ppb level", 1537 __func__); 1538 1539 /* update pc for ppb level of execution */ 1540 *p_msq = mi; 1541 1542 /* return to ppb level of execution */ 1543 return (0); 1544 1545 default: 1546 panic("%s: unknown microsequence opcode 0x%x", 1547 __func__, mi->opcode); 1548 } 1549 } 1550 1551 /* unreached */ 1552 } 1553 1554 static void 1555 ppcintr(void *arg) 1556 { 1557 device_t dev = (device_t)arg; 1558 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev); 1559 u_char ctr, ecr, str; 1560 1561 str = r_str(ppc); 1562 ctr = r_ctr(ppc); 1563 ecr = r_ecr(ppc); 1564 1565 #if PPC_DEBUG > 1 1566 printf("![%x/%x/%x]", ctr, ecr, str); 1567 #endif 1568 1569 /* don't use ecp mode with IRQENABLE set */ 1570 if (ctr & IRQENABLE) { 1571 return; 1572 } 1573 1574 /* interrupts are generated by nFault signal 1575 * only in ECP mode */ 1576 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1577 /* check if ppc driver has programmed the 1578 * nFault interrupt */ 1579 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1580 1581 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1582 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1583 } else { 1584 /* shall be handled by underlying layers XXX */ 1585 return; 1586 } 1587 } 1588 1589 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1590 /* disable interrupts (should be done by hardware though) */ 1591 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1592 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1593 ecr = r_ecr(ppc); 1594 1595 /* check if DMA completed */ 1596 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1597 #ifdef PPC_DEBUG 1598 printf("a"); 1599 #endif 1600 /* stop DMA */ 1601 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1602 ecr = r_ecr(ppc); 1603 1604 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1605 #ifdef PPC_DEBUG 1606 printf("d"); 1607 #endif 1608 isa_dmadone( 1609 ppc->ppc_dmaflags, 1610 ppc->ppc_dmaddr, 1611 ppc->ppc_dmacnt, 1612 ppc->ppc_dmachan); 1613 1614 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1615 1616 /* wakeup the waiting process */ 1617 wakeup((caddr_t)ppc); 1618 } 1619 } 1620 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1621 1622 /* classic interrupt I/O */ 1623 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1624 } 1625 1626 return; 1627 } 1628 1629 static int 1630 ppc_read(device_t dev, char *buf, int len, int mode) 1631 { 1632 return (EINVAL); 1633 } 1634 1635 /* 1636 * Call this function if you want to send data in any advanced mode 1637 * of your parallel port: FIFO, DMA 1638 * 1639 * If what you want is not possible (no ECP, no DMA...), 1640 * EINVAL is returned 1641 */ 1642 static int 1643 ppc_write(device_t dev, char *buf, int len, int how) 1644 { 1645 struct ppc_data *ppc = DEVTOSOFTC(dev); 1646 char ecr, ecr_sav, ctr, ctr_sav; 1647 int error = 0; 1648 int spin; 1649 1650 #ifdef PPC_DEBUG 1651 printf("w"); 1652 #endif 1653 1654 ecr_sav = r_ecr(ppc); 1655 ctr_sav = r_ctr(ppc); 1656 1657 /* 1658 * Send buffer with DMA, FIFO and interrupts 1659 */ 1660 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) { 1661 1662 if (ppc->ppc_dmachan > 0) { 1663 1664 /* byte mode, no intr, no DMA, dir=0, flush fifo 1665 */ 1666 ecr = PPC_ECR_STD | PPC_DISABLE_INTR; 1667 w_ecr(ppc, ecr); 1668 1669 /* disable nAck interrupts */ 1670 ctr = r_ctr(ppc); 1671 ctr &= ~IRQENABLE; 1672 w_ctr(ppc, ctr); 1673 1674 ppc->ppc_dmaflags = 0; 1675 ppc->ppc_dmaddr = (caddr_t)buf; 1676 ppc->ppc_dmacnt = (u_int)len; 1677 1678 switch (ppc->ppc_mode) { 1679 case PPB_COMPATIBLE: 1680 /* compatible mode with FIFO, no intr, DMA, dir=0 */ 1681 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1682 break; 1683 case PPB_ECP: 1684 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1685 break; 1686 default: 1687 error = EINVAL; 1688 goto error; 1689 } 1690 1691 w_ecr(ppc, ecr); 1692 ecr = r_ecr(ppc); 1693 1694 /* enter splhigh() not to be preempted 1695 * by the dma interrupt, we may miss 1696 * the wakeup otherwise 1697 */ 1698 crit_enter(); 1699 1700 ppc->ppc_dmastat = PPC_DMA_INIT; 1701 1702 /* enable interrupts */ 1703 ecr &= ~PPC_SERVICE_INTR; 1704 ppc->ppc_irqstat = PPC_IRQ_DMA; 1705 w_ecr(ppc, ecr); 1706 1707 isa_dmastart( 1708 ppc->ppc_dmaflags, 1709 ppc->ppc_dmaddr, 1710 ppc->ppc_dmacnt, 1711 ppc->ppc_dmachan); 1712 #ifdef PPC_DEBUG 1713 printf("s%d", ppc->ppc_dmacnt); 1714 #endif 1715 ppc->ppc_dmastat = PPC_DMA_STARTED; 1716 1717 /* Wait for the DMA completed interrupt. We hope we won't 1718 * miss it, otherwise a signal will be necessary to unlock the 1719 * process. 1720 */ 1721 do { 1722 /* release CPU */ 1723 error = tsleep((caddr_t)ppc, PCATCH, "ppcdma", 0); 1724 1725 } while (error == EWOULDBLOCK); 1726 1727 crit_exit(); 1728 1729 if (error) { 1730 #ifdef PPC_DEBUG 1731 printf("i"); 1732 #endif 1733 /* stop DMA */ 1734 isa_dmadone( 1735 ppc->ppc_dmaflags, ppc->ppc_dmaddr, 1736 ppc->ppc_dmacnt, ppc->ppc_dmachan); 1737 1738 /* no dma, no interrupt, flush the fifo */ 1739 w_ecr(ppc, PPC_ECR_RESET); 1740 1741 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1742 goto error; 1743 } 1744 1745 /* wait for an empty fifo */ 1746 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 1747 1748 for (spin=100; spin; spin--) 1749 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 1750 goto fifo_empty; 1751 #ifdef PPC_DEBUG 1752 printf("Z"); 1753 #endif 1754 error = tsleep((caddr_t)ppc, PCATCH, "ppcfifo", hz/100); 1755 if (error != EWOULDBLOCK) { 1756 #ifdef PPC_DEBUG 1757 printf("I"); 1758 #endif 1759 /* no dma, no interrupt, flush the fifo */ 1760 w_ecr(ppc, PPC_ECR_RESET); 1761 1762 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1763 error = EINTR; 1764 goto error; 1765 } 1766 } 1767 1768 fifo_empty: 1769 /* no dma, no interrupt, flush the fifo */ 1770 w_ecr(ppc, PPC_ECR_RESET); 1771 1772 } else 1773 error = EINVAL; /* XXX we should FIFO and 1774 * interrupts */ 1775 } else 1776 error = EINVAL; 1777 1778 error: 1779 1780 /* PDRQ must be kept unasserted until nPDACK is 1781 * deasserted for a minimum of 350ns (SMC datasheet) 1782 * 1783 * Consequence may be a FIFO that never empty 1784 */ 1785 DELAY(1); 1786 1787 w_ecr(ppc, ecr_sav); 1788 w_ctr(ppc, ctr_sav); 1789 1790 return (error); 1791 } 1792 1793 static void 1794 ppc_reset_epp(device_t dev) 1795 { 1796 struct ppc_data *ppc = DEVTOSOFTC(dev); 1797 1798 ppc_reset_epp_timeout(ppc); 1799 1800 return; 1801 } 1802 1803 static int 1804 ppc_setmode(device_t dev, int mode) 1805 { 1806 struct ppc_data *ppc = DEVTOSOFTC(dev); 1807 1808 switch (ppc->ppc_type) { 1809 case PPC_TYPE_SMCLIKE: 1810 return (ppc_smclike_setmode(ppc, mode)); 1811 break; 1812 1813 case PPC_TYPE_GENERIC: 1814 default: 1815 return (ppc_generic_setmode(ppc, mode)); 1816 break; 1817 } 1818 1819 /* not reached */ 1820 return (ENXIO); 1821 } 1822 1823 static struct isa_pnp_id lpc_ids[] = { 1824 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */ 1825 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */ 1826 { 0 } 1827 }; 1828 1829 static int 1830 ppc_probe(device_t dev) 1831 { 1832 #ifdef __i386__ 1833 static short next_bios_ppc = 0; 1834 #endif 1835 struct ppc_data *ppc; 1836 device_t parent; 1837 int error; 1838 u_long port; 1839 1840 parent = device_get_parent(dev); 1841 1842 error = ISA_PNP_PROBE(parent, dev, lpc_ids); 1843 if (error == ENXIO) 1844 return (ENXIO); 1845 else if (error != 0) /* XXX shall be set after detection */ 1846 device_set_desc(dev, "Parallel port"); 1847 1848 /* 1849 * Allocate the ppc_data structure. 1850 */ 1851 ppc = DEVTOSOFTC(dev); 1852 bzero(ppc, sizeof(struct ppc_data)); 1853 1854 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0; 1855 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0; 1856 1857 /* retrieve ISA parameters */ 1858 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL); 1859 1860 #ifdef __i386__ 1861 /* 1862 * If port not specified, use bios list. 1863 */ 1864 if (error) { 1865 if((next_bios_ppc < BIOS_MAX_PPC) && 1866 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1867 port = *(BIOS_PORTS+next_bios_ppc++); 1868 if (bootverbose) 1869 device_printf(dev, "parallel port found at 0x%x\n", 1870 (int) port); 1871 } else { 1872 device_printf(dev, "parallel port not found.\n"); 1873 return ENXIO; 1874 } 1875 bus_set_resource(dev, SYS_RES_IOPORT, 0, port, 1876 IO_LPTSIZE_EXTENDED); 1877 } 1878 #endif 1879 1880 /* IO port is mandatory */ 1881 1882 /* Try "extended" IO port range...*/ 1883 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1884 &ppc->rid_ioport, 0, ~0, 1885 IO_LPTSIZE_EXTENDED, RF_ACTIVE); 1886 1887 if (ppc->res_ioport != 0) { 1888 if (bootverbose) 1889 device_printf(dev, "using extended I/O port range\n"); 1890 } else { 1891 /* Failed? If so, then try the "normal" IO port range... */ 1892 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1893 &ppc->rid_ioport, 0, ~0, 1894 IO_LPTSIZE_NORMAL, 1895 RF_ACTIVE); 1896 if (ppc->res_ioport != 0) { 1897 if (bootverbose) 1898 device_printf(dev, "using normal I/O port range\n"); 1899 } else { 1900 device_printf(dev, "cannot reserve I/O port range\n"); 1901 goto error; 1902 } 1903 } 1904 1905 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1906 1907 ppc->bsh = rman_get_bushandle(ppc->res_ioport); 1908 ppc->bst = rman_get_bustag(ppc->res_ioport); 1909 1910 ppc->ppc_flags = device_get_flags(dev); 1911 1912 if (!(ppc->ppc_flags & 0x20)) { 1913 ppc->res_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &ppc->rid_irq, 1914 0ul, ~0ul, 1, RF_SHAREABLE); 1915 ppc->res_drq = bus_alloc_resource(dev, SYS_RES_DRQ, &ppc->rid_drq, 1916 0ul, ~0ul, 1, RF_ACTIVE); 1917 } 1918 1919 if (ppc->res_irq) 1920 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1921 if (ppc->res_drq) 1922 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1923 1924 ppc->ppc_unit = device_get_unit(dev); 1925 ppc->ppc_model = GENERIC; 1926 1927 ppc->ppc_mode = PPB_COMPATIBLE; 1928 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1929 1930 ppc->ppc_type = PPC_TYPE_GENERIC; 1931 1932 /* 1933 * Try to detect the chipset and its mode. 1934 */ 1935 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1936 goto error; 1937 1938 return (0); 1939 1940 error: 1941 if (ppc->res_irq != 0) { 1942 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1943 ppc->res_irq); 1944 } 1945 if (ppc->res_ioport != 0) { 1946 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1947 ppc->res_ioport); 1948 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1949 ppc->res_ioport); 1950 } 1951 if (ppc->res_drq != 0) { 1952 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1953 ppc->res_drq); 1954 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1955 ppc->res_drq); 1956 } 1957 return (ENXIO); 1958 } 1959 1960 static int 1961 ppc_attach(device_t dev) 1962 { 1963 struct ppc_data *ppc = DEVTOSOFTC(dev); 1964 1965 device_t ppbus; 1966 device_t parent = device_get_parent(dev); 1967 1968 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1969 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1970 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1971 ppc_epp_protocol[ppc->ppc_epp] : ""); 1972 1973 if (ppc->ppc_fifo) 1974 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1975 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1976 1977 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { 1978 /* acquire the DMA channel forever */ /* XXX */ 1979 isa_dma_acquire(ppc->ppc_dmachan); 1980 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ 1981 } 1982 1983 /* add ppbus as a child of this isa to parallel bridge */ 1984 ppbus = device_add_child(dev, "ppbus", -1); 1985 1986 /* 1987 * Probe the ppbus and attach devices found. 1988 */ 1989 device_probe_and_attach(ppbus); 1990 1991 /* register the ppc interrupt handler as default */ 1992 if (ppc->res_irq) { 1993 /* default to the tty mask for registration */ /* XXX */ 1994 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY, 1995 ppcintr, dev, 1996 &ppc->intr_cookie, NULL) == 0) { 1997 /* remember the ppcintr is registered */ 1998 ppc->ppc_registered = 1; 1999 } 2000 } 2001 2002 return (0); 2003 } 2004 2005 static u_char 2006 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 2007 { 2008 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 2009 switch (iop) { 2010 case PPB_OUTSB_EPP: 2011 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt); 2012 break; 2013 case PPB_OUTSW_EPP: 2014 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 2015 break; 2016 case PPB_OUTSL_EPP: 2017 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 2018 break; 2019 case PPB_INSB_EPP: 2020 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt); 2021 break; 2022 case PPB_INSW_EPP: 2023 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 2024 break; 2025 case PPB_INSL_EPP: 2026 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 2027 break; 2028 case PPB_RDTR: 2029 return (r_dtr(ppc)); 2030 break; 2031 case PPB_RSTR: 2032 return (r_str(ppc)); 2033 break; 2034 case PPB_RCTR: 2035 return (r_ctr(ppc)); 2036 break; 2037 case PPB_REPP_A: 2038 return (r_epp_A(ppc)); 2039 break; 2040 case PPB_REPP_D: 2041 return (r_epp_D(ppc)); 2042 break; 2043 case PPB_RECR: 2044 return (r_ecr(ppc)); 2045 break; 2046 case PPB_RFIFO: 2047 return (r_fifo(ppc)); 2048 break; 2049 case PPB_WDTR: 2050 w_dtr(ppc, byte); 2051 break; 2052 case PPB_WSTR: 2053 w_str(ppc, byte); 2054 break; 2055 case PPB_WCTR: 2056 w_ctr(ppc, byte); 2057 break; 2058 case PPB_WEPP_A: 2059 w_epp_A(ppc, byte); 2060 break; 2061 case PPB_WEPP_D: 2062 w_epp_D(ppc, byte); 2063 break; 2064 case PPB_WECR: 2065 w_ecr(ppc, byte); 2066 break; 2067 case PPB_WFIFO: 2068 w_fifo(ppc, byte); 2069 break; 2070 default: 2071 panic("%s: unknown I/O operation", __func__); 2072 break; 2073 } 2074 2075 return (0); /* not significative */ 2076 } 2077 2078 static int 2079 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 2080 { 2081 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 2082 2083 switch (index) { 2084 case PPC_IVAR_EPP_PROTO: 2085 *val = (u_long)ppc->ppc_epp; 2086 break; 2087 case PPC_IVAR_IRQ: 2088 *val = (u_long)ppc->ppc_irq; 2089 break; 2090 default: 2091 return (ENOENT); 2092 } 2093 2094 return (0); 2095 } 2096 2097 /* 2098 * Resource is useless here since ppbus devices' interrupt handlers are 2099 * multiplexed to the same resource initially allocated by ppc 2100 */ 2101 static int 2102 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags, 2103 void (*ihand)(void *), void *arg, 2104 void **cookiep, lwkt_serialize_t serializer) 2105 { 2106 int error; 2107 struct ppc_data *ppc = DEVTOSOFTC(bus); 2108 2109 if (ppc->ppc_registered) { 2110 /* XXX refuse registration if DMA is in progress */ 2111 2112 /* first, unregister the default interrupt handler */ 2113 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus), 2114 bus, ppc->res_irq, ppc->intr_cookie))) 2115 return (error); 2116 2117 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */ 2118 /* ppc->res_irq); */ 2119 2120 /* DMA/FIFO operation won't be possible anymore */ 2121 ppc->ppc_registered = 0; 2122 } 2123 2124 /* pass registration to the upper layer, ignore the incoming resource */ 2125 return (BUS_SETUP_INTR(device_get_parent(bus), child, 2126 r, flags, ihand, arg, cookiep, serializer)); 2127 } 2128 2129 /* 2130 * When no underlying device has a registered interrupt, register the ppc 2131 * layer one 2132 */ 2133 static int 2134 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih) 2135 { 2136 int error; 2137 struct ppc_data *ppc = DEVTOSOFTC(bus); 2138 device_t parent = device_get_parent(bus); 2139 2140 /* pass unregistration to the upper layer */ 2141 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih))) 2142 return (error); 2143 2144 /* default to the tty mask for registration */ /* XXX */ 2145 if (ppc->ppc_irq && 2146 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq, 2147 INTR_TYPE_TTY, ppcintr, bus, 2148 &ppc->intr_cookie, NULL)) 2149 ) { 2150 /* remember the ppcintr is registered */ 2151 ppc->ppc_registered = 1; 2152 } 2153 2154 return (error); 2155 } 2156 2157 DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0); 2158