1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/alc/if_alcvar.h,v 1.1 2009/06/10 02:07:58 yongari Exp $ 28 * $DragonFly$ 29 */ 30 31 #ifndef _IF_ALCVAR_H 32 #define _IF_ALCVAR_H 33 34 #define ALC_TX_RING_CNT 256 35 #define ALC_TX_RING_ALIGN sizeof(struct tx_desc) 36 #define ALC_RX_RING_CNT 256 37 #define ALC_RX_RING_ALIGN sizeof(struct rx_desc) 38 #define ALC_RX_BUF_ALIGN 4 39 #define ALC_RR_RING_CNT ALC_RX_RING_CNT 40 #define ALC_RR_RING_ALIGN sizeof(struct rx_rdesc) 41 #define ALC_CMB_ALIGN 8 42 #define ALC_SMB_ALIGN 8 43 44 #define ALC_TSO_MAXSEGSIZE 4096 45 #define ALC_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 46 #define ALC_MAXTXSEGS 32 47 48 #define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 49 #define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32) 50 51 #define ALC_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 52 53 /* Water mark to kick reclaiming Tx buffers. */ 54 #define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10) 55 56 #define ALC_MSI_MESSAGES 1 57 #define ALC_MSIX_MESSAGES 1 58 59 #define ALC_TX_RING_SZ \ 60 (sizeof(struct tx_desc) * ALC_TX_RING_CNT) 61 #define ALC_RX_RING_SZ \ 62 (sizeof(struct rx_desc) * ALC_RX_RING_CNT) 63 #define ALC_RR_RING_SZ \ 64 (sizeof(struct rx_rdesc) * ALC_RR_RING_CNT) 65 #define ALC_CMB_SZ (sizeof(struct cmb)) 66 #define ALC_SMB_SZ (sizeof(struct smb)) 67 68 #define ALC_PROC_MIN 16 69 #define ALC_PROC_MAX (ALC_RX_RING_CNT - 1) 70 #define ALC_PROC_DEFAULT (ALC_RX_RING_CNT / 4) 71 72 /* 73 * The number of bits reserved for MSS in AR813x/AR815x controllers 74 * are 13 bits. This limits the maximum interface MTU size in TSO 75 * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper 76 * stack should not generate TCP segments with MSS greater than the 77 * limit. Also Atheros says that maximum MTU for TSO is 6KB. 78 */ 79 #define ALC_TSO_MTU (6 * 1024) 80 81 82 #ifndef IFCAP_TSO4 83 #define IFCAP_TSO4 0 84 #endif 85 86 #ifndef CSUM_TSO 87 #define CSUM_TSO 0 88 #endif 89 90 91 struct alc_rxdesc { 92 struct mbuf *rx_m; 93 bus_dmamap_t rx_dmamap; 94 struct rx_desc *rx_desc; 95 }; 96 97 struct alc_txdesc { 98 struct mbuf *tx_m; 99 bus_dmamap_t tx_dmamap; 100 }; 101 102 struct alc_ring_data { 103 struct tx_desc *alc_tx_ring; 104 bus_addr_t alc_tx_ring_paddr; 105 struct rx_desc *alc_rx_ring; 106 bus_addr_t alc_rx_ring_paddr; 107 struct rx_rdesc *alc_rr_ring; 108 bus_addr_t alc_rr_ring_paddr; 109 struct cmb *alc_cmb; 110 bus_addr_t alc_cmb_paddr; 111 struct smb *alc_smb; 112 bus_addr_t alc_smb_paddr; 113 }; 114 115 struct alc_chain_data { 116 bus_dma_tag_t alc_parent_tag; 117 bus_dma_tag_t alc_buffer_tag; 118 bus_dma_tag_t alc_tx_tag; 119 struct alc_txdesc alc_txdesc[ALC_TX_RING_CNT]; 120 bus_dma_tag_t alc_rx_tag; 121 struct alc_rxdesc alc_rxdesc[ALC_RX_RING_CNT]; 122 bus_dma_tag_t alc_tx_ring_tag; 123 bus_dmamap_t alc_tx_ring_map; 124 bus_dma_tag_t alc_rx_ring_tag; 125 bus_dmamap_t alc_rx_ring_map; 126 bus_dma_tag_t alc_rr_ring_tag; 127 bus_dmamap_t alc_rr_ring_map; 128 bus_dmamap_t alc_rx_sparemap; 129 bus_dma_tag_t alc_cmb_tag; 130 bus_dmamap_t alc_cmb_map; 131 bus_dma_tag_t alc_smb_tag; 132 bus_dmamap_t alc_smb_map; 133 134 int alc_tx_prod; 135 int alc_tx_cons; 136 int alc_tx_cnt; 137 int alc_rx_cons; 138 int alc_rr_cons; 139 int alc_rxlen; 140 141 struct mbuf *alc_rxhead; 142 struct mbuf *alc_rxtail; 143 struct mbuf *alc_rxprev_tail; 144 }; 145 146 struct alc_hw_stats { 147 /* Rx stats. */ 148 uint32_t rx_frames; 149 uint32_t rx_bcast_frames; 150 uint32_t rx_mcast_frames; 151 uint32_t rx_pause_frames; 152 uint32_t rx_control_frames; 153 uint32_t rx_crcerrs; 154 uint32_t rx_lenerrs; 155 uint64_t rx_bytes; 156 uint32_t rx_runts; 157 uint32_t rx_fragments; 158 uint32_t rx_pkts_64; 159 uint32_t rx_pkts_65_127; 160 uint32_t rx_pkts_128_255; 161 uint32_t rx_pkts_256_511; 162 uint32_t rx_pkts_512_1023; 163 uint32_t rx_pkts_1024_1518; 164 uint32_t rx_pkts_1519_max; 165 uint32_t rx_pkts_truncated; 166 uint32_t rx_fifo_oflows; 167 uint32_t rx_rrs_errs; 168 uint32_t rx_alignerrs; 169 uint64_t rx_bcast_bytes; 170 uint64_t rx_mcast_bytes; 171 uint32_t rx_pkts_filtered; 172 /* Tx stats. */ 173 uint32_t tx_frames; 174 uint32_t tx_bcast_frames; 175 uint32_t tx_mcast_frames; 176 uint32_t tx_pause_frames; 177 uint32_t tx_excess_defer; 178 uint32_t tx_control_frames; 179 uint32_t tx_deferred; 180 uint64_t tx_bytes; 181 uint32_t tx_pkts_64; 182 uint32_t tx_pkts_65_127; 183 uint32_t tx_pkts_128_255; 184 uint32_t tx_pkts_256_511; 185 uint32_t tx_pkts_512_1023; 186 uint32_t tx_pkts_1024_1518; 187 uint32_t tx_pkts_1519_max; 188 uint32_t tx_single_colls; 189 uint32_t tx_multi_colls; 190 uint32_t tx_late_colls; 191 uint32_t tx_excess_colls; 192 uint32_t tx_abort; 193 uint32_t tx_underrun; 194 uint32_t tx_desc_underrun; 195 uint32_t tx_lenerrs; 196 uint32_t tx_pkts_truncated; 197 uint64_t tx_bcast_bytes; 198 uint64_t tx_mcast_bytes; 199 }; 200 201 struct alc_ident { 202 uint16_t vendorid; 203 uint16_t deviceid; 204 uint32_t max_framelen; 205 const char *name; 206 }; 207 208 /* 209 * Software state per device. 210 */ 211 struct alc_softc { 212 struct arpcom arpcom; 213 struct ifnet *alc_ifp; /* points to arpcom.ac_if */ 214 device_t alc_dev; 215 device_t alc_miibus; 216 struct resource *alc_res[1]; 217 struct resource_spec *alc_res_spec; 218 struct resource *alc_irq[ALC_MSI_MESSAGES]; 219 struct resource_spec *alc_irq_spec; 220 void *alc_intrhand[ALC_MSI_MESSAGES]; 221 struct alc_ident *alc_ident; 222 int alc_rev; 223 int alc_chip_rev; 224 int alc_phyaddr; 225 uint8_t alc_eaddr[ETHER_ADDR_LEN]; 226 uint32_t alc_dma_rd_burst; 227 uint32_t alc_dma_wr_burst; 228 uint32_t alc_rcb; 229 int alc_expcap; 230 int alc_pmcap; 231 int alc_flags; 232 #define ALC_FLAG_PCIE 0x0001 233 #define ALC_FLAG_PCIX 0x0002 234 #define ALC_FLAG_MSI 0x0004 235 #define ALC_FLAG_MSIX 0x0008 236 #define ALC_FLAG_PM 0x0010 237 #define ALC_FLAG_FASTETHER 0x0020 238 #define ALC_FLAG_JUMBO 0x0040 239 #define ALC_FLAG_ASPM_MON 0x0080 240 #define ALC_FLAG_CMB_BUG 0x0100 241 #define ALC_FLAG_SMB_BUG 0x0200 242 #define ALC_FLAG_L0S 0x0400 243 #define ALC_FLAG_L1S 0x0800 244 #define ALC_FLAG_APS 0x1000 245 #define ALC_FLAG_DETACH 0x4000 246 #define ALC_FLAG_LINK 0x8000 247 248 struct callout alc_tick_ch; 249 struct alc_hw_stats alc_stats; 250 struct alc_chain_data alc_cdata; 251 struct alc_ring_data alc_rdata; 252 int alc_if_flags; 253 int alc_watchdog_timer; 254 int alc_process_limit; 255 volatile int alc_morework; 256 int alc_int_rx_mod; 257 int alc_int_tx_mod; 258 int alc_buf_size; 259 260 struct sysctl_ctx_list alc_sysctl_ctx; 261 262 struct task alc_int_task; 263 struct task alc_tx_task; 264 struct taskqueue *alc_tq; 265 struct lock alc_lock; 266 }; 267 268 /* Register access macros. */ 269 #define CSR_WRITE_4(_sc, reg, val) \ 270 bus_write_4((_sc)->alc_res[0], (reg), (val)) 271 #define CSR_WRITE_2(_sc, reg, val) \ 272 bus_write_2((_sc)->alc_res[0], (reg), (val)) 273 #define CSR_WRITE_1(_sc, reg, val) \ 274 bus_write_1((_sc)->alc_res[0], (reg), (val)) 275 #define CSR_READ_2(_sc, reg) \ 276 bus_read_2((_sc)->alc_res[0], (reg)) 277 #define CSR_READ_4(_sc, reg) \ 278 bus_read_4((_sc)->alc_res[0], (reg)) 279 280 #define ALC_RXCHAIN_RESET(_sc) \ 281 do { \ 282 (_sc)->alc_cdata.alc_rxhead = NULL; \ 283 (_sc)->alc_cdata.alc_rxtail = NULL; \ 284 (_sc)->alc_cdata.alc_rxprev_tail = NULL; \ 285 (_sc)->alc_cdata.alc_rxlen = 0; \ 286 } while (0) 287 288 #define ALC_LOCK(_sc) lockmgr(&(_sc)->alc_lock, LK_EXCLUSIVE) 289 #define ALC_UNLOCK(_sc) lockmgr(&(_sc)->alc_lock, LK_RELEASE) 290 #define ALC_LOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->alc_lock, curthread) != 0) 291 292 #define ALC_TX_TIMEOUT 5 293 #define ALC_RESET_TIMEOUT 100 294 #define ALC_TIMEOUT 1000 295 #define ALC_PHY_TIMEOUT 1000 296 297 #endif /* _IF_ALCVAR_H */ 298