1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35 #ifndef _DEV_ATH_ATHVAR_H 36 #define _DEV_ATH_ATHVAR_H 37 38 #include <machine/atomic.h> 39 40 #include <dev/netif/ath/ath_hal/ah.h> 41 #include <dev/netif/ath/ath_hal/ah_desc.h> 42 #include <netproto/802_11/ieee80211_radiotap.h> 43 #include <dev/netif/ath/ath/if_athioctl.h> 44 #include <dev/netif/ath/ath/if_athrate.h> 45 #ifdef ATH_DEBUG_ALQ 46 #include <dev/netif/ath/ath/if_ath_alq.h> 47 #endif 48 49 #define ATH_TIMEOUT 1000 50 51 #if defined(__DragonFly__) 52 #define ATH_ENABLE_11N 53 #endif 54 55 /* 56 * There is a separate TX ath_buf pool for management frames. 57 * This ensures that management frames such as probe responses 58 * and BAR frames can be transmitted during periods of high 59 * TX activity. 60 */ 61 #define ATH_MGMT_TXBUF 32 62 63 /* 64 * 802.11n requires more TX and RX buffers to do AMPDU. 65 */ 66 #ifdef ATH_ENABLE_11N 67 #define ATH_TXBUF 512 68 #define ATH_RXBUF 512 69 #endif 70 71 #ifndef ATH_RXBUF 72 #define ATH_RXBUF 40 /* number of RX buffers */ 73 #endif 74 #ifndef ATH_TXBUF 75 #define ATH_TXBUF 200 /* number of TX buffers */ 76 #endif 77 #define ATH_BCBUF 4 /* number of beacon buffers */ 78 79 #define ATH_TXDESC 10 /* number of descriptors per buffer */ 80 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 81 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 82 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 83 84 #define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 85 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 86 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 87 88 /* 89 * The following bits can be set during the PCI (and perhaps non-PCI 90 * later) device probe path. 91 * 92 * It controls some of the driver and HAL behaviour. 93 */ 94 95 #define ATH_PCI_CUS198 0x0001 96 #define ATH_PCI_CUS230 0x0002 97 #define ATH_PCI_CUS217 0x0004 98 #define ATH_PCI_CUS252 0x0008 99 #define ATH_PCI_WOW 0x0010 100 #define ATH_PCI_BT_ANT_DIV 0x0020 101 #define ATH_PCI_D3_L1_WAR 0x0040 102 #define ATH_PCI_AR9565_1ANT 0x0080 103 #define ATH_PCI_AR9565_2ANT 0x0100 104 #define ATH_PCI_NO_PLL_PWRSAVE 0x0200 105 #define ATH_PCI_KILLER 0x0400 106 107 /* 108 * The key cache is used for h/w cipher state and also for 109 * tracking station state such as the current tx antenna. 110 * We also setup a mapping table between key cache slot indices 111 * and station state to short-circuit node lookups on rx. 112 * Different parts have different size key caches. We handle 113 * up to ATH_KEYMAX entries (could dynamically allocate state). 114 */ 115 #define ATH_KEYMAX 128 /* max key cache size we handle */ 116 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 117 118 struct taskqueue; 119 struct kthread; 120 struct ath_buf; 121 122 #define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 123 124 /* 125 * Per-TID state 126 * 127 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 128 */ 129 struct ath_tid { 130 TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */ 131 struct ath_node *an; /* pointer to parent */ 132 int tid; /* tid */ 133 int ac; /* which AC gets this trafic */ 134 int hwq_depth; /* how many buffers are on HW */ 135 u_int axq_depth; /* SW queue depth */ 136 137 struct { 138 TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */ 139 u_int axq_depth; /* SW queue depth */ 140 } filtq; 141 142 /* 143 * Entry on the ath_txq; when there's traffic 144 * to send 145 */ 146 TAILQ_ENTRY(ath_tid) axq_qelem; 147 int sched; 148 int paused; /* >0 if the TID has been paused */ 149 150 /* 151 * These are flags - perhaps later collapse 152 * down to a single uint32_t ? 153 */ 154 int addba_tx_pending; /* TX ADDBA pending */ 155 int bar_wait; /* waiting for BAR */ 156 int bar_tx; /* BAR TXed */ 157 int isfiltered; /* is this node currently filtered */ 158 159 /* 160 * Is the TID being cleaned up after a transition 161 * from aggregation to non-aggregation? 162 * When this is set to 1, this TID will be paused 163 * and no further traffic will be queued until all 164 * the hardware packets pending for this TID have been 165 * TXed/completed; at which point (non-aggregation) 166 * traffic will resume being TXed. 167 */ 168 int cleanup_inprogress; 169 /* 170 * How many hardware-queued packets are 171 * waiting to be cleaned up. 172 * This is only valid if cleanup_inprogress is 1. 173 */ 174 int incomp; 175 176 /* 177 * The following implements a ring representing 178 * the frames in the current BAW. 179 * To avoid copying the array content each time 180 * the BAW is moved, the baw_head/baw_tail point 181 * to the current BAW begin/end; when the BAW is 182 * shifted the head/tail of the array are also 183 * appropriately shifted. 184 */ 185 /* active tx buffers, beginning at current BAW */ 186 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 187 /* where the baw head is in the array */ 188 int baw_head; 189 /* where the BAW tail is in the array */ 190 int baw_tail; 191 }; 192 193 /* driver-specific node state */ 194 struct ath_node { 195 struct ieee80211_node an_node; /* base class */ 196 u_int8_t an_mgmtrix; /* min h/w rate index */ 197 u_int8_t an_mcastrix; /* mcast h/w rate index */ 198 uint32_t an_is_powersave; /* node is sleeping */ 199 uint32_t an_stack_psq; /* net80211 psq isn't empty */ 200 uint32_t an_tim_set; /* TIM has been set */ 201 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 202 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 203 char an_name[32]; /* eg "wlan0_a1" */ 204 struct lock an_mtx; /* protecting the rate control state */ 205 uint32_t an_swq_depth; /* how many SWQ packets for this 206 node */ 207 int clrdmask; /* has clrdmask been set */ 208 uint32_t an_leak_count; /* How many frames to leak during pause */ 209 /* variable-length rate control state follows */ 210 }; 211 #define ATH_NODE(ni) ((struct ath_node *)(ni)) 212 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 213 214 #define ATH_RSSI_LPF_LEN 10 215 #define ATH_RSSI_DUMMY_MARKER 0x127 216 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 217 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 218 #define ATH_LPF_RSSI(x, y, len) \ 219 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 220 #define ATH_RSSI_LPF(x, y) do { \ 221 if ((y) >= -20) \ 222 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 223 } while (0) 224 #define ATH_EP_RND(x,mul) \ 225 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 226 #define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 227 228 typedef enum { 229 ATH_BUFTYPE_NORMAL = 0, 230 ATH_BUFTYPE_MGMT = 1, 231 } ath_buf_type_t; 232 233 struct ath_buf { 234 TAILQ_ENTRY(ath_buf) bf_list; 235 struct ath_buf * bf_next; /* next buffer in the aggregate */ 236 int bf_nseg; 237 HAL_STATUS bf_rxstatus; 238 uint16_t bf_flags; /* status flags (below) */ 239 uint16_t bf_descid; /* 16 bit descriptor ID */ 240 struct ath_desc *bf_desc; /* virtual addr of desc */ 241 struct ath_desc_status bf_status; /* tx/rx status */ 242 bus_addr_t bf_daddr; /* physical addr of desc */ 243 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 244 struct mbuf *bf_m; /* mbuf for buf */ 245 struct ieee80211_node *bf_node; /* pointer to the node */ 246 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 247 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 248 bus_size_t bf_mapsize; 249 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 250 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 251 uint32_t bf_nextfraglen; /* length of next fragment */ 252 253 /* Completion function to call on TX complete (fail or not) */ 254 /* 255 * "fail" here is set to 1 if the queue entries were removed 256 * through a call to ath_tx_draintxq(). 257 */ 258 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 259 260 /* This state is kept to support software retries and aggregation */ 261 struct { 262 uint16_t bfs_seqno; /* sequence number of this packet */ 263 uint16_t bfs_ndelim; /* number of delims for padding */ 264 265 uint8_t bfs_retries; /* retry count */ 266 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 267 uint8_t bfs_nframes; /* number of frames in aggregate */ 268 uint8_t bfs_pri; /* packet AC priority */ 269 uint8_t bfs_tx_queue; /* destination hardware TX queue */ 270 271 u_int32_t bfs_aggr:1, /* part of aggregate? */ 272 bfs_aggrburst:1, /* part of aggregate burst? */ 273 bfs_isretried:1, /* retried frame? */ 274 bfs_dobaw:1, /* actually check against BAW? */ 275 bfs_addedbaw:1, /* has been added to the BAW */ 276 bfs_shpream:1, /* use short preamble */ 277 bfs_istxfrag:1, /* is fragmented */ 278 bfs_ismrr:1, /* do multi-rate TX retry */ 279 bfs_doprot:1, /* do RTS/CTS based protection */ 280 bfs_doratelookup:1; /* do rate lookup before each TX */ 281 282 /* 283 * These fields are passed into the 284 * descriptor setup functions. 285 */ 286 287 /* Make this an 8 bit value? */ 288 HAL_PKT_TYPE bfs_atype; /* packet type */ 289 290 uint32_t bfs_pktlen; /* length of this packet */ 291 292 uint16_t bfs_hdrlen; /* length of this packet header */ 293 uint16_t bfs_al; /* length of aggregate */ 294 295 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 296 uint8_t bfs_txrate0; /* first TX rate */ 297 uint8_t bfs_try0; /* first try count */ 298 299 uint16_t bfs_txpower; /* tx power */ 300 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 301 uint8_t bfs_ctsrate; /* CTS rate */ 302 303 /* 16 bit? */ 304 int32_t bfs_keyix; /* crypto key index */ 305 int32_t bfs_txantenna; /* TX antenna config */ 306 307 /* Make this an 8 bit value? */ 308 enum ieee80211_protmode bfs_protmode; 309 310 /* 16 bit? */ 311 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 312 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 313 } bf_state; 314 }; 315 typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 316 317 #define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 318 #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 319 #define ATH_BUF_FIFOEND 0x00000004 320 #define ATH_BUF_FIFOPTR 0x00000008 321 322 #define ATH_BUF_FLAGS_CLONE (ATH_BUF_MGMT) 323 324 /* 325 * DMA state for tx/rx descriptors. 326 */ 327 struct ath_descdma { 328 const char* dd_name; 329 struct ath_desc *dd_desc; /* descriptors */ 330 int dd_descsize; /* size of single descriptor */ 331 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 332 bus_size_t dd_desc_len; /* size of dd_desc */ 333 bus_dma_segment_t dd_dseg; 334 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 335 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 336 struct ath_buf *dd_bufptr; /* associated buffers */ 337 }; 338 339 /* 340 * Data transmit queue state. One of these exists for each 341 * hardware transmit queue. Packets sent to us from above 342 * are assigned to queues based on their priority. Not all 343 * devices support a complete set of hardware transmit queues. 344 * For those devices the array sc_ac2q will map multiple 345 * priorities to fewer hardware queues (typically all to one 346 * hardware queue). 347 */ 348 struct ath_txq { 349 struct ath_softc *axq_softc; /* Needed for scheduling */ 350 u_int axq_qnum; /* hardware q number */ 351 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 352 u_int axq_ac; /* WME AC */ 353 u_int axq_flags; 354 //#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 355 #define ATH_TXQ_PUTRUNNING 0x0002 /* ath_hal_puttxbuf has been called */ 356 u_int axq_depth; /* queue depth (stat only) */ 357 u_int axq_aggr_depth; /* how many aggregates are queued */ 358 u_int axq_intrcnt; /* interrupt count */ 359 u_int32_t *axq_link; /* link ptr in last TX desc */ 360 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 361 struct lock axq_lock; /* lock on q and link */ 362 363 /* 364 * This is the FIFO staging buffer when doing EDMA. 365 * 366 * For legacy chips, we just push the head pointer to 367 * the hardware and we ignore this list. 368 * 369 * For EDMA, the staging buffer is treated as normal; 370 * when it's time to push a list of frames to the hardware 371 * we move that list here and we stamp buffers with 372 * flags to identify the beginning/end of that particular 373 * FIFO entry. 374 */ 375 struct { 376 TAILQ_HEAD(axq_q_f_s, ath_buf) axq_q; 377 u_int axq_depth; 378 } fifo; 379 u_int axq_fifo_depth; /* depth of FIFO frames */ 380 381 /* 382 * XXX the holdingbf field is protected by the TXBUF lock 383 * for now, NOT the TXQ lock. 384 * 385 * Architecturally, it would likely be better to move 386 * the holdingbf field to a separate array in ath_softc 387 * just to highlight that it's not protected by the normal 388 * TX path lock. 389 */ 390 struct ath_buf *axq_holdingbf; /* holding TX buffer */ 391 char axq_name[12]; /* e.g. "ath0_txq4" */ 392 393 /* Per-TID traffic queue for software -> hardware TX */ 394 /* 395 * This is protected by the general TX path lock, not (for now) 396 * by the TXQ lock. 397 */ 398 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 399 }; 400 401 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 402 ksnprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 403 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 404 lockinit(&(_tq)->axq_lock, (_tq)->axq_name, 0, 0); \ 405 } while (0) 406 #define ATH_TXQ_LOCK_DESTROY(_tq) lockuninit(&(_tq)->axq_lock) 407 #define ATH_TXQ_LOCK(_tq) lockmgr(&(_tq)->axq_lock, LK_EXCLUSIVE) 408 #define ATH_TXQ_UNLOCK(_tq) lockmgr(&(_tq)->axq_lock, LK_RELEASE) 409 #define ATH_TXQ_LOCK_ASSERT(_tq) KKASSERT(lockstatus(&(_tq)->axq_lock, curthread) == LK_EXCLUSIVE) 410 #define ATH_TXQ_UNLOCK_ASSERT(_tq) KKASSERT(lockstatus(&(_tq)->axq_lock, curthread) != LK_EXCLUSIVE) 411 412 413 #define ATH_NODE_LOCK(_an) lockmgr(&(_an)->an_mtx, LK_EXCLUSIVE) 414 #define ATH_NODE_UNLOCK(_an) lockmgr(&(_an)->an_mtx, LK_RELEASE) 415 #define ATH_NODE_LOCK_ASSERT(_an) KKASSERT(lockstatus(&(_an)->an_mtx, curthread) == LK_EXCLUSIVE) 416 #define ATH_NODE_UNLOCK_ASSERT(_an) KKASSERT(lockstatus(&(_an)->an_mtx, curthread) != LK_EXCLUSIVE) 417 418 /* 419 * These are for the hardware queue. 420 */ 421 #define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 422 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 423 (_tq)->axq_depth++; \ 424 } while (0) 425 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 426 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 427 (_tq)->axq_depth++; \ 428 } while (0) 429 #define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 430 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 431 (_tq)->axq_depth--; \ 432 } while (0) 433 #define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 434 #define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 435 436 /* 437 * These are for the TID software queue. 438 */ 439 #define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \ 440 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \ 441 (_tq)->axq_depth++; \ 442 (_tq)->an->an_swq_depth++; \ 443 } while (0) 444 #define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \ 445 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \ 446 (_tq)->axq_depth++; \ 447 (_tq)->an->an_swq_depth++; \ 448 } while (0) 449 #define ATH_TID_REMOVE(_tq, _elm, _field) do { \ 450 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \ 451 (_tq)->axq_depth--; \ 452 (_tq)->an->an_swq_depth--; \ 453 } while (0) 454 #define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q) 455 #define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) 456 457 /* 458 * These are for the TID filtered frame queue 459 */ 460 #define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ 461 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \ 462 (_tq)->axq_depth++; \ 463 (_tq)->an->an_swq_depth++; \ 464 } while (0) 465 #define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \ 466 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \ 467 (_tq)->axq_depth++; \ 468 (_tq)->an->an_swq_depth++; \ 469 } while (0) 470 #define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \ 471 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \ 472 (_tq)->axq_depth--; \ 473 (_tq)->an->an_swq_depth--; \ 474 } while (0) 475 #define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q) 476 #define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field) 477 478 struct ath_vap { 479 struct ieee80211vap av_vap; /* base class */ 480 int av_bslot; /* beacon slot index */ 481 struct ath_buf *av_bcbuf; /* beacon buffer */ 482 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 483 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 484 485 void (*av_recv_mgmt)(struct ieee80211_node *, 486 struct mbuf *, int, int, int); 487 int (*av_newstate)(struct ieee80211vap *, 488 enum ieee80211_state, int); 489 void (*av_bmiss)(struct ieee80211vap *); 490 void (*av_node_ps)(struct ieee80211_node *, int); 491 int (*av_set_tim)(struct ieee80211_node *, int); 492 void (*av_recv_pspoll)(struct ieee80211_node *, 493 struct mbuf *); 494 }; 495 #define ATH_VAP(vap) ((struct ath_vap *)(vap)) 496 497 struct taskqueue; 498 struct ath_tx99; 499 500 /* 501 * Whether to reset the TX/RX queue with or without 502 * a queue flush. 503 */ 504 typedef enum { 505 ATH_RESET_DEFAULT = 0, 506 ATH_RESET_NOLOSS = 1, 507 ATH_RESET_FULL = 2, 508 } ATH_RESET_TYPE; 509 510 struct ath_rx_methods { 511 void (*recv_sched_queue)(struct ath_softc *sc, 512 HAL_RX_QUEUE q, int dosched); 513 void (*recv_sched)(struct ath_softc *sc, int dosched); 514 void (*recv_stop)(struct ath_softc *sc, int dodelay); 515 int (*recv_start)(struct ath_softc *sc); 516 void (*recv_flush)(struct ath_softc *sc); 517 void (*recv_tasklet)(void *arg, int npending); 518 int (*recv_rxbuf_init)(struct ath_softc *sc, 519 struct ath_buf *bf); 520 int (*recv_setup)(struct ath_softc *sc); 521 int (*recv_teardown)(struct ath_softc *sc); 522 }; 523 524 /* 525 * Represent the current state of the RX FIFO. 526 */ 527 struct ath_rx_edma { 528 struct ath_buf **m_fifo; 529 int m_fifolen; 530 int m_fifo_head; 531 int m_fifo_tail; 532 int m_fifo_depth; 533 struct mbuf *m_rxpending; 534 struct ath_buf *m_holdbf; 535 }; 536 537 struct ath_tx_edma_fifo { 538 struct ath_buf **m_fifo; 539 int m_fifolen; 540 int m_fifo_head; 541 int m_fifo_tail; 542 int m_fifo_depth; 543 }; 544 545 struct ath_tx_methods { 546 int (*xmit_setup)(struct ath_softc *sc); 547 int (*xmit_teardown)(struct ath_softc *sc); 548 void (*xmit_attach_comp_func)(struct ath_softc *sc); 549 550 void (*xmit_dma_restart)(struct ath_softc *sc, 551 struct ath_txq *txq); 552 void (*xmit_handoff)(struct ath_softc *sc, 553 struct ath_txq *txq, struct ath_buf *bf); 554 void (*xmit_drain)(struct ath_softc *sc, 555 ATH_RESET_TYPE reset_type); 556 }; 557 558 struct ath_softc { 559 struct ifnet *sc_ifp; /* interface common */ 560 struct ath_stats sc_stats; /* interface statistics */ 561 struct ath_tx_aggr_stats sc_aggr_stats; 562 struct ath_intr_stats sc_intr_stats; 563 uint64_t sc_debug; 564 uint64_t sc_ktrdebug; 565 int sc_nvaps; /* # vaps */ 566 int sc_nstavaps; /* # station vaps */ 567 int sc_nmeshvaps; /* # mbss vaps */ 568 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 569 u_int8_t sc_nbssid0; /* # vap's using base mac */ 570 uint32_t sc_bssidmask; /* bssid mask */ 571 572 struct ath_rx_methods sc_rx; 573 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 574 ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]; /* deferred RX completion */ 575 struct ath_tx_methods sc_tx; 576 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 577 578 /* 579 * This is (currently) protected by the TX queue lock; 580 * it should migrate to a separate lock later 581 * so as to minimise contention. 582 */ 583 ath_bufhead sc_txbuf_list; 584 585 int sc_rx_statuslen; 586 int sc_tx_desclen; 587 int sc_tx_statuslen; 588 int sc_tx_nmaps; /* Number of TX maps */ 589 int sc_edma_bufsize; 590 int sc_rx_stopped; /* XXX only for EDMA */ 591 int sc_rx_resetted; /* XXX only for EDMA */ 592 593 void (*sc_node_cleanup)(struct ieee80211_node *); 594 void (*sc_node_free)(struct ieee80211_node *); 595 device_t sc_dev; 596 HAL_BUS_TAG sc_st; /* bus space tag */ 597 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 598 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 599 struct lock sc_mtx; /* master lock (recursive) */ 600 struct lock sc_pcu_mtx; /* PCU access mutex */ 601 char sc_pcu_mtx_name[32]; 602 struct lock sc_rx_mtx; /* RX access mutex */ 603 char sc_rx_mtx_name[32]; 604 struct lock sc_tx_mtx; /* TX handling/comp mutex */ 605 char sc_tx_mtx_name[32]; 606 struct lock sc_tx_ic_mtx; /* TX queue mutex */ 607 char sc_tx_ic_mtx_name[32]; 608 struct taskqueue *sc_tq; /* private task queue */ 609 struct ath_hal *sc_ah; /* Atheros HAL */ 610 struct ath_ratectrl *sc_rc; /* tx rate control support */ 611 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 612 void (*sc_setdefantenna)(struct ath_softc *, u_int); 613 614 /* 615 * First set of flags. 616 */ 617 uint32_t sc_invalid : 1,/* disable hardware accesses */ 618 sc_mrretry : 1,/* multi-rate retry support */ 619 sc_mrrprot : 1,/* MRR + protection support */ 620 sc_softled : 1,/* enable LED gpio status */ 621 sc_hardled : 1,/* enable MAC LED status */ 622 sc_splitmic : 1,/* split TKIP MIC keys */ 623 sc_needmib : 1,/* enable MIB stats intr */ 624 sc_diversity: 1,/* enable rx diversity */ 625 sc_hasveol : 1,/* tx VEOL support */ 626 sc_ledstate : 1,/* LED on/off state */ 627 sc_blinking : 1,/* LED blink operation active */ 628 sc_mcastkey : 1,/* mcast key cache search */ 629 sc_scanning : 1,/* scanning active */ 630 sc_syncbeacon:1,/* sync/resync beacon timers */ 631 sc_hasclrkey: 1,/* CLR key supported */ 632 sc_xchanmode: 1,/* extended channel mode */ 633 sc_outdoor : 1,/* outdoor operation */ 634 sc_dturbo : 1,/* dynamic turbo in use */ 635 sc_hasbmask : 1,/* bssid mask support */ 636 sc_hasbmatch: 1,/* bssid match disable support*/ 637 sc_hastsfadd: 1,/* tsf adjust support */ 638 sc_beacons : 1,/* beacons running */ 639 sc_swbmiss : 1,/* sta mode using sw bmiss */ 640 sc_stagbeacons:1,/* use staggered beacons */ 641 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 642 sc_resume_up: 1,/* on resume, start all vaps */ 643 sc_tdma : 1,/* TDMA in use */ 644 sc_setcca : 1,/* set/clr CCA with TDMA */ 645 sc_resetcal : 1,/* reset cal state next trip */ 646 sc_rxslink : 1,/* do self-linked final descriptor */ 647 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 648 sc_isedma : 1,/* supports EDMA */ 649 sc_do_mybeacon : 1; /* supports mybeacon */ 650 651 /* 652 * Second set of flags. 653 */ 654 u_int32_t sc_use_ent : 1, 655 sc_rx_stbc : 1, 656 sc_tx_stbc : 1, 657 sc_hasenforcetxop : 1, /* support enforce TxOP */ 658 sc_hasdivcomb : 1, /* RX diversity combining */ 659 sc_rx_lnamixer : 1; /* RX using LNA mixing */ 660 661 int sc_cabq_enable; /* Enable cabq transmission */ 662 663 /* 664 * Enterprise mode configuration for AR9380 and later chipsets. 665 */ 666 uint32_t sc_ent_cfg; 667 668 uint32_t sc_eerd; /* regdomain from EEPROM */ 669 uint32_t sc_eecc; /* country code from EEPROM */ 670 /* rate tables */ 671 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 672 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 673 enum ieee80211_phymode sc_curmode; /* current phy mode */ 674 HAL_OPMODE sc_opmode; /* current operating mode */ 675 u_int16_t sc_curtxpow; /* current tx power limit */ 676 u_int16_t sc_curaid; /* current association id */ 677 struct ieee80211_channel *sc_curchan; /* current installed channel */ 678 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 679 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 680 struct { 681 u_int8_t ieeerate; /* IEEE rate */ 682 u_int8_t rxflags; /* radiotap rx flags */ 683 u_int8_t txflags; /* radiotap tx flags */ 684 u_int16_t ledon; /* softled on time */ 685 u_int16_t ledoff; /* softled off time */ 686 } sc_hwmap[32]; /* h/w rate ix mappings */ 687 u_int8_t sc_protrix; /* protection rate index */ 688 u_int8_t sc_lastdatarix; /* last data frame rate index */ 689 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 690 u_int sc_fftxqmin; /* min frames before staging */ 691 u_int sc_fftxqmax; /* max frames before drop */ 692 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 693 694 HAL_INT sc_imask; /* interrupt mask copy */ 695 696 /* 697 * These are modified in the interrupt handler as well as 698 * the task queues and other contexts. Thus these must be 699 * protected by a mutex, or they could clash. 700 * 701 * For now, access to these is behind the ATH_LOCK, 702 * just to save time. 703 */ 704 uint32_t sc_txq_active; /* bitmap of active TXQs */ 705 uint32_t sc_kickpcu; /* whether to kick the PCU */ 706 uint32_t sc_rxproc_cnt; /* In RX processing */ 707 uint32_t sc_txproc_cnt; /* In TX processing */ 708 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 709 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 710 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 711 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 712 713 u_int sc_keymax; /* size of key cache */ 714 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 715 716 /* 717 * Software based LED blinking 718 */ 719 u_int sc_ledpin; /* GPIO pin for driving LED */ 720 u_int sc_ledon; /* pin setting for LED on */ 721 u_int sc_ledidle; /* idle polling interval */ 722 int sc_ledevent; /* time of last LED event */ 723 u_int8_t sc_txrix; /* current tx rate for LED */ 724 u_int16_t sc_ledoff; /* off time for current blink */ 725 struct callout sc_ledtimer; /* led off timer */ 726 727 /* 728 * Hardware based LED blinking 729 */ 730 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 731 int sc_led_net_pin; /* MAC network LED GPIO pin */ 732 733 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 734 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 735 736 struct ath_descdma sc_rxdma; /* RX descriptors */ 737 ath_bufhead sc_rxbuf; /* receive buffer */ 738 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 739 struct task sc_rxtask; /* rx int processing */ 740 u_int8_t sc_defant; /* current default antenna */ 741 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 742 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 743 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 744 struct ath_rx_radiotap_header sc_rx_th; 745 int sc_rx_th_len; 746 u_int sc_monpass; /* frames to pass in mon.mode */ 747 748 struct ath_descdma sc_txdma; /* TX descriptors */ 749 uint16_t sc_txbuf_descid; 750 ath_bufhead sc_txbuf; /* transmit buffer */ 751 int sc_txbuf_cnt; /* how many buffers avail */ 752 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 753 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 754 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 755 struct lock sc_txbuflock; /* txbuf lock */ 756 char sc_txname[12]; /* e.g. "ath0_buf" */ 757 u_int sc_txqsetup; /* h/w queues setup */ 758 u_int sc_txintrperiod;/* tx interrupt batching */ 759 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 760 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 761 struct task sc_txtask; /* tx int processing */ 762 struct task sc_txqtask; /* tx proc processing */ 763 764 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 765 struct lock sc_txcomplock; /* TX EDMA completion lock */ 766 char sc_txcompname[12]; /* eg ath0_txcomp */ 767 768 int sc_wd_timer; /* count down for wd timer */ 769 struct callout sc_wd_ch; /* tx watchdog timer */ 770 struct ath_tx_radiotap_header sc_tx_th; 771 int sc_tx_th_len; 772 773 struct ath_descdma sc_bdma; /* beacon descriptors */ 774 ath_bufhead sc_bbuf; /* beacon buffers */ 775 u_int sc_bhalq; /* HAL q for outgoing beacons */ 776 u_int sc_bmisscount; /* missed beacon transmits */ 777 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 778 struct ath_txq *sc_cabq; /* tx q for cab frames */ 779 struct task sc_bmisstask; /* bmiss int processing */ 780 struct task sc_bstucktask; /* stuck beacon processing */ 781 struct task sc_resettask; /* interface reset task */ 782 struct task sc_fataltask; /* fatal task */ 783 enum { 784 OK, /* no change needed */ 785 UPDATE, /* update pending */ 786 COMMIT /* beacon sent, commit change */ 787 } sc_updateslot; /* slot time update fsm */ 788 int sc_slotupdate; /* slot to advance fsm */ 789 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 790 int sc_nbcnvaps; /* # vaps with beacons */ 791 792 struct callout sc_cal_ch; /* callout handle for cals */ 793 int sc_lastlongcal; /* last long cal completed */ 794 int sc_lastcalreset;/* last cal reset done */ 795 int sc_lastani; /* last ANI poll */ 796 int sc_lastshortcal; /* last short calibration */ 797 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 798 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 799 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 800 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 801 u_int sc_tdmaswba; /* TDMA SWBA counter */ 802 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 803 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 804 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 805 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 806 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 807 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 808 uint32_t sc_txchainmask; /* hardware TX chainmask */ 809 uint32_t sc_rxchainmask; /* hardware RX chainmask */ 810 uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */ 811 uint32_t sc_cur_rxchainmask; /* currently configured RX chainmask */ 812 uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 813 int sc_aggr_limit; /* TX limit on all aggregates */ 814 int sc_delim_min_pad; /* Minimum delimiter count */ 815 816 /* Queue limits */ 817 818 /* 819 * To avoid queue starvation in congested conditions, 820 * these parameters tune the maximum number of frames 821 * queued to the data/mcastq before they're dropped. 822 * 823 * This is to prevent: 824 * + a single destination overwhelming everything, including 825 * management/multicast frames; 826 * + multicast frames overwhelming everything (when the 827 * air is sufficiently busy that cabq can't drain.) 828 * + A node in powersave shouldn't be allowed to exhaust 829 * all available mbufs; 830 * 831 * These implement: 832 * + data_minfree is the maximum number of free buffers 833 * overall to successfully allow a data frame. 834 * 835 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 836 */ 837 int sc_txq_node_maxdepth; 838 int sc_txq_data_minfree; 839 int sc_txq_mcastq_maxdepth; 840 int sc_txq_node_psq_maxdepth; 841 842 /* 843 * Software queue twiddles 844 * 845 * hwq_limit_nonaggr: 846 * when to begin limiting non-aggregate frames to the 847 * hardware queue, regardless of the TID. 848 * hwq_limit_aggr: 849 * when to begin limiting A-MPDU frames to the 850 * hardware queue, regardless of the TID. 851 * tid_hwq_lo: how low the per-TID hwq count has to be before the 852 * TID will be scheduled again 853 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 854 * stops being scheduled. 855 */ 856 int sc_hwq_limit_nonaggr; 857 int sc_hwq_limit_aggr; 858 int sc_tid_hwq_lo; 859 int sc_tid_hwq_hi; 860 861 /* DFS related state */ 862 void *sc_dfs; /* Used by an optional DFS module */ 863 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 864 struct task sc_dfstask; /* DFS processing task */ 865 866 /* Spectral related state */ 867 void *sc_spectral; 868 int sc_dospectral; 869 870 /* LNA diversity related state */ 871 void *sc_lna_div; 872 int sc_dolnadiv; 873 874 /* ALQ */ 875 #ifdef ATH_DEBUG_ALQ 876 struct if_ath_alq sc_alq; 877 #endif 878 879 /* TX AMPDU handling */ 880 int (*sc_addba_request)(struct ieee80211_node *, 881 struct ieee80211_tx_ampdu *, int, int, int); 882 int (*sc_addba_response)(struct ieee80211_node *, 883 struct ieee80211_tx_ampdu *, int, int, int); 884 void (*sc_addba_stop)(struct ieee80211_node *, 885 struct ieee80211_tx_ampdu *); 886 void (*sc_addba_response_timeout) 887 (struct ieee80211_node *, 888 struct ieee80211_tx_ampdu *); 889 void (*sc_bar_response)(struct ieee80211_node *ni, 890 struct ieee80211_tx_ampdu *tap, 891 int status); 892 893 /* 894 * Powersave state tracking. 895 * 896 * target/cur powerstate is the chip power state. 897 * target selfgen state is the self-generated frames 898 * state. The chip can be awake but transmitted frames 899 * can have the PWRMGT bit set to 1 so the destination 900 * thinks the node is asleep. 901 */ 902 HAL_POWER_MODE sc_target_powerstate; 903 HAL_POWER_MODE sc_target_selfgen_state; 904 905 HAL_POWER_MODE sc_cur_powerstate; 906 907 int sc_powersave_refcnt; 908 909 /* ATH_PCI_* flags */ 910 uint32_t sc_pci_devinfo; 911 }; 912 913 #define ATH_LOCK_INIT(_sc) \ 914 lockinit(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 915 0, LK_CANRECURSE) 916 #define ATH_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_mtx) 917 #define ATH_LOCK(_sc) lockmgr(&(_sc)->sc_mtx, LK_EXCLUSIVE) 918 #define ATH_UNLOCK(_sc) lockmgr(&(_sc)->sc_mtx, LK_RELEASE) 919 #define ATH_LOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_mtx, curthread) == LK_EXCLUSIVE) 920 #define ATH_UNLOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_mtx, curthread) != LK_EXCLUSIVE) 921 922 /* 923 * The TX lock is non-reentrant and serialises the TX frame send 924 * and completion operations. 925 */ 926 #define ATH_TX_LOCK_INIT(_sc) do {\ 927 ksnprintf((_sc)->sc_tx_mtx_name, \ 928 sizeof((_sc)->sc_tx_mtx_name), \ 929 "%s TX lock", \ 930 device_get_nameunit((_sc)->sc_dev)); \ 931 lockinit(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \ 932 0, 0); \ 933 } while (0) 934 #define ATH_TX_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_tx_mtx) 935 #define ATH_TX_LOCK(_sc) lockmgr(&(_sc)->sc_tx_mtx, LK_EXCLUSIVE) 936 #define ATH_TX_UNLOCK(_sc) lockmgr(&(_sc)->sc_tx_mtx, LK_RELEASE) 937 #define ATH_TX_LOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_tx_mtx, curthread) == LK_EXCLUSIVE) 938 #define ATH_TX_UNLOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_tx_mtx, curthread) != LK_EXCLUSIVE) 939 940 /* 941 * The IC TX lock is non-reentrant and serialises packet queuing from 942 * the upper layers. 943 */ 944 #define ATH_TX_IC_LOCK_INIT(_sc) do {\ 945 ksnprintf((_sc)->sc_tx_ic_mtx_name, \ 946 sizeof((_sc)->sc_tx_ic_mtx_name), \ 947 "%s IC TX lock", \ 948 device_get_nameunit((_sc)->sc_dev)); \ 949 lockinit(&(_sc)->sc_tx_ic_mtx, (_sc)->sc_tx_ic_mtx_name, \ 950 0, 0); \ 951 } while (0) 952 #define ATH_TX_IC_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_tx_ic_mtx) 953 #define ATH_TX_IC_LOCK(_sc) lockmgr(&(_sc)->sc_tx_ic_mtx, LK_EXCLUSIVE) 954 #define ATH_TX_IC_UNLOCK(_sc) lockmgr(&(_sc)->sc_tx_ic_mtx, LK_RELEASE) 955 #define ATH_TX_IC_LOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_tx_ic_mtx, curthread) == LK_EXCLUSIVE) 956 #define ATH_TX_IC_UNLOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_tx_ic_mtx, curthread) != LK_EXCLUSIVE) 957 958 /* 959 * The PCU lock is non-recursive and should be treated as a spinlock. 960 * Although currently the interrupt code is run in netisr context and 961 * doesn't require this, this may change in the future. 962 * Please keep this in mind when protecting certain code paths 963 * with the PCU lock. 964 * 965 * The PCU lock is used to serialise access to the PCU so things such 966 * as TX, RX, state change (eg channel change), channel reset and updates 967 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 968 * 969 * Although the current single-thread taskqueue mechanism protects the 970 * majority of these situations by simply serialising them, there are 971 * a few others which occur at the same time. These include the TX path 972 * (which only acquires ATH_LOCK when recycling buffers to the free list), 973 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 974 */ 975 #define ATH_PCU_LOCK_INIT(_sc) do {\ 976 ksnprintf((_sc)->sc_pcu_mtx_name, \ 977 sizeof((_sc)->sc_pcu_mtx_name), \ 978 "%s PCU lock", \ 979 device_get_nameunit((_sc)->sc_dev)); \ 980 lockinit(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 981 0, 0); \ 982 } while (0) 983 #define ATH_PCU_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_pcu_mtx) 984 #define ATH_PCU_LOCK(_sc) lockmgr(&(_sc)->sc_pcu_mtx, LK_EXCLUSIVE) 985 #define ATH_PCU_UNLOCK(_sc) lockmgr(&(_sc)->sc_pcu_mtx, LK_RELEASE) 986 #define ATH_PCU_LOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_pcu_mtx, curthread) == LK_EXCLUSIVE) 987 #define ATH_PCU_UNLOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_pcu_mtx, curthread) != LK_EXCLUSIVE) 988 989 /* 990 * The RX lock is primarily a(nother) workaround to ensure that the 991 * RX FIFO/list isn't modified by various execution paths. 992 * Even though RX occurs in a single context (the ath taskqueue), the 993 * RX path can be executed via various reset/channel change paths. 994 */ 995 #define ATH_RX_LOCK_INIT(_sc) do {\ 996 ksnprintf((_sc)->sc_rx_mtx_name, \ 997 sizeof((_sc)->sc_rx_mtx_name), \ 998 "%s RX lock", \ 999 device_get_nameunit((_sc)->sc_dev)); \ 1000 lockinit(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 1001 0, 0); \ 1002 } while (0) 1003 #define ATH_RX_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_rx_mtx) 1004 #define ATH_RX_LOCK(_sc) lockmgr(&(_sc)->sc_rx_mtx, LK_EXCLUSIVE) 1005 #define ATH_RX_UNLOCK(_sc) lockmgr(&(_sc)->sc_rx_mtx, LK_RELEASE) 1006 #define ATH_RX_LOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_rx_mtx, curthread) == LK_EXCLUSIVE) 1007 #define ATH_RX_UNLOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->sc_rx_mtx, curthread) != LK_EXCLUSIVE) 1008 1009 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 1010 1011 #define ATH_TXBUF_LOCK_INIT(_sc) do { \ 1012 ksnprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 1013 device_get_nameunit((_sc)->sc_dev)); \ 1014 lockinit(&(_sc)->sc_txbuflock, (_sc)->sc_txname, 0, 0); \ 1015 } while (0) 1016 #define ATH_TXBUF_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_txbuflock) 1017 #define ATH_TXBUF_LOCK(_sc) lockmgr(&(_sc)->sc_txbuflock, LK_EXCLUSIVE) 1018 #define ATH_TXBUF_UNLOCK(_sc) lockmgr(&(_sc)->sc_txbuflock, LK_RELEASE) 1019 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ 1020 KKASSERT(lockstatus(&(_sc)->sc_txbuflock, curthread) == LK_EXCLUSIVE) 1021 #define ATH_TXBUF_UNLOCK_ASSERT(_sc) \ 1022 KKASSERT(lockstatus(&(_sc)->sc_txbuflock, curthread) != LK_EXCLUSIVE) 1023 1024 #define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 1025 ksnprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 1026 "%s_buf", \ 1027 device_get_nameunit((_sc)->sc_dev)); \ 1028 lockinit(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, 0, \ 1029 0); \ 1030 } while (0) 1031 #define ATH_TXSTATUS_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_txcomplock) 1032 #define ATH_TXSTATUS_LOCK(_sc) lockmgr(&(_sc)->sc_txcomplock, LK_EXCLUSIVE) 1033 #define ATH_TXSTATUS_UNLOCK(_sc) lockmgr(&(_sc)->sc_txcomplock, LK_RELEASE) 1034 #define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 1035 KKASSERT(lockstatus(&(_sc)->sc_txcomplock, curthread) == LK_EXCLUSIVE) 1036 1037 int ath_attach(u_int16_t, struct ath_softc *); 1038 int ath_detach(struct ath_softc *); 1039 void ath_resume(struct ath_softc *); 1040 void ath_suspend(struct ath_softc *); 1041 void ath_shutdown(struct ath_softc *); 1042 void ath_intr(void *); 1043 1044 #if defined(__DragonFly__) 1045 1046 #define IF_LOCK(ifsnd) /* XXX */ 1047 #define IF_UNLOCK(ifsnd) /* XXX */ 1048 1049 #endif 1050 1051 /* 1052 * HAL definitions to comply with local coding convention. 1053 */ 1054 #define ath_hal_detach(_ah) \ 1055 ((*(_ah)->ah_detach)((_ah))) 1056 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 1057 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 1058 #define ath_hal_macversion(_ah) \ 1059 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 1060 #define ath_hal_getratetable(_ah, _mode) \ 1061 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 1062 #define ath_hal_getmac(_ah, _mac) \ 1063 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 1064 #define ath_hal_setmac(_ah, _mac) \ 1065 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 1066 #define ath_hal_getbssidmask(_ah, _mask) \ 1067 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 1068 #define ath_hal_setbssidmask(_ah, _mask) \ 1069 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 1070 #define ath_hal_intrset(_ah, _mask) \ 1071 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 1072 #define ath_hal_intrget(_ah) \ 1073 ((*(_ah)->ah_getInterrupts)((_ah))) 1074 #define ath_hal_intrpend(_ah) \ 1075 ((*(_ah)->ah_isInterruptPending)((_ah))) 1076 #define ath_hal_getisr(_ah, _pmask) \ 1077 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 1078 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 1079 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 1080 #define ath_hal_setpower(_ah, _mode) \ 1081 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 1082 #define ath_hal_setselfgenpower(_ah, _mode) \ 1083 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_FALSE)) 1084 #define ath_hal_keycachesize(_ah) \ 1085 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 1086 #define ath_hal_keyreset(_ah, _ix) \ 1087 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 1088 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 1089 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 1090 #define ath_hal_keyisvalid(_ah, _ix) \ 1091 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 1092 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 1093 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 1094 #define ath_hal_getrxfilter(_ah) \ 1095 ((*(_ah)->ah_getRxFilter)((_ah))) 1096 #define ath_hal_setrxfilter(_ah, _filter) \ 1097 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 1098 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 1099 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 1100 #define ath_hal_waitforbeacon(_ah, _bf) \ 1101 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 1102 #define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 1103 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 1104 /* NB: common across all chips */ 1105 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 1106 #define ath_hal_gettsf32(_ah) \ 1107 OS_REG_READ(_ah, AR_TSF_L32) 1108 #define ath_hal_gettsf64(_ah) \ 1109 ((*(_ah)->ah_getTsf64)((_ah))) 1110 #define ath_hal_settsf64(_ah, _val) \ 1111 ((*(_ah)->ah_setTsf64)((_ah), (_val))) 1112 #define ath_hal_resettsf(_ah) \ 1113 ((*(_ah)->ah_resetTsf)((_ah))) 1114 #define ath_hal_rxena(_ah) \ 1115 ((*(_ah)->ah_enableReceive)((_ah))) 1116 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 1117 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 1118 #define ath_hal_gettxbuf(_ah, _q) \ 1119 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 1120 #define ath_hal_numtxpending(_ah, _q) \ 1121 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 1122 #define ath_hal_getrxbuf(_ah, _rxq) \ 1123 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 1124 #define ath_hal_txstart(_ah, _q) \ 1125 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 1126 #define ath_hal_setchannel(_ah, _chan) \ 1127 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 1128 #define ath_hal_calibrate(_ah, _chan, _iqcal) \ 1129 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 1130 #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 1131 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 1132 #define ath_hal_calreset(_ah, _chan) \ 1133 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 1134 #define ath_hal_setledstate(_ah, _state) \ 1135 ((*(_ah)->ah_setLedState)((_ah), (_state))) 1136 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 1137 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 1138 #define ath_hal_beaconreset(_ah) \ 1139 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 1140 #define ath_hal_beaconsettimers(_ah, _bt) \ 1141 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 1142 #define ath_hal_beacontimers(_ah, _bs) \ 1143 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 1144 #define ath_hal_getnexttbtt(_ah) \ 1145 ((*(_ah)->ah_getNextTBTT)((_ah))) 1146 #define ath_hal_setassocid(_ah, _bss, _associd) \ 1147 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 1148 #define ath_hal_phydisable(_ah) \ 1149 ((*(_ah)->ah_phyDisable)((_ah))) 1150 #define ath_hal_setopmode(_ah) \ 1151 ((*(_ah)->ah_setPCUConfig)((_ah))) 1152 #define ath_hal_stoptxdma(_ah, _qnum) \ 1153 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 1154 #define ath_hal_stoppcurecv(_ah) \ 1155 ((*(_ah)->ah_stopPcuReceive)((_ah))) 1156 #define ath_hal_startpcurecv(_ah) \ 1157 ((*(_ah)->ah_startPcuReceive)((_ah))) 1158 #define ath_hal_stopdmarecv(_ah) \ 1159 ((*(_ah)->ah_stopDmaReceive)((_ah))) 1160 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 1161 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 1162 (_indata), (_insize), (_outdata), (_outsize))) 1163 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 1164 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 1165 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 1166 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1167 #define ath_hal_resettxqueue(_ah, _q) \ 1168 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1169 #define ath_hal_releasetxqueue(_ah, _q) \ 1170 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1171 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 1172 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 1173 #define ath_hal_settxqueueprops(_ah, _q, _qi) \ 1174 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 1175 /* NB: common across all chips */ 1176 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 1177 #define ath_hal_txqenabled(_ah, _qnum) \ 1178 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 1179 #define ath_hal_getrfgain(_ah) \ 1180 ((*(_ah)->ah_getRfGain)((_ah))) 1181 #define ath_hal_getdefantenna(_ah) \ 1182 ((*(_ah)->ah_getDefAntenna)((_ah))) 1183 #define ath_hal_setdefantenna(_ah, _ant) \ 1184 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 1185 #define ath_hal_rxmonitor(_ah, _arg, _chan) \ 1186 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1187 #define ath_hal_ani_poll(_ah, _chan) \ 1188 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 1189 #define ath_hal_mibevent(_ah, _stats) \ 1190 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 1191 #define ath_hal_setslottime(_ah, _us) \ 1192 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1193 #define ath_hal_getslottime(_ah) \ 1194 ((*(_ah)->ah_getSlotTime)((_ah))) 1195 #define ath_hal_setacktimeout(_ah, _us) \ 1196 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 1197 #define ath_hal_getacktimeout(_ah) \ 1198 ((*(_ah)->ah_getAckTimeout)((_ah))) 1199 #define ath_hal_setctstimeout(_ah, _us) \ 1200 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 1201 #define ath_hal_getctstimeout(_ah) \ 1202 ((*(_ah)->ah_getCTSTimeout)((_ah))) 1203 #define ath_hal_getcapability(_ah, _cap, _param, _result) \ 1204 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1205 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 1206 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 1207 #define ath_hal_ciphersupported(_ah, _cipher) \ 1208 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1209 #define ath_hal_getregdomain(_ah, _prd) \ 1210 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 1211 #define ath_hal_setregdomain(_ah, _rd) \ 1212 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 1213 #define ath_hal_getcountrycode(_ah, _pcc) \ 1214 (*(_pcc) = (_ah)->ah_countryCode) 1215 #define ath_hal_gettkipmic(_ah) \ 1216 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 1217 #define ath_hal_settkipmic(_ah, _v) \ 1218 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 1219 #define ath_hal_hastkipsplit(_ah) \ 1220 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1221 #define ath_hal_gettkipsplit(_ah) \ 1222 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1223 #define ath_hal_settkipsplit(_ah, _v) \ 1224 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 1225 #define ath_hal_haswmetkipmic(_ah) \ 1226 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 1227 #define ath_hal_hwphycounters(_ah) \ 1228 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 1229 #define ath_hal_hasdiversity(_ah) \ 1230 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 1231 #define ath_hal_getdiversity(_ah) \ 1232 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 1233 #define ath_hal_setdiversity(_ah, _v) \ 1234 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 1235 #define ath_hal_getantennaswitch(_ah) \ 1236 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 1237 #define ath_hal_setantennaswitch(_ah, _v) \ 1238 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1239 #define ath_hal_getdiag(_ah, _pv) \ 1240 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1241 #define ath_hal_setdiag(_ah, _v) \ 1242 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1243 #define ath_hal_getnumtxqueues(_ah, _pv) \ 1244 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1245 #define ath_hal_hasveol(_ah) \ 1246 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1247 #define ath_hal_hastxpowlimit(_ah) \ 1248 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1249 #define ath_hal_settxpowlimit(_ah, _pow) \ 1250 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1251 #define ath_hal_gettxpowlimit(_ah, _ppow) \ 1252 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1253 #define ath_hal_getmaxtxpow(_ah, _ppow) \ 1254 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1255 #define ath_hal_gettpscale(_ah, _scale) \ 1256 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1257 #define ath_hal_settpscale(_ah, _v) \ 1258 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1259 #define ath_hal_hastpc(_ah) \ 1260 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1261 #define ath_hal_gettpc(_ah) \ 1262 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1263 #define ath_hal_settpc(_ah, _v) \ 1264 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1265 #define ath_hal_hasbursting(_ah) \ 1266 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1267 #define ath_hal_setmcastkeysearch(_ah, _v) \ 1268 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1269 #define ath_hal_hasmcastkeysearch(_ah) \ 1270 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1271 #define ath_hal_getmcastkeysearch(_ah) \ 1272 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1273 #define ath_hal_hasfastframes(_ah) \ 1274 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1275 #define ath_hal_hasbssidmask(_ah) \ 1276 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1277 #define ath_hal_hasbssidmatch(_ah) \ 1278 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1279 #define ath_hal_hastsfadjust(_ah) \ 1280 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1281 #define ath_hal_gettsfadjust(_ah) \ 1282 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1283 #define ath_hal_settsfadjust(_ah, _onoff) \ 1284 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1285 #define ath_hal_hasrfsilent(_ah) \ 1286 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1287 #define ath_hal_getrfkill(_ah) \ 1288 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1289 #define ath_hal_setrfkill(_ah, _onoff) \ 1290 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1291 #define ath_hal_getrfsilent(_ah, _prfsilent) \ 1292 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1293 #define ath_hal_setrfsilent(_ah, _rfsilent) \ 1294 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1295 #define ath_hal_gettpack(_ah, _ptpack) \ 1296 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1297 #define ath_hal_settpack(_ah, _tpack) \ 1298 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1299 #define ath_hal_gettpcts(_ah, _ptpcts) \ 1300 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1301 #define ath_hal_settpcts(_ah, _tpcts) \ 1302 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1303 #define ath_hal_hasintmit(_ah) \ 1304 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1305 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1306 #define ath_hal_getintmit(_ah) \ 1307 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1308 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1309 #define ath_hal_setintmit(_ah, _v) \ 1310 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1311 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1312 #define ath_hal_hasmybeacon(_ah) \ 1313 (ath_hal_getcapability(_ah, HAL_CAP_DO_MYBEACON, 1, NULL) == HAL_OK) 1314 1315 #define ath_hal_hasenforcetxop(_ah) \ 1316 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK) 1317 #define ath_hal_getenforcetxop(_ah) \ 1318 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, NULL) == HAL_OK) 1319 #define ath_hal_setenforcetxop(_ah, _v) \ 1320 ath_hal_setcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, _v, NULL) 1321 1322 #define ath_hal_hasrxlnamixer(_ah) \ 1323 (ath_hal_getcapability(_ah, HAL_CAP_RX_LNA_MIXING, 0, NULL) == HAL_OK) 1324 1325 #define ath_hal_hasdivantcomb(_ah) \ 1326 (ath_hal_getcapability(_ah, HAL_CAP_ANT_DIV_COMB, 0, NULL) == HAL_OK) 1327 1328 /* EDMA definitions */ 1329 #define ath_hal_hasedma(_ah) \ 1330 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1331 0, NULL) == HAL_OK) 1332 #define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1333 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1334 == HAL_OK) 1335 #define ath_hal_getntxmaps(_ah, _req) \ 1336 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1337 == HAL_OK) 1338 #define ath_hal_gettxdesclen(_ah, _req) \ 1339 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1340 == HAL_OK) 1341 #define ath_hal_gettxstatuslen(_ah, _req) \ 1342 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1343 == HAL_OK) 1344 #define ath_hal_getrxstatuslen(_ah, _req) \ 1345 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1346 == HAL_OK) 1347 #define ath_hal_setrxbufsize(_ah, _req) \ 1348 ((int)ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1349 == HAL_OK) 1350 1351 #define ath_hal_getchannoise(_ah, _c) \ 1352 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1353 1354 /* 802.11n HAL methods */ 1355 #define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1356 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1357 #define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1358 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1359 #define ath_hal_setrxchainmask(_ah, _rx) \ 1360 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1361 #define ath_hal_settxchainmask(_ah, _tx) \ 1362 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1363 #define ath_hal_split4ktrans(_ah) \ 1364 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1365 0, NULL) == HAL_OK) 1366 #define ath_hal_self_linked_final_rxdesc(_ah) \ 1367 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1368 0, NULL) == HAL_OK) 1369 #define ath_hal_gtxto_supported(_ah) \ 1370 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1371 #define ath_hal_has_long_rxdesc_tsf(_ah) \ 1372 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1373 0, NULL) == HAL_OK) 1374 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1375 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1376 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1377 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1378 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1379 _txr0, _txtr0, _keyix, _ant, _flags, \ 1380 _rtsrate, _rtsdura) \ 1381 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1382 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1383 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1384 #define ath_hal_setupxtxdesc(_ah, _ds, \ 1385 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1386 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1387 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1388 #define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1389 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1390 (_first), (_last), (_ds0))) 1391 #define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1392 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1393 #define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1394 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1395 #define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1396 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1397 #define ath_hal_settxdesclink(_ah, _ds, _link) \ 1398 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1399 #define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1400 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1401 #define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1402 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1403 #define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1404 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1405 (_size))) 1406 #define ath_hal_gettxrawtxdesc(_ah, _txstatus) \ 1407 ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus))) 1408 1409 #define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1410 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1411 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1412 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1413 #define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1414 _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1415 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1416 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1417 (_first), (_last), (_lastaggr))) 1418 #define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1419 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1420 1421 #define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1422 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1423 (_series), (_ns), (_flags))) 1424 1425 #define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1426 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1427 #define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \ 1428 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1429 #define ath_hal_set11n_aggr_last(_ah, _ds) \ 1430 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1431 1432 #define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1433 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1434 #define ath_hal_clr11n_aggr(_ah, _ds) \ 1435 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1436 #define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \ 1437 ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v))) 1438 1439 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1440 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1441 #define ath_hal_gpioset(_ah, _gpio, _b) \ 1442 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1443 #define ath_hal_gpioget(_ah, _gpio) \ 1444 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1445 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1446 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1447 1448 /* 1449 * PCIe suspend/resume/poweron/poweroff related macros 1450 */ 1451 #define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1452 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1453 #define ath_hal_disablepcie(_ah) \ 1454 ((*(_ah)->ah_disablePCIE)((_ah))) 1455 1456 /* 1457 * This is badly-named; you need to set the correct parameters 1458 * to begin to receive useful radar events; and even then 1459 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1460 * more information. 1461 */ 1462 #define ath_hal_enabledfs(_ah, _param) \ 1463 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1464 #define ath_hal_getdfsthresh(_ah, _param) \ 1465 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1466 #define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1467 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1468 #define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1469 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1470 (_buf), (_event))) 1471 #define ath_hal_is_fast_clock_enabled(_ah) \ 1472 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1473 #define ath_hal_radar_wait(_ah, _chan) \ 1474 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1475 #define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1476 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1477 #define ath_hal_get_chan_ext_busy(_ah) \ 1478 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1479 #define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \ 1480 ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask))) 1481 1482 #define ath_hal_spectral_supported(_ah) \ 1483 (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK) 1484 #define ath_hal_spectral_get_config(_ah, _p) \ 1485 ((*(_ah)->ah_spectralGetConfig)((_ah), (_p))) 1486 #define ath_hal_spectral_configure(_ah, _p) \ 1487 ((*(_ah)->ah_spectralConfigure)((_ah), (_p))) 1488 #define ath_hal_spectral_start(_ah) \ 1489 ((*(_ah)->ah_spectralStart)((_ah))) 1490 #define ath_hal_spectral_stop(_ah) \ 1491 ((*(_ah)->ah_spectralStop)((_ah))) 1492 1493 #define ath_hal_btcoex_supported(_ah) \ 1494 (ath_hal_getcapability(_ah, HAL_CAP_BT_COEX, 0, NULL) == HAL_OK) 1495 #define ath_hal_btcoex_set_info(_ah, _info) \ 1496 ((*(_ah)->ah_btCoexSetInfo)((_ah), (_info))) 1497 #define ath_hal_btcoex_set_config(_ah, _cfg) \ 1498 ((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg))) 1499 #define ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \ 1500 ((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid))) 1501 #define ath_hal_btcoex_set_weights(_ah, _weight) \ 1502 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight))) 1503 #define ath_hal_btcoex_set_weights(_ah, _weight) \ 1504 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight))) 1505 #define ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \ 1506 ((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr))) 1507 #define ath_hal_btcoex_set_parameter(_ah, _attrib, _val) \ 1508 ((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val))) 1509 #define ath_hal_btcoex_enable(_ah) \ 1510 ((*(_ah)->ah_btCoexEnable)((_ah))) 1511 #define ath_hal_btcoex_disable(_ah) \ 1512 ((*(_ah)->ah_btCoexDisable)((_ah))) 1513 1514 #define ath_hal_div_comb_conf_get(_ah, _conf) \ 1515 ((*(_ah)->ah_divLnaConfGet)((_ah), (_conf))) 1516 #define ath_hal_div_comb_conf_set(_ah, _conf) \ 1517 ((*(_ah)->ah_divLnaConfSet)((_ah), (_conf))) 1518 1519 #endif /* _DEV_ATH_ATHVAR_H */ 1520