1572ff6f6SMatthew Dillon /*
2572ff6f6SMatthew Dillon * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc.
4572ff6f6SMatthew Dillon *
5572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8572ff6f6SMatthew Dillon *
9572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16572ff6f6SMatthew Dillon *
17572ff6f6SMatthew Dillon * $FreeBSD$
18572ff6f6SMatthew Dillon */
19572ff6f6SMatthew Dillon
20572ff6f6SMatthew Dillon #ifndef _ATH_AH_H_
21572ff6f6SMatthew Dillon #define _ATH_AH_H_
22572ff6f6SMatthew Dillon /*
23572ff6f6SMatthew Dillon * Atheros Hardware Access Layer
24572ff6f6SMatthew Dillon *
25572ff6f6SMatthew Dillon * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
26572ff6f6SMatthew Dillon * structure for use with the device. Hardware-related operations that
27572ff6f6SMatthew Dillon * follow must call back into the HAL through interface, supplying the
28572ff6f6SMatthew Dillon * reference as the first parameter.
29572ff6f6SMatthew Dillon */
30572ff6f6SMatthew Dillon
31572ff6f6SMatthew Dillon #include "ah_osdep.h"
32572ff6f6SMatthew Dillon
33572ff6f6SMatthew Dillon /*
34572ff6f6SMatthew Dillon * The maximum number of TX/RX chains supported.
35572ff6f6SMatthew Dillon * This is intended to be used by various statistics gathering operations
36572ff6f6SMatthew Dillon * (NF, RSSI, EVM).
37572ff6f6SMatthew Dillon */
38572ff6f6SMatthew Dillon #define AH_MAX_CHAINS 3
39572ff6f6SMatthew Dillon #define AH_MIMO_MAX_EVM_PILOTS 6
40572ff6f6SMatthew Dillon
41572ff6f6SMatthew Dillon /*
42572ff6f6SMatthew Dillon * __ahdecl is analogous to _cdecl; it defines the calling
43572ff6f6SMatthew Dillon * convention used within the HAL. For most systems this
44572ff6f6SMatthew Dillon * can just default to be empty and the compiler will (should)
45572ff6f6SMatthew Dillon * use _cdecl. For systems where _cdecl is not compatible this
46572ff6f6SMatthew Dillon * must be defined. See linux/ah_osdep.h for an example.
47572ff6f6SMatthew Dillon */
48572ff6f6SMatthew Dillon #ifndef __ahdecl
49572ff6f6SMatthew Dillon #define __ahdecl
50572ff6f6SMatthew Dillon #endif
51572ff6f6SMatthew Dillon
52572ff6f6SMatthew Dillon /*
53572ff6f6SMatthew Dillon * Status codes that may be returned by the HAL. Note that
54572ff6f6SMatthew Dillon * interfaces that return a status code set it only when an
55572ff6f6SMatthew Dillon * error occurs--i.e. you cannot check it for success.
56572ff6f6SMatthew Dillon */
57572ff6f6SMatthew Dillon typedef enum {
58572ff6f6SMatthew Dillon HAL_OK = 0, /* No error */
59572ff6f6SMatthew Dillon HAL_ENXIO = 1, /* No hardware present */
60572ff6f6SMatthew Dillon HAL_ENOMEM = 2, /* Memory allocation failed */
61572ff6f6SMatthew Dillon HAL_EIO = 3, /* Hardware didn't respond as expected */
62572ff6f6SMatthew Dillon HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
63572ff6f6SMatthew Dillon HAL_EEVERSION = 5, /* EEPROM version invalid */
64572ff6f6SMatthew Dillon HAL_EELOCKED = 6, /* EEPROM unreadable */
65572ff6f6SMatthew Dillon HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
66572ff6f6SMatthew Dillon HAL_EEREAD = 8, /* EEPROM read problem */
67572ff6f6SMatthew Dillon HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
68572ff6f6SMatthew Dillon HAL_EESIZE = 10, /* EEPROM size not supported */
69572ff6f6SMatthew Dillon HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
70572ff6f6SMatthew Dillon HAL_EINVAL = 12, /* Invalid parameter to function */
71572ff6f6SMatthew Dillon HAL_ENOTSUPP = 13, /* Hardware revision not supported */
72572ff6f6SMatthew Dillon HAL_ESELFTEST = 14, /* Hardware self-test failed */
73572ff6f6SMatthew Dillon HAL_EINPROGRESS = 15, /* Operation incomplete */
74572ff6f6SMatthew Dillon HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */
75572ff6f6SMatthew Dillon HAL_EEBADCC = 17, /* EEPROM invalid country code */
76572ff6f6SMatthew Dillon HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */
77572ff6f6SMatthew Dillon } HAL_STATUS;
78572ff6f6SMatthew Dillon
79572ff6f6SMatthew Dillon typedef enum {
80572ff6f6SMatthew Dillon AH_FALSE = 0, /* NB: lots of code assumes false is zero */
81572ff6f6SMatthew Dillon AH_TRUE = 1,
82572ff6f6SMatthew Dillon } HAL_BOOL;
83572ff6f6SMatthew Dillon
84572ff6f6SMatthew Dillon typedef enum {
85572ff6f6SMatthew Dillon HAL_CAP_REG_DMN = 0, /* current regulatory domain */
86572ff6f6SMatthew Dillon HAL_CAP_CIPHER = 1, /* hardware supports cipher */
87572ff6f6SMatthew Dillon HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
88572ff6f6SMatthew Dillon HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
89572ff6f6SMatthew Dillon HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
90572ff6f6SMatthew Dillon HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */
91572ff6f6SMatthew Dillon HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
92572ff6f6SMatthew Dillon HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
93572ff6f6SMatthew Dillon HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */
94572ff6f6SMatthew Dillon HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */
95572ff6f6SMatthew Dillon HAL_CAP_DIAG = 11, /* hardware diagnostic support */
96572ff6f6SMatthew Dillon HAL_CAP_COMPRESSION = 12, /* hardware supports compression */
97572ff6f6SMatthew Dillon HAL_CAP_BURST = 13, /* hardware supports packet bursting */
98572ff6f6SMatthew Dillon HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
99572ff6f6SMatthew Dillon HAL_CAP_TXPOW = 15, /* global tx power limit */
100572ff6f6SMatthew Dillon HAL_CAP_TPC = 16, /* per-packet tx power control */
101572ff6f6SMatthew Dillon HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */
102572ff6f6SMatthew Dillon HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */
103572ff6f6SMatthew Dillon HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */
104572ff6f6SMatthew Dillon HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */
105572ff6f6SMatthew Dillon /* 21 was HAL_CAP_XR */
106572ff6f6SMatthew Dillon HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */
107572ff6f6SMatthew Dillon /* 23 was HAL_CAP_CHAN_HALFRATE */
108572ff6f6SMatthew Dillon /* 24 was HAL_CAP_CHAN_QUARTERRATE */
109572ff6f6SMatthew Dillon HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */
110572ff6f6SMatthew Dillon HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
111572ff6f6SMatthew Dillon HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
112572ff6f6SMatthew Dillon HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
113572ff6f6SMatthew Dillon HAL_CAP_PCIE_PS = 29,
114572ff6f6SMatthew Dillon HAL_CAP_HT = 30, /* hardware can support HT */
115572ff6f6SMatthew Dillon HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */
116572ff6f6SMatthew Dillon HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */
117572ff6f6SMatthew Dillon HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */
118572ff6f6SMatthew Dillon HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */
119572ff6f6SMatthew Dillon HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */
120572ff6f6SMatthew Dillon
121572ff6f6SMatthew Dillon HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */
122572ff6f6SMatthew Dillon HAL_CAP_RIFS_RX = 39,
123572ff6f6SMatthew Dillon HAL_CAP_RIFS_TX = 40,
124572ff6f6SMatthew Dillon HAL_CAP_FORCE_PPM = 41,
125572ff6f6SMatthew Dillon HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */
126572ff6f6SMatthew Dillon HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */
127572ff6f6SMatthew Dillon HAL_CAP_DFS_DMN = 44, /* current DFS domain */
128572ff6f6SMatthew Dillon HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */
129572ff6f6SMatthew Dillon HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */
130572ff6f6SMatthew Dillon
131572ff6f6SMatthew Dillon HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep
132572ff6f6SMatthew Dillon automatically after waking up to receive TIM */
133572ff6f6SMatthew Dillon HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */
134572ff6f6SMatthew Dillon HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */
135572ff6f6SMatthew Dillon HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */
136572ff6f6SMatthew Dillon HAL_CAP_BB_RIFS_HANG = 52,
137572ff6f6SMatthew Dillon HAL_CAP_RIFS_RX_ENABLED = 53,
138572ff6f6SMatthew Dillon HAL_CAP_BB_DFS_HANG = 54,
139572ff6f6SMatthew Dillon
140572ff6f6SMatthew Dillon HAL_CAP_RX_STBC = 58,
141572ff6f6SMatthew Dillon HAL_CAP_TX_STBC = 59,
142572ff6f6SMatthew Dillon
143572ff6f6SMatthew Dillon HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */
144572ff6f6SMatthew Dillon HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */
145572ff6f6SMatthew Dillon
146572ff6f6SMatthew Dillon HAL_CAP_DS = 67, /* 2 stream */
147572ff6f6SMatthew Dillon HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68,
148572ff6f6SMatthew Dillon HAL_CAP_MAC_HANG = 69, /* can MAC hang */
149572ff6f6SMatthew Dillon HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */
150572ff6f6SMatthew Dillon
151572ff6f6SMatthew Dillon HAL_CAP_TS = 72, /* 3 stream */
152572ff6f6SMatthew Dillon
153572ff6f6SMatthew Dillon HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */
154572ff6f6SMatthew Dillon HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */
155572ff6f6SMatthew Dillon HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */
156572ff6f6SMatthew Dillon HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */
157572ff6f6SMatthew Dillon HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */
158572ff6f6SMatthew Dillon HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */
159572ff6f6SMatthew Dillon HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */
160572ff6f6SMatthew Dillon HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */
161572ff6f6SMatthew Dillon HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */
162572ff6f6SMatthew Dillon HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */
163572ff6f6SMatthew Dillon
164572ff6f6SMatthew Dillon HAL_CAP_BB_PANIC_WATCHDOG = 92,
165572ff6f6SMatthew Dillon
166572ff6f6SMatthew Dillon HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */
167572ff6f6SMatthew Dillon
168572ff6f6SMatthew Dillon HAL_CAP_LDPC = 99,
169572ff6f6SMatthew Dillon
170572ff6f6SMatthew Dillon HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */
171572ff6f6SMatthew Dillon
172572ff6f6SMatthew Dillon HAL_CAP_ANT_DIV_COMB = 105, /* Enable antenna diversity/combining */
173572ff6f6SMatthew Dillon HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */
174572ff6f6SMatthew Dillon HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */
175572ff6f6SMatthew Dillon HAL_CAP_LDPCWAR = 108,
176572ff6f6SMatthew Dillon HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */
177572ff6f6SMatthew Dillon HAL_CAP_ENABLE_APM = 110, /* APM enabled */
178572ff6f6SMatthew Dillon HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111,
179572ff6f6SMatthew Dillon HAL_CAP_PCIE_LCR_OFFSET = 112,
180572ff6f6SMatthew Dillon
181572ff6f6SMatthew Dillon HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */
182572ff6f6SMatthew Dillon HAL_CAP_MCI = 118,
183572ff6f6SMatthew Dillon HAL_CAP_SMARTANTENNA = 119,
184572ff6f6SMatthew Dillon HAL_CAP_TRAFFIC_FAST_RECOVER = 120,
185572ff6f6SMatthew Dillon HAL_CAP_TX_DIVERSITY = 121,
186572ff6f6SMatthew Dillon HAL_CAP_CRDC = 122,
187572ff6f6SMatthew Dillon
188572ff6f6SMatthew Dillon /* The following are private to the FreeBSD HAL (224 onward) */
189572ff6f6SMatthew Dillon
190572ff6f6SMatthew Dillon HAL_CAP_INTMIT = 229, /* interference mitigation */
191572ff6f6SMatthew Dillon HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */
192572ff6f6SMatthew Dillon HAL_CAP_BB_HANG = 235, /* can baseband hang */
193572ff6f6SMatthew Dillon HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */
194572ff6f6SMatthew Dillon HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */
195572ff6f6SMatthew Dillon HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */
196572ff6f6SMatthew Dillon HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */
197572ff6f6SMatthew Dillon HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */
198572ff6f6SMatthew Dillon HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */
199572ff6f6SMatthew Dillon HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */
200572ff6f6SMatthew Dillon HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */
201572ff6f6SMatthew Dillon HAL_CAP_RX_LNA_MIXING = 247, /* RX hardware uses LNA mixing */
202d98a0bcfSMatthew Dillon HAL_CAP_DO_MYBEACON = 248, /* Supports HAL_RX_FILTER_MYBEACON */
203572ff6f6SMatthew Dillon } HAL_CAPABILITY_TYPE;
204572ff6f6SMatthew Dillon
205572ff6f6SMatthew Dillon /*
206572ff6f6SMatthew Dillon * "States" for setting the LED. These correspond to
207572ff6f6SMatthew Dillon * the possible 802.11 operational states and there may
208572ff6f6SMatthew Dillon * be a many-to-one mapping between these states and the
209572ff6f6SMatthew Dillon * actual hardware state for the LED's (i.e. the hardware
210572ff6f6SMatthew Dillon * may have fewer states).
211572ff6f6SMatthew Dillon */
212572ff6f6SMatthew Dillon typedef enum {
213572ff6f6SMatthew Dillon HAL_LED_INIT = 0,
214572ff6f6SMatthew Dillon HAL_LED_SCAN = 1,
215572ff6f6SMatthew Dillon HAL_LED_AUTH = 2,
216572ff6f6SMatthew Dillon HAL_LED_ASSOC = 3,
217572ff6f6SMatthew Dillon HAL_LED_RUN = 4
218572ff6f6SMatthew Dillon } HAL_LED_STATE;
219572ff6f6SMatthew Dillon
220572ff6f6SMatthew Dillon /*
221572ff6f6SMatthew Dillon * Transmit queue types/numbers. These are used to tag
222572ff6f6SMatthew Dillon * each transmit queue in the hardware and to identify a set
223572ff6f6SMatthew Dillon * of transmit queues for operations such as start/stop dma.
224572ff6f6SMatthew Dillon */
225572ff6f6SMatthew Dillon typedef enum {
226572ff6f6SMatthew Dillon HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
227572ff6f6SMatthew Dillon HAL_TX_QUEUE_DATA = 1, /* data xmit q's */
228572ff6f6SMatthew Dillon HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */
229572ff6f6SMatthew Dillon HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
230572ff6f6SMatthew Dillon HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */
231572ff6f6SMatthew Dillon HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */
232572ff6f6SMatthew Dillon HAL_TX_QUEUE_CFEND = 6,
233572ff6f6SMatthew Dillon HAL_TX_QUEUE_PAPRD = 7,
234572ff6f6SMatthew Dillon } HAL_TX_QUEUE;
235572ff6f6SMatthew Dillon
236572ff6f6SMatthew Dillon #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
237572ff6f6SMatthew Dillon
238572ff6f6SMatthew Dillon /*
239572ff6f6SMatthew Dillon * Receive queue types. These are used to tag
240572ff6f6SMatthew Dillon * each transmit queue in the hardware and to identify a set
241572ff6f6SMatthew Dillon * of transmit queues for operations such as start/stop dma.
242572ff6f6SMatthew Dillon */
243572ff6f6SMatthew Dillon typedef enum {
244572ff6f6SMatthew Dillon HAL_RX_QUEUE_HP = 0, /* high priority recv queue */
245572ff6f6SMatthew Dillon HAL_RX_QUEUE_LP = 1, /* low priority recv queue */
246572ff6f6SMatthew Dillon } HAL_RX_QUEUE;
247572ff6f6SMatthew Dillon
248572ff6f6SMatthew Dillon #define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */
249572ff6f6SMatthew Dillon
250572ff6f6SMatthew Dillon #define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */
251572ff6f6SMatthew Dillon
252572ff6f6SMatthew Dillon /*
253572ff6f6SMatthew Dillon * Transmit queue subtype. These map directly to
254572ff6f6SMatthew Dillon * WME Access Categories (except for UPSD). Refer
255572ff6f6SMatthew Dillon * to Table 5 of the WME spec.
256572ff6f6SMatthew Dillon */
257572ff6f6SMatthew Dillon typedef enum {
258572ff6f6SMatthew Dillon HAL_WME_AC_BK = 0, /* background access category */
259572ff6f6SMatthew Dillon HAL_WME_AC_BE = 1, /* best effort access category*/
260572ff6f6SMatthew Dillon HAL_WME_AC_VI = 2, /* video access category */
261572ff6f6SMatthew Dillon HAL_WME_AC_VO = 3, /* voice access category */
262572ff6f6SMatthew Dillon HAL_WME_UPSD = 4, /* uplink power save */
263572ff6f6SMatthew Dillon } HAL_TX_QUEUE_SUBTYPE;
264572ff6f6SMatthew Dillon
265572ff6f6SMatthew Dillon /*
266572ff6f6SMatthew Dillon * Transmit queue flags that control various
267572ff6f6SMatthew Dillon * operational parameters.
268572ff6f6SMatthew Dillon */
269572ff6f6SMatthew Dillon typedef enum {
270572ff6f6SMatthew Dillon /*
271572ff6f6SMatthew Dillon * Per queue interrupt enables. When set the associated
272572ff6f6SMatthew Dillon * interrupt may be delivered for packets sent through
273572ff6f6SMatthew Dillon * the queue. Without these enabled no interrupts will
274572ff6f6SMatthew Dillon * be delivered for transmits through the queue.
275572ff6f6SMatthew Dillon */
276572ff6f6SMatthew Dillon HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
277572ff6f6SMatthew Dillon HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
278572ff6f6SMatthew Dillon HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
279572ff6f6SMatthew Dillon HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
280572ff6f6SMatthew Dillon HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
281572ff6f6SMatthew Dillon /*
282572ff6f6SMatthew Dillon * Enable hardware compression for packets sent through
283572ff6f6SMatthew Dillon * the queue. The compression buffer must be setup and
284572ff6f6SMatthew Dillon * packets must have a key entry marked in the tx descriptor.
285572ff6f6SMatthew Dillon */
286572ff6f6SMatthew Dillon HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
287572ff6f6SMatthew Dillon /*
288572ff6f6SMatthew Dillon * Disable queue when veol is hit or ready time expires.
289572ff6f6SMatthew Dillon * By default the queue is disabled only on reaching the
290572ff6f6SMatthew Dillon * physical end of queue (i.e. a null link ptr in the
291572ff6f6SMatthew Dillon * descriptor chain).
292572ff6f6SMatthew Dillon */
293572ff6f6SMatthew Dillon HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
294572ff6f6SMatthew Dillon /*
295572ff6f6SMatthew Dillon * Schedule frames on delivery of a DBA (DMA Beacon Alert)
296572ff6f6SMatthew Dillon * event. Frames will be transmitted only when this timer
297572ff6f6SMatthew Dillon * fires, e.g to transmit a beacon in ap or adhoc modes.
298572ff6f6SMatthew Dillon */
299572ff6f6SMatthew Dillon HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */
300572ff6f6SMatthew Dillon /*
301572ff6f6SMatthew Dillon * Each transmit queue has a counter that is incremented
302572ff6f6SMatthew Dillon * each time the queue is enabled and decremented when
303572ff6f6SMatthew Dillon * the list of frames to transmit is traversed (or when
304572ff6f6SMatthew Dillon * the ready time for the queue expires). This counter
305572ff6f6SMatthew Dillon * must be non-zero for frames to be scheduled for
306572ff6f6SMatthew Dillon * transmission. The following controls disable bumping
307572ff6f6SMatthew Dillon * this counter under certain conditions. Typically this
308572ff6f6SMatthew Dillon * is used to gate frames based on the contents of another
309572ff6f6SMatthew Dillon * queue (e.g. CAB traffic may only follow a beacon frame).
310572ff6f6SMatthew Dillon * These are meaningful only when frames are scheduled
311572ff6f6SMatthew Dillon * with a non-ASAP policy (e.g. DBA-gated).
312572ff6f6SMatthew Dillon */
313572ff6f6SMatthew Dillon HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
314572ff6f6SMatthew Dillon HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
315572ff6f6SMatthew Dillon
316572ff6f6SMatthew Dillon /*
317572ff6f6SMatthew Dillon * Fragment burst backoff policy. Normally the no backoff
318572ff6f6SMatthew Dillon * is done after a successful transmission, the next fragment
319572ff6f6SMatthew Dillon * is sent at SIFS. If this flag is set backoff is done
320572ff6f6SMatthew Dillon * after each fragment, regardless whether it was ack'd or
321572ff6f6SMatthew Dillon * not, after the backoff count reaches zero a normal channel
322572ff6f6SMatthew Dillon * access procedure is done before the next transmit (i.e.
323572ff6f6SMatthew Dillon * wait AIFS instead of SIFS).
324572ff6f6SMatthew Dillon */
325572ff6f6SMatthew Dillon HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
326572ff6f6SMatthew Dillon /*
327572ff6f6SMatthew Dillon * Disable post-tx backoff following each frame.
328572ff6f6SMatthew Dillon */
329572ff6f6SMatthew Dillon HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
330572ff6f6SMatthew Dillon /*
331572ff6f6SMatthew Dillon * DCU arbiter lockout control. This controls how
332572ff6f6SMatthew Dillon * lower priority tx queues are handled with respect to
333572ff6f6SMatthew Dillon * to a specific queue when multiple queues have frames
334572ff6f6SMatthew Dillon * to send. No lockout means lower priority queues arbitrate
335572ff6f6SMatthew Dillon * concurrently with this queue. Intra-frame lockout
336572ff6f6SMatthew Dillon * means lower priority queues are locked out until the
337572ff6f6SMatthew Dillon * current frame transmits (e.g. including backoffs and bursting).
338572ff6f6SMatthew Dillon * Global lockout means nothing lower can arbitrary so
339572ff6f6SMatthew Dillon * long as there is traffic activity on this queue (frames,
340572ff6f6SMatthew Dillon * backoff, etc).
341572ff6f6SMatthew Dillon */
342572ff6f6SMatthew Dillon HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
343572ff6f6SMatthew Dillon HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
344572ff6f6SMatthew Dillon
345572ff6f6SMatthew Dillon HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
346572ff6f6SMatthew Dillon HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */
347572ff6f6SMatthew Dillon } HAL_TX_QUEUE_FLAGS;
348572ff6f6SMatthew Dillon
349572ff6f6SMatthew Dillon typedef struct {
350572ff6f6SMatthew Dillon uint32_t tqi_ver; /* hal TXQ version */
351572ff6f6SMatthew Dillon HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
352572ff6f6SMatthew Dillon HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
353572ff6f6SMatthew Dillon uint32_t tqi_priority; /* (not used) */
354572ff6f6SMatthew Dillon uint32_t tqi_aifs; /* aifs */
355572ff6f6SMatthew Dillon uint32_t tqi_cwmin; /* cwMin */
356572ff6f6SMatthew Dillon uint32_t tqi_cwmax; /* cwMax */
357572ff6f6SMatthew Dillon uint16_t tqi_shretry; /* rts retry limit */
358572ff6f6SMatthew Dillon uint16_t tqi_lgretry; /* long retry limit (not used)*/
359572ff6f6SMatthew Dillon uint32_t tqi_cbrPeriod; /* CBR period (us) */
360572ff6f6SMatthew Dillon uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */
361572ff6f6SMatthew Dillon uint32_t tqi_burstTime; /* max burst duration (us) */
362572ff6f6SMatthew Dillon uint32_t tqi_readyTime; /* frame schedule time (us) */
363572ff6f6SMatthew Dillon uint32_t tqi_compBuf; /* comp buffer phys addr */
364572ff6f6SMatthew Dillon } HAL_TXQ_INFO;
365572ff6f6SMatthew Dillon
366572ff6f6SMatthew Dillon #define HAL_TQI_NONVAL 0xffff
367572ff6f6SMatthew Dillon
368572ff6f6SMatthew Dillon /* token to use for aifs, cwmin, cwmax */
369572ff6f6SMatthew Dillon #define HAL_TXQ_USEDEFAULT ((uint32_t) -1)
370572ff6f6SMatthew Dillon
371572ff6f6SMatthew Dillon /* compression definitions */
372572ff6f6SMatthew Dillon #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */
373572ff6f6SMatthew Dillon #define HAL_COMP_BUF_ALIGN_SIZE 512
374572ff6f6SMatthew Dillon
375572ff6f6SMatthew Dillon /*
376572ff6f6SMatthew Dillon * Transmit packet types. This belongs in ah_desc.h, but
377572ff6f6SMatthew Dillon * is here so we can give a proper type to various parameters
378572ff6f6SMatthew Dillon * (and not require everyone include the file).
379572ff6f6SMatthew Dillon *
380572ff6f6SMatthew Dillon * NB: These values are intentionally assigned for
381572ff6f6SMatthew Dillon * direct use when setting up h/w descriptors.
382572ff6f6SMatthew Dillon */
383572ff6f6SMatthew Dillon typedef enum {
384572ff6f6SMatthew Dillon HAL_PKT_TYPE_NORMAL = 0,
385572ff6f6SMatthew Dillon HAL_PKT_TYPE_ATIM = 1,
386572ff6f6SMatthew Dillon HAL_PKT_TYPE_PSPOLL = 2,
387572ff6f6SMatthew Dillon HAL_PKT_TYPE_BEACON = 3,
388572ff6f6SMatthew Dillon HAL_PKT_TYPE_PROBE_RESP = 4,
389572ff6f6SMatthew Dillon HAL_PKT_TYPE_CHIRP = 5,
390572ff6f6SMatthew Dillon HAL_PKT_TYPE_GRP_POLL = 6,
391572ff6f6SMatthew Dillon HAL_PKT_TYPE_AMPDU = 7,
392572ff6f6SMatthew Dillon } HAL_PKT_TYPE;
393572ff6f6SMatthew Dillon
394572ff6f6SMatthew Dillon /* Rx Filter Frame Types */
395572ff6f6SMatthew Dillon typedef enum {
396572ff6f6SMatthew Dillon /*
397572ff6f6SMatthew Dillon * These bits correspond to AR_RX_FILTER for all chips.
398572ff6f6SMatthew Dillon * Not all bits are supported by all chips.
399572ff6f6SMatthew Dillon */
400572ff6f6SMatthew Dillon HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
401572ff6f6SMatthew Dillon HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
402572ff6f6SMatthew Dillon HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
403572ff6f6SMatthew Dillon HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
404572ff6f6SMatthew Dillon HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
405572ff6f6SMatthew Dillon HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
406572ff6f6SMatthew Dillon HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
407572ff6f6SMatthew Dillon HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
408d98a0bcfSMatthew Dillon HAL_RX_FILTER_MYBEACON = 0x00000200, /* Filter beacons other than mine */
409572ff6f6SMatthew Dillon HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
410572ff6f6SMatthew Dillon HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */
411572ff6f6SMatthew Dillon HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */
412572ff6f6SMatthew Dillon HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */
413572ff6f6SMatthew Dillon HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
414572ff6f6SMatthew Dillon /* Allow all mcast/bcast frames */
415572ff6f6SMatthew Dillon
416572ff6f6SMatthew Dillon /*
417*b14ca477SMatthew Dillon * Magic RX filter flags that aren't targeting hardware bits
418572ff6f6SMatthew Dillon * but instead the HAL sets individual bits - eg PHYERR will result
419572ff6f6SMatthew Dillon * in OFDM/CCK timing error frames being received.
420572ff6f6SMatthew Dillon */
421572ff6f6SMatthew Dillon HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */
422572ff6f6SMatthew Dillon } HAL_RX_FILTER;
423572ff6f6SMatthew Dillon
424572ff6f6SMatthew Dillon typedef enum {
425572ff6f6SMatthew Dillon HAL_PM_AWAKE = 0,
426572ff6f6SMatthew Dillon HAL_PM_FULL_SLEEP = 1,
427572ff6f6SMatthew Dillon HAL_PM_NETWORK_SLEEP = 2,
428572ff6f6SMatthew Dillon HAL_PM_UNDEFINED = 3
429572ff6f6SMatthew Dillon } HAL_POWER_MODE;
430572ff6f6SMatthew Dillon
431572ff6f6SMatthew Dillon /*
432572ff6f6SMatthew Dillon * Enterprise mode flags
433572ff6f6SMatthew Dillon */
434572ff6f6SMatthew Dillon #define AH_ENT_DUAL_BAND_DISABLE 0x00000001
435572ff6f6SMatthew Dillon #define AH_ENT_CHAIN2_DISABLE 0x00000002
436572ff6f6SMatthew Dillon #define AH_ENT_5MHZ_DISABLE 0x00000004
437572ff6f6SMatthew Dillon #define AH_ENT_10MHZ_DISABLE 0x00000008
438572ff6f6SMatthew Dillon #define AH_ENT_49GHZ_DISABLE 0x00000010
439572ff6f6SMatthew Dillon #define AH_ENT_LOOPBACK_DISABLE 0x00000020
440572ff6f6SMatthew Dillon #define AH_ENT_TPC_PERF_DISABLE 0x00000040
441572ff6f6SMatthew Dillon #define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080
442572ff6f6SMatthew Dillon #define AH_ENT_SPECTRAL_PRECISION 0x00000300
443572ff6f6SMatthew Dillon #define AH_ENT_SPECTRAL_PRECISION_S 8
444572ff6f6SMatthew Dillon #define AH_ENT_RTSCTS_DELIM_WAR 0x00010000
445572ff6f6SMatthew Dillon
446572ff6f6SMatthew Dillon #define AH_FIRST_DESC_NDELIMS 60
447572ff6f6SMatthew Dillon
448572ff6f6SMatthew Dillon /*
449572ff6f6SMatthew Dillon * NOTE WELL:
450572ff6f6SMatthew Dillon * These are mapped to take advantage of the common locations for many of
451572ff6f6SMatthew Dillon * the bits on all of the currently supported MAC chips. This is to make
452572ff6f6SMatthew Dillon * the ISR as efficient as possible, while still abstracting HW differences.
453572ff6f6SMatthew Dillon * When new hardware breaks this commonality this enumerated type, as well
454572ff6f6SMatthew Dillon * as the HAL functions using it, must be modified. All values are directly
455572ff6f6SMatthew Dillon * mapped unless commented otherwise.
456572ff6f6SMatthew Dillon */
457572ff6f6SMatthew Dillon typedef enum {
458572ff6f6SMatthew Dillon HAL_INT_RX = 0x00000001, /* Non-common mapping */
459572ff6f6SMatthew Dillon HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */
460572ff6f6SMatthew Dillon HAL_INT_RXERR = 0x00000004,
461572ff6f6SMatthew Dillon HAL_INT_RXHP = 0x00000001, /* EDMA */
462572ff6f6SMatthew Dillon HAL_INT_RXLP = 0x00000002, /* EDMA */
463572ff6f6SMatthew Dillon HAL_INT_RXNOFRM = 0x00000008,
464572ff6f6SMatthew Dillon HAL_INT_RXEOL = 0x00000010,
465572ff6f6SMatthew Dillon HAL_INT_RXORN = 0x00000020,
466572ff6f6SMatthew Dillon HAL_INT_TX = 0x00000040, /* Non-common mapping */
467572ff6f6SMatthew Dillon HAL_INT_TXDESC = 0x00000080,
468572ff6f6SMatthew Dillon HAL_INT_TIM_TIMER= 0x00000100,
469572ff6f6SMatthew Dillon HAL_INT_MCI = 0x00000200,
470572ff6f6SMatthew Dillon HAL_INT_BBPANIC = 0x00000400,
471572ff6f6SMatthew Dillon HAL_INT_TXURN = 0x00000800,
472572ff6f6SMatthew Dillon HAL_INT_MIB = 0x00001000,
473572ff6f6SMatthew Dillon HAL_INT_RXPHY = 0x00004000,
474572ff6f6SMatthew Dillon HAL_INT_RXKCM = 0x00008000,
475572ff6f6SMatthew Dillon HAL_INT_SWBA = 0x00010000,
476572ff6f6SMatthew Dillon HAL_INT_BRSSI = 0x00020000,
477572ff6f6SMatthew Dillon HAL_INT_BMISS = 0x00040000,
478572ff6f6SMatthew Dillon HAL_INT_BNR = 0x00100000,
479572ff6f6SMatthew Dillon HAL_INT_TIM = 0x00200000, /* Non-common mapping */
480572ff6f6SMatthew Dillon HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
481572ff6f6SMatthew Dillon HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
482572ff6f6SMatthew Dillon HAL_INT_GPIO = 0x01000000,
483572ff6f6SMatthew Dillon HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
484572ff6f6SMatthew Dillon HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
485572ff6f6SMatthew Dillon HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
486572ff6f6SMatthew Dillon /* Atheros ref driver has a generic timer interrupt now..*/
487572ff6f6SMatthew Dillon HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */
488572ff6f6SMatthew Dillon HAL_INT_CST = 0x10000000, /* Non-common mapping */
489572ff6f6SMatthew Dillon HAL_INT_GTT = 0x20000000, /* Non-common mapping */
490572ff6f6SMatthew Dillon HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
491572ff6f6SMatthew Dillon #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */
492572ff6f6SMatthew Dillon HAL_INT_BMISC = HAL_INT_TIM
493572ff6f6SMatthew Dillon | HAL_INT_DTIM
494572ff6f6SMatthew Dillon | HAL_INT_DTIMSYNC
495572ff6f6SMatthew Dillon | HAL_INT_CABEND
496572ff6f6SMatthew Dillon | HAL_INT_TBTT,
497572ff6f6SMatthew Dillon
498572ff6f6SMatthew Dillon /* Interrupt bits that map directly to ISR/IMR bits */
499572ff6f6SMatthew Dillon HAL_INT_COMMON = HAL_INT_RXNOFRM
500572ff6f6SMatthew Dillon | HAL_INT_RXDESC
501572ff6f6SMatthew Dillon | HAL_INT_RXEOL
502572ff6f6SMatthew Dillon | HAL_INT_RXORN
503572ff6f6SMatthew Dillon | HAL_INT_TXDESC
504572ff6f6SMatthew Dillon | HAL_INT_TXURN
505572ff6f6SMatthew Dillon | HAL_INT_MIB
506572ff6f6SMatthew Dillon | HAL_INT_RXPHY
507572ff6f6SMatthew Dillon | HAL_INT_RXKCM
508572ff6f6SMatthew Dillon | HAL_INT_SWBA
509572ff6f6SMatthew Dillon | HAL_INT_BMISS
510572ff6f6SMatthew Dillon | HAL_INT_BRSSI
511572ff6f6SMatthew Dillon | HAL_INT_BNR
512572ff6f6SMatthew Dillon | HAL_INT_GPIO,
513572ff6f6SMatthew Dillon } HAL_INT;
514572ff6f6SMatthew Dillon
515572ff6f6SMatthew Dillon /*
516572ff6f6SMatthew Dillon * MSI vector assignments
517572ff6f6SMatthew Dillon */
518572ff6f6SMatthew Dillon typedef enum {
519572ff6f6SMatthew Dillon HAL_MSIVEC_MISC = 0,
520572ff6f6SMatthew Dillon HAL_MSIVEC_TX = 1,
521572ff6f6SMatthew Dillon HAL_MSIVEC_RXLP = 2,
522572ff6f6SMatthew Dillon HAL_MSIVEC_RXHP = 3,
523572ff6f6SMatthew Dillon } HAL_MSIVEC;
524572ff6f6SMatthew Dillon
525572ff6f6SMatthew Dillon typedef enum {
526572ff6f6SMatthew Dillon HAL_INT_LINE = 0,
527572ff6f6SMatthew Dillon HAL_INT_MSI = 1,
528572ff6f6SMatthew Dillon } HAL_INT_TYPE;
529572ff6f6SMatthew Dillon
530572ff6f6SMatthew Dillon /* For interrupt mitigation registers */
531572ff6f6SMatthew Dillon typedef enum {
532572ff6f6SMatthew Dillon HAL_INT_RX_FIRSTPKT=0,
533572ff6f6SMatthew Dillon HAL_INT_RX_LASTPKT,
534572ff6f6SMatthew Dillon HAL_INT_TX_FIRSTPKT,
535572ff6f6SMatthew Dillon HAL_INT_TX_LASTPKT,
536572ff6f6SMatthew Dillon HAL_INT_THRESHOLD
537572ff6f6SMatthew Dillon } HAL_INT_MITIGATION;
538572ff6f6SMatthew Dillon
539572ff6f6SMatthew Dillon /* XXX this is duplicate information! */
540572ff6f6SMatthew Dillon typedef struct {
541572ff6f6SMatthew Dillon u_int32_t cyclecnt_diff; /* delta cycle count */
542572ff6f6SMatthew Dillon u_int32_t rxclr_cnt; /* rx clear count */
543*b14ca477SMatthew Dillon u_int32_t extrxclr_cnt; /* ext chan rx clear count */
544572ff6f6SMatthew Dillon u_int32_t txframecnt_diff; /* delta tx frame count */
545572ff6f6SMatthew Dillon u_int32_t rxframecnt_diff; /* delta rx frame count */
546572ff6f6SMatthew Dillon u_int32_t listen_time; /* listen time in msec - time for which ch is free */
547572ff6f6SMatthew Dillon u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */
548572ff6f6SMatthew Dillon u_int32_t cckphyerr_cnt; /* CCK err count since last reset */
549572ff6f6SMatthew Dillon u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */
550572ff6f6SMatthew Dillon HAL_BOOL valid; /* if the stats are valid*/
551572ff6f6SMatthew Dillon } HAL_ANISTATS;
552572ff6f6SMatthew Dillon
553572ff6f6SMatthew Dillon typedef struct {
554572ff6f6SMatthew Dillon u_int8_t txctl_offset;
555572ff6f6SMatthew Dillon u_int8_t txctl_numwords;
556572ff6f6SMatthew Dillon u_int8_t txstatus_offset;
557572ff6f6SMatthew Dillon u_int8_t txstatus_numwords;
558572ff6f6SMatthew Dillon
559572ff6f6SMatthew Dillon u_int8_t rxctl_offset;
560572ff6f6SMatthew Dillon u_int8_t rxctl_numwords;
561572ff6f6SMatthew Dillon u_int8_t rxstatus_offset;
562572ff6f6SMatthew Dillon u_int8_t rxstatus_numwords;
563572ff6f6SMatthew Dillon
564572ff6f6SMatthew Dillon u_int8_t macRevision;
565572ff6f6SMatthew Dillon } HAL_DESC_INFO;
566572ff6f6SMatthew Dillon
567572ff6f6SMatthew Dillon typedef enum {
568572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0,
569572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1,
570572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2,
571572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3,
572572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4,
573572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5,
574572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6,
575572ff6f6SMatthew Dillon
576572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA,
577572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK,
578572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA,
579572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK,
580572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX,
581572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX,
582572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX,
583572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX,
584572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE,
585572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA,
586572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0,
587572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1,
588572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2,
589572ff6f6SMatthew Dillon HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES
590572ff6f6SMatthew Dillon } HAL_GPIO_MUX_TYPE;
591572ff6f6SMatthew Dillon
592572ff6f6SMatthew Dillon typedef enum {
593572ff6f6SMatthew Dillon HAL_GPIO_INTR_LOW = 0,
594572ff6f6SMatthew Dillon HAL_GPIO_INTR_HIGH = 1,
595572ff6f6SMatthew Dillon HAL_GPIO_INTR_DISABLE = 2
596572ff6f6SMatthew Dillon } HAL_GPIO_INTR_TYPE;
597572ff6f6SMatthew Dillon
598572ff6f6SMatthew Dillon typedef struct halCounters {
599572ff6f6SMatthew Dillon u_int32_t tx_frame_count;
600572ff6f6SMatthew Dillon u_int32_t rx_frame_count;
601572ff6f6SMatthew Dillon u_int32_t rx_clear_count;
602572ff6f6SMatthew Dillon u_int32_t cycle_count;
603572ff6f6SMatthew Dillon u_int8_t is_rx_active; // true (1) or false (0)
604572ff6f6SMatthew Dillon u_int8_t is_tx_active; // true (1) or false (0)
605572ff6f6SMatthew Dillon } HAL_COUNTERS;
606572ff6f6SMatthew Dillon
607572ff6f6SMatthew Dillon typedef enum {
608572ff6f6SMatthew Dillon HAL_RFGAIN_INACTIVE = 0,
609572ff6f6SMatthew Dillon HAL_RFGAIN_READ_REQUESTED = 1,
610572ff6f6SMatthew Dillon HAL_RFGAIN_NEED_CHANGE = 2
611572ff6f6SMatthew Dillon } HAL_RFGAIN;
612572ff6f6SMatthew Dillon
613572ff6f6SMatthew Dillon typedef uint16_t HAL_CTRY_CODE; /* country code */
614572ff6f6SMatthew Dillon typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */
615572ff6f6SMatthew Dillon
616572ff6f6SMatthew Dillon #define HAL_ANTENNA_MIN_MODE 0
617572ff6f6SMatthew Dillon #define HAL_ANTENNA_FIXED_A 1
618572ff6f6SMatthew Dillon #define HAL_ANTENNA_FIXED_B 2
619572ff6f6SMatthew Dillon #define HAL_ANTENNA_MAX_MODE 3
620572ff6f6SMatthew Dillon
621572ff6f6SMatthew Dillon typedef struct {
622572ff6f6SMatthew Dillon uint32_t ackrcv_bad;
623572ff6f6SMatthew Dillon uint32_t rts_bad;
624572ff6f6SMatthew Dillon uint32_t rts_good;
625572ff6f6SMatthew Dillon uint32_t fcs_bad;
626572ff6f6SMatthew Dillon uint32_t beacons;
627572ff6f6SMatthew Dillon } HAL_MIB_STATS;
628572ff6f6SMatthew Dillon
629572ff6f6SMatthew Dillon /*
630572ff6f6SMatthew Dillon * These bits represent what's in ah_currentRDext.
631572ff6f6SMatthew Dillon */
632572ff6f6SMatthew Dillon typedef enum {
633572ff6f6SMatthew Dillon REG_EXT_FCC_MIDBAND = 0,
634572ff6f6SMatthew Dillon REG_EXT_JAPAN_MIDBAND = 1,
635572ff6f6SMatthew Dillon REG_EXT_FCC_DFS_HT40 = 2,
636572ff6f6SMatthew Dillon REG_EXT_JAPAN_NONDFS_HT40 = 3,
637572ff6f6SMatthew Dillon REG_EXT_JAPAN_DFS_HT40 = 4
638572ff6f6SMatthew Dillon } REG_EXT_BITMAP;
639572ff6f6SMatthew Dillon
640572ff6f6SMatthew Dillon enum {
641572ff6f6SMatthew Dillon HAL_MODE_11A = 0x001, /* 11a channels */
642572ff6f6SMatthew Dillon HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
643572ff6f6SMatthew Dillon HAL_MODE_11B = 0x004, /* 11b channels */
644572ff6f6SMatthew Dillon HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
645572ff6f6SMatthew Dillon #ifdef notdef
646572ff6f6SMatthew Dillon HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
647572ff6f6SMatthew Dillon #else
648572ff6f6SMatthew Dillon HAL_MODE_11G = 0x008, /* XXX historical */
649572ff6f6SMatthew Dillon #endif
650572ff6f6SMatthew Dillon HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
651572ff6f6SMatthew Dillon HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
652572ff6f6SMatthew Dillon HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */
653572ff6f6SMatthew Dillon HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */
654572ff6f6SMatthew Dillon HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */
655572ff6f6SMatthew Dillon HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */
656572ff6f6SMatthew Dillon HAL_MODE_11NG_HT20 = 0x008000,
657572ff6f6SMatthew Dillon HAL_MODE_11NA_HT20 = 0x010000,
658572ff6f6SMatthew Dillon HAL_MODE_11NG_HT40PLUS = 0x020000,
659572ff6f6SMatthew Dillon HAL_MODE_11NG_HT40MINUS = 0x040000,
660572ff6f6SMatthew Dillon HAL_MODE_11NA_HT40PLUS = 0x080000,
661572ff6f6SMatthew Dillon HAL_MODE_11NA_HT40MINUS = 0x100000,
662572ff6f6SMatthew Dillon HAL_MODE_ALL = 0xffffff
663572ff6f6SMatthew Dillon };
664572ff6f6SMatthew Dillon
665572ff6f6SMatthew Dillon typedef struct {
666572ff6f6SMatthew Dillon int rateCount; /* NB: for proper padding */
667572ff6f6SMatthew Dillon uint8_t rateCodeToIndex[256]; /* back mapping */
668572ff6f6SMatthew Dillon struct {
669572ff6f6SMatthew Dillon uint8_t valid; /* valid for rate control use */
670572ff6f6SMatthew Dillon uint8_t phy; /* CCK/OFDM/XR */
671572ff6f6SMatthew Dillon uint32_t rateKbps; /* transfer rate in kbs */
672572ff6f6SMatthew Dillon uint8_t rateCode; /* rate for h/w descriptors */
673572ff6f6SMatthew Dillon uint8_t shortPreamble; /* mask for enabling short
674572ff6f6SMatthew Dillon * preamble in CCK rate code */
675572ff6f6SMatthew Dillon uint8_t dot11Rate; /* value for supported rates
676572ff6f6SMatthew Dillon * info element of MLME */
677572ff6f6SMatthew Dillon uint8_t controlRate; /* index of next lower basic
678572ff6f6SMatthew Dillon * rate; used for dur. calcs */
679572ff6f6SMatthew Dillon uint16_t lpAckDuration; /* long preamble ACK duration */
680572ff6f6SMatthew Dillon uint16_t spAckDuration; /* short preamble ACK duration*/
681572ff6f6SMatthew Dillon } info[64];
682572ff6f6SMatthew Dillon } HAL_RATE_TABLE;
683572ff6f6SMatthew Dillon
684572ff6f6SMatthew Dillon typedef struct {
685572ff6f6SMatthew Dillon u_int rs_count; /* number of valid entries */
686572ff6f6SMatthew Dillon uint8_t rs_rates[64]; /* rates */
687572ff6f6SMatthew Dillon } HAL_RATE_SET;
688572ff6f6SMatthew Dillon
689572ff6f6SMatthew Dillon /*
690572ff6f6SMatthew Dillon * 802.11n specific structures and enums
691572ff6f6SMatthew Dillon */
692572ff6f6SMatthew Dillon typedef enum {
693572ff6f6SMatthew Dillon HAL_CHAINTYPE_TX = 1, /* Tx chain type */
694572ff6f6SMatthew Dillon HAL_CHAINTYPE_RX = 2, /* RX chain type */
695572ff6f6SMatthew Dillon } HAL_CHAIN_TYPE;
696572ff6f6SMatthew Dillon
697572ff6f6SMatthew Dillon typedef struct {
698572ff6f6SMatthew Dillon u_int Tries;
699572ff6f6SMatthew Dillon u_int Rate; /* hardware rate code */
700572ff6f6SMatthew Dillon u_int RateIndex; /* rate series table index */
701572ff6f6SMatthew Dillon u_int PktDuration;
702572ff6f6SMatthew Dillon u_int ChSel;
703572ff6f6SMatthew Dillon u_int RateFlags;
704572ff6f6SMatthew Dillon #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
705572ff6f6SMatthew Dillon #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
706572ff6f6SMatthew Dillon #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
707572ff6f6SMatthew Dillon #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */
708572ff6f6SMatthew Dillon u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */
709572ff6f6SMatthew Dillon } HAL_11N_RATE_SERIES;
710572ff6f6SMatthew Dillon
711572ff6f6SMatthew Dillon typedef enum {
712572ff6f6SMatthew Dillon HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
713572ff6f6SMatthew Dillon HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */
714572ff6f6SMatthew Dillon } HAL_HT_MACMODE;
715572ff6f6SMatthew Dillon
716572ff6f6SMatthew Dillon typedef enum {
717572ff6f6SMatthew Dillon HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
718572ff6f6SMatthew Dillon HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */
719572ff6f6SMatthew Dillon } HAL_HT_PHYMODE;
720572ff6f6SMatthew Dillon
721572ff6f6SMatthew Dillon typedef enum {
722572ff6f6SMatthew Dillon HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
723572ff6f6SMatthew Dillon HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */
724572ff6f6SMatthew Dillon } HAL_HT_EXTPROTSPACING;
725572ff6f6SMatthew Dillon
726572ff6f6SMatthew Dillon
727572ff6f6SMatthew Dillon typedef enum {
728572ff6f6SMatthew Dillon HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
729572ff6f6SMatthew Dillon HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
730572ff6f6SMatthew Dillon } HAL_HT_RXCLEAR;
731572ff6f6SMatthew Dillon
732572ff6f6SMatthew Dillon typedef enum {
733572ff6f6SMatthew Dillon HAL_FREQ_BAND_5GHZ = 0,
734572ff6f6SMatthew Dillon HAL_FREQ_BAND_2GHZ = 1,
735572ff6f6SMatthew Dillon } HAL_FREQ_BAND;
736572ff6f6SMatthew Dillon
737572ff6f6SMatthew Dillon /*
738572ff6f6SMatthew Dillon * Antenna switch control. By default antenna selection
739572ff6f6SMatthew Dillon * enables multiple (2) antenna use. To force use of the
740572ff6f6SMatthew Dillon * A or B antenna only specify a fixed setting. Fixing
741572ff6f6SMatthew Dillon * the antenna will also disable any diversity support.
742572ff6f6SMatthew Dillon */
743572ff6f6SMatthew Dillon typedef enum {
744572ff6f6SMatthew Dillon HAL_ANT_VARIABLE = 0, /* variable by programming */
745572ff6f6SMatthew Dillon HAL_ANT_FIXED_A = 1, /* fixed antenna A */
746572ff6f6SMatthew Dillon HAL_ANT_FIXED_B = 2, /* fixed antenna B */
747572ff6f6SMatthew Dillon } HAL_ANT_SETTING;
748572ff6f6SMatthew Dillon
749572ff6f6SMatthew Dillon typedef enum {
750572ff6f6SMatthew Dillon HAL_M_STA = 1, /* infrastructure station */
751572ff6f6SMatthew Dillon HAL_M_IBSS = 0, /* IBSS (adhoc) station */
752572ff6f6SMatthew Dillon HAL_M_HOSTAP = 6, /* Software Access Point */
753572ff6f6SMatthew Dillon HAL_M_MONITOR = 8 /* Monitor mode */
754572ff6f6SMatthew Dillon } HAL_OPMODE;
755572ff6f6SMatthew Dillon
756*b14ca477SMatthew Dillon typedef enum {
757*b14ca477SMatthew Dillon HAL_RESET_NORMAL = 0, /* Do normal reset */
758*b14ca477SMatthew Dillon HAL_RESET_BBPANIC = 1, /* Reset because of BB panic */
759*b14ca477SMatthew Dillon HAL_RESET_FORCE_COLD = 2, /* Force full reset */
760*b14ca477SMatthew Dillon } HAL_RESET_TYPE;
761*b14ca477SMatthew Dillon
762572ff6f6SMatthew Dillon typedef struct {
763572ff6f6SMatthew Dillon uint8_t kv_type; /* one of HAL_CIPHER */
764572ff6f6SMatthew Dillon uint8_t kv_apsd; /* Mask for APSD enabled ACs */
765572ff6f6SMatthew Dillon uint16_t kv_len; /* length in bits */
766572ff6f6SMatthew Dillon uint8_t kv_val[16]; /* enough for 128-bit keys */
767572ff6f6SMatthew Dillon uint8_t kv_mic[8]; /* TKIP MIC key */
768572ff6f6SMatthew Dillon uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
769572ff6f6SMatthew Dillon } HAL_KEYVAL;
770572ff6f6SMatthew Dillon
771572ff6f6SMatthew Dillon /*
772572ff6f6SMatthew Dillon * This is the TX descriptor field which marks the key padding requirement.
773572ff6f6SMatthew Dillon * The naming is unfortunately unclear.
774572ff6f6SMatthew Dillon */
775572ff6f6SMatthew Dillon #define AH_KEYTYPE_MASK 0x0F
776572ff6f6SMatthew Dillon typedef enum {
777572ff6f6SMatthew Dillon HAL_KEY_TYPE_CLEAR,
778572ff6f6SMatthew Dillon HAL_KEY_TYPE_WEP,
779572ff6f6SMatthew Dillon HAL_KEY_TYPE_AES,
780572ff6f6SMatthew Dillon HAL_KEY_TYPE_TKIP,
781572ff6f6SMatthew Dillon } HAL_KEY_TYPE;
782572ff6f6SMatthew Dillon
783572ff6f6SMatthew Dillon typedef enum {
784572ff6f6SMatthew Dillon HAL_CIPHER_WEP = 0,
785572ff6f6SMatthew Dillon HAL_CIPHER_AES_OCB = 1,
786572ff6f6SMatthew Dillon HAL_CIPHER_AES_CCM = 2,
787572ff6f6SMatthew Dillon HAL_CIPHER_CKIP = 3,
788572ff6f6SMatthew Dillon HAL_CIPHER_TKIP = 4,
789572ff6f6SMatthew Dillon HAL_CIPHER_CLR = 5, /* no encryption */
790572ff6f6SMatthew Dillon
791572ff6f6SMatthew Dillon HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
792572ff6f6SMatthew Dillon } HAL_CIPHER;
793572ff6f6SMatthew Dillon
794572ff6f6SMatthew Dillon enum {
795572ff6f6SMatthew Dillon HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */
796572ff6f6SMatthew Dillon HAL_SLOT_TIME_9 = 9,
797572ff6f6SMatthew Dillon HAL_SLOT_TIME_20 = 20,
798572ff6f6SMatthew Dillon };
799572ff6f6SMatthew Dillon
800572ff6f6SMatthew Dillon /*
801572ff6f6SMatthew Dillon * Per-station beacon timer state. Note that the specified
802572ff6f6SMatthew Dillon * beacon interval (given in TU's) can also include flags
803572ff6f6SMatthew Dillon * to force a TSF reset and to enable the beacon xmit logic.
804572ff6f6SMatthew Dillon * If bs_cfpmaxduration is non-zero the hardware is setup to
805572ff6f6SMatthew Dillon * coexist with a PCF-capable AP.
806572ff6f6SMatthew Dillon */
807572ff6f6SMatthew Dillon typedef struct {
808572ff6f6SMatthew Dillon uint32_t bs_nexttbtt; /* next beacon in TU */
809572ff6f6SMatthew Dillon uint32_t bs_nextdtim; /* next DTIM in TU */
810572ff6f6SMatthew Dillon uint32_t bs_intval; /* beacon interval+flags */
811572ff6f6SMatthew Dillon /*
812572ff6f6SMatthew Dillon * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF
813572ff6f6SMatthew Dillon * are all 1:1 correspondances with the pre-11n chip AR_BEACON
814572ff6f6SMatthew Dillon * register.
815572ff6f6SMatthew Dillon */
816572ff6f6SMatthew Dillon #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
817572ff6f6SMatthew Dillon #define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */
818572ff6f6SMatthew Dillon #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
819572ff6f6SMatthew Dillon #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
820572ff6f6SMatthew Dillon #define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */
821572ff6f6SMatthew Dillon uint32_t bs_dtimperiod;
822572ff6f6SMatthew Dillon uint16_t bs_cfpperiod; /* CFP period in TU */
823572ff6f6SMatthew Dillon uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
824572ff6f6SMatthew Dillon uint32_t bs_cfpnext; /* next CFP in TU */
825572ff6f6SMatthew Dillon uint16_t bs_timoffset; /* byte offset to TIM bitmap */
826572ff6f6SMatthew Dillon uint16_t bs_bmissthreshold; /* beacon miss threshold */
827572ff6f6SMatthew Dillon uint32_t bs_sleepduration; /* max sleep duration */
828572ff6f6SMatthew Dillon uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */
829572ff6f6SMatthew Dillon } HAL_BEACON_STATE;
830572ff6f6SMatthew Dillon
831572ff6f6SMatthew Dillon /*
832572ff6f6SMatthew Dillon * Like HAL_BEACON_STATE but for non-station mode setup.
833572ff6f6SMatthew Dillon * NB: see above flag definitions for bt_intval.
834572ff6f6SMatthew Dillon */
835572ff6f6SMatthew Dillon typedef struct {
836572ff6f6SMatthew Dillon uint32_t bt_intval; /* beacon interval+flags */
837572ff6f6SMatthew Dillon uint32_t bt_nexttbtt; /* next beacon in TU */
838572ff6f6SMatthew Dillon uint32_t bt_nextatim; /* next ATIM in TU */
839572ff6f6SMatthew Dillon uint32_t bt_nextdba; /* next DBA in 1/8th TU */
840572ff6f6SMatthew Dillon uint32_t bt_nextswba; /* next SWBA in 1/8th TU */
841572ff6f6SMatthew Dillon uint32_t bt_flags; /* timer enables */
842572ff6f6SMatthew Dillon #define HAL_BEACON_TBTT_EN 0x00000001
843572ff6f6SMatthew Dillon #define HAL_BEACON_DBA_EN 0x00000002
844572ff6f6SMatthew Dillon #define HAL_BEACON_SWBA_EN 0x00000004
845572ff6f6SMatthew Dillon } HAL_BEACON_TIMERS;
846572ff6f6SMatthew Dillon
847572ff6f6SMatthew Dillon /*
848572ff6f6SMatthew Dillon * Per-node statistics maintained by the driver for use in
849572ff6f6SMatthew Dillon * optimizing signal quality and other operational aspects.
850572ff6f6SMatthew Dillon */
851572ff6f6SMatthew Dillon typedef struct {
852572ff6f6SMatthew Dillon uint32_t ns_avgbrssi; /* average beacon rssi */
853572ff6f6SMatthew Dillon uint32_t ns_avgrssi; /* average data rssi */
854572ff6f6SMatthew Dillon uint32_t ns_avgtxrssi; /* average tx rssi */
855572ff6f6SMatthew Dillon } HAL_NODE_STATS;
856572ff6f6SMatthew Dillon
857572ff6f6SMatthew Dillon #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
858572ff6f6SMatthew Dillon
859*b14ca477SMatthew Dillon /*
860*b14ca477SMatthew Dillon * This is the ANI state and MIB stats.
861*b14ca477SMatthew Dillon *
862*b14ca477SMatthew Dillon * It's used by the HAL modules to keep state /and/ by the debug ioctl
863*b14ca477SMatthew Dillon * to fetch ANI information.
864*b14ca477SMatthew Dillon */
865*b14ca477SMatthew Dillon typedef struct {
866*b14ca477SMatthew Dillon uint32_t ast_ani_niup; /* ANI increased noise immunity */
867*b14ca477SMatthew Dillon uint32_t ast_ani_nidown; /* ANI decreased noise immunity */
868*b14ca477SMatthew Dillon uint32_t ast_ani_spurup; /* ANI increased spur immunity */
869*b14ca477SMatthew Dillon uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */
870*b14ca477SMatthew Dillon uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */
871*b14ca477SMatthew Dillon uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
872*b14ca477SMatthew Dillon uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
873*b14ca477SMatthew Dillon uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
874*b14ca477SMatthew Dillon uint32_t ast_ani_stepup; /* ANI increased first step level */
875*b14ca477SMatthew Dillon uint32_t ast_ani_stepdown;/* ANI decreased first step level */
876*b14ca477SMatthew Dillon uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
877*b14ca477SMatthew Dillon uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */
878*b14ca477SMatthew Dillon uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
879*b14ca477SMatthew Dillon uint32_t ast_ani_lzero; /* ANI listen time forced to zero */
880*b14ca477SMatthew Dillon uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
881*b14ca477SMatthew Dillon HAL_MIB_STATS ast_mibstats; /* MIB counter stats */
882*b14ca477SMatthew Dillon HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */
883*b14ca477SMatthew Dillon } HAL_ANI_STATS;
884*b14ca477SMatthew Dillon
885*b14ca477SMatthew Dillon typedef struct {
886*b14ca477SMatthew Dillon uint8_t noiseImmunityLevel;
887*b14ca477SMatthew Dillon uint8_t spurImmunityLevel;
888*b14ca477SMatthew Dillon uint8_t firstepLevel;
889*b14ca477SMatthew Dillon uint8_t ofdmWeakSigDetectOff;
890*b14ca477SMatthew Dillon uint8_t cckWeakSigThreshold;
891*b14ca477SMatthew Dillon uint32_t listenTime;
892*b14ca477SMatthew Dillon
893*b14ca477SMatthew Dillon /* NB: intentionally ordered so data exported to user space is first */
894*b14ca477SMatthew Dillon uint32_t txFrameCount; /* Last txFrameCount */
895*b14ca477SMatthew Dillon uint32_t rxFrameCount; /* Last rx Frame count */
896*b14ca477SMatthew Dillon uint32_t cycleCount; /* Last cycleCount
897*b14ca477SMatthew Dillon (to detect wrap-around) */
898*b14ca477SMatthew Dillon uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */
899*b14ca477SMatthew Dillon uint32_t cckPhyErrCount; /* CCK err count since last reset */
900*b14ca477SMatthew Dillon } HAL_ANI_STATE;
901572ff6f6SMatthew Dillon
902572ff6f6SMatthew Dillon struct ath_desc;
903572ff6f6SMatthew Dillon struct ath_tx_status;
904572ff6f6SMatthew Dillon struct ath_rx_status;
905572ff6f6SMatthew Dillon struct ieee80211_channel;
906572ff6f6SMatthew Dillon
907572ff6f6SMatthew Dillon /*
908572ff6f6SMatthew Dillon * This is a channel survey sample entry.
909572ff6f6SMatthew Dillon *
910572ff6f6SMatthew Dillon * The AR5212 ANI routines fill these samples. The ANI code then uses it
911572ff6f6SMatthew Dillon * when calculating listen time; it is also exported via a diagnostic
912572ff6f6SMatthew Dillon * API.
913572ff6f6SMatthew Dillon */
914572ff6f6SMatthew Dillon typedef struct {
915572ff6f6SMatthew Dillon uint32_t seq_num;
916572ff6f6SMatthew Dillon uint32_t tx_busy;
917572ff6f6SMatthew Dillon uint32_t rx_busy;
918572ff6f6SMatthew Dillon uint32_t chan_busy;
919572ff6f6SMatthew Dillon uint32_t ext_chan_busy;
920572ff6f6SMatthew Dillon uint32_t cycle_count;
921572ff6f6SMatthew Dillon /* XXX TODO */
922572ff6f6SMatthew Dillon uint32_t ofdm_phyerr_count;
923572ff6f6SMatthew Dillon uint32_t cck_phyerr_count;
924572ff6f6SMatthew Dillon } HAL_SURVEY_SAMPLE;
925572ff6f6SMatthew Dillon
926572ff6f6SMatthew Dillon /*
927572ff6f6SMatthew Dillon * This provides 3.2 seconds of sample space given an
928572ff6f6SMatthew Dillon * ANI time of 1/10th of a second. This may not be enough!
929572ff6f6SMatthew Dillon */
930572ff6f6SMatthew Dillon #define CHANNEL_SURVEY_SAMPLE_COUNT 32
931572ff6f6SMatthew Dillon
932572ff6f6SMatthew Dillon typedef struct {
933572ff6f6SMatthew Dillon HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT];
934572ff6f6SMatthew Dillon uint32_t cur_sample; /* current sample in sequence */
935572ff6f6SMatthew Dillon uint32_t cur_seq; /* current sequence number */
936572ff6f6SMatthew Dillon } HAL_CHANNEL_SURVEY;
937572ff6f6SMatthew Dillon
938572ff6f6SMatthew Dillon /*
939572ff6f6SMatthew Dillon * ANI commands.
940572ff6f6SMatthew Dillon *
941572ff6f6SMatthew Dillon * These are used both internally and externally via the diagnostic
942572ff6f6SMatthew Dillon * API.
943572ff6f6SMatthew Dillon *
944572ff6f6SMatthew Dillon * Note that this is NOT the ANI commands being used via the INTMIT
945572ff6f6SMatthew Dillon * capability - that has a different mapping for some reason.
946572ff6f6SMatthew Dillon */
947572ff6f6SMatthew Dillon typedef enum {
948572ff6f6SMatthew Dillon HAL_ANI_PRESENT = 0, /* is ANI support present */
949572ff6f6SMatthew Dillon HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */
950572ff6f6SMatthew Dillon HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */
951572ff6f6SMatthew Dillon HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */
952572ff6f6SMatthew Dillon HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */
953572ff6f6SMatthew Dillon HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */
954572ff6f6SMatthew Dillon HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */
955572ff6f6SMatthew Dillon HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */
956572ff6f6SMatthew Dillon HAL_ANI_MRC_CCK = 8,
957572ff6f6SMatthew Dillon } HAL_ANI_CMD;
958572ff6f6SMatthew Dillon
959572ff6f6SMatthew Dillon #define HAL_ANI_ALL 0xffffffff
960572ff6f6SMatthew Dillon
961572ff6f6SMatthew Dillon /*
962572ff6f6SMatthew Dillon * This is the layout of the ANI INTMIT capability.
963572ff6f6SMatthew Dillon *
964572ff6f6SMatthew Dillon * Notice that the command values differ to HAL_ANI_CMD.
965572ff6f6SMatthew Dillon */
966572ff6f6SMatthew Dillon typedef enum {
967572ff6f6SMatthew Dillon HAL_CAP_INTMIT_PRESENT = 0,
968572ff6f6SMatthew Dillon HAL_CAP_INTMIT_ENABLE = 1,
969572ff6f6SMatthew Dillon HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2,
970572ff6f6SMatthew Dillon HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3,
971572ff6f6SMatthew Dillon HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4,
972572ff6f6SMatthew Dillon HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5,
973572ff6f6SMatthew Dillon HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6
974572ff6f6SMatthew Dillon } HAL_CAP_INTMIT_CMD;
975572ff6f6SMatthew Dillon
976572ff6f6SMatthew Dillon typedef struct {
977572ff6f6SMatthew Dillon int32_t pe_firpwr; /* FIR pwr out threshold */
978572ff6f6SMatthew Dillon int32_t pe_rrssi; /* Radar rssi thresh */
979572ff6f6SMatthew Dillon int32_t pe_height; /* Pulse height thresh */
980572ff6f6SMatthew Dillon int32_t pe_prssi; /* Pulse rssi thresh */
981572ff6f6SMatthew Dillon int32_t pe_inband; /* Inband thresh */
982572ff6f6SMatthew Dillon
983572ff6f6SMatthew Dillon /* The following params are only for AR5413 and later */
984572ff6f6SMatthew Dillon u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */
985572ff6f6SMatthew Dillon u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */
986572ff6f6SMatthew Dillon u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */
987572ff6f6SMatthew Dillon int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */
988572ff6f6SMatthew Dillon int32_t pe_blockradar; /*
989572ff6f6SMatthew Dillon * Enable to block radar check if pkt detect is done via OFDM
990572ff6f6SMatthew Dillon * weak signal detect or pkt is detected immediately after tx
991572ff6f6SMatthew Dillon * to rx transition
992572ff6f6SMatthew Dillon */
993572ff6f6SMatthew Dillon int32_t pe_enmaxrssi; /*
994572ff6f6SMatthew Dillon * Enable to use the max rssi instead of the last rssi during
995572ff6f6SMatthew Dillon * fine gain changes for radar detection
996572ff6f6SMatthew Dillon */
997572ff6f6SMatthew Dillon int32_t pe_extchannel; /* Enable DFS on ext channel */
998572ff6f6SMatthew Dillon int32_t pe_enabled; /* Whether radar detection is enabled */
999572ff6f6SMatthew Dillon int32_t pe_enrelpwr;
1000572ff6f6SMatthew Dillon int32_t pe_en_relstep_check;
1001572ff6f6SMatthew Dillon } HAL_PHYERR_PARAM;
1002572ff6f6SMatthew Dillon
1003572ff6f6SMatthew Dillon #define HAL_PHYERR_PARAM_NOVAL 65535
1004572ff6f6SMatthew Dillon
1005572ff6f6SMatthew Dillon typedef struct {
1006572ff6f6SMatthew Dillon u_int16_t ss_fft_period; /* Skip interval for FFT reports */
1007572ff6f6SMatthew Dillon u_int16_t ss_period; /* Spectral scan period */
1008572ff6f6SMatthew Dillon u_int16_t ss_count; /* # of reports to return from ss_active */
1009572ff6f6SMatthew Dillon u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */
1010572ff6f6SMatthew Dillon u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT threshold configuration */
1011572ff6f6SMatthew Dillon u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */
1012572ff6f6SMatthew Dillon int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */
1013572ff6f6SMatthew Dillon int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */
1014572ff6f6SMatthew Dillon int32_t ss_nf_temp_data; /* temperature data taken during nf scan */
1015572ff6f6SMatthew Dillon int ss_enabled;
1016572ff6f6SMatthew Dillon int ss_active;
1017572ff6f6SMatthew Dillon } HAL_SPECTRAL_PARAM;
1018572ff6f6SMatthew Dillon #define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF
1019572ff6f6SMatthew Dillon #define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */
1020572ff6f6SMatthew Dillon
1021572ff6f6SMatthew Dillon /*
1022572ff6f6SMatthew Dillon * DFS operating mode flags.
1023572ff6f6SMatthew Dillon */
1024572ff6f6SMatthew Dillon typedef enum {
1025572ff6f6SMatthew Dillon HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */
1026572ff6f6SMatthew Dillon HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */
1027572ff6f6SMatthew Dillon HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */
1028572ff6f6SMatthew Dillon HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */
1029572ff6f6SMatthew Dillon } HAL_DFS_DOMAIN;
1030572ff6f6SMatthew Dillon
1031572ff6f6SMatthew Dillon
1032572ff6f6SMatthew Dillon /*
1033572ff6f6SMatthew Dillon * MFP decryption options for initializing the MAC.
1034572ff6f6SMatthew Dillon */
1035572ff6f6SMatthew Dillon typedef enum {
1036572ff6f6SMatthew Dillon HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */
1037572ff6f6SMatthew Dillon HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */
1038572ff6f6SMatthew Dillon HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */
1039572ff6f6SMatthew Dillon } HAL_MFP_OPT_T;
1040572ff6f6SMatthew Dillon
1041572ff6f6SMatthew Dillon /* LNA config supported */
1042572ff6f6SMatthew Dillon typedef enum {
1043572ff6f6SMatthew Dillon HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0,
1044572ff6f6SMatthew Dillon HAL_ANT_DIV_COMB_LNA2 = 1,
1045572ff6f6SMatthew Dillon HAL_ANT_DIV_COMB_LNA1 = 2,
1046572ff6f6SMatthew Dillon HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3,
1047572ff6f6SMatthew Dillon } HAL_ANT_DIV_COMB_LNA_CONF;
1048572ff6f6SMatthew Dillon
1049572ff6f6SMatthew Dillon typedef struct {
1050572ff6f6SMatthew Dillon u_int8_t main_lna_conf;
1051572ff6f6SMatthew Dillon u_int8_t alt_lna_conf;
1052572ff6f6SMatthew Dillon u_int8_t fast_div_bias;
1053572ff6f6SMatthew Dillon u_int8_t main_gaintb;
1054572ff6f6SMatthew Dillon u_int8_t alt_gaintb;
1055572ff6f6SMatthew Dillon u_int8_t antdiv_configgroup;
1056572ff6f6SMatthew Dillon int8_t lna1_lna2_delta;
1057572ff6f6SMatthew Dillon } HAL_ANT_COMB_CONFIG;
1058572ff6f6SMatthew Dillon
1059572ff6f6SMatthew Dillon #define DEFAULT_ANTDIV_CONFIG_GROUP 0x00
1060572ff6f6SMatthew Dillon #define HAL_ANTDIV_CONFIG_GROUP_1 0x01
1061572ff6f6SMatthew Dillon #define HAL_ANTDIV_CONFIG_GROUP_2 0x02
1062572ff6f6SMatthew Dillon #define HAL_ANTDIV_CONFIG_GROUP_3 0x03
1063572ff6f6SMatthew Dillon
1064572ff6f6SMatthew Dillon /*
1065572ff6f6SMatthew Dillon * Flag for setting QUIET period
1066572ff6f6SMatthew Dillon */
1067572ff6f6SMatthew Dillon typedef enum {
1068572ff6f6SMatthew Dillon HAL_QUIET_DISABLE = 0x0,
1069572ff6f6SMatthew Dillon HAL_QUIET_ENABLE = 0x1,
1070572ff6f6SMatthew Dillon HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */
1071572ff6f6SMatthew Dillon HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */
1072572ff6f6SMatthew Dillon } HAL_QUIET_FLAG;
1073572ff6f6SMatthew Dillon
1074572ff6f6SMatthew Dillon #define HAL_DFS_EVENT_PRICH 0x0000001
1075572ff6f6SMatthew Dillon #define HAL_DFS_EVENT_EXTCH 0x0000002
1076572ff6f6SMatthew Dillon #define HAL_DFS_EVENT_EXTEARLY 0x0000004
1077572ff6f6SMatthew Dillon #define HAL_DFS_EVENT_ISDC 0x0000008
1078572ff6f6SMatthew Dillon
1079572ff6f6SMatthew Dillon struct hal_dfs_event {
1080572ff6f6SMatthew Dillon uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */
1081572ff6f6SMatthew Dillon uint32_t re_ts; /* Original 15 bit recv timestamp */
1082572ff6f6SMatthew Dillon uint8_t re_rssi; /* rssi of radar event */
1083572ff6f6SMatthew Dillon uint8_t re_dur; /* duration of radar pulse */
1084572ff6f6SMatthew Dillon uint32_t re_flags; /* Flags (see above) */
1085572ff6f6SMatthew Dillon };
1086572ff6f6SMatthew Dillon typedef struct hal_dfs_event HAL_DFS_EVENT;
1087572ff6f6SMatthew Dillon
1088572ff6f6SMatthew Dillon /*
1089572ff6f6SMatthew Dillon * Generic Timer domain
1090572ff6f6SMatthew Dillon */
1091572ff6f6SMatthew Dillon typedef enum {
1092572ff6f6SMatthew Dillon HAL_GEN_TIMER_TSF = 0,
1093572ff6f6SMatthew Dillon HAL_GEN_TIMER_TSF2,
1094572ff6f6SMatthew Dillon HAL_GEN_TIMER_TSF_ANY
1095572ff6f6SMatthew Dillon } HAL_GEN_TIMER_DOMAIN;
1096572ff6f6SMatthew Dillon
1097572ff6f6SMatthew Dillon /*
1098572ff6f6SMatthew Dillon * BT Co-existence definitions
1099572ff6f6SMatthew Dillon */
1100572ff6f6SMatthew Dillon typedef enum {
1101572ff6f6SMatthew Dillon HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */
1102572ff6f6SMatthew Dillon HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */
1103572ff6f6SMatthew Dillon HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */
1104572ff6f6SMatthew Dillon HAL_MAX_BT_MODULES
1105572ff6f6SMatthew Dillon } HAL_BT_MODULE;
1106572ff6f6SMatthew Dillon
1107572ff6f6SMatthew Dillon typedef struct {
1108572ff6f6SMatthew Dillon HAL_BT_MODULE bt_module;
1109572ff6f6SMatthew Dillon u_int8_t bt_coex_config;
1110572ff6f6SMatthew Dillon u_int8_t bt_gpio_bt_active;
1111572ff6f6SMatthew Dillon u_int8_t bt_gpio_bt_priority;
1112572ff6f6SMatthew Dillon u_int8_t bt_gpio_wlan_active;
1113572ff6f6SMatthew Dillon u_int8_t bt_active_polarity;
1114572ff6f6SMatthew Dillon HAL_BOOL bt_single_ant;
1115572ff6f6SMatthew Dillon u_int8_t bt_dutyCycle;
1116572ff6f6SMatthew Dillon u_int8_t bt_isolation;
1117572ff6f6SMatthew Dillon u_int8_t bt_period;
1118572ff6f6SMatthew Dillon } HAL_BT_COEX_INFO;
1119572ff6f6SMatthew Dillon
1120572ff6f6SMatthew Dillon typedef enum {
1121572ff6f6SMatthew Dillon HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */
1122572ff6f6SMatthew Dillon HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */
1123572ff6f6SMatthew Dillon HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */
1124572ff6f6SMatthew Dillon HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */
1125572ff6f6SMatthew Dillon } HAL_BT_COEX_MODE;
1126572ff6f6SMatthew Dillon
1127572ff6f6SMatthew Dillon typedef enum {
1128572ff6f6SMatthew Dillon HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */
1129572ff6f6SMatthew Dillon HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */
1130572ff6f6SMatthew Dillon HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */
1131572ff6f6SMatthew Dillon HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */
1132572ff6f6SMatthew Dillon HAL_BT_COEX_CFG_3WIRE, /* 3-wire */
1133572ff6f6SMatthew Dillon HAL_BT_COEX_CFG_MCI /* MCI */
1134572ff6f6SMatthew Dillon } HAL_BT_COEX_CFG;
1135572ff6f6SMatthew Dillon
1136572ff6f6SMatthew Dillon typedef enum {
1137572ff6f6SMatthew Dillon HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */
1138572ff6f6SMatthew Dillon HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */
1139572ff6f6SMatthew Dillon HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */
1140572ff6f6SMatthew Dillon HAL_BT_COEX_MCI_MAX_TX_PWR, /* Set max tx power for concurrent tx */
1141572ff6f6SMatthew Dillon HAL_BT_COEX_MCI_FTP_STOMP_RX, /* Use a different weight for stomp low */
1142572ff6f6SMatthew Dillon } HAL_BT_COEX_SET_PARAMETER;
1143572ff6f6SMatthew Dillon
1144572ff6f6SMatthew Dillon #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
1145572ff6f6SMatthew Dillon #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
1146572ff6f6SMatthew Dillon /* Check Rx Diversity is allowed */
1147572ff6f6SMatthew Dillon #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004
1148572ff6f6SMatthew Dillon /* Check Diversity is on or off */
1149572ff6f6SMatthew Dillon #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008
1150572ff6f6SMatthew Dillon
1151572ff6f6SMatthew Dillon #define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b
1152572ff6f6SMatthew Dillon /* main: LNA1, alt: LNA2 */
1153572ff6f6SMatthew Dillon #define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09
1154572ff6f6SMatthew Dillon #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04
1155572ff6f6SMatthew Dillon #define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09
1156572ff6f6SMatthew Dillon #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02
1157572ff6f6SMatthew Dillon #define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06
1158572ff6f6SMatthew Dillon
1159572ff6f6SMatthew Dillon #define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30
1160572ff6f6SMatthew Dillon
1161572ff6f6SMatthew Dillon #define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666
1162572ff6f6SMatthew Dillon
1163572ff6f6SMatthew Dillon #define HAL_BT_COEX_HELIUS_CHAINMASK 0x02
1164572ff6f6SMatthew Dillon
1165572ff6f6SMatthew Dillon #define HAL_BT_COEX_LOW_ACK_POWER 0x0
1166572ff6f6SMatthew Dillon #define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f
1167572ff6f6SMatthew Dillon
1168572ff6f6SMatthew Dillon typedef enum {
1169572ff6f6SMatthew Dillon HAL_BT_COEX_NO_STOMP = 0,
1170572ff6f6SMatthew Dillon HAL_BT_COEX_STOMP_ALL,
1171572ff6f6SMatthew Dillon HAL_BT_COEX_STOMP_LOW,
1172572ff6f6SMatthew Dillon HAL_BT_COEX_STOMP_NONE,
1173572ff6f6SMatthew Dillon HAL_BT_COEX_STOMP_ALL_FORCE,
1174572ff6f6SMatthew Dillon HAL_BT_COEX_STOMP_LOW_FORCE,
1175572ff6f6SMatthew Dillon } HAL_BT_COEX_STOMP_TYPE;
1176572ff6f6SMatthew Dillon
1177572ff6f6SMatthew Dillon typedef struct {
1178572ff6f6SMatthew Dillon /* extend rx_clear after tx/rx to protect the burst (in usec). */
1179572ff6f6SMatthew Dillon u_int8_t bt_time_extend;
1180572ff6f6SMatthew Dillon
1181572ff6f6SMatthew Dillon /*
1182572ff6f6SMatthew Dillon * extend rx_clear as long as txsm is
1183572ff6f6SMatthew Dillon * transmitting or waiting for ack.
1184572ff6f6SMatthew Dillon */
1185572ff6f6SMatthew Dillon HAL_BOOL bt_txstate_extend;
1186572ff6f6SMatthew Dillon
1187572ff6f6SMatthew Dillon /*
1188572ff6f6SMatthew Dillon * extend rx_clear so that when tx_frame
1189572ff6f6SMatthew Dillon * is asserted, rx_clear will drop.
1190572ff6f6SMatthew Dillon */
1191572ff6f6SMatthew Dillon HAL_BOOL bt_txframe_extend;
1192572ff6f6SMatthew Dillon
1193572ff6f6SMatthew Dillon /*
1194572ff6f6SMatthew Dillon * coexistence mode
1195572ff6f6SMatthew Dillon */
1196572ff6f6SMatthew Dillon HAL_BT_COEX_MODE bt_mode;
1197572ff6f6SMatthew Dillon
1198572ff6f6SMatthew Dillon /*
1199572ff6f6SMatthew Dillon * treat BT high priority traffic as
1200572ff6f6SMatthew Dillon * a quiet collision
1201572ff6f6SMatthew Dillon */
1202572ff6f6SMatthew Dillon HAL_BOOL bt_quiet_collision;
1203572ff6f6SMatthew Dillon
1204572ff6f6SMatthew Dillon /*
1205572ff6f6SMatthew Dillon * invert rx_clear as WLAN_ACTIVE
1206572ff6f6SMatthew Dillon */
1207572ff6f6SMatthew Dillon HAL_BOOL bt_rxclear_polarity;
1208572ff6f6SMatthew Dillon
1209572ff6f6SMatthew Dillon /*
1210572ff6f6SMatthew Dillon * slotted mode only. indicate the time in usec
1211572ff6f6SMatthew Dillon * from the rising edge of BT_ACTIVE to the time
1212572ff6f6SMatthew Dillon * BT_PRIORITY can be sampled to indicate priority.
1213572ff6f6SMatthew Dillon */
1214572ff6f6SMatthew Dillon u_int8_t bt_priority_time;
1215572ff6f6SMatthew Dillon
1216572ff6f6SMatthew Dillon /*
1217572ff6f6SMatthew Dillon * slotted mode only. indicate the time in usec
1218572ff6f6SMatthew Dillon * from the rising edge of BT_ACTIVE to the time
1219572ff6f6SMatthew Dillon * BT_PRIORITY can be sampled to indicate tx/rx and
1220572ff6f6SMatthew Dillon * BT_FREQ is sampled.
1221572ff6f6SMatthew Dillon */
1222572ff6f6SMatthew Dillon u_int8_t bt_first_slot_time;
1223572ff6f6SMatthew Dillon
1224572ff6f6SMatthew Dillon /*
1225572ff6f6SMatthew Dillon * slotted mode only. rx_clear and bt_ant decision
1226572ff6f6SMatthew Dillon * will be held the entire time that BT_ACTIVE is asserted,
1227*b14ca477SMatthew Dillon * otherwise the decision is made before every slot boundary.
1228572ff6f6SMatthew Dillon */
1229572ff6f6SMatthew Dillon HAL_BOOL bt_hold_rxclear;
1230572ff6f6SMatthew Dillon } HAL_BT_COEX_CONFIG;
1231572ff6f6SMatthew Dillon
1232572ff6f6SMatthew Dillon struct hal_bb_panic_info {
1233572ff6f6SMatthew Dillon u_int32_t status;
1234572ff6f6SMatthew Dillon u_int32_t tsf;
1235572ff6f6SMatthew Dillon u_int32_t phy_panic_wd_ctl1;
1236572ff6f6SMatthew Dillon u_int32_t phy_panic_wd_ctl2;
1237572ff6f6SMatthew Dillon u_int32_t phy_gen_ctrl;
1238572ff6f6SMatthew Dillon u_int32_t rxc_pcnt;
1239572ff6f6SMatthew Dillon u_int32_t rxf_pcnt;
1240572ff6f6SMatthew Dillon u_int32_t txf_pcnt;
1241572ff6f6SMatthew Dillon u_int32_t cycles;
1242572ff6f6SMatthew Dillon u_int32_t wd;
1243572ff6f6SMatthew Dillon u_int32_t det;
1244572ff6f6SMatthew Dillon u_int32_t rdar;
1245572ff6f6SMatthew Dillon u_int32_t r_odfm;
1246572ff6f6SMatthew Dillon u_int32_t r_cck;
1247572ff6f6SMatthew Dillon u_int32_t t_odfm;
1248572ff6f6SMatthew Dillon u_int32_t t_cck;
1249572ff6f6SMatthew Dillon u_int32_t agc;
1250572ff6f6SMatthew Dillon u_int32_t src;
1251572ff6f6SMatthew Dillon };
1252572ff6f6SMatthew Dillon
1253572ff6f6SMatthew Dillon /* Serialize Register Access Mode */
1254572ff6f6SMatthew Dillon typedef enum {
1255572ff6f6SMatthew Dillon SER_REG_MODE_OFF = 0,
1256572ff6f6SMatthew Dillon SER_REG_MODE_ON = 1,
1257572ff6f6SMatthew Dillon SER_REG_MODE_AUTO = 2,
1258572ff6f6SMatthew Dillon } SER_REG_MODE;
1259572ff6f6SMatthew Dillon
1260572ff6f6SMatthew Dillon typedef struct
1261572ff6f6SMatthew Dillon {
1262572ff6f6SMatthew Dillon int ah_debug; /* only used if AH_DEBUG is defined */
1263572ff6f6SMatthew Dillon int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */
1264572ff6f6SMatthew Dillon
1265572ff6f6SMatthew Dillon /* NB: these are deprecated; they exist for now for compatibility */
1266572ff6f6SMatthew Dillon int ah_dma_beacon_response_time;/* in TU's */
1267572ff6f6SMatthew Dillon int ah_sw_beacon_response_time; /* in TU's */
1268572ff6f6SMatthew Dillon int ah_additional_swba_backoff; /* in TU's */
1269572ff6f6SMatthew Dillon int ah_force_full_reset; /* force full chip reset rather then warm reset */
1270572ff6f6SMatthew Dillon int ah_serialise_reg_war; /* force serialisation of register IO */
1271572ff6f6SMatthew Dillon
1272572ff6f6SMatthew Dillon /* XXX these don't belong here, they're just for the ar9300 HAL port effort */
1273572ff6f6SMatthew Dillon int ath_hal_desc_tpc; /* Per-packet TPC */
1274572ff6f6SMatthew Dillon int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */
1275572ff6f6SMatthew Dillon int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */
1276572ff6f6SMatthew Dillon int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */
1277572ff6f6SMatthew Dillon int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */
1278572ff6f6SMatthew Dillon
1279572ff6f6SMatthew Dillon /* I'm not sure what the default values for these should be */
1280572ff6f6SMatthew Dillon int ath_hal_pll_pwr_save;
1281572ff6f6SMatthew Dillon int ath_hal_pcie_power_save_enable;
1282572ff6f6SMatthew Dillon int ath_hal_intr_mitigation_rx;
1283572ff6f6SMatthew Dillon int ath_hal_intr_mitigation_tx;
1284572ff6f6SMatthew Dillon
1285572ff6f6SMatthew Dillon int ath_hal_pcie_clock_req;
1286572ff6f6SMatthew Dillon #define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0)
1287572ff6f6SMatthew Dillon #define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1)
1288572ff6f6SMatthew Dillon #define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2)
1289572ff6f6SMatthew Dillon
1290572ff6f6SMatthew Dillon int ath_hal_pcie_waen;
1291572ff6f6SMatthew Dillon int ath_hal_pcie_ser_des_write;
1292572ff6f6SMatthew Dillon
1293572ff6f6SMatthew Dillon /* these are important for correct AR9300 behaviour */
1294572ff6f6SMatthew Dillon int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */
1295572ff6f6SMatthew Dillon int ath_hal_diversity_control;
1296572ff6f6SMatthew Dillon int ath_hal_antenna_switch_swap;
1297572ff6f6SMatthew Dillon int ath_hal_ext_lna_ctl_gpio;
1298572ff6f6SMatthew Dillon int ath_hal_spur_mode;
1299572ff6f6SMatthew Dillon int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */
1300572ff6f6SMatthew Dillon int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */
1301572ff6f6SMatthew Dillon int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */
1302572ff6f6SMatthew Dillon
1303572ff6f6SMatthew Dillon /* For now, set this to 0 - net80211 needs to know about hardware MFP support */
1304572ff6f6SMatthew Dillon int ath_hal_mfp_support;
1305572ff6f6SMatthew Dillon
1306572ff6f6SMatthew Dillon int ath_hal_enable_ani; /* should set this.. */
1307572ff6f6SMatthew Dillon int ath_hal_cwm_ignore_ext_cca;
1308572ff6f6SMatthew Dillon int ath_hal_show_bb_panic;
1309572ff6f6SMatthew Dillon int ath_hal_ant_ctrl_comm2g_switch_enable;
1310572ff6f6SMatthew Dillon int ath_hal_ext_atten_margin_cfg;
1311848b370cSMatthew Dillon int ath_hal_min_gainidx;
1312572ff6f6SMatthew Dillon int ath_hal_war70c;
1313572ff6f6SMatthew Dillon uint32_t ath_hal_mci_config;
1314572ff6f6SMatthew Dillon } HAL_OPS_CONFIG;
1315572ff6f6SMatthew Dillon
1316572ff6f6SMatthew Dillon /*
1317572ff6f6SMatthew Dillon * Hardware Access Layer (HAL) API.
1318572ff6f6SMatthew Dillon *
1319572ff6f6SMatthew Dillon * Clients of the HAL call ath_hal_attach to obtain a reference to an
1320572ff6f6SMatthew Dillon * ath_hal structure for use with the device. Hardware-related operations
1321572ff6f6SMatthew Dillon * that follow must call back into the HAL through interface, supplying
1322572ff6f6SMatthew Dillon * the reference as the first parameter. Note that before using the
1323572ff6f6SMatthew Dillon * reference returned by ath_hal_attach the caller should verify the
1324572ff6f6SMatthew Dillon * ABI version number.
1325572ff6f6SMatthew Dillon */
1326572ff6f6SMatthew Dillon struct ath_hal {
1327572ff6f6SMatthew Dillon uint32_t ah_magic; /* consistency check magic number */
1328572ff6f6SMatthew Dillon uint16_t ah_devid; /* PCI device ID */
1329572ff6f6SMatthew Dillon uint16_t ah_subvendorid; /* PCI subvendor ID */
1330572ff6f6SMatthew Dillon HAL_SOFTC ah_sc; /* back pointer to driver/os state */
1331572ff6f6SMatthew Dillon HAL_BUS_TAG ah_st; /* params for register r+w */
1332572ff6f6SMatthew Dillon HAL_BUS_HANDLE ah_sh;
1333572ff6f6SMatthew Dillon HAL_CTRY_CODE ah_countryCode;
1334572ff6f6SMatthew Dillon
1335572ff6f6SMatthew Dillon uint32_t ah_macVersion; /* MAC version id */
1336572ff6f6SMatthew Dillon uint16_t ah_macRev; /* MAC revision */
1337572ff6f6SMatthew Dillon uint16_t ah_phyRev; /* PHY revision */
1338572ff6f6SMatthew Dillon /* NB: when only one radio is present the rev is in 5Ghz */
1339572ff6f6SMatthew Dillon uint16_t ah_analog5GhzRev;/* 5GHz radio revision */
1340572ff6f6SMatthew Dillon uint16_t ah_analog2GhzRev;/* 2GHz radio revision */
1341572ff6f6SMatthew Dillon
1342572ff6f6SMatthew Dillon uint16_t *ah_eepromdata; /* eeprom buffer, if needed */
1343572ff6f6SMatthew Dillon
1344572ff6f6SMatthew Dillon uint32_t ah_intrstate[8]; /* last int state */
1345572ff6f6SMatthew Dillon uint32_t ah_syncstate; /* last sync intr state */
1346572ff6f6SMatthew Dillon
1347d98a0bcfSMatthew Dillon /* Current powerstate from HAL calls */
1348d98a0bcfSMatthew Dillon HAL_POWER_MODE ah_powerMode;
1349d98a0bcfSMatthew Dillon
1350572ff6f6SMatthew Dillon HAL_OPS_CONFIG ah_config;
1351572ff6f6SMatthew Dillon const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
1352572ff6f6SMatthew Dillon u_int mode);
1353572ff6f6SMatthew Dillon void __ahdecl(*ah_detach)(struct ath_hal*);
1354572ff6f6SMatthew Dillon
1355572ff6f6SMatthew Dillon /* Reset functions */
1356572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
1357572ff6f6SMatthew Dillon struct ieee80211_channel *,
1358*b14ca477SMatthew Dillon HAL_BOOL bChannelChange,
1359*b14ca477SMatthew Dillon HAL_RESET_TYPE resetType,
1360*b14ca477SMatthew Dillon HAL_STATUS *status);
1361572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
1362572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
1363572ff6f6SMatthew Dillon void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore,
1364572ff6f6SMatthew Dillon HAL_BOOL power_off);
1365572ff6f6SMatthew Dillon void __ahdecl(*ah_disablePCIE)(struct ath_hal *);
1366572ff6f6SMatthew Dillon void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
1367572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*,
1368572ff6f6SMatthew Dillon struct ieee80211_channel *, HAL_BOOL *);
1369572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *,
1370572ff6f6SMatthew Dillon struct ieee80211_channel *, u_int chainMask,
1371572ff6f6SMatthew Dillon HAL_BOOL longCal, HAL_BOOL *isCalDone);
1372572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *,
1373572ff6f6SMatthew Dillon const struct ieee80211_channel *);
1374572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *,
1375572ff6f6SMatthew Dillon const struct ieee80211_channel *, uint16_t *);
1376572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
1377572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *,
1378572ff6f6SMatthew Dillon const struct ieee80211_channel *);
1379572ff6f6SMatthew Dillon
1380572ff6f6SMatthew Dillon /* Transmit functions */
1381572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
1382572ff6f6SMatthew Dillon HAL_BOOL incTrigLevel);
1383572ff6f6SMatthew Dillon int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
1384572ff6f6SMatthew Dillon const HAL_TXQ_INFO *qInfo);
1385572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q,
1386572ff6f6SMatthew Dillon const HAL_TXQ_INFO *qInfo);
1387572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q,
1388572ff6f6SMatthew Dillon HAL_TXQ_INFO *qInfo);
1389572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
1390572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
1391572ff6f6SMatthew Dillon uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
1392572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp);
1393572ff6f6SMatthew Dillon uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q);
1394572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
1395572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
1396572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
1397572ff6f6SMatthew Dillon u_int pktLen, u_int hdrLen,
1398572ff6f6SMatthew Dillon HAL_PKT_TYPE type, u_int txPower,
1399572ff6f6SMatthew Dillon u_int txRate0, u_int txTries0,
1400572ff6f6SMatthew Dillon u_int keyIx, u_int antMode, u_int flags,
1401572ff6f6SMatthew Dillon u_int rtsctsRate, u_int rtsctsDuration,
1402572ff6f6SMatthew Dillon u_int compicvLen, u_int compivLen,
1403572ff6f6SMatthew Dillon u_int comp);
1404572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*,
1405572ff6f6SMatthew Dillon u_int txRate1, u_int txTries1,
1406572ff6f6SMatthew Dillon u_int txRate2, u_int txTries2,
1407572ff6f6SMatthew Dillon u_int txRate3, u_int txTries3);
1408572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
1409572ff6f6SMatthew Dillon HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,
1410572ff6f6SMatthew Dillon u_int descId, u_int qcuId, HAL_BOOL firstSeg,
1411572ff6f6SMatthew Dillon HAL_BOOL lastSeg, const struct ath_desc *);
1412572ff6f6SMatthew Dillon HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
1413572ff6f6SMatthew Dillon struct ath_desc *, struct ath_tx_status *);
1414572ff6f6SMatthew Dillon void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *);
1415572ff6f6SMatthew Dillon void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
1416572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *,
1417572ff6f6SMatthew Dillon const struct ath_desc *ds, int *rates, int *tries);
1418572ff6f6SMatthew Dillon void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds,
1419572ff6f6SMatthew Dillon uint32_t link);
1420572ff6f6SMatthew Dillon void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds,
1421572ff6f6SMatthew Dillon uint32_t *link);
1422572ff6f6SMatthew Dillon void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds,
1423572ff6f6SMatthew Dillon uint32_t **linkptr);
1424572ff6f6SMatthew Dillon void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *,
1425572ff6f6SMatthew Dillon void *ts_start, uint32_t ts_paddr_start,
1426572ff6f6SMatthew Dillon uint16_t size);
1427572ff6f6SMatthew Dillon void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *);
1428572ff6f6SMatthew Dillon
1429572ff6f6SMatthew Dillon /* Receive Functions */
1430572ff6f6SMatthew Dillon uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE);
1431572ff6f6SMatthew Dillon void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE);
1432572ff6f6SMatthew Dillon void __ahdecl(*ah_enableReceive)(struct ath_hal*);
1433572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
1434572ff6f6SMatthew Dillon void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
1435572ff6f6SMatthew Dillon void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
1436572ff6f6SMatthew Dillon void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
1437572ff6f6SMatthew Dillon uint32_t filter0, uint32_t filter1);
1438572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
1439572ff6f6SMatthew Dillon uint32_t index);
1440572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
1441572ff6f6SMatthew Dillon uint32_t index);
1442572ff6f6SMatthew Dillon uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
1443572ff6f6SMatthew Dillon void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t);
1444572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
1445572ff6f6SMatthew Dillon uint32_t size, u_int flags);
1446572ff6f6SMatthew Dillon HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *,
1447572ff6f6SMatthew Dillon struct ath_desc *, uint32_t phyAddr,
1448572ff6f6SMatthew Dillon struct ath_desc *next, uint64_t tsf,
1449572ff6f6SMatthew Dillon struct ath_rx_status *);
1450572ff6f6SMatthew Dillon void __ahdecl(*ah_rxMonitor)(struct ath_hal *,
1451572ff6f6SMatthew Dillon const HAL_NODE_STATS *,
1452572ff6f6SMatthew Dillon const struct ieee80211_channel *);
1453572ff6f6SMatthew Dillon void __ahdecl(*ah_aniPoll)(struct ath_hal *,
1454572ff6f6SMatthew Dillon const struct ieee80211_channel *);
1455572ff6f6SMatthew Dillon void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
1456572ff6f6SMatthew Dillon const HAL_NODE_STATS *);
1457572ff6f6SMatthew Dillon
1458572ff6f6SMatthew Dillon /* Misc Functions */
1459572ff6f6SMatthew Dillon HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
1460572ff6f6SMatthew Dillon HAL_CAPABILITY_TYPE, uint32_t capability,
1461572ff6f6SMatthew Dillon uint32_t *result);
1462572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *,
1463572ff6f6SMatthew Dillon HAL_CAPABILITY_TYPE, uint32_t capability,
1464572ff6f6SMatthew Dillon uint32_t setting, HAL_STATUS *);
1465572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request,
1466572ff6f6SMatthew Dillon const void *args, uint32_t argsize,
1467572ff6f6SMatthew Dillon void **result, uint32_t *resultsize);
1468572ff6f6SMatthew Dillon void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *);
1469572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*);
1470572ff6f6SMatthew Dillon void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *);
1471572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*);
1472572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
1473572ff6f6SMatthew Dillon uint16_t, HAL_STATUS *);
1474572ff6f6SMatthew Dillon void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
1475572ff6f6SMatthew Dillon void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
1476572ff6f6SMatthew Dillon const uint8_t *bssid, uint16_t assocId);
1477572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *,
1478572ff6f6SMatthew Dillon uint32_t gpio, HAL_GPIO_MUX_TYPE);
1479572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
1480572ff6f6SMatthew Dillon uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
1481572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,
1482572ff6f6SMatthew Dillon uint32_t gpio, uint32_t val);
1483572ff6f6SMatthew Dillon void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
1484572ff6f6SMatthew Dillon uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
1485572ff6f6SMatthew Dillon uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
1486572ff6f6SMatthew Dillon void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t);
1487572ff6f6SMatthew Dillon void __ahdecl(*ah_resetTsf)(struct ath_hal*);
1488572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
1489572ff6f6SMatthew Dillon void __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
1490572ff6f6SMatthew Dillon HAL_MIB_STATS*);
1491572ff6f6SMatthew Dillon HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
1492572ff6f6SMatthew Dillon u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
1493572ff6f6SMatthew Dillon void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int);
1494572ff6f6SMatthew Dillon HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*);
1495572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*,
1496572ff6f6SMatthew Dillon HAL_ANT_SETTING);
1497572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int);
1498572ff6f6SMatthew Dillon u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*);
1499572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
1500572ff6f6SMatthew Dillon u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*);
1501572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
1502572ff6f6SMatthew Dillon u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
1503572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int);
1504572ff6f6SMatthew Dillon u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*);
1505572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
1506572ff6f6SMatthew Dillon u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
1507572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int);
1508572ff6f6SMatthew Dillon void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int);
1509572ff6f6SMatthew Dillon HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period,
1510572ff6f6SMatthew Dillon uint32_t duration, uint32_t nextStart,
1511572ff6f6SMatthew Dillon HAL_QUIET_FLAG flag);
1512572ff6f6SMatthew Dillon void __ahdecl(*ah_setChainMasks)(struct ath_hal *,
1513572ff6f6SMatthew Dillon uint32_t, uint32_t);
1514572ff6f6SMatthew Dillon
1515572ff6f6SMatthew Dillon /* DFS functions */
1516572ff6f6SMatthew Dillon void __ahdecl(*ah_enableDfs)(struct ath_hal *ah,
1517572ff6f6SMatthew Dillon HAL_PHYERR_PARAM *pe);
1518572ff6f6SMatthew Dillon void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah,
1519572ff6f6SMatthew Dillon HAL_PHYERR_PARAM *pe);
1520572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah,
1521572ff6f6SMatthew Dillon HAL_PHYERR_PARAM *pe);
1522572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah,
1523572ff6f6SMatthew Dillon struct ath_rx_status *rxs, uint64_t fulltsf,
1524572ff6f6SMatthew Dillon const char *buf, HAL_DFS_EVENT *event);
1525572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah);
1526572ff6f6SMatthew Dillon
1527572ff6f6SMatthew Dillon /* Spectral Scan functions */
1528572ff6f6SMatthew Dillon void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah,
1529572ff6f6SMatthew Dillon HAL_SPECTRAL_PARAM *sp);
1530572ff6f6SMatthew Dillon void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah,
1531572ff6f6SMatthew Dillon HAL_SPECTRAL_PARAM *sp);
1532572ff6f6SMatthew Dillon void __ahdecl(*ah_spectralStart)(struct ath_hal *);
1533572ff6f6SMatthew Dillon void __ahdecl(*ah_spectralStop)(struct ath_hal *);
1534572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *);
1535572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *);
1536572ff6f6SMatthew Dillon /* XXX getNfPri() and getNfExt() */
1537572ff6f6SMatthew Dillon
1538572ff6f6SMatthew Dillon /* Key Cache Functions */
1539572ff6f6SMatthew Dillon uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
1540572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
1541572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,
1542572ff6f6SMatthew Dillon uint16_t);
1543572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
1544572ff6f6SMatthew Dillon uint16_t, const HAL_KEYVAL *,
1545572ff6f6SMatthew Dillon const uint8_t *, int);
1546572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
1547572ff6f6SMatthew Dillon uint16_t, const uint8_t *);
1548572ff6f6SMatthew Dillon
1549572ff6f6SMatthew Dillon /* Power Management Functions */
1550572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*,
1551572ff6f6SMatthew Dillon HAL_POWER_MODE mode, int setChip);
1552572ff6f6SMatthew Dillon HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
1553572ff6f6SMatthew Dillon int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *,
1554572ff6f6SMatthew Dillon const struct ieee80211_channel *);
1555572ff6f6SMatthew Dillon
1556572ff6f6SMatthew Dillon /* Beacon Management Functions */
1557572ff6f6SMatthew Dillon void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
1558572ff6f6SMatthew Dillon const HAL_BEACON_TIMERS *);
1559572ff6f6SMatthew Dillon /* NB: deprecated, use ah_setBeaconTimers instead */
1560572ff6f6SMatthew Dillon void __ahdecl(*ah_beaconInit)(struct ath_hal *,
1561572ff6f6SMatthew Dillon uint32_t nexttbtt, uint32_t intval);
1562572ff6f6SMatthew Dillon void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
1563572ff6f6SMatthew Dillon const HAL_BEACON_STATE *);
1564572ff6f6SMatthew Dillon void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
1565572ff6f6SMatthew Dillon uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *);
1566572ff6f6SMatthew Dillon
1567572ff6f6SMatthew Dillon /* 802.11n Functions */
1568572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *,
1569572ff6f6SMatthew Dillon struct ath_desc *,
1570572ff6f6SMatthew Dillon HAL_DMA_ADDR *bufAddrList,
1571572ff6f6SMatthew Dillon uint32_t *segLenList,
1572572ff6f6SMatthew Dillon u_int, u_int, HAL_PKT_TYPE,
1573572ff6f6SMatthew Dillon u_int, HAL_CIPHER, uint8_t, HAL_BOOL,
1574572ff6f6SMatthew Dillon HAL_BOOL, HAL_BOOL);
1575572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *,
1576572ff6f6SMatthew Dillon struct ath_desc *, u_int, u_int, u_int,
1577572ff6f6SMatthew Dillon u_int, u_int, u_int, u_int, u_int);
1578572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *,
1579572ff6f6SMatthew Dillon struct ath_desc *, const struct ath_desc *);
1580572ff6f6SMatthew Dillon void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *,
1581572ff6f6SMatthew Dillon struct ath_desc *, u_int, u_int,
1582572ff6f6SMatthew Dillon HAL_11N_RATE_SERIES [], u_int, u_int);
1583572ff6f6SMatthew Dillon
1584572ff6f6SMatthew Dillon /*
1585572ff6f6SMatthew Dillon * The next 4 (set11ntxdesc -> set11naggrlast) are specific
1586572ff6f6SMatthew Dillon * to the EDMA HAL. Descriptors are chained together by
1587572ff6f6SMatthew Dillon * using filltxdesc (not ChainTxDesc) and then setting the
1588572ff6f6SMatthew Dillon * aggregate flags appropriately using first/middle/last.
1589572ff6f6SMatthew Dillon */
1590572ff6f6SMatthew Dillon void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *,
1591572ff6f6SMatthew Dillon void *, u_int, HAL_PKT_TYPE, u_int, u_int,
1592572ff6f6SMatthew Dillon u_int);
1593572ff6f6SMatthew Dillon void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *,
1594572ff6f6SMatthew Dillon struct ath_desc *, u_int, u_int);
1595572ff6f6SMatthew Dillon void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *,
1596572ff6f6SMatthew Dillon struct ath_desc *, u_int);
1597572ff6f6SMatthew Dillon void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *,
1598572ff6f6SMatthew Dillon struct ath_desc *);
1599572ff6f6SMatthew Dillon void __ahdecl(*ah_clr11nAggr)(struct ath_hal *,
1600572ff6f6SMatthew Dillon struct ath_desc *);
1601572ff6f6SMatthew Dillon void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *,
1602572ff6f6SMatthew Dillon struct ath_desc *, u_int);
1603572ff6f6SMatthew Dillon void __ahdecl(*ah_set11nVirtMoreFrag)(struct ath_hal *,
1604572ff6f6SMatthew Dillon struct ath_desc *, u_int);
1605572ff6f6SMatthew Dillon
1606572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *,
1607572ff6f6SMatthew Dillon HAL_SURVEY_SAMPLE *);
1608572ff6f6SMatthew Dillon
1609572ff6f6SMatthew Dillon uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *);
1610572ff6f6SMatthew Dillon void __ahdecl(*ah_set11nMac2040)(struct ath_hal *,
1611572ff6f6SMatthew Dillon HAL_HT_MACMODE);
1612572ff6f6SMatthew Dillon HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah);
1613572ff6f6SMatthew Dillon void __ahdecl(*ah_set11nRxClear)(struct ath_hal *,
1614572ff6f6SMatthew Dillon HAL_HT_RXCLEAR);
1615572ff6f6SMatthew Dillon
1616572ff6f6SMatthew Dillon /* Interrupt functions */
1617572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
1618572ff6f6SMatthew Dillon HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
1619572ff6f6SMatthew Dillon HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
1620572ff6f6SMatthew Dillon HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
1621572ff6f6SMatthew Dillon
1622572ff6f6SMatthew Dillon /* Bluetooth Coexistence functions */
1623572ff6f6SMatthew Dillon void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *,
1624572ff6f6SMatthew Dillon HAL_BT_COEX_INFO *);
1625572ff6f6SMatthew Dillon void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *,
1626572ff6f6SMatthew Dillon HAL_BT_COEX_CONFIG *);
1627572ff6f6SMatthew Dillon void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *,
1628572ff6f6SMatthew Dillon int);
1629572ff6f6SMatthew Dillon void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *,
1630572ff6f6SMatthew Dillon uint32_t);
1631572ff6f6SMatthew Dillon void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *,
1632572ff6f6SMatthew Dillon uint32_t);
1633572ff6f6SMatthew Dillon void __ahdecl(*ah_btCoexSetParameter)(struct ath_hal *,
1634572ff6f6SMatthew Dillon uint32_t, uint32_t);
1635572ff6f6SMatthew Dillon void __ahdecl(*ah_btCoexDisable)(struct ath_hal *);
1636572ff6f6SMatthew Dillon int __ahdecl(*ah_btCoexEnable)(struct ath_hal *);
1637572ff6f6SMatthew Dillon
1638848b370cSMatthew Dillon /* Bluetooth MCI methods */
1639848b370cSMatthew Dillon void __ahdecl(*ah_btMciSetup)(struct ath_hal *,
1640848b370cSMatthew Dillon uint32_t, void *, uint16_t, uint32_t);
1641848b370cSMatthew Dillon HAL_BOOL __ahdecl(*ah_btMciSendMessage)(struct ath_hal *,
1642848b370cSMatthew Dillon uint8_t, uint32_t, uint32_t *, uint8_t,
1643848b370cSMatthew Dillon HAL_BOOL, HAL_BOOL);
1644848b370cSMatthew Dillon uint32_t __ahdecl(*ah_btMciGetInterrupt)(struct ath_hal *,
1645848b370cSMatthew Dillon uint32_t *, uint32_t *);
1646848b370cSMatthew Dillon uint32_t __ahdecl(*ah_btMciGetState)(struct ath_hal *,
1647848b370cSMatthew Dillon uint32_t, uint32_t *);
1648848b370cSMatthew Dillon void __ahdecl(*ah_btMciDetach)(struct ath_hal *);
1649848b370cSMatthew Dillon
1650572ff6f6SMatthew Dillon /* LNA diversity configuration */
1651572ff6f6SMatthew Dillon void __ahdecl(*ah_divLnaConfGet)(struct ath_hal *,
1652572ff6f6SMatthew Dillon HAL_ANT_COMB_CONFIG *);
1653572ff6f6SMatthew Dillon void __ahdecl(*ah_divLnaConfSet)(struct ath_hal *,
1654572ff6f6SMatthew Dillon HAL_ANT_COMB_CONFIG *);
1655572ff6f6SMatthew Dillon };
1656572ff6f6SMatthew Dillon
1657572ff6f6SMatthew Dillon /*
1658572ff6f6SMatthew Dillon * Check the PCI vendor ID and device ID against Atheros' values
1659572ff6f6SMatthew Dillon * and return a printable description for any Atheros hardware.
1660572ff6f6SMatthew Dillon * AH_NULL is returned if the ID's do not describe Atheros hardware.
1661572ff6f6SMatthew Dillon */
1662572ff6f6SMatthew Dillon extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid);
1663572ff6f6SMatthew Dillon
1664572ff6f6SMatthew Dillon /*
1665572ff6f6SMatthew Dillon * Attach the HAL for use with the specified device. The device is
1666572ff6f6SMatthew Dillon * defined by the PCI device ID. The caller provides an opaque pointer
1667572ff6f6SMatthew Dillon * to an upper-layer data structure (HAL_SOFTC) that is stored in the
1668572ff6f6SMatthew Dillon * HAL state block for later use. Hardware register accesses are done
1669572ff6f6SMatthew Dillon * using the specified bus tag and handle. On successful return a
1670572ff6f6SMatthew Dillon * reference to a state block is returned that must be supplied in all
1671572ff6f6SMatthew Dillon * subsequent HAL calls. Storage associated with this reference is
1672572ff6f6SMatthew Dillon * dynamically allocated and must be freed by calling the ah_detach
1673572ff6f6SMatthew Dillon * method when the client is done. If the attach operation fails a
1674572ff6f6SMatthew Dillon * null (AH_NULL) reference will be returned and a status code will
1675572ff6f6SMatthew Dillon * be returned if the status parameter is non-zero.
1676572ff6f6SMatthew Dillon */
1677572ff6f6SMatthew Dillon extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
1678848b370cSMatthew Dillon HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata,
1679848b370cSMatthew Dillon HAL_OPS_CONFIG *ah_config, HAL_STATUS* status);
1680572ff6f6SMatthew Dillon
1681572ff6f6SMatthew Dillon extern const char *ath_hal_mac_name(struct ath_hal *);
1682572ff6f6SMatthew Dillon extern const char *ath_hal_rf_name(struct ath_hal *);
1683572ff6f6SMatthew Dillon
1684572ff6f6SMatthew Dillon /*
1685572ff6f6SMatthew Dillon * Regulatory interfaces. Drivers should use ath_hal_init_channels to
1686572ff6f6SMatthew Dillon * request a set of channels for a particular country code and/or
1687572ff6f6SMatthew Dillon * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then
1688572ff6f6SMatthew Dillon * this list is constructed according to the contents of the EEPROM.
1689572ff6f6SMatthew Dillon * ath_hal_getchannels acts similarly but does not alter the operating
1690572ff6f6SMatthew Dillon * state; this can be used to collect information for a particular
1691572ff6f6SMatthew Dillon * regulatory configuration. Finally ath_hal_set_channels installs a
1692572ff6f6SMatthew Dillon * channel list constructed outside the driver. The HAL will adopt the
1693572ff6f6SMatthew Dillon * channel list and setup internal state according to the specified
1694572ff6f6SMatthew Dillon * regulatory configuration (e.g. conformance test limits).
1695572ff6f6SMatthew Dillon *
1696572ff6f6SMatthew Dillon * For all interfaces the channel list is returned in the supplied array.
1697572ff6f6SMatthew Dillon * maxchans defines the maximum size of this array. nchans contains the
1698572ff6f6SMatthew Dillon * actual number of channels returned. If a problem occurred then a
1699572ff6f6SMatthew Dillon * status code != HAL_OK is returned.
1700572ff6f6SMatthew Dillon */
1701572ff6f6SMatthew Dillon struct ieee80211_channel;
1702572ff6f6SMatthew Dillon
1703572ff6f6SMatthew Dillon /*
1704572ff6f6SMatthew Dillon * Return a list of channels according to the specified regulatory.
1705572ff6f6SMatthew Dillon */
1706572ff6f6SMatthew Dillon extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *,
1707572ff6f6SMatthew Dillon struct ieee80211_channel *chans, u_int maxchans, int *nchans,
1708572ff6f6SMatthew Dillon u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,
1709572ff6f6SMatthew Dillon HAL_BOOL enableExtendedChannels);
1710572ff6f6SMatthew Dillon
1711572ff6f6SMatthew Dillon /*
1712572ff6f6SMatthew Dillon * Return a list of channels and install it as the current operating
1713572ff6f6SMatthew Dillon * regulatory list.
1714572ff6f6SMatthew Dillon */
1715572ff6f6SMatthew Dillon extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *,
1716572ff6f6SMatthew Dillon struct ieee80211_channel *chans, u_int maxchans, int *nchans,
1717572ff6f6SMatthew Dillon u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd,
1718572ff6f6SMatthew Dillon HAL_BOOL enableExtendedChannels);
1719572ff6f6SMatthew Dillon
1720572ff6f6SMatthew Dillon /*
1721572ff6f6SMatthew Dillon * Install the list of channels as the current operating regulatory
1722572ff6f6SMatthew Dillon * and setup related state according to the country code and sku.
1723572ff6f6SMatthew Dillon */
1724572ff6f6SMatthew Dillon extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *,
1725572ff6f6SMatthew Dillon struct ieee80211_channel *chans, int nchans,
1726572ff6f6SMatthew Dillon HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn);
1727572ff6f6SMatthew Dillon
1728572ff6f6SMatthew Dillon /*
1729572ff6f6SMatthew Dillon * Fetch the ctl/ext noise floor values reported by a MIMO
1730572ff6f6SMatthew Dillon * radio. Returns 1 for valid results, 0 for invalid channel.
1731572ff6f6SMatthew Dillon */
1732572ff6f6SMatthew Dillon extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
1733572ff6f6SMatthew Dillon const struct ieee80211_channel *chan, int16_t *nf_ctl,
1734572ff6f6SMatthew Dillon int16_t *nf_ext);
1735572ff6f6SMatthew Dillon
1736572ff6f6SMatthew Dillon /*
1737572ff6f6SMatthew Dillon * Calibrate noise floor data following a channel scan or similar.
1738572ff6f6SMatthew Dillon * This must be called prior retrieving noise floor data.
1739572ff6f6SMatthew Dillon */
1740572ff6f6SMatthew Dillon extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
1741572ff6f6SMatthew Dillon
1742572ff6f6SMatthew Dillon /*
1743572ff6f6SMatthew Dillon * Return bit mask of wireless modes supported by the hardware.
1744572ff6f6SMatthew Dillon */
1745572ff6f6SMatthew Dillon extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*);
1746572ff6f6SMatthew Dillon
1747572ff6f6SMatthew Dillon /*
1748572ff6f6SMatthew Dillon * Get the HAL wireless mode for the given channel.
1749572ff6f6SMatthew Dillon */
1750572ff6f6SMatthew Dillon extern int ath_hal_get_curmode(struct ath_hal *ah,
1751572ff6f6SMatthew Dillon const struct ieee80211_channel *chan);
1752572ff6f6SMatthew Dillon
1753572ff6f6SMatthew Dillon /*
1754572ff6f6SMatthew Dillon * Calculate the packet TX time for a legacy or 11n frame
1755572ff6f6SMatthew Dillon */
1756572ff6f6SMatthew Dillon extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah,
1757572ff6f6SMatthew Dillon const HAL_RATE_TABLE *rates, uint32_t frameLen,
1758572ff6f6SMatthew Dillon uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble);
1759572ff6f6SMatthew Dillon
1760572ff6f6SMatthew Dillon /*
1761572ff6f6SMatthew Dillon * Calculate the duration of an 11n frame.
1762572ff6f6SMatthew Dillon */
1763572ff6f6SMatthew Dillon extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate,
1764572ff6f6SMatthew Dillon int streams, HAL_BOOL isht40, HAL_BOOL isShortGI);
1765572ff6f6SMatthew Dillon
1766572ff6f6SMatthew Dillon /*
1767572ff6f6SMatthew Dillon * Calculate the transmit duration of a legacy frame.
1768572ff6f6SMatthew Dillon */
1769572ff6f6SMatthew Dillon extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
1770572ff6f6SMatthew Dillon const HAL_RATE_TABLE *rates, uint32_t frameLen,
1771572ff6f6SMatthew Dillon uint16_t rateix, HAL_BOOL shortPreamble);
1772572ff6f6SMatthew Dillon
1773572ff6f6SMatthew Dillon /*
1774572ff6f6SMatthew Dillon * Adjust the TSF.
1775572ff6f6SMatthew Dillon */
1776572ff6f6SMatthew Dillon extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta);
1777572ff6f6SMatthew Dillon
1778572ff6f6SMatthew Dillon /*
1779572ff6f6SMatthew Dillon * Enable or disable CCA.
1780572ff6f6SMatthew Dillon */
1781572ff6f6SMatthew Dillon void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena);
1782572ff6f6SMatthew Dillon
1783572ff6f6SMatthew Dillon /*
1784572ff6f6SMatthew Dillon * Get CCA setting.
1785572ff6f6SMatthew Dillon */
1786572ff6f6SMatthew Dillon int __ahdecl ath_hal_getcca(struct ath_hal *ah);
1787572ff6f6SMatthew Dillon
1788572ff6f6SMatthew Dillon /*
1789572ff6f6SMatthew Dillon * Read EEPROM data from ah_eepromdata
1790572ff6f6SMatthew Dillon */
1791572ff6f6SMatthew Dillon HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah,
1792572ff6f6SMatthew Dillon u_int off, uint16_t *data);
1793572ff6f6SMatthew Dillon
1794572ff6f6SMatthew Dillon /*
1795572ff6f6SMatthew Dillon * For now, simply pass through MFP frames.
1796572ff6f6SMatthew Dillon */
1797572ff6f6SMatthew Dillon static inline u_int32_t
ath_hal_get_mfp_qos(struct ath_hal * ah)1798572ff6f6SMatthew Dillon ath_hal_get_mfp_qos(struct ath_hal *ah)
1799572ff6f6SMatthew Dillon {
1800572ff6f6SMatthew Dillon //return AH_PRIVATE(ah)->ah_mfp_qos;
1801572ff6f6SMatthew Dillon return HAL_MFP_QOSDATA;
1802572ff6f6SMatthew Dillon }
1803572ff6f6SMatthew Dillon
1804572ff6f6SMatthew Dillon #endif /* _ATH_AH_H_ */
1805