1572ff6f6SMatthew Dillon /*
2572ff6f6SMatthew Dillon * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc.
4572ff6f6SMatthew Dillon *
5572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8572ff6f6SMatthew Dillon *
9572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16572ff6f6SMatthew Dillon *
17572ff6f6SMatthew Dillon * $FreeBSD$
18572ff6f6SMatthew Dillon */
19572ff6f6SMatthew Dillon #include "opt_ah.h"
20572ff6f6SMatthew Dillon
21572ff6f6SMatthew Dillon #include "ah.h"
22572ff6f6SMatthew Dillon #include "ah_internal.h"
23572ff6f6SMatthew Dillon
24572ff6f6SMatthew Dillon #include "ah_eeprom_v3.h"
25572ff6f6SMatthew Dillon
26572ff6f6SMatthew Dillon #include "ar5212/ar5212.h"
27572ff6f6SMatthew Dillon #include "ar5212/ar5212reg.h"
28572ff6f6SMatthew Dillon #include "ar5212/ar5212phy.h"
29572ff6f6SMatthew Dillon
30572ff6f6SMatthew Dillon #define AH_5212_5112
31572ff6f6SMatthew Dillon #include "ar5212/ar5212.ini"
32572ff6f6SMatthew Dillon
33572ff6f6SMatthew Dillon #define N(a) (sizeof(a)/sizeof(a[0]))
34572ff6f6SMatthew Dillon
35572ff6f6SMatthew Dillon struct ar5112State {
36572ff6f6SMatthew Dillon RF_HAL_FUNCS base; /* public state, must be first */
37572ff6f6SMatthew Dillon uint16_t pcdacTable[PWR_TABLE_SIZE];
38572ff6f6SMatthew Dillon
39572ff6f6SMatthew Dillon uint32_t Bank1Data[N(ar5212Bank1_5112)];
40572ff6f6SMatthew Dillon uint32_t Bank2Data[N(ar5212Bank2_5112)];
41572ff6f6SMatthew Dillon uint32_t Bank3Data[N(ar5212Bank3_5112)];
42572ff6f6SMatthew Dillon uint32_t Bank6Data[N(ar5212Bank6_5112)];
43572ff6f6SMatthew Dillon uint32_t Bank7Data[N(ar5212Bank7_5112)];
44572ff6f6SMatthew Dillon };
45572ff6f6SMatthew Dillon #define AR5112(ah) ((struct ar5112State *) AH5212(ah)->ah_rfHal)
46572ff6f6SMatthew Dillon
47572ff6f6SMatthew Dillon static void ar5212GetLowerUpperIndex(uint16_t v,
48572ff6f6SMatthew Dillon uint16_t *lp, uint16_t listSize,
49572ff6f6SMatthew Dillon uint32_t *vlo, uint32_t *vhi);
50572ff6f6SMatthew Dillon static HAL_BOOL getFullPwrTable(uint16_t numPcdacs, uint16_t *pcdacs,
51572ff6f6SMatthew Dillon int16_t *power, int16_t maxPower, int16_t *retVals);
52572ff6f6SMatthew Dillon static int16_t getPminAndPcdacTableFromPowerTable(int16_t *pwrTableT4,
53572ff6f6SMatthew Dillon uint16_t retVals[]);
54572ff6f6SMatthew Dillon static int16_t getPminAndPcdacTableFromTwoPowerTables(int16_t *pwrTableLXpdT4,
55572ff6f6SMatthew Dillon int16_t *pwrTableHXpdT4, uint16_t retVals[], int16_t *pMid);
56572ff6f6SMatthew Dillon static int16_t interpolate_signed(uint16_t target,
57572ff6f6SMatthew Dillon uint16_t srcLeft, uint16_t srcRight,
58572ff6f6SMatthew Dillon int16_t targetLeft, int16_t targetRight);
59572ff6f6SMatthew Dillon
60572ff6f6SMatthew Dillon extern void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
61572ff6f6SMatthew Dillon uint32_t numBits, uint32_t firstBit, uint32_t column);
62572ff6f6SMatthew Dillon
63572ff6f6SMatthew Dillon static void
ar5112WriteRegs(struct ath_hal * ah,u_int modesIndex,u_int freqIndex,int writes)64572ff6f6SMatthew Dillon ar5112WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
65572ff6f6SMatthew Dillon int writes)
66572ff6f6SMatthew Dillon {
67572ff6f6SMatthew Dillon HAL_INI_WRITE_ARRAY(ah, ar5212Modes_5112, modesIndex, writes);
68572ff6f6SMatthew Dillon HAL_INI_WRITE_ARRAY(ah, ar5212Common_5112, 1, writes);
69572ff6f6SMatthew Dillon HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_5112, freqIndex, writes);
70572ff6f6SMatthew Dillon }
71572ff6f6SMatthew Dillon
72572ff6f6SMatthew Dillon /*
73572ff6f6SMatthew Dillon * Take the MHz channel value and set the Channel value
74572ff6f6SMatthew Dillon *
75572ff6f6SMatthew Dillon * ASSUMES: Writes enabled to analog bus
76572ff6f6SMatthew Dillon */
77572ff6f6SMatthew Dillon static HAL_BOOL
ar5112SetChannel(struct ath_hal * ah,const struct ieee80211_channel * chan)78572ff6f6SMatthew Dillon ar5112SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
79572ff6f6SMatthew Dillon {
80572ff6f6SMatthew Dillon uint16_t freq = ath_hal_gethwchannel(ah, chan);
81572ff6f6SMatthew Dillon uint32_t channelSel = 0;
82572ff6f6SMatthew Dillon uint32_t bModeSynth = 0;
83572ff6f6SMatthew Dillon uint32_t aModeRefSel = 0;
84572ff6f6SMatthew Dillon uint32_t reg32 = 0;
85572ff6f6SMatthew Dillon
86572ff6f6SMatthew Dillon OS_MARK(ah, AH_MARK_SETCHANNEL, freq);
87572ff6f6SMatthew Dillon
88572ff6f6SMatthew Dillon if (freq < 4800) {
89572ff6f6SMatthew Dillon uint32_t txctl;
90572ff6f6SMatthew Dillon
91572ff6f6SMatthew Dillon if (((freq - 2192) % 5) == 0) {
92572ff6f6SMatthew Dillon channelSel = ((freq - 672) * 2 - 3040)/10;
93572ff6f6SMatthew Dillon bModeSynth = 0;
94572ff6f6SMatthew Dillon } else if (((freq - 2224) % 5) == 0) {
95572ff6f6SMatthew Dillon channelSel = ((freq - 704) * 2 - 3040) / 10;
96572ff6f6SMatthew Dillon bModeSynth = 1;
97572ff6f6SMatthew Dillon } else {
98572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
99572ff6f6SMatthew Dillon "%s: invalid channel %u MHz\n",
100572ff6f6SMatthew Dillon __func__, freq);
101572ff6f6SMatthew Dillon return AH_FALSE;
102572ff6f6SMatthew Dillon }
103572ff6f6SMatthew Dillon
104572ff6f6SMatthew Dillon channelSel = (channelSel << 2) & 0xff;
105572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(channelSel, 8);
106572ff6f6SMatthew Dillon
107572ff6f6SMatthew Dillon txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
108572ff6f6SMatthew Dillon if (freq == 2484) {
109572ff6f6SMatthew Dillon /* Enable channel spreading for channel 14 */
110572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
111572ff6f6SMatthew Dillon txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
112572ff6f6SMatthew Dillon } else {
113572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
114572ff6f6SMatthew Dillon txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
115572ff6f6SMatthew Dillon }
116572ff6f6SMatthew Dillon } else if (((freq % 5) == 2) && (freq <= 5435)) {
117572ff6f6SMatthew Dillon freq = freq - 2; /* Align to even 5MHz raster */
118572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(
119572ff6f6SMatthew Dillon (uint32_t)(((freq - 4800)*10)/25 + 1), 8);
120572ff6f6SMatthew Dillon aModeRefSel = ath_hal_reverseBits(0, 2);
121572ff6f6SMatthew Dillon } else if ((freq % 20) == 0 && freq >= 5120) {
122572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(
123572ff6f6SMatthew Dillon ((freq - 4800) / 20 << 2), 8);
124572ff6f6SMatthew Dillon aModeRefSel = ath_hal_reverseBits(3, 2);
125572ff6f6SMatthew Dillon } else if ((freq % 10) == 0) {
126572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(
127572ff6f6SMatthew Dillon ((freq - 4800) / 10 << 1), 8);
128572ff6f6SMatthew Dillon aModeRefSel = ath_hal_reverseBits(2, 2);
129572ff6f6SMatthew Dillon } else if ((freq % 5) == 0) {
130572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(
131572ff6f6SMatthew Dillon (freq - 4800) / 5, 8);
132572ff6f6SMatthew Dillon aModeRefSel = ath_hal_reverseBits(1, 2);
133572ff6f6SMatthew Dillon } else {
134572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
135572ff6f6SMatthew Dillon __func__, freq);
136572ff6f6SMatthew Dillon return AH_FALSE;
137572ff6f6SMatthew Dillon }
138572ff6f6SMatthew Dillon
139572ff6f6SMatthew Dillon reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
140572ff6f6SMatthew Dillon (1 << 12) | 0x1;
141572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
142572ff6f6SMatthew Dillon
143572ff6f6SMatthew Dillon reg32 >>= 8;
144572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);
145572ff6f6SMatthew Dillon
146572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_curchan = chan;
147572ff6f6SMatthew Dillon return AH_TRUE;
148572ff6f6SMatthew Dillon }
149572ff6f6SMatthew Dillon
150572ff6f6SMatthew Dillon /*
151572ff6f6SMatthew Dillon * Return a reference to the requested RF Bank.
152572ff6f6SMatthew Dillon */
153572ff6f6SMatthew Dillon static uint32_t *
ar5112GetRfBank(struct ath_hal * ah,int bank)154572ff6f6SMatthew Dillon ar5112GetRfBank(struct ath_hal *ah, int bank)
155572ff6f6SMatthew Dillon {
156572ff6f6SMatthew Dillon struct ar5112State *priv = AR5112(ah);
157572ff6f6SMatthew Dillon
158572ff6f6SMatthew Dillon HALASSERT(priv != AH_NULL);
159572ff6f6SMatthew Dillon switch (bank) {
160572ff6f6SMatthew Dillon case 1: return priv->Bank1Data;
161572ff6f6SMatthew Dillon case 2: return priv->Bank2Data;
162572ff6f6SMatthew Dillon case 3: return priv->Bank3Data;
163572ff6f6SMatthew Dillon case 6: return priv->Bank6Data;
164572ff6f6SMatthew Dillon case 7: return priv->Bank7Data;
165572ff6f6SMatthew Dillon }
166572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
167572ff6f6SMatthew Dillon __func__, bank);
168572ff6f6SMatthew Dillon return AH_NULL;
169572ff6f6SMatthew Dillon }
170572ff6f6SMatthew Dillon
171572ff6f6SMatthew Dillon /*
172572ff6f6SMatthew Dillon * Reads EEPROM header info from device structure and programs
173572ff6f6SMatthew Dillon * all rf registers
174572ff6f6SMatthew Dillon *
175572ff6f6SMatthew Dillon * REQUIRES: Access to the analog rf device
176572ff6f6SMatthew Dillon */
177572ff6f6SMatthew Dillon static HAL_BOOL
ar5112SetRfRegs(struct ath_hal * ah,const struct ieee80211_channel * chan,uint16_t modesIndex,uint16_t * rfXpdGain)178572ff6f6SMatthew Dillon ar5112SetRfRegs(struct ath_hal *ah,
179572ff6f6SMatthew Dillon const struct ieee80211_channel *chan,
180572ff6f6SMatthew Dillon uint16_t modesIndex, uint16_t *rfXpdGain)
181572ff6f6SMatthew Dillon {
182572ff6f6SMatthew Dillon #define RF_BANK_SETUP(_priv, _ix, _col) do { \
183572ff6f6SMatthew Dillon int i; \
184572ff6f6SMatthew Dillon for (i = 0; i < N(ar5212Bank##_ix##_5112); i++) \
185572ff6f6SMatthew Dillon (_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_5112[i][_col];\
186572ff6f6SMatthew Dillon } while (0)
187572ff6f6SMatthew Dillon uint16_t freq = ath_hal_gethwchannel(ah, chan);
188572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
189572ff6f6SMatthew Dillon const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
190572ff6f6SMatthew Dillon uint16_t rfXpdSel, gainI;
191572ff6f6SMatthew Dillon uint16_t ob5GHz = 0, db5GHz = 0;
192572ff6f6SMatthew Dillon uint16_t ob2GHz = 0, db2GHz = 0;
193572ff6f6SMatthew Dillon struct ar5112State *priv = AR5112(ah);
194572ff6f6SMatthew Dillon GAIN_VALUES *gv = &ahp->ah_gainValues;
195572ff6f6SMatthew Dillon int regWrites = 0;
196572ff6f6SMatthew Dillon
197572ff6f6SMatthew Dillon HALASSERT(priv);
198572ff6f6SMatthew Dillon
199572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
200572ff6f6SMatthew Dillon __func__, chan->ic_freq, chan->ic_flags, modesIndex);
201572ff6f6SMatthew Dillon
202572ff6f6SMatthew Dillon /* Setup rf parameters */
203572ff6f6SMatthew Dillon switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
204572ff6f6SMatthew Dillon case IEEE80211_CHAN_A:
205572ff6f6SMatthew Dillon if (freq > 4000 && freq < 5260) {
206572ff6f6SMatthew Dillon ob5GHz = ee->ee_ob1;
207572ff6f6SMatthew Dillon db5GHz = ee->ee_db1;
208572ff6f6SMatthew Dillon } else if (freq >= 5260 && freq < 5500) {
209572ff6f6SMatthew Dillon ob5GHz = ee->ee_ob2;
210572ff6f6SMatthew Dillon db5GHz = ee->ee_db2;
211572ff6f6SMatthew Dillon } else if (freq >= 5500 && freq < 5725) {
212572ff6f6SMatthew Dillon ob5GHz = ee->ee_ob3;
213572ff6f6SMatthew Dillon db5GHz = ee->ee_db3;
214572ff6f6SMatthew Dillon } else if (freq >= 5725) {
215572ff6f6SMatthew Dillon ob5GHz = ee->ee_ob4;
216572ff6f6SMatthew Dillon db5GHz = ee->ee_db4;
217572ff6f6SMatthew Dillon } else {
218572ff6f6SMatthew Dillon /* XXX else */
219572ff6f6SMatthew Dillon }
220572ff6f6SMatthew Dillon rfXpdSel = ee->ee_xpd[headerInfo11A];
221572ff6f6SMatthew Dillon gainI = ee->ee_gainI[headerInfo11A];
222572ff6f6SMatthew Dillon break;
223572ff6f6SMatthew Dillon case IEEE80211_CHAN_B:
224572ff6f6SMatthew Dillon ob2GHz = ee->ee_ob2GHz[0];
225572ff6f6SMatthew Dillon db2GHz = ee->ee_db2GHz[0];
226572ff6f6SMatthew Dillon rfXpdSel = ee->ee_xpd[headerInfo11B];
227572ff6f6SMatthew Dillon gainI = ee->ee_gainI[headerInfo11B];
228572ff6f6SMatthew Dillon break;
229572ff6f6SMatthew Dillon case IEEE80211_CHAN_G:
230572ff6f6SMatthew Dillon case IEEE80211_CHAN_PUREG: /* NB: really 108G */
231572ff6f6SMatthew Dillon ob2GHz = ee->ee_ob2GHz[1];
232572ff6f6SMatthew Dillon db2GHz = ee->ee_ob2GHz[1];
233572ff6f6SMatthew Dillon rfXpdSel = ee->ee_xpd[headerInfo11G];
234572ff6f6SMatthew Dillon gainI = ee->ee_gainI[headerInfo11G];
235572ff6f6SMatthew Dillon break;
236572ff6f6SMatthew Dillon default:
237572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
238572ff6f6SMatthew Dillon __func__, chan->ic_flags);
239572ff6f6SMatthew Dillon return AH_FALSE;
240572ff6f6SMatthew Dillon }
241572ff6f6SMatthew Dillon
242572ff6f6SMatthew Dillon /* Setup Bank 1 Write */
243572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 1, 1);
244572ff6f6SMatthew Dillon
245572ff6f6SMatthew Dillon /* Setup Bank 2 Write */
246572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 2, modesIndex);
247572ff6f6SMatthew Dillon
248572ff6f6SMatthew Dillon /* Setup Bank 3 Write */
249572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 3, modesIndex);
250572ff6f6SMatthew Dillon
251572ff6f6SMatthew Dillon /* Setup Bank 6 Write */
252572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 6, modesIndex);
253572ff6f6SMatthew Dillon
254572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, rfXpdSel, 1, 302, 0);
255572ff6f6SMatthew Dillon
256572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, rfXpdGain[0], 2, 270, 0);
257572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, rfXpdGain[1], 2, 257, 0);
258572ff6f6SMatthew Dillon
259572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_OFDM(chan)) {
260572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data,
261572ff6f6SMatthew Dillon gv->currStep->paramVal[GP_PWD_138], 1, 168, 3);
262572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data,
263572ff6f6SMatthew Dillon gv->currStep->paramVal[GP_PWD_137], 1, 169, 3);
264572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data,
265572ff6f6SMatthew Dillon gv->currStep->paramVal[GP_PWD_136], 1, 170, 3);
266572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data,
267572ff6f6SMatthew Dillon gv->currStep->paramVal[GP_PWD_132], 1, 174, 3);
268572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data,
269572ff6f6SMatthew Dillon gv->currStep->paramVal[GP_PWD_131], 1, 175, 3);
270572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data,
271572ff6f6SMatthew Dillon gv->currStep->paramVal[GP_PWD_130], 1, 176, 3);
272572ff6f6SMatthew Dillon }
273572ff6f6SMatthew Dillon
274572ff6f6SMatthew Dillon /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
275572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_2GHZ(chan)) {
276572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 287, 0);
277572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 290, 0);
278572ff6f6SMatthew Dillon } else {
279572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, ob5GHz, 3, 279, 0);
280572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, db5GHz, 3, 282, 0);
281572ff6f6SMatthew Dillon }
282572ff6f6SMatthew Dillon
283572ff6f6SMatthew Dillon /* Lower synth voltage for X112 Rev 2.0 only */
284572ff6f6SMatthew Dillon if (IS_RADX112_REV2(ah)) {
285572ff6f6SMatthew Dillon /* Non-Reversed analyg registers - so values are pre-reversed */
286572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, 2, 2, 90, 2);
287572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, 2, 2, 92, 2);
288572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, 2, 2, 94, 2);
289572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, 2, 1, 254, 2);
290572ff6f6SMatthew Dillon }
291572ff6f6SMatthew Dillon
292572ff6f6SMatthew Dillon /* Decrease Power Consumption for 5312/5213 and up */
293572ff6f6SMatthew Dillon if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {
294572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, 1, 1, 281, 1);
295572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, 1, 2, 1, 3);
296572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, 1, 2, 3, 3);
297572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, 1, 1, 139, 3);
298572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, 1, 1, 140, 3);
299572ff6f6SMatthew Dillon }
300572ff6f6SMatthew Dillon
301572ff6f6SMatthew Dillon /* Setup Bank 7 Setup */
302572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 7, modesIndex);
303572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_OFDM(chan))
304572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank7Data,
305572ff6f6SMatthew Dillon gv->currStep->paramVal[GP_MIXGAIN_OVR], 2, 37, 0);
306572ff6f6SMatthew Dillon
307572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank7Data, gainI, 6, 14, 0);
308572ff6f6SMatthew Dillon
309572ff6f6SMatthew Dillon /* Adjust params for Derby TX power control */
310572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan)) {
311572ff6f6SMatthew Dillon uint32_t rfDelay, rfPeriod;
312572ff6f6SMatthew Dillon
313572ff6f6SMatthew Dillon rfDelay = 0xf;
314572ff6f6SMatthew Dillon rfPeriod = (IEEE80211_IS_CHAN_HALF(chan)) ? 0x8 : 0xf;
315572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank7Data, rfDelay, 4, 58, 0);
316572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank7Data, rfPeriod, 4, 70, 0);
317572ff6f6SMatthew Dillon }
318572ff6f6SMatthew Dillon
319572ff6f6SMatthew Dillon #ifdef notyet
320572ff6f6SMatthew Dillon /* Analog registers are setup - EAR can modify */
321572ff6f6SMatthew Dillon if (ar5212IsEarEngaged(pDev, chan))
322572ff6f6SMatthew Dillon uint32_t modifier;
323572ff6f6SMatthew Dillon ar5212EarModify(pDev, EAR_LC_RF_WRITE, chan, &modifier);
324572ff6f6SMatthew Dillon #endif
325572ff6f6SMatthew Dillon /* Write Analog registers */
326572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank1_5112, priv->Bank1Data, regWrites);
327572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank2_5112, priv->Bank2Data, regWrites);
328572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank3_5112, priv->Bank3Data, regWrites);
329572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank6_5112, priv->Bank6Data, regWrites);
330572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank7_5112, priv->Bank7Data, regWrites);
331572ff6f6SMatthew Dillon
332572ff6f6SMatthew Dillon /* Now that we have reprogrammed rfgain value, clear the flag. */
333572ff6f6SMatthew Dillon ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
334572ff6f6SMatthew Dillon return AH_TRUE;
335572ff6f6SMatthew Dillon #undef RF_BANK_SETUP
336572ff6f6SMatthew Dillon }
337572ff6f6SMatthew Dillon
338572ff6f6SMatthew Dillon /*
339572ff6f6SMatthew Dillon * Read the transmit power levels from the structures taken from EEPROM
340572ff6f6SMatthew Dillon * Interpolate read transmit power values for this channel
341572ff6f6SMatthew Dillon * Organize the transmit power values into a table for writing into the hardware
342572ff6f6SMatthew Dillon */
343572ff6f6SMatthew Dillon static HAL_BOOL
ar5112SetPowerTable(struct ath_hal * ah,int16_t * pPowerMin,int16_t * pPowerMax,const struct ieee80211_channel * chan,uint16_t * rfXpdGain)344572ff6f6SMatthew Dillon ar5112SetPowerTable(struct ath_hal *ah,
345572ff6f6SMatthew Dillon int16_t *pPowerMin, int16_t *pPowerMax,
346572ff6f6SMatthew Dillon const struct ieee80211_channel *chan,
347572ff6f6SMatthew Dillon uint16_t *rfXpdGain)
348572ff6f6SMatthew Dillon {
349572ff6f6SMatthew Dillon uint16_t freq = ath_hal_gethwchannel(ah, chan);
350572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
351572ff6f6SMatthew Dillon const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
352572ff6f6SMatthew Dillon uint32_t numXpdGain = IS_RADX112_REV2(ah) ? 2 : 1;
353572ff6f6SMatthew Dillon uint32_t xpdGainMask = 0;
354572ff6f6SMatthew Dillon int16_t powerMid, *pPowerMid = &powerMid;
355572ff6f6SMatthew Dillon
356572ff6f6SMatthew Dillon const EXPN_DATA_PER_CHANNEL_5112 *pRawCh;
357572ff6f6SMatthew Dillon const EEPROM_POWER_EXPN_5112 *pPowerExpn = AH_NULL;
358572ff6f6SMatthew Dillon
359572ff6f6SMatthew Dillon uint32_t ii, jj, kk;
360572ff6f6SMatthew Dillon int16_t minPwr_t4, maxPwr_t4, Pmin, Pmid;
361572ff6f6SMatthew Dillon
362572ff6f6SMatthew Dillon uint32_t chan_idx_L = 0, chan_idx_R = 0;
363572ff6f6SMatthew Dillon uint16_t chan_L, chan_R;
364572ff6f6SMatthew Dillon
365572ff6f6SMatthew Dillon int16_t pwr_table0[64];
366572ff6f6SMatthew Dillon int16_t pwr_table1[64];
367572ff6f6SMatthew Dillon uint16_t pcdacs[10];
368572ff6f6SMatthew Dillon int16_t powers[10];
369572ff6f6SMatthew Dillon uint16_t numPcd;
370572ff6f6SMatthew Dillon int16_t powTableLXPD[2][64];
371572ff6f6SMatthew Dillon int16_t powTableHXPD[2][64];
372572ff6f6SMatthew Dillon int16_t tmpPowerTable[64];
373572ff6f6SMatthew Dillon uint16_t xgainList[2];
374572ff6f6SMatthew Dillon uint16_t xpdMask;
375572ff6f6SMatthew Dillon
376572ff6f6SMatthew Dillon switch (chan->ic_flags & IEEE80211_CHAN_ALLTURBOFULL) {
377572ff6f6SMatthew Dillon case IEEE80211_CHAN_A:
378572ff6f6SMatthew Dillon case IEEE80211_CHAN_ST:
379572ff6f6SMatthew Dillon pPowerExpn = &ee->ee_modePowerArray5112[headerInfo11A];
380572ff6f6SMatthew Dillon xpdGainMask = ee->ee_xgain[headerInfo11A];
381572ff6f6SMatthew Dillon break;
382572ff6f6SMatthew Dillon case IEEE80211_CHAN_B:
383572ff6f6SMatthew Dillon pPowerExpn = &ee->ee_modePowerArray5112[headerInfo11B];
384572ff6f6SMatthew Dillon xpdGainMask = ee->ee_xgain[headerInfo11B];
385572ff6f6SMatthew Dillon break;
386572ff6f6SMatthew Dillon case IEEE80211_CHAN_G:
387572ff6f6SMatthew Dillon case IEEE80211_CHAN_108G:
388572ff6f6SMatthew Dillon pPowerExpn = &ee->ee_modePowerArray5112[headerInfo11G];
389572ff6f6SMatthew Dillon xpdGainMask = ee->ee_xgain[headerInfo11G];
390572ff6f6SMatthew Dillon break;
391572ff6f6SMatthew Dillon default:
392572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown channel flags 0x%x\n",
393572ff6f6SMatthew Dillon __func__, chan->ic_flags);
394572ff6f6SMatthew Dillon return AH_FALSE;
395572ff6f6SMatthew Dillon }
396572ff6f6SMatthew Dillon
397572ff6f6SMatthew Dillon if ((xpdGainMask & pPowerExpn->xpdMask) < 1) {
398572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
399572ff6f6SMatthew Dillon "%s: desired xpdGainMask 0x%x not supported by "
400572ff6f6SMatthew Dillon "calibrated xpdMask 0x%x\n", __func__,
401572ff6f6SMatthew Dillon xpdGainMask, pPowerExpn->xpdMask);
402572ff6f6SMatthew Dillon return AH_FALSE;
403572ff6f6SMatthew Dillon }
404572ff6f6SMatthew Dillon
405572ff6f6SMatthew Dillon maxPwr_t4 = (int16_t)(2*(*pPowerMax)); /* pwr_t2 -> pwr_t4 */
406572ff6f6SMatthew Dillon minPwr_t4 = (int16_t)(2*(*pPowerMin)); /* pwr_t2 -> pwr_t4 */
407572ff6f6SMatthew Dillon
408572ff6f6SMatthew Dillon xgainList[0] = 0xDEAD;
409572ff6f6SMatthew Dillon xgainList[1] = 0xDEAD;
410572ff6f6SMatthew Dillon
411572ff6f6SMatthew Dillon kk = 0;
412572ff6f6SMatthew Dillon xpdMask = pPowerExpn->xpdMask;
413572ff6f6SMatthew Dillon for (jj = 0; jj < NUM_XPD_PER_CHANNEL; jj++) {
414572ff6f6SMatthew Dillon if (((xpdMask >> jj) & 1) > 0) {
415572ff6f6SMatthew Dillon if (kk > 1) {
416572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
417572ff6f6SMatthew Dillon "A maximum of 2 xpdGains supported"
418572ff6f6SMatthew Dillon "in pExpnPower data\n");
419572ff6f6SMatthew Dillon return AH_FALSE;
420572ff6f6SMatthew Dillon }
421572ff6f6SMatthew Dillon xgainList[kk++] = (uint16_t)jj;
422572ff6f6SMatthew Dillon }
423572ff6f6SMatthew Dillon }
424572ff6f6SMatthew Dillon
425572ff6f6SMatthew Dillon ar5212GetLowerUpperIndex(freq, &pPowerExpn->pChannels[0],
426572ff6f6SMatthew Dillon pPowerExpn->numChannels, &chan_idx_L, &chan_idx_R);
427572ff6f6SMatthew Dillon
428572ff6f6SMatthew Dillon kk = 0;
429572ff6f6SMatthew Dillon for (ii = chan_idx_L; ii <= chan_idx_R; ii++) {
430572ff6f6SMatthew Dillon pRawCh = &(pPowerExpn->pDataPerChannel[ii]);
431572ff6f6SMatthew Dillon if (xgainList[1] == 0xDEAD) {
432572ff6f6SMatthew Dillon jj = xgainList[0];
433572ff6f6SMatthew Dillon numPcd = pRawCh->pDataPerXPD[jj].numPcdacs;
434572ff6f6SMatthew Dillon OS_MEMCPY(&pcdacs[0], &pRawCh->pDataPerXPD[jj].pcdac[0],
435572ff6f6SMatthew Dillon numPcd * sizeof(uint16_t));
436572ff6f6SMatthew Dillon OS_MEMCPY(&powers[0], &pRawCh->pDataPerXPD[jj].pwr_t4[0],
437572ff6f6SMatthew Dillon numPcd * sizeof(int16_t));
438572ff6f6SMatthew Dillon if (!getFullPwrTable(numPcd, &pcdacs[0], &powers[0],
439572ff6f6SMatthew Dillon pRawCh->maxPower_t4, &tmpPowerTable[0])) {
440572ff6f6SMatthew Dillon return AH_FALSE;
441572ff6f6SMatthew Dillon }
442572ff6f6SMatthew Dillon OS_MEMCPY(&powTableLXPD[kk][0], &tmpPowerTable[0],
443572ff6f6SMatthew Dillon 64*sizeof(int16_t));
444572ff6f6SMatthew Dillon } else {
445572ff6f6SMatthew Dillon jj = xgainList[0];
446572ff6f6SMatthew Dillon numPcd = pRawCh->pDataPerXPD[jj].numPcdacs;
447572ff6f6SMatthew Dillon OS_MEMCPY(&pcdacs[0], &pRawCh->pDataPerXPD[jj].pcdac[0],
448572ff6f6SMatthew Dillon numPcd*sizeof(uint16_t));
449572ff6f6SMatthew Dillon OS_MEMCPY(&powers[0],
450572ff6f6SMatthew Dillon &pRawCh->pDataPerXPD[jj].pwr_t4[0],
451572ff6f6SMatthew Dillon numPcd*sizeof(int16_t));
452572ff6f6SMatthew Dillon if (!getFullPwrTable(numPcd, &pcdacs[0], &powers[0],
453572ff6f6SMatthew Dillon pRawCh->maxPower_t4, &tmpPowerTable[0])) {
454572ff6f6SMatthew Dillon return AH_FALSE;
455572ff6f6SMatthew Dillon }
456572ff6f6SMatthew Dillon OS_MEMCPY(&powTableLXPD[kk][0], &tmpPowerTable[0],
457572ff6f6SMatthew Dillon 64 * sizeof(int16_t));
458572ff6f6SMatthew Dillon
459572ff6f6SMatthew Dillon jj = xgainList[1];
460572ff6f6SMatthew Dillon numPcd = pRawCh->pDataPerXPD[jj].numPcdacs;
461572ff6f6SMatthew Dillon OS_MEMCPY(&pcdacs[0], &pRawCh->pDataPerXPD[jj].pcdac[0],
462572ff6f6SMatthew Dillon numPcd * sizeof(uint16_t));
463572ff6f6SMatthew Dillon OS_MEMCPY(&powers[0],
464572ff6f6SMatthew Dillon &pRawCh->pDataPerXPD[jj].pwr_t4[0],
465572ff6f6SMatthew Dillon numPcd * sizeof(int16_t));
466572ff6f6SMatthew Dillon if (!getFullPwrTable(numPcd, &pcdacs[0], &powers[0],
467572ff6f6SMatthew Dillon pRawCh->maxPower_t4, &tmpPowerTable[0])) {
468572ff6f6SMatthew Dillon return AH_FALSE;
469572ff6f6SMatthew Dillon }
470572ff6f6SMatthew Dillon OS_MEMCPY(&powTableHXPD[kk][0], &tmpPowerTable[0],
471572ff6f6SMatthew Dillon 64 * sizeof(int16_t));
472572ff6f6SMatthew Dillon }
473572ff6f6SMatthew Dillon kk++;
474572ff6f6SMatthew Dillon }
475572ff6f6SMatthew Dillon
476572ff6f6SMatthew Dillon chan_L = pPowerExpn->pChannels[chan_idx_L];
477572ff6f6SMatthew Dillon chan_R = pPowerExpn->pChannels[chan_idx_R];
478572ff6f6SMatthew Dillon kk = chan_idx_R - chan_idx_L;
479572ff6f6SMatthew Dillon
480572ff6f6SMatthew Dillon if (xgainList[1] == 0xDEAD) {
481572ff6f6SMatthew Dillon for (jj = 0; jj < 64; jj++) {
482572ff6f6SMatthew Dillon pwr_table0[jj] = interpolate_signed(
483572ff6f6SMatthew Dillon freq, chan_L, chan_R,
484572ff6f6SMatthew Dillon powTableLXPD[0][jj], powTableLXPD[kk][jj]);
485572ff6f6SMatthew Dillon }
486572ff6f6SMatthew Dillon Pmin = getPminAndPcdacTableFromPowerTable(&pwr_table0[0],
487572ff6f6SMatthew Dillon ahp->ah_pcdacTable);
488572ff6f6SMatthew Dillon *pPowerMin = (int16_t) (Pmin / 2);
489572ff6f6SMatthew Dillon *pPowerMid = (int16_t) (pwr_table0[63] / 2);
490572ff6f6SMatthew Dillon *pPowerMax = (int16_t) (pwr_table0[63] / 2);
491572ff6f6SMatthew Dillon rfXpdGain[0] = xgainList[0];
492572ff6f6SMatthew Dillon rfXpdGain[1] = rfXpdGain[0];
493572ff6f6SMatthew Dillon } else {
494572ff6f6SMatthew Dillon for (jj = 0; jj < 64; jj++) {
495572ff6f6SMatthew Dillon pwr_table0[jj] = interpolate_signed(
496572ff6f6SMatthew Dillon freq, chan_L, chan_R,
497572ff6f6SMatthew Dillon powTableLXPD[0][jj], powTableLXPD[kk][jj]);
498572ff6f6SMatthew Dillon pwr_table1[jj] = interpolate_signed(
499572ff6f6SMatthew Dillon freq, chan_L, chan_R,
500572ff6f6SMatthew Dillon powTableHXPD[0][jj], powTableHXPD[kk][jj]);
501572ff6f6SMatthew Dillon }
502572ff6f6SMatthew Dillon if (numXpdGain == 2) {
503572ff6f6SMatthew Dillon Pmin = getPminAndPcdacTableFromTwoPowerTables(
504572ff6f6SMatthew Dillon &pwr_table0[0], &pwr_table1[0],
505572ff6f6SMatthew Dillon ahp->ah_pcdacTable, &Pmid);
506572ff6f6SMatthew Dillon *pPowerMin = (int16_t) (Pmin / 2);
507572ff6f6SMatthew Dillon *pPowerMid = (int16_t) (Pmid / 2);
508572ff6f6SMatthew Dillon *pPowerMax = (int16_t) (pwr_table0[63] / 2);
509572ff6f6SMatthew Dillon rfXpdGain[0] = xgainList[0];
510572ff6f6SMatthew Dillon rfXpdGain[1] = xgainList[1];
511572ff6f6SMatthew Dillon } else if (minPwr_t4 <= pwr_table1[63] &&
512572ff6f6SMatthew Dillon maxPwr_t4 <= pwr_table1[63]) {
513572ff6f6SMatthew Dillon Pmin = getPminAndPcdacTableFromPowerTable(
514572ff6f6SMatthew Dillon &pwr_table1[0], ahp->ah_pcdacTable);
515572ff6f6SMatthew Dillon rfXpdGain[0] = xgainList[1];
516572ff6f6SMatthew Dillon rfXpdGain[1] = rfXpdGain[0];
517572ff6f6SMatthew Dillon *pPowerMin = (int16_t) (Pmin / 2);
518572ff6f6SMatthew Dillon *pPowerMid = (int16_t) (pwr_table1[63] / 2);
519572ff6f6SMatthew Dillon *pPowerMax = (int16_t) (pwr_table1[63] / 2);
520572ff6f6SMatthew Dillon } else {
521572ff6f6SMatthew Dillon Pmin = getPminAndPcdacTableFromPowerTable(
522572ff6f6SMatthew Dillon &pwr_table0[0], ahp->ah_pcdacTable);
523572ff6f6SMatthew Dillon rfXpdGain[0] = xgainList[0];
524572ff6f6SMatthew Dillon rfXpdGain[1] = rfXpdGain[0];
525572ff6f6SMatthew Dillon *pPowerMin = (int16_t) (Pmin/2);
526572ff6f6SMatthew Dillon *pPowerMid = (int16_t) (pwr_table0[63] / 2);
527572ff6f6SMatthew Dillon *pPowerMax = (int16_t) (pwr_table0[63] / 2);
528572ff6f6SMatthew Dillon }
529572ff6f6SMatthew Dillon }
530572ff6f6SMatthew Dillon
531572ff6f6SMatthew Dillon /*
532572ff6f6SMatthew Dillon * Move 5112 rates to match power tables where the max
533572ff6f6SMatthew Dillon * power table entry corresponds with maxPower.
534572ff6f6SMatthew Dillon */
535572ff6f6SMatthew Dillon HALASSERT(*pPowerMax <= PCDAC_STOP);
536572ff6f6SMatthew Dillon ahp->ah_txPowerIndexOffset = PCDAC_STOP - *pPowerMax;
537572ff6f6SMatthew Dillon
538572ff6f6SMatthew Dillon return AH_TRUE;
539572ff6f6SMatthew Dillon }
540572ff6f6SMatthew Dillon
541572ff6f6SMatthew Dillon /*
542572ff6f6SMatthew Dillon * Returns interpolated or the scaled up interpolated value
543572ff6f6SMatthew Dillon */
544572ff6f6SMatthew Dillon static int16_t
interpolate_signed(uint16_t target,uint16_t srcLeft,uint16_t srcRight,int16_t targetLeft,int16_t targetRight)545572ff6f6SMatthew Dillon interpolate_signed(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
546572ff6f6SMatthew Dillon int16_t targetLeft, int16_t targetRight)
547572ff6f6SMatthew Dillon {
548572ff6f6SMatthew Dillon int16_t rv;
549572ff6f6SMatthew Dillon
550572ff6f6SMatthew Dillon if (srcRight != srcLeft) {
551572ff6f6SMatthew Dillon rv = ((target - srcLeft)*targetRight +
552572ff6f6SMatthew Dillon (srcRight - target)*targetLeft) / (srcRight - srcLeft);
553572ff6f6SMatthew Dillon } else {
554572ff6f6SMatthew Dillon rv = targetLeft;
555572ff6f6SMatthew Dillon }
556572ff6f6SMatthew Dillon return rv;
557572ff6f6SMatthew Dillon }
558572ff6f6SMatthew Dillon
559572ff6f6SMatthew Dillon /*
560572ff6f6SMatthew Dillon * Return indices surrounding the value in sorted integer lists.
561572ff6f6SMatthew Dillon *
562572ff6f6SMatthew Dillon * NB: the input list is assumed to be sorted in ascending order
563572ff6f6SMatthew Dillon */
564572ff6f6SMatthew Dillon static void
ar5212GetLowerUpperIndex(uint16_t v,uint16_t * lp,uint16_t listSize,uint32_t * vlo,uint32_t * vhi)565572ff6f6SMatthew Dillon ar5212GetLowerUpperIndex(uint16_t v, uint16_t *lp, uint16_t listSize,
566572ff6f6SMatthew Dillon uint32_t *vlo, uint32_t *vhi)
567572ff6f6SMatthew Dillon {
568572ff6f6SMatthew Dillon uint32_t target = v;
569572ff6f6SMatthew Dillon uint16_t *ep = lp+listSize;
570572ff6f6SMatthew Dillon uint16_t *tp;
571572ff6f6SMatthew Dillon
572572ff6f6SMatthew Dillon /*
573572ff6f6SMatthew Dillon * Check first and last elements for out-of-bounds conditions.
574572ff6f6SMatthew Dillon */
575572ff6f6SMatthew Dillon if (target < lp[0]) {
576572ff6f6SMatthew Dillon *vlo = *vhi = 0;
577572ff6f6SMatthew Dillon return;
578572ff6f6SMatthew Dillon }
579572ff6f6SMatthew Dillon if (target >= ep[-1]) {
580572ff6f6SMatthew Dillon *vlo = *vhi = listSize - 1;
581572ff6f6SMatthew Dillon return;
582572ff6f6SMatthew Dillon }
583572ff6f6SMatthew Dillon
584572ff6f6SMatthew Dillon /* look for value being near or between 2 values in list */
585572ff6f6SMatthew Dillon for (tp = lp; tp < ep; tp++) {
586572ff6f6SMatthew Dillon /*
587572ff6f6SMatthew Dillon * If value is close to the current value of the list
588572ff6f6SMatthew Dillon * then target is not between values, it is one of the values
589572ff6f6SMatthew Dillon */
590572ff6f6SMatthew Dillon if (*tp == target) {
591572ff6f6SMatthew Dillon *vlo = *vhi = tp - lp;
592572ff6f6SMatthew Dillon return;
593572ff6f6SMatthew Dillon }
594572ff6f6SMatthew Dillon /*
595572ff6f6SMatthew Dillon * Look for value being between current value and next value
596572ff6f6SMatthew Dillon * if so return these 2 values
597572ff6f6SMatthew Dillon */
598572ff6f6SMatthew Dillon if (target < tp[1]) {
599572ff6f6SMatthew Dillon *vlo = tp - lp;
600572ff6f6SMatthew Dillon *vhi = *vlo + 1;
601572ff6f6SMatthew Dillon return;
602572ff6f6SMatthew Dillon }
603572ff6f6SMatthew Dillon }
604572ff6f6SMatthew Dillon }
605572ff6f6SMatthew Dillon
606572ff6f6SMatthew Dillon static HAL_BOOL
getFullPwrTable(uint16_t numPcdacs,uint16_t * pcdacs,int16_t * power,int16_t maxPower,int16_t * retVals)607572ff6f6SMatthew Dillon getFullPwrTable(uint16_t numPcdacs, uint16_t *pcdacs, int16_t *power, int16_t maxPower, int16_t *retVals)
608572ff6f6SMatthew Dillon {
609572ff6f6SMatthew Dillon uint16_t ii;
610572ff6f6SMatthew Dillon uint16_t idxL = 0;
611572ff6f6SMatthew Dillon uint16_t idxR = 1;
612572ff6f6SMatthew Dillon
613572ff6f6SMatthew Dillon if (numPcdacs < 2) {
614572ff6f6SMatthew Dillon HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
615572ff6f6SMatthew Dillon "%s: at least 2 pcdac values needed [%d]\n",
616572ff6f6SMatthew Dillon __func__, numPcdacs);
617572ff6f6SMatthew Dillon return AH_FALSE;
618572ff6f6SMatthew Dillon }
619572ff6f6SMatthew Dillon for (ii = 0; ii < 64; ii++) {
620*93d72667SSascha Wildner if (idxR < numPcdacs-1 && ii>pcdacs[idxR]) {
621572ff6f6SMatthew Dillon idxL++;
622572ff6f6SMatthew Dillon idxR++;
623572ff6f6SMatthew Dillon }
624572ff6f6SMatthew Dillon retVals[ii] = interpolate_signed(ii,
625572ff6f6SMatthew Dillon pcdacs[idxL], pcdacs[idxR], power[idxL], power[idxR]);
626572ff6f6SMatthew Dillon if (retVals[ii] >= maxPower) {
627572ff6f6SMatthew Dillon while (ii < 64)
628572ff6f6SMatthew Dillon retVals[ii++] = maxPower;
629572ff6f6SMatthew Dillon }
630572ff6f6SMatthew Dillon }
631572ff6f6SMatthew Dillon return AH_TRUE;
632572ff6f6SMatthew Dillon }
633572ff6f6SMatthew Dillon
634572ff6f6SMatthew Dillon /*
635572ff6f6SMatthew Dillon * Takes a single calibration curve and creates a power table.
636572ff6f6SMatthew Dillon * Adjusts the new power table so the max power is relative
637572ff6f6SMatthew Dillon * to the maximum index in the power table.
638572ff6f6SMatthew Dillon *
639572ff6f6SMatthew Dillon * WARNING: rates must be adjusted for this relative power table
640572ff6f6SMatthew Dillon */
641572ff6f6SMatthew Dillon static int16_t
getPminAndPcdacTableFromPowerTable(int16_t * pwrTableT4,uint16_t retVals[])642572ff6f6SMatthew Dillon getPminAndPcdacTableFromPowerTable(int16_t *pwrTableT4, uint16_t retVals[])
643572ff6f6SMatthew Dillon {
644572ff6f6SMatthew Dillon int16_t ii, jj, jjMax;
645572ff6f6SMatthew Dillon int16_t pMin, currPower, pMax;
646572ff6f6SMatthew Dillon
647572ff6f6SMatthew Dillon /* If the spread is > 31.5dB, keep the upper 31.5dB range */
648572ff6f6SMatthew Dillon if ((pwrTableT4[63] - pwrTableT4[0]) > 126) {
649572ff6f6SMatthew Dillon pMin = pwrTableT4[63] - 126;
650572ff6f6SMatthew Dillon } else {
651572ff6f6SMatthew Dillon pMin = pwrTableT4[0];
652572ff6f6SMatthew Dillon }
653572ff6f6SMatthew Dillon
654572ff6f6SMatthew Dillon pMax = pwrTableT4[63];
655572ff6f6SMatthew Dillon jjMax = 63;
656572ff6f6SMatthew Dillon
657572ff6f6SMatthew Dillon /* Search for highest pcdac 0.25dB below maxPower */
658572ff6f6SMatthew Dillon while ((pwrTableT4[jjMax] > (pMax - 1) ) && (jjMax >= 0)) {
659572ff6f6SMatthew Dillon jjMax--;
660572ff6f6SMatthew Dillon }
661572ff6f6SMatthew Dillon
662572ff6f6SMatthew Dillon jj = jjMax;
663572ff6f6SMatthew Dillon currPower = pMax;
664572ff6f6SMatthew Dillon for (ii = 63; ii >= 0; ii--) {
665572ff6f6SMatthew Dillon while ((jj < 64) && (jj > 0) && (pwrTableT4[jj] >= currPower)) {
666572ff6f6SMatthew Dillon jj--;
667572ff6f6SMatthew Dillon }
668572ff6f6SMatthew Dillon if (jj == 0) {
669572ff6f6SMatthew Dillon while (ii >= 0) {
670572ff6f6SMatthew Dillon retVals[ii] = retVals[ii + 1];
671572ff6f6SMatthew Dillon ii--;
672572ff6f6SMatthew Dillon }
673572ff6f6SMatthew Dillon break;
674572ff6f6SMatthew Dillon }
675572ff6f6SMatthew Dillon retVals[ii] = jj;
676572ff6f6SMatthew Dillon currPower -= 2; // corresponds to a 0.5dB step
677572ff6f6SMatthew Dillon }
678572ff6f6SMatthew Dillon return pMin;
679572ff6f6SMatthew Dillon }
680572ff6f6SMatthew Dillon
681572ff6f6SMatthew Dillon /*
682572ff6f6SMatthew Dillon * Combines the XPD curves from two calibration sets into a single
683572ff6f6SMatthew Dillon * power table and adjusts the power table so the max power is relative
684572ff6f6SMatthew Dillon * to the maximum index in the power table
685572ff6f6SMatthew Dillon *
686572ff6f6SMatthew Dillon * WARNING: rates must be adjusted for this relative power table
687572ff6f6SMatthew Dillon */
688572ff6f6SMatthew Dillon static int16_t
getPminAndPcdacTableFromTwoPowerTables(int16_t * pwrTableLXpdT4,int16_t * pwrTableHXpdT4,uint16_t retVals[],int16_t * pMid)689572ff6f6SMatthew Dillon getPminAndPcdacTableFromTwoPowerTables(int16_t *pwrTableLXpdT4,
690572ff6f6SMatthew Dillon int16_t *pwrTableHXpdT4, uint16_t retVals[], int16_t *pMid)
691572ff6f6SMatthew Dillon {
692572ff6f6SMatthew Dillon int16_t ii, jj, jjMax;
693572ff6f6SMatthew Dillon int16_t pMin, pMax, currPower;
694572ff6f6SMatthew Dillon int16_t *pwrTableT4;
695572ff6f6SMatthew Dillon uint16_t msbFlag = 0x40; // turns on the 7th bit of the pcdac
696572ff6f6SMatthew Dillon
697572ff6f6SMatthew Dillon /* If the spread is > 31.5dB, keep the upper 31.5dB range */
698572ff6f6SMatthew Dillon if ((pwrTableLXpdT4[63] - pwrTableHXpdT4[0]) > 126) {
699572ff6f6SMatthew Dillon pMin = pwrTableLXpdT4[63] - 126;
700572ff6f6SMatthew Dillon } else {
701572ff6f6SMatthew Dillon pMin = pwrTableHXpdT4[0];
702572ff6f6SMatthew Dillon }
703572ff6f6SMatthew Dillon
704572ff6f6SMatthew Dillon pMax = pwrTableLXpdT4[63];
705572ff6f6SMatthew Dillon jjMax = 63;
706572ff6f6SMatthew Dillon /* Search for highest pcdac 0.25dB below maxPower */
707572ff6f6SMatthew Dillon while ((pwrTableLXpdT4[jjMax] > (pMax - 1) ) && (jjMax >= 0)){
708572ff6f6SMatthew Dillon jjMax--;
709572ff6f6SMatthew Dillon }
710572ff6f6SMatthew Dillon
711572ff6f6SMatthew Dillon *pMid = pwrTableHXpdT4[63];
712572ff6f6SMatthew Dillon jj = jjMax;
713572ff6f6SMatthew Dillon ii = 63;
714572ff6f6SMatthew Dillon currPower = pMax;
715572ff6f6SMatthew Dillon pwrTableT4 = &(pwrTableLXpdT4[0]);
716572ff6f6SMatthew Dillon while (ii >= 0) {
717572ff6f6SMatthew Dillon if ((currPower <= *pMid) || ( (jj == 0) && (msbFlag == 0x40))){
718572ff6f6SMatthew Dillon msbFlag = 0x00;
719572ff6f6SMatthew Dillon pwrTableT4 = &(pwrTableHXpdT4[0]);
720572ff6f6SMatthew Dillon jj = 63;
721572ff6f6SMatthew Dillon }
722572ff6f6SMatthew Dillon while ((jj > 0) && (pwrTableT4[jj] >= currPower)) {
723572ff6f6SMatthew Dillon jj--;
724572ff6f6SMatthew Dillon }
725572ff6f6SMatthew Dillon if ((jj == 0) && (msbFlag == 0x00)) {
726572ff6f6SMatthew Dillon while (ii >= 0) {
727572ff6f6SMatthew Dillon retVals[ii] = retVals[ii+1];
728572ff6f6SMatthew Dillon ii--;
729572ff6f6SMatthew Dillon }
730572ff6f6SMatthew Dillon break;
731572ff6f6SMatthew Dillon }
732572ff6f6SMatthew Dillon retVals[ii] = jj | msbFlag;
733572ff6f6SMatthew Dillon currPower -= 2; // corresponds to a 0.5dB step
734572ff6f6SMatthew Dillon ii--;
735572ff6f6SMatthew Dillon }
736572ff6f6SMatthew Dillon return pMin;
737572ff6f6SMatthew Dillon }
738572ff6f6SMatthew Dillon
739572ff6f6SMatthew Dillon static int16_t
ar5112GetMinPower(struct ath_hal * ah,const EXPN_DATA_PER_CHANNEL_5112 * data)740572ff6f6SMatthew Dillon ar5112GetMinPower(struct ath_hal *ah, const EXPN_DATA_PER_CHANNEL_5112 *data)
741572ff6f6SMatthew Dillon {
742572ff6f6SMatthew Dillon int i, minIndex;
743572ff6f6SMatthew Dillon int16_t minGain,minPwr,minPcdac,retVal;
744572ff6f6SMatthew Dillon
745572ff6f6SMatthew Dillon /* Assume NUM_POINTS_XPD0 > 0 */
746572ff6f6SMatthew Dillon minGain = data->pDataPerXPD[0].xpd_gain;
747572ff6f6SMatthew Dillon for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) {
748572ff6f6SMatthew Dillon if (data->pDataPerXPD[i].xpd_gain < minGain) {
749572ff6f6SMatthew Dillon minIndex = i;
750572ff6f6SMatthew Dillon minGain = data->pDataPerXPD[i].xpd_gain;
751572ff6f6SMatthew Dillon }
752572ff6f6SMatthew Dillon }
753572ff6f6SMatthew Dillon minPwr = data->pDataPerXPD[minIndex].pwr_t4[0];
754572ff6f6SMatthew Dillon minPcdac = data->pDataPerXPD[minIndex].pcdac[0];
755572ff6f6SMatthew Dillon for (i=1; i<NUM_POINTS_XPD0; i++) {
756572ff6f6SMatthew Dillon if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) {
757572ff6f6SMatthew Dillon minPwr = data->pDataPerXPD[minIndex].pwr_t4[i];
758572ff6f6SMatthew Dillon minPcdac = data->pDataPerXPD[minIndex].pcdac[i];
759572ff6f6SMatthew Dillon }
760572ff6f6SMatthew Dillon }
761572ff6f6SMatthew Dillon retVal = minPwr - (minPcdac*2);
762572ff6f6SMatthew Dillon return(retVal);
763572ff6f6SMatthew Dillon }
764572ff6f6SMatthew Dillon
765572ff6f6SMatthew Dillon static HAL_BOOL
ar5112GetChannelMaxMinPower(struct ath_hal * ah,const struct ieee80211_channel * chan,int16_t * maxPow,int16_t * minPow)766572ff6f6SMatthew Dillon ar5112GetChannelMaxMinPower(struct ath_hal *ah,
767572ff6f6SMatthew Dillon const struct ieee80211_channel *chan,
768572ff6f6SMatthew Dillon int16_t *maxPow, int16_t *minPow)
769572ff6f6SMatthew Dillon {
770572ff6f6SMatthew Dillon uint16_t freq = chan->ic_freq; /* NB: never mapped */
771572ff6f6SMatthew Dillon const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
772572ff6f6SMatthew Dillon int numChannels=0,i,last;
773572ff6f6SMatthew Dillon int totalD, totalF,totalMin;
774572ff6f6SMatthew Dillon const EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;
775572ff6f6SMatthew Dillon const EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;
776572ff6f6SMatthew Dillon
777572ff6f6SMatthew Dillon *maxPow = 0;
778572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_A(chan)) {
779572ff6f6SMatthew Dillon powerArray = ee->ee_modePowerArray5112;
780572ff6f6SMatthew Dillon data = powerArray[headerInfo11A].pDataPerChannel;
781572ff6f6SMatthew Dillon numChannels = powerArray[headerInfo11A].numChannels;
782572ff6f6SMatthew Dillon } else if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan)) {
783572ff6f6SMatthew Dillon /* XXX - is this correct? Should we also use the same power for turbo G? */
784572ff6f6SMatthew Dillon powerArray = ee->ee_modePowerArray5112;
785572ff6f6SMatthew Dillon data = powerArray[headerInfo11G].pDataPerChannel;
786572ff6f6SMatthew Dillon numChannels = powerArray[headerInfo11G].numChannels;
787572ff6f6SMatthew Dillon } else if (IEEE80211_IS_CHAN_B(chan)) {
788572ff6f6SMatthew Dillon powerArray = ee->ee_modePowerArray5112;
789572ff6f6SMatthew Dillon data = powerArray[headerInfo11B].pDataPerChannel;
790572ff6f6SMatthew Dillon numChannels = powerArray[headerInfo11B].numChannels;
791572ff6f6SMatthew Dillon } else {
792572ff6f6SMatthew Dillon return (AH_TRUE);
793572ff6f6SMatthew Dillon }
794572ff6f6SMatthew Dillon /* Make sure the channel is in the range of the TP values
795572ff6f6SMatthew Dillon * (freq piers)
796572ff6f6SMatthew Dillon */
797572ff6f6SMatthew Dillon if (numChannels < 1)
798572ff6f6SMatthew Dillon return(AH_FALSE);
799572ff6f6SMatthew Dillon
800572ff6f6SMatthew Dillon if ((freq < data[0].channelValue) ||
801572ff6f6SMatthew Dillon (freq > data[numChannels-1].channelValue)) {
802572ff6f6SMatthew Dillon if (freq < data[0].channelValue) {
803572ff6f6SMatthew Dillon *maxPow = data[0].maxPower_t4;
804572ff6f6SMatthew Dillon *minPow = ar5112GetMinPower(ah, &data[0]);
805572ff6f6SMatthew Dillon return(AH_TRUE);
806572ff6f6SMatthew Dillon } else {
807572ff6f6SMatthew Dillon *maxPow = data[numChannels - 1].maxPower_t4;
808572ff6f6SMatthew Dillon *minPow = ar5112GetMinPower(ah, &data[numChannels - 1]);
809572ff6f6SMatthew Dillon return(AH_TRUE);
810572ff6f6SMatthew Dillon }
811572ff6f6SMatthew Dillon }
812572ff6f6SMatthew Dillon
813572ff6f6SMatthew Dillon /* Linearly interpolate the power value now */
814572ff6f6SMatthew Dillon for (last=0,i=0;
815572ff6f6SMatthew Dillon (i<numChannels) && (freq > data[i].channelValue);
816572ff6f6SMatthew Dillon last=i++);
817572ff6f6SMatthew Dillon totalD = data[i].channelValue - data[last].channelValue;
818572ff6f6SMatthew Dillon if (totalD > 0) {
819572ff6f6SMatthew Dillon totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
820572ff6f6SMatthew Dillon *maxPow = (int8_t) ((totalF*(freq-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
821572ff6f6SMatthew Dillon
822572ff6f6SMatthew Dillon totalMin = ar5112GetMinPower(ah,&data[i]) - ar5112GetMinPower(ah, &data[last]);
823572ff6f6SMatthew Dillon *minPow = (int8_t) ((totalMin*(freq-data[last].channelValue) + ar5112GetMinPower(ah, &data[last])*totalD)/totalD);
824572ff6f6SMatthew Dillon return (AH_TRUE);
825572ff6f6SMatthew Dillon } else {
826572ff6f6SMatthew Dillon if (freq == data[i].channelValue) {
827572ff6f6SMatthew Dillon *maxPow = data[i].maxPower_t4;
828572ff6f6SMatthew Dillon *minPow = ar5112GetMinPower(ah, &data[i]);
829572ff6f6SMatthew Dillon return(AH_TRUE);
830572ff6f6SMatthew Dillon } else
831572ff6f6SMatthew Dillon return(AH_FALSE);
832572ff6f6SMatthew Dillon }
833572ff6f6SMatthew Dillon }
834572ff6f6SMatthew Dillon
835572ff6f6SMatthew Dillon /*
836572ff6f6SMatthew Dillon * Free memory for analog bank scratch buffers
837572ff6f6SMatthew Dillon */
838572ff6f6SMatthew Dillon static void
ar5112RfDetach(struct ath_hal * ah)839572ff6f6SMatthew Dillon ar5112RfDetach(struct ath_hal *ah)
840572ff6f6SMatthew Dillon {
841572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
842572ff6f6SMatthew Dillon
843572ff6f6SMatthew Dillon HALASSERT(ahp->ah_rfHal != AH_NULL);
844572ff6f6SMatthew Dillon ath_hal_free(ahp->ah_rfHal);
845572ff6f6SMatthew Dillon ahp->ah_rfHal = AH_NULL;
846572ff6f6SMatthew Dillon }
847572ff6f6SMatthew Dillon
848572ff6f6SMatthew Dillon /*
849572ff6f6SMatthew Dillon * Allocate memory for analog bank scratch buffers
850572ff6f6SMatthew Dillon * Scratch Buffer will be reinitialized every reset so no need to zero now
851572ff6f6SMatthew Dillon */
852572ff6f6SMatthew Dillon static HAL_BOOL
ar5112RfAttach(struct ath_hal * ah,HAL_STATUS * status)853572ff6f6SMatthew Dillon ar5112RfAttach(struct ath_hal *ah, HAL_STATUS *status)
854572ff6f6SMatthew Dillon {
855572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
856572ff6f6SMatthew Dillon struct ar5112State *priv;
857572ff6f6SMatthew Dillon
858572ff6f6SMatthew Dillon HALASSERT(ah->ah_magic == AR5212_MAGIC);
859572ff6f6SMatthew Dillon
860572ff6f6SMatthew Dillon HALASSERT(ahp->ah_rfHal == AH_NULL);
861572ff6f6SMatthew Dillon priv = ath_hal_malloc(sizeof(struct ar5112State));
862572ff6f6SMatthew Dillon if (priv == AH_NULL) {
863572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
864572ff6f6SMatthew Dillon "%s: cannot allocate private state\n", __func__);
865572ff6f6SMatthew Dillon *status = HAL_ENOMEM; /* XXX */
866572ff6f6SMatthew Dillon return AH_FALSE;
867572ff6f6SMatthew Dillon }
868572ff6f6SMatthew Dillon priv->base.rfDetach = ar5112RfDetach;
869572ff6f6SMatthew Dillon priv->base.writeRegs = ar5112WriteRegs;
870572ff6f6SMatthew Dillon priv->base.getRfBank = ar5112GetRfBank;
871572ff6f6SMatthew Dillon priv->base.setChannel = ar5112SetChannel;
872572ff6f6SMatthew Dillon priv->base.setRfRegs = ar5112SetRfRegs;
873572ff6f6SMatthew Dillon priv->base.setPowerTable = ar5112SetPowerTable;
874572ff6f6SMatthew Dillon priv->base.getChannelMaxMinPower = ar5112GetChannelMaxMinPower;
875572ff6f6SMatthew Dillon priv->base.getNfAdjust = ar5212GetNfAdjust;
876572ff6f6SMatthew Dillon
877572ff6f6SMatthew Dillon ahp->ah_pcdacTable = priv->pcdacTable;
878572ff6f6SMatthew Dillon ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
879572ff6f6SMatthew Dillon ahp->ah_rfHal = &priv->base;
880572ff6f6SMatthew Dillon
881572ff6f6SMatthew Dillon return AH_TRUE;
882572ff6f6SMatthew Dillon }
883572ff6f6SMatthew Dillon
884572ff6f6SMatthew Dillon static HAL_BOOL
ar5112Probe(struct ath_hal * ah)885572ff6f6SMatthew Dillon ar5112Probe(struct ath_hal *ah)
886572ff6f6SMatthew Dillon {
887572ff6f6SMatthew Dillon return IS_RAD5112(ah);
888572ff6f6SMatthew Dillon }
889572ff6f6SMatthew Dillon AH_RF(RF5112, ar5112Probe, ar5112RfAttach);
890