1*572ff6f6SMatthew Dillon /*
2*572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3*572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc.
4*572ff6f6SMatthew Dillon *
5*572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6*572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7*572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8*572ff6f6SMatthew Dillon *
9*572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10*572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11*572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12*572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13*572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14*572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15*572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16*572ff6f6SMatthew Dillon *
17*572ff6f6SMatthew Dillon * $FreeBSD$
18*572ff6f6SMatthew Dillon */
19*572ff6f6SMatthew Dillon #include "opt_ah.h"
20*572ff6f6SMatthew Dillon
21*572ff6f6SMatthew Dillon #include "ah.h"
22*572ff6f6SMatthew Dillon #include "ah_desc.h"
23*572ff6f6SMatthew Dillon #include "ah_internal.h"
24*572ff6f6SMatthew Dillon
25*572ff6f6SMatthew Dillon #include "ar5416/ar5416.h"
26*572ff6f6SMatthew Dillon #include "ar5416/ar5416reg.h"
27*572ff6f6SMatthew Dillon #include "ar5416/ar5416desc.h"
28*572ff6f6SMatthew Dillon
29*572ff6f6SMatthew Dillon /*
30*572ff6f6SMatthew Dillon * Get the receive filter.
31*572ff6f6SMatthew Dillon */
32*572ff6f6SMatthew Dillon uint32_t
ar5416GetRxFilter(struct ath_hal * ah)33*572ff6f6SMatthew Dillon ar5416GetRxFilter(struct ath_hal *ah)
34*572ff6f6SMatthew Dillon {
35*572ff6f6SMatthew Dillon uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
36*572ff6f6SMatthew Dillon uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
37*572ff6f6SMatthew Dillon
38*572ff6f6SMatthew Dillon if (phybits & AR_PHY_ERR_RADAR)
39*572ff6f6SMatthew Dillon bits |= HAL_RX_FILTER_PHYRADAR;
40*572ff6f6SMatthew Dillon if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
41*572ff6f6SMatthew Dillon bits |= HAL_RX_FILTER_PHYERR;
42*572ff6f6SMatthew Dillon return bits;
43*572ff6f6SMatthew Dillon }
44*572ff6f6SMatthew Dillon
45*572ff6f6SMatthew Dillon /*
46*572ff6f6SMatthew Dillon * Set the receive filter.
47*572ff6f6SMatthew Dillon */
48*572ff6f6SMatthew Dillon void
ar5416SetRxFilter(struct ath_hal * ah,u_int32_t bits)49*572ff6f6SMatthew Dillon ar5416SetRxFilter(struct ath_hal *ah, u_int32_t bits)
50*572ff6f6SMatthew Dillon {
51*572ff6f6SMatthew Dillon uint32_t phybits;
52*572ff6f6SMatthew Dillon
53*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff));
54*572ff6f6SMatthew Dillon phybits = 0;
55*572ff6f6SMatthew Dillon if (bits & HAL_RX_FILTER_PHYRADAR)
56*572ff6f6SMatthew Dillon phybits |= AR_PHY_ERR_RADAR;
57*572ff6f6SMatthew Dillon if (bits & HAL_RX_FILTER_PHYERR)
58*572ff6f6SMatthew Dillon phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
59*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
60*572ff6f6SMatthew Dillon if (phybits) {
61*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_RXCFG,
62*572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
63*572ff6f6SMatthew Dillon } else {
64*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_RXCFG,
65*572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
66*572ff6f6SMatthew Dillon }
67*572ff6f6SMatthew Dillon }
68*572ff6f6SMatthew Dillon
69*572ff6f6SMatthew Dillon /*
70*572ff6f6SMatthew Dillon * Stop Receive at the DMA engine
71*572ff6f6SMatthew Dillon */
72*572ff6f6SMatthew Dillon HAL_BOOL
ar5416StopDmaReceive(struct ath_hal * ah)73*572ff6f6SMatthew Dillon ar5416StopDmaReceive(struct ath_hal *ah)
74*572ff6f6SMatthew Dillon {
75*572ff6f6SMatthew Dillon HAL_BOOL status;
76*572ff6f6SMatthew Dillon
77*572ff6f6SMatthew Dillon OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP);
78*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
79*572ff6f6SMatthew Dillon if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
80*572ff6f6SMatthew Dillon OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR);
81*572ff6f6SMatthew Dillon #ifdef AH_DEBUG
82*572ff6f6SMatthew Dillon ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n"
83*572ff6f6SMatthew Dillon "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
84*572ff6f6SMatthew Dillon __func__,
85*572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_CR),
86*572ff6f6SMatthew Dillon OS_REG_READ(ah, AR_DIAG_SW));
87*572ff6f6SMatthew Dillon #endif
88*572ff6f6SMatthew Dillon status = AH_FALSE;
89*572ff6f6SMatthew Dillon } else {
90*572ff6f6SMatthew Dillon status = AH_TRUE;
91*572ff6f6SMatthew Dillon }
92*572ff6f6SMatthew Dillon
93*572ff6f6SMatthew Dillon /*
94*572ff6f6SMatthew Dillon * XXX Is this to flush whatever is in a FIFO somewhere?
95*572ff6f6SMatthew Dillon * XXX If so, what should the correct behaviour should be?
96*572ff6f6SMatthew Dillon */
97*572ff6f6SMatthew Dillon if (AR_SREV_9100(ah))
98*572ff6f6SMatthew Dillon OS_DELAY(3000);
99*572ff6f6SMatthew Dillon
100*572ff6f6SMatthew Dillon return (status);
101*572ff6f6SMatthew Dillon }
102*572ff6f6SMatthew Dillon
103*572ff6f6SMatthew Dillon /*
104*572ff6f6SMatthew Dillon * Start receive at the PCU engine
105*572ff6f6SMatthew Dillon */
106*572ff6f6SMatthew Dillon void
ar5416StartPcuReceive(struct ath_hal * ah)107*572ff6f6SMatthew Dillon ar5416StartPcuReceive(struct ath_hal *ah)
108*572ff6f6SMatthew Dillon {
109*572ff6f6SMatthew Dillon struct ath_hal_private *ahp = AH_PRIVATE(ah);
110*572ff6f6SMatthew Dillon
111*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__);
112*572ff6f6SMatthew Dillon ar5212EnableMibCounters(ah);
113*572ff6f6SMatthew Dillon /* NB: restore current settings */
114*572ff6f6SMatthew Dillon ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE);
115*572ff6f6SMatthew Dillon /*
116*572ff6f6SMatthew Dillon * NB: must do after enabling phy errors to avoid rx
117*572ff6f6SMatthew Dillon * frames w/ corrupted descriptor status.
118*572ff6f6SMatthew Dillon */
119*572ff6f6SMatthew Dillon OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
120*572ff6f6SMatthew Dillon }
121*572ff6f6SMatthew Dillon
122*572ff6f6SMatthew Dillon /*
123*572ff6f6SMatthew Dillon * Stop receive at the PCU engine
124*572ff6f6SMatthew Dillon * and abort current frame in PCU
125*572ff6f6SMatthew Dillon */
126*572ff6f6SMatthew Dillon void
ar5416StopPcuReceive(struct ath_hal * ah)127*572ff6f6SMatthew Dillon ar5416StopPcuReceive(struct ath_hal *ah)
128*572ff6f6SMatthew Dillon {
129*572ff6f6SMatthew Dillon OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
130*572ff6f6SMatthew Dillon
131*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RX, "%s: Stop PCU Receive \n", __func__);
132*572ff6f6SMatthew Dillon ar5212DisableMibCounters(ah);
133*572ff6f6SMatthew Dillon }
134*572ff6f6SMatthew Dillon
135*572ff6f6SMatthew Dillon /*
136*572ff6f6SMatthew Dillon * Initialize RX descriptor, by clearing the status and setting
137*572ff6f6SMatthew Dillon * the size (and any other flags).
138*572ff6f6SMatthew Dillon */
139*572ff6f6SMatthew Dillon HAL_BOOL
ar5416SetupRxDesc(struct ath_hal * ah,struct ath_desc * ds,uint32_t size,u_int flags)140*572ff6f6SMatthew Dillon ar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
141*572ff6f6SMatthew Dillon uint32_t size, u_int flags)
142*572ff6f6SMatthew Dillon {
143*572ff6f6SMatthew Dillon struct ar5416_desc *ads = AR5416DESC(ds);
144*572ff6f6SMatthew Dillon
145*572ff6f6SMatthew Dillon HALASSERT((size &~ AR_BufLen) == 0);
146*572ff6f6SMatthew Dillon
147*572ff6f6SMatthew Dillon ads->ds_ctl1 = size & AR_BufLen;
148*572ff6f6SMatthew Dillon if (flags & HAL_RXDESC_INTREQ)
149*572ff6f6SMatthew Dillon ads->ds_ctl1 |= AR_RxIntrReq;
150*572ff6f6SMatthew Dillon
151*572ff6f6SMatthew Dillon /* this should be enough */
152*572ff6f6SMatthew Dillon ads->ds_rxstatus8 &= ~AR_RxDone;
153*572ff6f6SMatthew Dillon
154*572ff6f6SMatthew Dillon /* clear the rest of the status fields */
155*572ff6f6SMatthew Dillon OS_MEMZERO(&(ads->u), sizeof(ads->u));
156*572ff6f6SMatthew Dillon
157*572ff6f6SMatthew Dillon return AH_TRUE;
158*572ff6f6SMatthew Dillon }
159*572ff6f6SMatthew Dillon
160*572ff6f6SMatthew Dillon /*
161*572ff6f6SMatthew Dillon * Process an RX descriptor, and return the status to the caller.
162*572ff6f6SMatthew Dillon * Copy some hardware specific items into the software portion
163*572ff6f6SMatthew Dillon * of the descriptor.
164*572ff6f6SMatthew Dillon *
165*572ff6f6SMatthew Dillon * NB: the caller is responsible for validating the memory contents
166*572ff6f6SMatthew Dillon * of the descriptor (e.g. flushing any cached copy).
167*572ff6f6SMatthew Dillon */
168*572ff6f6SMatthew Dillon HAL_STATUS
ar5416ProcRxDesc(struct ath_hal * ah,struct ath_desc * ds,uint32_t pa,struct ath_desc * nds,uint64_t tsf,struct ath_rx_status * rs)169*572ff6f6SMatthew Dillon ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
170*572ff6f6SMatthew Dillon uint32_t pa, struct ath_desc *nds, uint64_t tsf,
171*572ff6f6SMatthew Dillon struct ath_rx_status *rs)
172*572ff6f6SMatthew Dillon {
173*572ff6f6SMatthew Dillon struct ar5416_desc *ads = AR5416DESC(ds);
174*572ff6f6SMatthew Dillon
175*572ff6f6SMatthew Dillon if ((ads->ds_rxstatus8 & AR_RxDone) == 0)
176*572ff6f6SMatthew Dillon return HAL_EINPROGRESS;
177*572ff6f6SMatthew Dillon
178*572ff6f6SMatthew Dillon rs->rs_status = 0;
179*572ff6f6SMatthew Dillon rs->rs_flags = 0;
180*572ff6f6SMatthew Dillon
181*572ff6f6SMatthew Dillon rs->rs_datalen = ads->ds_rxstatus1 & AR_DataLen;
182*572ff6f6SMatthew Dillon rs->rs_tstamp = ads->AR_RcvTimestamp;
183*572ff6f6SMatthew Dillon
184*572ff6f6SMatthew Dillon /* XXX what about KeyCacheMiss? */
185*572ff6f6SMatthew Dillon
186*572ff6f6SMatthew Dillon rs->rs_rssi = MS(ads->ds_rxstatus4, AR_RxRSSICombined);
187*572ff6f6SMatthew Dillon rs->rs_rssi_ctl[0] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt00);
188*572ff6f6SMatthew Dillon rs->rs_rssi_ctl[1] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt01);
189*572ff6f6SMatthew Dillon rs->rs_rssi_ctl[2] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt02);
190*572ff6f6SMatthew Dillon rs->rs_rssi_ext[0] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt10);
191*572ff6f6SMatthew Dillon rs->rs_rssi_ext[1] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt11);
192*572ff6f6SMatthew Dillon rs->rs_rssi_ext[2] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt12);
193*572ff6f6SMatthew Dillon
194*572ff6f6SMatthew Dillon if (ads->ds_rxstatus8 & AR_RxKeyIdxValid)
195*572ff6f6SMatthew Dillon rs->rs_keyix = MS(ads->ds_rxstatus8, AR_KeyIdx);
196*572ff6f6SMatthew Dillon else
197*572ff6f6SMatthew Dillon rs->rs_keyix = HAL_RXKEYIX_INVALID;
198*572ff6f6SMatthew Dillon
199*572ff6f6SMatthew Dillon /* NB: caller expected to do rate table mapping */
200*572ff6f6SMatthew Dillon rs->rs_rate = RXSTATUS_RATE(ah, ads);
201*572ff6f6SMatthew Dillon rs->rs_more = (ads->ds_rxstatus1 & AR_RxMore) ? 1 : 0;
202*572ff6f6SMatthew Dillon
203*572ff6f6SMatthew Dillon rs->rs_isaggr = (ads->ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
204*572ff6f6SMatthew Dillon rs->rs_moreaggr = (ads->ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
205*572ff6f6SMatthew Dillon rs->rs_antenna = MS(ads->ds_rxstatus3, AR_RxAntenna);
206*572ff6f6SMatthew Dillon
207*572ff6f6SMatthew Dillon if (ads->ds_rxstatus3 & AR_GI)
208*572ff6f6SMatthew Dillon rs->rs_flags |= HAL_RX_GI;
209*572ff6f6SMatthew Dillon if (ads->ds_rxstatus3 & AR_2040)
210*572ff6f6SMatthew Dillon rs->rs_flags |= HAL_RX_2040;
211*572ff6f6SMatthew Dillon
212*572ff6f6SMatthew Dillon /*
213*572ff6f6SMatthew Dillon * Only the AR9280 and later chips support STBC RX, so
214*572ff6f6SMatthew Dillon * ensure we only set this bit for those chips.
215*572ff6f6SMatthew Dillon */
216*572ff6f6SMatthew Dillon if (AR_SREV_MERLIN_10_OR_LATER(ah)
217*572ff6f6SMatthew Dillon && ads->ds_rxstatus3 & AR_STBCFrame)
218*572ff6f6SMatthew Dillon rs->rs_flags |= HAL_RX_STBC;
219*572ff6f6SMatthew Dillon
220*572ff6f6SMatthew Dillon if (ads->ds_rxstatus8 & AR_PreDelimCRCErr)
221*572ff6f6SMatthew Dillon rs->rs_flags |= HAL_RX_DELIM_CRC_PRE;
222*572ff6f6SMatthew Dillon if (ads->ds_rxstatus8 & AR_PostDelimCRCErr)
223*572ff6f6SMatthew Dillon rs->rs_flags |= HAL_RX_DELIM_CRC_POST;
224*572ff6f6SMatthew Dillon if (ads->ds_rxstatus8 & AR_DecryptBusyErr)
225*572ff6f6SMatthew Dillon rs->rs_flags |= HAL_RX_DECRYPT_BUSY;
226*572ff6f6SMatthew Dillon if (ads->ds_rxstatus8 & AR_HiRxChain)
227*572ff6f6SMatthew Dillon rs->rs_flags |= HAL_RX_HI_RX_CHAIN;
228*572ff6f6SMatthew Dillon
229*572ff6f6SMatthew Dillon if ((ads->ds_rxstatus8 & AR_RxFrameOK) == 0) {
230*572ff6f6SMatthew Dillon /*
231*572ff6f6SMatthew Dillon * These four bits should not be set together. The
232*572ff6f6SMatthew Dillon * 5416 spec states a Michael error can only occur if
233*572ff6f6SMatthew Dillon * DecryptCRCErr not set (and TKIP is used). Experience
234*572ff6f6SMatthew Dillon * indicates however that you can also get Michael errors
235*572ff6f6SMatthew Dillon * when a CRC error is detected, but these are specious.
236*572ff6f6SMatthew Dillon * Consequently we filter them out here so we don't
237*572ff6f6SMatthew Dillon * confuse and/or complicate drivers.
238*572ff6f6SMatthew Dillon */
239*572ff6f6SMatthew Dillon
240*572ff6f6SMatthew Dillon /*
241*572ff6f6SMatthew Dillon * The AR5416 sometimes sets both AR_CRCErr and AR_PHYErr
242*572ff6f6SMatthew Dillon * when reporting radar pulses. In this instance
243*572ff6f6SMatthew Dillon * set HAL_RXERR_PHY as well as HAL_RXERR_CRC and
244*572ff6f6SMatthew Dillon * let the driver layer figure out what to do.
245*572ff6f6SMatthew Dillon *
246*572ff6f6SMatthew Dillon * See PR kern/169362.
247*572ff6f6SMatthew Dillon */
248*572ff6f6SMatthew Dillon if (ads->ds_rxstatus8 & AR_PHYErr) {
249*572ff6f6SMatthew Dillon u_int phyerr;
250*572ff6f6SMatthew Dillon
251*572ff6f6SMatthew Dillon /*
252*572ff6f6SMatthew Dillon * Packets with OFDM_RESTART on post delimiter are CRC OK and
253*572ff6f6SMatthew Dillon * usable and MAC ACKs them.
254*572ff6f6SMatthew Dillon * To avoid packet from being lost, we remove the PHY Err flag
255*572ff6f6SMatthew Dillon * so that driver layer does not drop them.
256*572ff6f6SMatthew Dillon */
257*572ff6f6SMatthew Dillon phyerr = MS(ads->ds_rxstatus8, AR_PHYErrCode);
258*572ff6f6SMatthew Dillon
259*572ff6f6SMatthew Dillon if ((phyerr == HAL_PHYERR_OFDM_RESTART) &&
260*572ff6f6SMatthew Dillon (ads->ds_rxstatus8 & AR_PostDelimCRCErr)) {
261*572ff6f6SMatthew Dillon ath_hal_printf(ah,
262*572ff6f6SMatthew Dillon "%s: OFDM_RESTART on post-delim CRC error\n",
263*572ff6f6SMatthew Dillon __func__);
264*572ff6f6SMatthew Dillon rs->rs_phyerr = 0;
265*572ff6f6SMatthew Dillon } else {
266*572ff6f6SMatthew Dillon rs->rs_status |= HAL_RXERR_PHY;
267*572ff6f6SMatthew Dillon rs->rs_phyerr = phyerr;
268*572ff6f6SMatthew Dillon }
269*572ff6f6SMatthew Dillon }
270*572ff6f6SMatthew Dillon if (ads->ds_rxstatus8 & AR_CRCErr)
271*572ff6f6SMatthew Dillon rs->rs_status |= HAL_RXERR_CRC;
272*572ff6f6SMatthew Dillon else if (ads->ds_rxstatus8 & AR_DecryptCRCErr)
273*572ff6f6SMatthew Dillon rs->rs_status |= HAL_RXERR_DECRYPT;
274*572ff6f6SMatthew Dillon else if (ads->ds_rxstatus8 & AR_MichaelErr)
275*572ff6f6SMatthew Dillon rs->rs_status |= HAL_RXERR_MIC;
276*572ff6f6SMatthew Dillon }
277*572ff6f6SMatthew Dillon
278*572ff6f6SMatthew Dillon return HAL_OK;
279*572ff6f6SMatthew Dillon }
280