1*572ff6f6SMatthew Dillon /*
2*572ff6f6SMatthew Dillon * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
3*572ff6f6SMatthew Dillon * Copyright (c) 2008 Atheros Communications, Inc.
4*572ff6f6SMatthew Dillon *
5*572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6*572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7*572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8*572ff6f6SMatthew Dillon *
9*572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10*572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11*572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12*572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13*572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14*572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15*572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16*572ff6f6SMatthew Dillon *
17*572ff6f6SMatthew Dillon * $FreeBSD$
18*572ff6f6SMatthew Dillon */
19*572ff6f6SMatthew Dillon #include "opt_ah.h"
20*572ff6f6SMatthew Dillon
21*572ff6f6SMatthew Dillon /*
22*572ff6f6SMatthew Dillon * NB: Merlin and later have a simpler RF backend.
23*572ff6f6SMatthew Dillon */
24*572ff6f6SMatthew Dillon #include "ah.h"
25*572ff6f6SMatthew Dillon #include "ah_internal.h"
26*572ff6f6SMatthew Dillon
27*572ff6f6SMatthew Dillon #include "ah_eeprom_v14.h"
28*572ff6f6SMatthew Dillon
29*572ff6f6SMatthew Dillon #include "ar9002/ar9287.h"
30*572ff6f6SMatthew Dillon #include "ar5416/ar5416reg.h"
31*572ff6f6SMatthew Dillon #include "ar5416/ar5416phy.h"
32*572ff6f6SMatthew Dillon
33*572ff6f6SMatthew Dillon #define N(a) (sizeof(a)/sizeof(a[0]))
34*572ff6f6SMatthew Dillon
35*572ff6f6SMatthew Dillon struct ar9287State {
36*572ff6f6SMatthew Dillon RF_HAL_FUNCS base; /* public state, must be first */
37*572ff6f6SMatthew Dillon uint16_t pcdacTable[1]; /* XXX */
38*572ff6f6SMatthew Dillon };
39*572ff6f6SMatthew Dillon #define AR9287(ah) ((struct ar9287State *) AH5212(ah)->ah_rfHal)
40*572ff6f6SMatthew Dillon
41*572ff6f6SMatthew Dillon static HAL_BOOL ar9287GetChannelMaxMinPower(struct ath_hal *,
42*572ff6f6SMatthew Dillon const struct ieee80211_channel *, int16_t *maxPow,int16_t *minPow);
43*572ff6f6SMatthew Dillon int16_t ar9287GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c);
44*572ff6f6SMatthew Dillon
45*572ff6f6SMatthew Dillon static void
ar9287WriteRegs(struct ath_hal * ah,u_int modesIndex,u_int freqIndex,int writes)46*572ff6f6SMatthew Dillon ar9287WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
47*572ff6f6SMatthew Dillon int writes)
48*572ff6f6SMatthew Dillon {
49*572ff6f6SMatthew Dillon (void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain,
50*572ff6f6SMatthew Dillon freqIndex, writes);
51*572ff6f6SMatthew Dillon }
52*572ff6f6SMatthew Dillon
53*572ff6f6SMatthew Dillon /*
54*572ff6f6SMatthew Dillon * Take the MHz channel value and set the Channel value
55*572ff6f6SMatthew Dillon *
56*572ff6f6SMatthew Dillon * ASSUMES: Writes enabled to analog bus
57*572ff6f6SMatthew Dillon *
58*572ff6f6SMatthew Dillon * Actual Expression,
59*572ff6f6SMatthew Dillon *
60*572ff6f6SMatthew Dillon * For 2GHz channel,
61*572ff6f6SMatthew Dillon * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
62*572ff6f6SMatthew Dillon * (freq_ref = 40MHz)
63*572ff6f6SMatthew Dillon *
64*572ff6f6SMatthew Dillon * For 5GHz channel,
65*572ff6f6SMatthew Dillon * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
66*572ff6f6SMatthew Dillon * (freq_ref = 40MHz/(24>>amodeRefSel))
67*572ff6f6SMatthew Dillon *
68*572ff6f6SMatthew Dillon * For 5GHz channels which are 5MHz spaced,
69*572ff6f6SMatthew Dillon * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
70*572ff6f6SMatthew Dillon * (freq_ref = 40MHz)
71*572ff6f6SMatthew Dillon */
72*572ff6f6SMatthew Dillon static HAL_BOOL
ar9287SetChannel(struct ath_hal * ah,const struct ieee80211_channel * chan)73*572ff6f6SMatthew Dillon ar9287SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
74*572ff6f6SMatthew Dillon {
75*572ff6f6SMatthew Dillon uint16_t bMode, fracMode, aModeRefSel = 0;
76*572ff6f6SMatthew Dillon uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
77*572ff6f6SMatthew Dillon CHAN_CENTERS centers;
78*572ff6f6SMatthew Dillon uint32_t refDivA = 24;
79*572ff6f6SMatthew Dillon
80*572ff6f6SMatthew Dillon OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);
81*572ff6f6SMatthew Dillon
82*572ff6f6SMatthew Dillon ar5416GetChannelCenters(ah, chan, ¢ers);
83*572ff6f6SMatthew Dillon freq = centers.synth_center;
84*572ff6f6SMatthew Dillon
85*572ff6f6SMatthew Dillon reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL);
86*572ff6f6SMatthew Dillon reg32 &= 0xc0000000;
87*572ff6f6SMatthew Dillon
88*572ff6f6SMatthew Dillon if (freq < 4800) { /* 2 GHz, fractional mode */
89*572ff6f6SMatthew Dillon uint32_t txctl;
90*572ff6f6SMatthew Dillon int regWrites = 0;
91*572ff6f6SMatthew Dillon
92*572ff6f6SMatthew Dillon bMode = 1;
93*572ff6f6SMatthew Dillon fracMode = 1;
94*572ff6f6SMatthew Dillon aModeRefSel = 0;
95*572ff6f6SMatthew Dillon channelSel = (freq * 0x10000)/15;
96*572ff6f6SMatthew Dillon
97*572ff6f6SMatthew Dillon if (AR_SREV_KIWI_11_OR_LATER(ah)) {
98*572ff6f6SMatthew Dillon if (freq == 2484) {
99*572ff6f6SMatthew Dillon ath_hal_ini_write(ah,
100*572ff6f6SMatthew Dillon &AH9287(ah)->ah_ini_cckFirJapan2484, 1,
101*572ff6f6SMatthew Dillon regWrites);
102*572ff6f6SMatthew Dillon } else {
103*572ff6f6SMatthew Dillon ath_hal_ini_write(ah,
104*572ff6f6SMatthew Dillon &AH9287(ah)->ah_ini_cckFirNormal, 1,
105*572ff6f6SMatthew Dillon regWrites);
106*572ff6f6SMatthew Dillon }
107*572ff6f6SMatthew Dillon }
108*572ff6f6SMatthew Dillon
109*572ff6f6SMatthew Dillon txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
110*572ff6f6SMatthew Dillon if (freq == 2484) {
111*572ff6f6SMatthew Dillon /* Enable channel spreading for channel 14 */
112*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
113*572ff6f6SMatthew Dillon txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
114*572ff6f6SMatthew Dillon } else {
115*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
116*572ff6f6SMatthew Dillon txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
117*572ff6f6SMatthew Dillon }
118*572ff6f6SMatthew Dillon } else {
119*572ff6f6SMatthew Dillon bMode = 0;
120*572ff6f6SMatthew Dillon fracMode = 0;
121*572ff6f6SMatthew Dillon
122*572ff6f6SMatthew Dillon if ((freq % 20) == 0) {
123*572ff6f6SMatthew Dillon aModeRefSel = 3;
124*572ff6f6SMatthew Dillon } else if ((freq % 10) == 0) {
125*572ff6f6SMatthew Dillon aModeRefSel = 2;
126*572ff6f6SMatthew Dillon } else {
127*572ff6f6SMatthew Dillon aModeRefSel = 0;
128*572ff6f6SMatthew Dillon /*
129*572ff6f6SMatthew Dillon * Enable 2G (fractional) mode for channels which
130*572ff6f6SMatthew Dillon * are 5MHz spaced
131*572ff6f6SMatthew Dillon */
132*572ff6f6SMatthew Dillon fracMode = 1;
133*572ff6f6SMatthew Dillon refDivA = 1;
134*572ff6f6SMatthew Dillon channelSel = (freq * 0x8000)/15;
135*572ff6f6SMatthew Dillon
136*572ff6f6SMatthew Dillon /* RefDivA setting */
137*572ff6f6SMatthew Dillon OS_A_REG_RMW_FIELD(ah, AR_AN_SYNTH9,
138*572ff6f6SMatthew Dillon AR_AN_SYNTH9_REFDIVA, refDivA);
139*572ff6f6SMatthew Dillon }
140*572ff6f6SMatthew Dillon if (!fracMode) {
141*572ff6f6SMatthew Dillon ndiv = (freq * (refDivA >> aModeRefSel))/60;
142*572ff6f6SMatthew Dillon channelSel = ndiv & 0x1ff;
143*572ff6f6SMatthew Dillon channelFrac = (ndiv & 0xfffffe00) * 2;
144*572ff6f6SMatthew Dillon channelSel = (channelSel << 17) | channelFrac;
145*572ff6f6SMatthew Dillon }
146*572ff6f6SMatthew Dillon }
147*572ff6f6SMatthew Dillon
148*572ff6f6SMatthew Dillon reg32 = reg32 | (bMode << 29) | (fracMode << 28) |
149*572ff6f6SMatthew Dillon (aModeRefSel << 26) | (channelSel);
150*572ff6f6SMatthew Dillon
151*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
152*572ff6f6SMatthew Dillon
153*572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_curchan = chan;
154*572ff6f6SMatthew Dillon
155*572ff6f6SMatthew Dillon return AH_TRUE;
156*572ff6f6SMatthew Dillon }
157*572ff6f6SMatthew Dillon
158*572ff6f6SMatthew Dillon /*
159*572ff6f6SMatthew Dillon * Return a reference to the requested RF Bank.
160*572ff6f6SMatthew Dillon */
161*572ff6f6SMatthew Dillon static uint32_t *
ar9287GetRfBank(struct ath_hal * ah,int bank)162*572ff6f6SMatthew Dillon ar9287GetRfBank(struct ath_hal *ah, int bank)
163*572ff6f6SMatthew Dillon {
164*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
165*572ff6f6SMatthew Dillon __func__, bank);
166*572ff6f6SMatthew Dillon return AH_NULL;
167*572ff6f6SMatthew Dillon }
168*572ff6f6SMatthew Dillon
169*572ff6f6SMatthew Dillon /*
170*572ff6f6SMatthew Dillon * Reads EEPROM header info from device structure and programs
171*572ff6f6SMatthew Dillon * all rf registers
172*572ff6f6SMatthew Dillon */
173*572ff6f6SMatthew Dillon static HAL_BOOL
ar9287SetRfRegs(struct ath_hal * ah,const struct ieee80211_channel * chan,uint16_t modesIndex,uint16_t * rfXpdGain)174*572ff6f6SMatthew Dillon ar9287SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
175*572ff6f6SMatthew Dillon uint16_t modesIndex, uint16_t *rfXpdGain)
176*572ff6f6SMatthew Dillon {
177*572ff6f6SMatthew Dillon return AH_TRUE; /* nothing to do */
178*572ff6f6SMatthew Dillon }
179*572ff6f6SMatthew Dillon
180*572ff6f6SMatthew Dillon /*
181*572ff6f6SMatthew Dillon * Read the transmit power levels from the structures taken from EEPROM
182*572ff6f6SMatthew Dillon * Interpolate read transmit power values for this channel
183*572ff6f6SMatthew Dillon * Organize the transmit power values into a table for writing into the hardware
184*572ff6f6SMatthew Dillon */
185*572ff6f6SMatthew Dillon
186*572ff6f6SMatthew Dillon static HAL_BOOL
ar9287SetPowerTable(struct ath_hal * ah,int16_t * pPowerMin,int16_t * pPowerMax,const struct ieee80211_channel * chan,uint16_t * rfXpdGain)187*572ff6f6SMatthew Dillon ar9287SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax,
188*572ff6f6SMatthew Dillon const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
189*572ff6f6SMatthew Dillon {
190*572ff6f6SMatthew Dillon return AH_TRUE;
191*572ff6f6SMatthew Dillon }
192*572ff6f6SMatthew Dillon
193*572ff6f6SMatthew Dillon #if 0
194*572ff6f6SMatthew Dillon static int16_t
195*572ff6f6SMatthew Dillon ar9287GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)
196*572ff6f6SMatthew Dillon {
197*572ff6f6SMatthew Dillon int i, minIndex;
198*572ff6f6SMatthew Dillon int16_t minGain,minPwr,minPcdac,retVal;
199*572ff6f6SMatthew Dillon
200*572ff6f6SMatthew Dillon /* Assume NUM_POINTS_XPD0 > 0 */
201*572ff6f6SMatthew Dillon minGain = data->pDataPerXPD[0].xpd_gain;
202*572ff6f6SMatthew Dillon for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) {
203*572ff6f6SMatthew Dillon if (data->pDataPerXPD[i].xpd_gain < minGain) {
204*572ff6f6SMatthew Dillon minIndex = i;
205*572ff6f6SMatthew Dillon minGain = data->pDataPerXPD[i].xpd_gain;
206*572ff6f6SMatthew Dillon }
207*572ff6f6SMatthew Dillon }
208*572ff6f6SMatthew Dillon minPwr = data->pDataPerXPD[minIndex].pwr_t4[0];
209*572ff6f6SMatthew Dillon minPcdac = data->pDataPerXPD[minIndex].pcdac[0];
210*572ff6f6SMatthew Dillon for (i=1; i<NUM_POINTS_XPD0; i++) {
211*572ff6f6SMatthew Dillon if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) {
212*572ff6f6SMatthew Dillon minPwr = data->pDataPerXPD[minIndex].pwr_t4[i];
213*572ff6f6SMatthew Dillon minPcdac = data->pDataPerXPD[minIndex].pcdac[i];
214*572ff6f6SMatthew Dillon }
215*572ff6f6SMatthew Dillon }
216*572ff6f6SMatthew Dillon retVal = minPwr - (minPcdac*2);
217*572ff6f6SMatthew Dillon return(retVal);
218*572ff6f6SMatthew Dillon }
219*572ff6f6SMatthew Dillon #endif
220*572ff6f6SMatthew Dillon
221*572ff6f6SMatthew Dillon static HAL_BOOL
ar9287GetChannelMaxMinPower(struct ath_hal * ah,const struct ieee80211_channel * chan,int16_t * maxPow,int16_t * minPow)222*572ff6f6SMatthew Dillon ar9287GetChannelMaxMinPower(struct ath_hal *ah,
223*572ff6f6SMatthew Dillon const struct ieee80211_channel *chan,
224*572ff6f6SMatthew Dillon int16_t *maxPow, int16_t *minPow)
225*572ff6f6SMatthew Dillon {
226*572ff6f6SMatthew Dillon #if 0
227*572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
228*572ff6f6SMatthew Dillon int numChannels=0,i,last;
229*572ff6f6SMatthew Dillon int totalD, totalF,totalMin;
230*572ff6f6SMatthew Dillon EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;
231*572ff6f6SMatthew Dillon EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;
232*572ff6f6SMatthew Dillon
233*572ff6f6SMatthew Dillon *maxPow = 0;
234*572ff6f6SMatthew Dillon if (IS_CHAN_A(chan)) {
235*572ff6f6SMatthew Dillon powerArray = ahp->ah_modePowerArray5112;
236*572ff6f6SMatthew Dillon data = powerArray[headerInfo11A].pDataPerChannel;
237*572ff6f6SMatthew Dillon numChannels = powerArray[headerInfo11A].numChannels;
238*572ff6f6SMatthew Dillon } else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {
239*572ff6f6SMatthew Dillon /* XXX - is this correct? Should we also use the same power for turbo G? */
240*572ff6f6SMatthew Dillon powerArray = ahp->ah_modePowerArray5112;
241*572ff6f6SMatthew Dillon data = powerArray[headerInfo11G].pDataPerChannel;
242*572ff6f6SMatthew Dillon numChannels = powerArray[headerInfo11G].numChannels;
243*572ff6f6SMatthew Dillon } else if (IS_CHAN_B(chan)) {
244*572ff6f6SMatthew Dillon powerArray = ahp->ah_modePowerArray5112;
245*572ff6f6SMatthew Dillon data = powerArray[headerInfo11B].pDataPerChannel;
246*572ff6f6SMatthew Dillon numChannels = powerArray[headerInfo11B].numChannels;
247*572ff6f6SMatthew Dillon } else {
248*572ff6f6SMatthew Dillon return (AH_TRUE);
249*572ff6f6SMatthew Dillon }
250*572ff6f6SMatthew Dillon /* Make sure the channel is in the range of the TP values
251*572ff6f6SMatthew Dillon * (freq piers)
252*572ff6f6SMatthew Dillon */
253*572ff6f6SMatthew Dillon if ((numChannels < 1) ||
254*572ff6f6SMatthew Dillon (chan->channel < data[0].channelValue) ||
255*572ff6f6SMatthew Dillon (chan->channel > data[numChannels-1].channelValue))
256*572ff6f6SMatthew Dillon return(AH_FALSE);
257*572ff6f6SMatthew Dillon
258*572ff6f6SMatthew Dillon /* Linearly interpolate the power value now */
259*572ff6f6SMatthew Dillon for (last=0,i=0;
260*572ff6f6SMatthew Dillon (i<numChannels) && (chan->channel > data[i].channelValue);
261*572ff6f6SMatthew Dillon last=i++);
262*572ff6f6SMatthew Dillon totalD = data[i].channelValue - data[last].channelValue;
263*572ff6f6SMatthew Dillon if (totalD > 0) {
264*572ff6f6SMatthew Dillon totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
265*572ff6f6SMatthew Dillon *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
266*572ff6f6SMatthew Dillon
267*572ff6f6SMatthew Dillon totalMin = ar9287GetMinPower(ah,&data[i]) - ar9287GetMinPower(ah, &data[last]);
268*572ff6f6SMatthew Dillon *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar9287GetMinPower(ah, &data[last])*totalD)/totalD);
269*572ff6f6SMatthew Dillon return (AH_TRUE);
270*572ff6f6SMatthew Dillon } else {
271*572ff6f6SMatthew Dillon if (chan->channel == data[i].channelValue) {
272*572ff6f6SMatthew Dillon *maxPow = data[i].maxPower_t4;
273*572ff6f6SMatthew Dillon *minPow = ar9287GetMinPower(ah, &data[i]);
274*572ff6f6SMatthew Dillon return(AH_TRUE);
275*572ff6f6SMatthew Dillon } else
276*572ff6f6SMatthew Dillon return(AH_FALSE);
277*572ff6f6SMatthew Dillon }
278*572ff6f6SMatthew Dillon #else
279*572ff6f6SMatthew Dillon *maxPow = *minPow = 0;
280*572ff6f6SMatthew Dillon return AH_FALSE;
281*572ff6f6SMatthew Dillon #endif
282*572ff6f6SMatthew Dillon }
283*572ff6f6SMatthew Dillon
284*572ff6f6SMatthew Dillon /*
285*572ff6f6SMatthew Dillon * The ordering of nfarray is thus:
286*572ff6f6SMatthew Dillon *
287*572ff6f6SMatthew Dillon * nfarray[0]: Chain 0 ctl
288*572ff6f6SMatthew Dillon * nfarray[1]: Chain 1 ctl
289*572ff6f6SMatthew Dillon * nfarray[2]: Chain 2 ctl
290*572ff6f6SMatthew Dillon * nfarray[3]: Chain 0 ext
291*572ff6f6SMatthew Dillon * nfarray[4]: Chain 1 ext
292*572ff6f6SMatthew Dillon * nfarray[5]: Chain 2 ext
293*572ff6f6SMatthew Dillon */
294*572ff6f6SMatthew Dillon static void
ar9287GetNoiseFloor(struct ath_hal * ah,int16_t nfarray[])295*572ff6f6SMatthew Dillon ar9287GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
296*572ff6f6SMatthew Dillon {
297*572ff6f6SMatthew Dillon int16_t nf;
298*572ff6f6SMatthew Dillon
299*572ff6f6SMatthew Dillon nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
300*572ff6f6SMatthew Dillon if (nf & 0x100)
301*572ff6f6SMatthew Dillon nf = 0 - ((nf ^ 0x1ff) + 1);
302*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_NFCAL,
303*572ff6f6SMatthew Dillon "NF calibrated [ctl] [chain 0] is %d\n", nf);
304*572ff6f6SMatthew Dillon nfarray[0] = nf;
305*572ff6f6SMatthew Dillon
306*572ff6f6SMatthew Dillon nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
307*572ff6f6SMatthew Dillon if (nf & 0x100)
308*572ff6f6SMatthew Dillon nf = 0 - ((nf ^ 0x1ff) + 1);
309*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_NFCAL,
310*572ff6f6SMatthew Dillon "NF calibrated [ctl] [chain 1] is %d\n", nf);
311*572ff6f6SMatthew Dillon nfarray[1] = nf;
312*572ff6f6SMatthew Dillon
313*572ff6f6SMatthew Dillon nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
314*572ff6f6SMatthew Dillon if (nf & 0x100)
315*572ff6f6SMatthew Dillon nf = 0 - ((nf ^ 0x1ff) + 1);
316*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_NFCAL,
317*572ff6f6SMatthew Dillon "NF calibrated [ext] [chain 0] is %d\n", nf);
318*572ff6f6SMatthew Dillon nfarray[3] = nf;
319*572ff6f6SMatthew Dillon
320*572ff6f6SMatthew Dillon nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
321*572ff6f6SMatthew Dillon if (nf & 0x100)
322*572ff6f6SMatthew Dillon nf = 0 - ((nf ^ 0x1ff) + 1);
323*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_NFCAL,
324*572ff6f6SMatthew Dillon "NF calibrated [ext] [chain 1] is %d\n", nf);
325*572ff6f6SMatthew Dillon nfarray[4] = nf;
326*572ff6f6SMatthew Dillon
327*572ff6f6SMatthew Dillon /* Chain 2 - invalid */
328*572ff6f6SMatthew Dillon nfarray[2] = 0;
329*572ff6f6SMatthew Dillon nfarray[5] = 0;
330*572ff6f6SMatthew Dillon
331*572ff6f6SMatthew Dillon }
332*572ff6f6SMatthew Dillon
333*572ff6f6SMatthew Dillon /*
334*572ff6f6SMatthew Dillon * Adjust NF based on statistical values for 5GHz frequencies.
335*572ff6f6SMatthew Dillon * Stubbed:Not used by Fowl
336*572ff6f6SMatthew Dillon */
337*572ff6f6SMatthew Dillon int16_t
ar9287GetNfAdjust(struct ath_hal * ah,const HAL_CHANNEL_INTERNAL * c)338*572ff6f6SMatthew Dillon ar9287GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
339*572ff6f6SMatthew Dillon {
340*572ff6f6SMatthew Dillon return 0;
341*572ff6f6SMatthew Dillon }
342*572ff6f6SMatthew Dillon
343*572ff6f6SMatthew Dillon /*
344*572ff6f6SMatthew Dillon * Free memory for analog bank scratch buffers
345*572ff6f6SMatthew Dillon */
346*572ff6f6SMatthew Dillon static void
ar9287RfDetach(struct ath_hal * ah)347*572ff6f6SMatthew Dillon ar9287RfDetach(struct ath_hal *ah)
348*572ff6f6SMatthew Dillon {
349*572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
350*572ff6f6SMatthew Dillon
351*572ff6f6SMatthew Dillon HALASSERT(ahp->ah_rfHal != AH_NULL);
352*572ff6f6SMatthew Dillon ath_hal_free(ahp->ah_rfHal);
353*572ff6f6SMatthew Dillon ahp->ah_rfHal = AH_NULL;
354*572ff6f6SMatthew Dillon }
355*572ff6f6SMatthew Dillon
356*572ff6f6SMatthew Dillon HAL_BOOL
ar9287RfAttach(struct ath_hal * ah,HAL_STATUS * status)357*572ff6f6SMatthew Dillon ar9287RfAttach(struct ath_hal *ah, HAL_STATUS *status)
358*572ff6f6SMatthew Dillon {
359*572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
360*572ff6f6SMatthew Dillon struct ar9287State *priv;
361*572ff6f6SMatthew Dillon
362*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR9280 radio\n", __func__);
363*572ff6f6SMatthew Dillon
364*572ff6f6SMatthew Dillon HALASSERT(ahp->ah_rfHal == AH_NULL);
365*572ff6f6SMatthew Dillon priv = ath_hal_malloc(sizeof(struct ar9287State));
366*572ff6f6SMatthew Dillon if (priv == AH_NULL) {
367*572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
368*572ff6f6SMatthew Dillon "%s: cannot allocate private state\n", __func__);
369*572ff6f6SMatthew Dillon *status = HAL_ENOMEM; /* XXX */
370*572ff6f6SMatthew Dillon return AH_FALSE;
371*572ff6f6SMatthew Dillon }
372*572ff6f6SMatthew Dillon priv->base.rfDetach = ar9287RfDetach;
373*572ff6f6SMatthew Dillon priv->base.writeRegs = ar9287WriteRegs;
374*572ff6f6SMatthew Dillon priv->base.getRfBank = ar9287GetRfBank;
375*572ff6f6SMatthew Dillon priv->base.setChannel = ar9287SetChannel;
376*572ff6f6SMatthew Dillon priv->base.setRfRegs = ar9287SetRfRegs;
377*572ff6f6SMatthew Dillon priv->base.setPowerTable = ar9287SetPowerTable;
378*572ff6f6SMatthew Dillon priv->base.getChannelMaxMinPower = ar9287GetChannelMaxMinPower;
379*572ff6f6SMatthew Dillon priv->base.getNfAdjust = ar9287GetNfAdjust;
380*572ff6f6SMatthew Dillon
381*572ff6f6SMatthew Dillon ahp->ah_pcdacTable = priv->pcdacTable;
382*572ff6f6SMatthew Dillon ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
383*572ff6f6SMatthew Dillon ahp->ah_rfHal = &priv->base;
384*572ff6f6SMatthew Dillon /*
385*572ff6f6SMatthew Dillon * Set noise floor adjust method; we arrange a
386*572ff6f6SMatthew Dillon * direct call instead of thunking.
387*572ff6f6SMatthew Dillon */
388*572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust;
389*572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_getNoiseFloor = ar9287GetNoiseFloor;
390*572ff6f6SMatthew Dillon
391*572ff6f6SMatthew Dillon return AH_TRUE;
392*572ff6f6SMatthew Dillon }
393*572ff6f6SMatthew Dillon
394*572ff6f6SMatthew Dillon static HAL_BOOL
ar9287RfProbe(struct ath_hal * ah)395*572ff6f6SMatthew Dillon ar9287RfProbe(struct ath_hal *ah)
396*572ff6f6SMatthew Dillon {
397*572ff6f6SMatthew Dillon return (AR_SREV_KIWI(ah));
398*572ff6f6SMatthew Dillon }
399*572ff6f6SMatthew Dillon
400*572ff6f6SMatthew Dillon AH_RF(RF9287, ar9287RfProbe, ar9287RfAttach);
401