1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.3 2004/03/14 15:36:48 joerg Exp $ 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/ethernet.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #include <net/bpf.h> 51 52 #include <net/if_types.h> 53 #include <net/vlan/if_vlan_var.h> 54 55 #include <netinet/in_systm.h> 56 #include <netinet/in.h> 57 #include <netinet/ip.h> 58 59 #include <machine/bus_memio.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include <bus/pci/pcireg.h> 66 #include <bus/pci/pcivar.h> 67 #include <bus/pci/pcidevs.h> 68 69 #include <dev/netif/mii_layer/mii.h> 70 #include <dev/netif/mii_layer/miivar.h> 71 72 #include "if_bfereg.h" 73 74 MODULE_DEPEND(bfe, pci, 1, 1, 1); 75 MODULE_DEPEND(bfe, ether, 1, 1, 1); 76 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 77 78 /* "controller miibus0" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 81 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 82 83 static struct bfe_type bfe_devs[] = { 84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 85 "Broadcom BCM4401 Fast Ethernet" }, 86 { 0, 0, NULL } 87 }; 88 89 static int bfe_probe(device_t); 90 static int bfe_attach(device_t); 91 static int bfe_detach(device_t); 92 static void bfe_release_resources(struct bfe_softc *); 93 static void bfe_intr(void *); 94 static void bfe_start(struct ifnet *); 95 static int bfe_ioctl(struct ifnet *, u_long, caddr_t); 96 static void bfe_init(void *); 97 static void bfe_stop(struct bfe_softc *); 98 static void bfe_watchdog(struct ifnet *); 99 static void bfe_shutdown(device_t); 100 static void bfe_tick(void *); 101 static void bfe_txeof(struct bfe_softc *); 102 static void bfe_rxeof(struct bfe_softc *); 103 static void bfe_set_rx_mode(struct bfe_softc *); 104 static int bfe_list_rx_init(struct bfe_softc *); 105 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*); 106 static void bfe_rx_ring_free(struct bfe_softc *); 107 108 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 109 static int bfe_ifmedia_upd(struct ifnet *); 110 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 111 static int bfe_miibus_readreg(device_t, int, int); 112 static int bfe_miibus_writereg(device_t, int, int, int); 113 static void bfe_miibus_statchg(device_t); 114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 115 u_long, const int); 116 static void bfe_get_config(struct bfe_softc *sc); 117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 118 static void bfe_stats_update(struct bfe_softc *); 119 static void bfe_clear_stats (struct bfe_softc *); 120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 122 static int bfe_resetphy(struct bfe_softc *); 123 static int bfe_setupphy(struct bfe_softc *); 124 static void bfe_chip_reset(struct bfe_softc *); 125 static void bfe_chip_halt(struct bfe_softc *); 126 static void bfe_core_reset(struct bfe_softc *); 127 static void bfe_core_disable(struct bfe_softc *); 128 static int bfe_dma_alloc(device_t); 129 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int); 130 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int); 131 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 132 133 static device_method_t bfe_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, bfe_probe), 136 DEVMETHOD(device_attach, bfe_attach), 137 DEVMETHOD(device_detach, bfe_detach), 138 DEVMETHOD(device_shutdown, bfe_shutdown), 139 140 /* bus interface */ 141 DEVMETHOD(bus_print_child, bus_generic_print_child), 142 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 143 144 /* MII interface */ 145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 148 149 { 0, 0 } 150 }; 151 152 static driver_t bfe_driver = { 153 "bfe", 154 bfe_methods, 155 sizeof(struct bfe_softc) 156 }; 157 158 static devclass_t bfe_devclass; 159 160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 162 163 /* 164 * Probe for a Broadcom 4401 chip. 165 */ 166 static int 167 bfe_probe(device_t dev) 168 { 169 struct bfe_type *t; 170 struct bfe_softc *sc; 171 172 t = bfe_devs; 173 174 sc = device_get_softc(dev); 175 bzero(sc, sizeof(struct bfe_softc)); 176 sc->bfe_unit = device_get_unit(dev); 177 sc->bfe_dev = dev; 178 179 while (t->bfe_name != NULL) { 180 if ((pci_get_vendor(dev) == t->bfe_vid) && 181 (pci_get_device(dev) == t->bfe_did)) { 182 device_set_desc_copy(dev, t->bfe_name); 183 return(0); 184 } 185 t++; 186 } 187 188 return(ENXIO); 189 } 190 191 static int 192 bfe_dma_alloc(device_t dev) 193 { 194 struct bfe_softc *sc; 195 int error, i; 196 197 sc = device_get_softc(dev); 198 199 /* parent tag */ 200 error = bus_dma_tag_create(NULL, /* parent */ 201 PAGE_SIZE, 0, /* alignment, boundary */ 202 BUS_SPACE_MAXADDR, /* lowaddr */ 203 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 204 NULL, NULL, /* filter, filterarg */ 205 MAXBSIZE, /* maxsize */ 206 BUS_SPACE_UNRESTRICTED, /* num of segments */ 207 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 208 BUS_DMA_ALLOCNOW, /* flags */ 209 &sc->bfe_parent_tag); 210 211 if (error) { 212 device_printf(dev, "could not allocate dma tag\n"); 213 return(ENOMEM); 214 } 215 216 217 /* tag for TX ring */ 218 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE, 219 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 220 NULL, NULL, BFE_TX_LIST_SIZE, 1, 221 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag); 222 223 if (error) { 224 device_printf(dev, "could not allocate dma tag\n"); 225 return(ENOMEM); 226 } 227 228 /* tag for RX ring */ 229 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE, 230 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 231 NULL, NULL, BFE_RX_LIST_SIZE, 1, 232 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag); 233 234 if (error) { 235 device_printf(dev, "could not allocate dma tag\n"); 236 return(ENOMEM); 237 } 238 239 /* tag for mbufs */ 240 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0, 241 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 242 1, BUS_SPACE_MAXSIZE_32BIT, 0, 243 &sc->bfe_tag); 244 245 if (error) { 246 device_printf(dev, "could not allocate dma tag\n"); 247 return(ENOMEM); 248 } 249 250 /* pre allocate dmamaps for RX list */ 251 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 252 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map); 253 if (error) { 254 device_printf(dev, "cannot create DMA map for RX\n"); 255 return(ENOMEM); 256 } 257 } 258 259 /* pre allocate dmamaps for TX list */ 260 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 261 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map); 262 if (error) { 263 device_printf(dev, "cannot create DMA map for TX\n"); 264 return(ENOMEM); 265 } 266 } 267 268 /* Alloc dma for rx ring */ 269 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 270 BUS_DMA_WAITOK, &sc->bfe_rx_map); 271 272 if (error) 273 return(ENOMEM); 274 275 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 276 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 277 sc->bfe_rx_list, sizeof(struct bfe_desc), 278 bfe_dma_map, &sc->bfe_rx_dma, 0); 279 280 if (error) 281 return(ENOMEM); 282 283 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 284 285 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 286 BUS_DMA_WAITOK, &sc->bfe_tx_map); 287 if (error) 288 return(ENOMEM); 289 290 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 291 sc->bfe_tx_list, sizeof(struct bfe_desc), 292 bfe_dma_map, &sc->bfe_tx_dma, 0); 293 if (error) 294 return(ENOMEM); 295 296 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 297 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 298 299 return(0); 300 } 301 302 static int 303 bfe_attach(device_t dev) 304 { 305 struct ifnet *ifp; 306 struct bfe_softc *sc; 307 int unit, error = 0, rid; 308 309 sc = device_get_softc(dev); 310 311 unit = device_get_unit(dev); 312 sc->bfe_dev = dev; 313 sc->bfe_unit = unit; 314 315 /* 316 * Handle power management nonsense. 317 */ 318 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 319 uint32_t membase, irq; 320 321 /* Save important PCI config data. */ 322 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 323 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 324 325 /* Reset the power state. */ 326 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 327 sc->bfe_unit, pci_get_powerstate(dev)); 328 329 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 330 331 /* Restore PCI config data. */ 332 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 333 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 334 } 335 336 /* 337 * Map control/status registers. 338 */ 339 pci_enable_busmaster(dev); 340 341 rid = BFE_PCI_MEMLO; 342 sc->bfe_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, 343 RF_ACTIVE); 344 if (sc->bfe_res == NULL) { 345 printf ("bfe%d: couldn't map memory\n", unit); 346 error = ENXIO; 347 goto fail; 348 } 349 350 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 351 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 352 353 /* Allocate interrupt */ 354 rid = 0; 355 356 sc->bfe_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 357 RF_SHAREABLE | RF_ACTIVE); 358 if (sc->bfe_irq == NULL) { 359 printf("bfe%d: couldn't map interrupt\n", unit); 360 error = ENXIO; 361 goto fail; 362 } 363 364 if (bfe_dma_alloc(dev)) { 365 printf("bfe%d: failed to allocate DMA resources\n", sc->bfe_unit); 366 bfe_release_resources(sc); 367 error = ENXIO; 368 goto fail; 369 } 370 371 /* Set up ifnet structure */ 372 ifp = &sc->arpcom.ac_if; 373 ifp->if_softc = sc; 374 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 375 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 376 ifp->if_ioctl = bfe_ioctl; 377 ifp->if_output = ether_output; 378 ifp->if_start = bfe_start; 379 ifp->if_watchdog = bfe_watchdog; 380 ifp->if_init = bfe_init; 381 ifp->if_mtu = ETHERMTU; 382 ifp->if_baudrate = 10000000; 383 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN; 384 385 bfe_get_config(sc); 386 387 printf("bfe%d: Ethernet address: %6D\n", unit, sc->arpcom.ac_enaddr, ":"); 388 389 /* Reset the chip and turn on the PHY */ 390 bfe_chip_reset(sc); 391 392 if (mii_phy_probe(dev, &sc->bfe_miibus, 393 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 394 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 395 error = ENXIO; 396 goto fail; 397 } 398 399 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 400 callout_handle_init(&sc->bfe_stat_ch); 401 402 /* 403 * Hook interrupt last to avoid having to lock softc 404 */ 405 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 406 bfe_intr, sc, &sc->bfe_intrhand); 407 408 if (error) { 409 bfe_release_resources(sc); 410 printf("bfe%d: couldn't set up irq\n", unit); 411 goto fail; 412 } 413 fail: 414 if (error) 415 bfe_release_resources(sc); 416 return(error); 417 } 418 419 static int 420 bfe_detach(device_t dev) 421 { 422 struct bfe_softc *sc; 423 struct ifnet *ifp; 424 int s; 425 426 sc = device_get_softc(dev); 427 428 s = splimp(); 429 430 ifp = &sc->arpcom.ac_if; 431 432 if (device_is_attached(dev)) { 433 bfe_stop(sc); 434 ether_ifdetach(ifp); 435 } 436 437 bfe_chip_reset(sc); 438 439 bus_generic_detach(dev); 440 if (sc->bfe_miibus != NULL) 441 device_delete_child(dev, sc->bfe_miibus); 442 443 bfe_release_resources(sc); 444 splx(s); 445 446 return(0); 447 } 448 449 /* 450 * Stop all chip I/O so that the kernel's probe routines don't 451 * get confused by errant DMAs when rebooting. 452 */ 453 static void 454 bfe_shutdown(device_t dev) 455 { 456 struct bfe_softc *sc; 457 int s; 458 459 sc = device_get_softc(dev); 460 461 s = splimp(); 462 bfe_stop(sc); 463 splx(s); 464 465 return; 466 } 467 468 static int 469 bfe_miibus_readreg(device_t dev, int phy, int reg) 470 { 471 struct bfe_softc *sc; 472 uint32_t ret; 473 474 sc = device_get_softc(dev); 475 if (phy != sc->bfe_phyaddr) 476 return(0); 477 bfe_readphy(sc, reg, &ret); 478 479 return(ret); 480 } 481 482 static int 483 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 484 { 485 struct bfe_softc *sc; 486 487 sc = device_get_softc(dev); 488 if (phy != sc->bfe_phyaddr) 489 return(0); 490 bfe_writephy(sc, reg, val); 491 492 return(0); 493 } 494 495 static void 496 bfe_miibus_statchg(device_t dev) 497 { 498 return; 499 } 500 501 static void 502 bfe_tx_ring_free(struct bfe_softc *sc) 503 { 504 int i; 505 506 for (i = 0; i < BFE_TX_LIST_CNT; i++) 507 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 508 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 509 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 510 bus_dmamap_unload(sc->bfe_tag, 511 sc->bfe_tx_ring[i].bfe_map); 512 bus_dmamap_destroy(sc->bfe_tag, 513 sc->bfe_tx_ring[i].bfe_map); 514 } 515 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 516 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 517 } 518 519 static void 520 bfe_rx_ring_free(struct bfe_softc *sc) 521 { 522 int i; 523 524 for (i = 0; i < BFE_RX_LIST_CNT; i++) 525 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 526 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 527 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 528 bus_dmamap_unload(sc->bfe_tag, 529 sc->bfe_rx_ring[i].bfe_map); 530 bus_dmamap_destroy(sc->bfe_tag, 531 sc->bfe_rx_ring[i].bfe_map); 532 } 533 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 534 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 535 } 536 537 538 static int 539 bfe_list_rx_init(struct bfe_softc *sc) 540 { 541 int i; 542 543 for (i = 0; i < BFE_RX_LIST_CNT; i++) 544 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 545 return(ENOBUFS); 546 547 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 548 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 549 550 sc->bfe_rx_cons = 0; 551 552 return(0); 553 } 554 555 static int 556 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 557 { 558 struct bfe_rxheader *rx_header; 559 struct bfe_desc *d; 560 struct bfe_data *r; 561 uint32_t ctrl; 562 563 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 564 return(EINVAL); 565 566 if (m == NULL) { 567 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 568 if (m == NULL) 569 return(ENOBUFS); 570 m->m_len = m->m_pkthdr.len = MCLBYTES; 571 } 572 else 573 m->m_data = m->m_ext.ext_buf; 574 575 rx_header = mtod(m, struct bfe_rxheader *); 576 rx_header->len = 0; 577 rx_header->flags = 0; 578 579 /* Map the mbuf into DMA */ 580 sc->bfe_rx_cnt = c; 581 d = &sc->bfe_rx_list[c]; 582 r = &sc->bfe_rx_ring[c]; 583 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 584 MCLBYTES, bfe_dma_map_desc, d, 0); 585 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 586 587 ctrl = ETHER_MAX_LEN + 32; 588 589 if(c == BFE_RX_LIST_CNT - 1) 590 ctrl |= BFE_DESC_EOT; 591 592 d->bfe_ctrl = ctrl; 593 r->bfe_mbuf = m; 594 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 595 return(0); 596 } 597 598 static void 599 bfe_get_config(struct bfe_softc *sc) 600 { 601 uint8_t eeprom[128]; 602 603 bfe_read_eeprom(sc, eeprom); 604 605 sc->arpcom.ac_enaddr[0] = eeprom[79]; 606 sc->arpcom.ac_enaddr[1] = eeprom[78]; 607 sc->arpcom.ac_enaddr[2] = eeprom[81]; 608 sc->arpcom.ac_enaddr[3] = eeprom[80]; 609 sc->arpcom.ac_enaddr[4] = eeprom[83]; 610 sc->arpcom.ac_enaddr[5] = eeprom[82]; 611 612 sc->bfe_phyaddr = eeprom[90] & 0x1f; 613 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 614 615 sc->bfe_core_unit = 0; 616 sc->bfe_dma_offset = BFE_PCI_DMA; 617 } 618 619 static void 620 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 621 { 622 uint32_t bar_orig, pci_rev, val; 623 624 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 625 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 626 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 627 628 val = CSR_READ_4(sc, BFE_SBINTVEC); 629 val |= cores; 630 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 631 632 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 633 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 634 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 635 636 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 637 } 638 639 static void 640 bfe_clear_stats(struct bfe_softc *sc) 641 { 642 u_long reg; 643 int s; 644 645 s = splimp(); 646 647 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 648 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 649 CSR_READ_4(sc, reg); 650 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 651 CSR_READ_4(sc, reg); 652 653 splx(s); 654 } 655 656 static int 657 bfe_resetphy(struct bfe_softc *sc) 658 { 659 uint32_t val; 660 int s; 661 662 s = splimp(); 663 bfe_writephy(sc, 0, BMCR_RESET); 664 DELAY(100); 665 bfe_readphy(sc, 0, &val); 666 if (val & BMCR_RESET) { 667 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 668 splx(s); 669 return(ENXIO); 670 } 671 splx(s); 672 return(0); 673 } 674 675 static void 676 bfe_chip_halt(struct bfe_softc *sc) 677 { 678 int s; 679 680 s = splimp(); 681 /* disable interrupts - not that it actually does..*/ 682 CSR_WRITE_4(sc, BFE_IMASK, 0); 683 CSR_READ_4(sc, BFE_IMASK); 684 685 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 686 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 687 688 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 689 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 690 DELAY(10); 691 692 splx(s); 693 } 694 695 static void 696 bfe_chip_reset(struct bfe_softc *sc) 697 { 698 uint32_t val; 699 int s; 700 701 s = splimp(); 702 703 /* Set the interrupt vector for the enet core */ 704 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 705 706 /* is core up? */ 707 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 708 if (val == BFE_CLOCK) { 709 /* It is, so shut it down */ 710 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 711 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 712 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 713 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 714 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 715 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 716 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 717 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 718 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 719 } 720 721 bfe_core_reset(sc); 722 bfe_clear_stats(sc); 723 724 /* 725 * We want the phy registers to be accessible even when 726 * the driver is "downed" so initialize MDC preamble, frequency, 727 * and whether internal or external phy here. 728 */ 729 730 /* 4402 has 62.5Mhz SB clock and internal phy */ 731 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 732 733 /* Internal or external PHY? */ 734 val = CSR_READ_4(sc, BFE_DEVCTRL); 735 if (!(val & BFE_IPP)) 736 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 737 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 738 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 739 DELAY(100); 740 } 741 742 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB); 743 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 744 BFE_LAZY_FC_MASK)); 745 746 /* 747 * We don't want lazy interrupts, so just send them at the end of a 748 * frame, please 749 */ 750 BFE_OR(sc, BFE_RCV_LAZY, 0); 751 752 /* Set max lengths, accounting for VLAN tags */ 753 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 754 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 755 756 /* Set watermark XXX - magic */ 757 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 758 759 /* 760 * Initialise DMA channels - not forgetting dma addresses need to be 761 * added to BFE_PCI_DMA 762 */ 763 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 764 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 765 766 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 767 BFE_RX_CTRL_ENABLE); 768 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 769 770 bfe_resetphy(sc); 771 bfe_setupphy(sc); 772 773 splx(s); 774 } 775 776 static void 777 bfe_core_disable(struct bfe_softc *sc) 778 { 779 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 780 return; 781 782 /* 783 * Set reject, wait for it set, then wait for the core to stop being busy 784 * Then set reset and reject and enable the clocks 785 */ 786 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 787 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 788 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 789 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 790 BFE_RESET)); 791 CSR_READ_4(sc, BFE_SBTMSLOW); 792 DELAY(10); 793 /* Leave reset and reject set */ 794 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 795 DELAY(10); 796 } 797 798 static void 799 bfe_core_reset(struct bfe_softc *sc) 800 { 801 uint32_t val; 802 803 /* Disable the core */ 804 bfe_core_disable(sc); 805 806 /* and bring it back up */ 807 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 808 CSR_READ_4(sc, BFE_SBTMSLOW); 809 DELAY(10); 810 811 /* Chip bug, clear SERR, IB and TO if they are set. */ 812 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 813 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 814 val = CSR_READ_4(sc, BFE_SBIMSTATE); 815 if (val & (BFE_IBE | BFE_TO)) 816 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 817 818 /* Clear reset and allow it to move through the core */ 819 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 820 CSR_READ_4(sc, BFE_SBTMSLOW); 821 DELAY(10); 822 823 /* Leave the clock set */ 824 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 825 CSR_READ_4(sc, BFE_SBTMSLOW); 826 DELAY(10); 827 } 828 829 static void 830 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 831 { 832 uint32_t val; 833 834 val = ((uint32_t) data[2]) << 24; 835 val |= ((uint32_t) data[3]) << 16; 836 val |= ((uint32_t) data[4]) << 8; 837 val |= ((uint32_t) data[5]); 838 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 839 val = (BFE_CAM_HI_VALID | 840 (((uint32_t) data[0]) << 8) | 841 (((uint32_t) data[1]))); 842 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 843 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 844 (index << BFE_CAM_INDEX_SHIFT))); 845 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 846 } 847 848 static void 849 bfe_set_rx_mode(struct bfe_softc *sc) 850 { 851 struct ifnet *ifp = &sc->arpcom.ac_if; 852 uint32_t val; 853 int i = 0; 854 855 val = CSR_READ_4(sc, BFE_RXCONF); 856 857 if (ifp->if_flags & IFF_PROMISC) 858 val |= BFE_RXCONF_PROMISC; 859 else 860 val &= ~BFE_RXCONF_PROMISC; 861 862 if (ifp->if_flags & IFF_BROADCAST) 863 val &= ~BFE_RXCONF_DBCAST; 864 else 865 val |= BFE_RXCONF_DBCAST; 866 867 868 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 869 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 870 871 CSR_WRITE_4(sc, BFE_RXCONF, val); 872 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 873 } 874 875 static void 876 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 877 { 878 uint32_t *ptr; 879 880 ptr = arg; 881 *ptr = segs->ds_addr; 882 } 883 884 static void 885 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 886 { 887 struct bfe_desc *d; 888 889 d = arg; 890 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 891 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 892 } 893 894 static void 895 bfe_release_resources(struct bfe_softc *sc) 896 { 897 device_t dev; 898 int i; 899 900 dev = sc->bfe_dev; 901 902 if (sc->bfe_intrhand != NULL) 903 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 904 905 if (sc->bfe_irq != NULL) 906 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 907 908 if (sc->bfe_res != NULL) 909 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 910 911 if (sc->bfe_tx_tag != NULL) { 912 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 913 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, sc->bfe_tx_map); 914 bus_dma_tag_destroy(sc->bfe_tx_tag); 915 sc->bfe_tx_tag = NULL; 916 } 917 918 if (sc->bfe_rx_tag != NULL) { 919 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 920 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, sc->bfe_rx_map); 921 bus_dma_tag_destroy(sc->bfe_rx_tag); 922 sc->bfe_rx_tag = NULL; 923 } 924 925 if (sc->bfe_tag != NULL) { 926 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 927 bus_dmamap_destroy(sc->bfe_tag, 928 sc->bfe_tx_ring[i].bfe_map); 929 } 930 bus_dma_tag_destroy(sc->bfe_tag); 931 sc->bfe_tag = NULL; 932 } 933 934 if (sc->bfe_parent_tag != NULL) 935 bus_dma_tag_destroy(sc->bfe_parent_tag); 936 } 937 938 static void 939 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 940 { 941 long i; 942 uint16_t *ptr = (uint16_t *)data; 943 944 for (i = 0; i < 128; i += 2) 945 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 946 } 947 948 static int 949 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 950 u_long timeout, const int clear) 951 { 952 u_long i; 953 954 for (i = 0; i < timeout; i++) { 955 uint32_t val = CSR_READ_4(sc, reg); 956 957 if (clear && !(val & bit)) 958 break; 959 if (!clear && (val & bit)) 960 break; 961 DELAY(10); 962 } 963 if (i == timeout) { 964 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 965 "%x to %s.\n", sc->bfe_unit, bit, reg, 966 (clear ? "clear" : "set")); 967 return -1; 968 } 969 return 0; 970 } 971 972 static int 973 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 974 { 975 int err; 976 int s; 977 978 s = splimp(); 979 /* Clear MII ISR */ 980 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 981 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 982 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 983 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 984 (reg << BFE_MDIO_RA_SHIFT) | 985 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 986 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 987 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 988 989 splx(s); 990 return(err); 991 } 992 993 static int 994 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 995 { 996 int status; 997 int s; 998 999 s = splimp(); 1000 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1001 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1002 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1003 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1004 (reg << BFE_MDIO_RA_SHIFT) | 1005 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1006 (val & BFE_MDIO_DATA_DATA))); 1007 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1008 1009 splx(s); 1010 1011 return status; 1012 } 1013 1014 /* 1015 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1016 * twice 1017 */ 1018 static int 1019 bfe_setupphy(struct bfe_softc *sc) 1020 { 1021 uint32_t val; 1022 int s; 1023 1024 s = splimp(); 1025 1026 /* Enable activity LED */ 1027 bfe_readphy(sc, 26, &val); 1028 bfe_writephy(sc, 26, val & 0x7fff); 1029 bfe_readphy(sc, 26, &val); 1030 1031 /* Enable traffic meter LED mode */ 1032 bfe_readphy(sc, 27, &val); 1033 bfe_writephy(sc, 27, val | (1 << 6)); 1034 1035 splx(s); 1036 return(0); 1037 } 1038 1039 static void 1040 bfe_stats_update(struct bfe_softc *sc) 1041 { 1042 u_long reg; 1043 uint32_t *val; 1044 1045 val = &sc->bfe_hwstats.tx_good_octets; 1046 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1047 *val++ += CSR_READ_4(sc, reg); 1048 val = &sc->bfe_hwstats.rx_good_octets; 1049 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1050 *val++ += CSR_READ_4(sc, reg); 1051 } 1052 1053 static void 1054 bfe_txeof(struct bfe_softc *sc) 1055 { 1056 struct ifnet *ifp; 1057 int s; 1058 uint32_t i, chipidx; 1059 1060 s = splimp(); 1061 1062 ifp = &sc->arpcom.ac_if; 1063 1064 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1065 chipidx /= sizeof(struct bfe_desc); 1066 1067 i = sc->bfe_tx_cons; 1068 /* Go through the mbufs and free those that have been transmitted */ 1069 while (i != chipidx) { 1070 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1071 if (r->bfe_mbuf != NULL) { 1072 ifp->if_opackets++; 1073 m_freem(r->bfe_mbuf); 1074 r->bfe_mbuf = NULL; 1075 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1076 } 1077 sc->bfe_tx_cnt--; 1078 BFE_INC(i, BFE_TX_LIST_CNT); 1079 } 1080 1081 if (i != sc->bfe_tx_cons) { 1082 /* we freed up some mbufs */ 1083 sc->bfe_tx_cons = i; 1084 ifp->if_flags &= ~IFF_OACTIVE; 1085 } 1086 if (sc->bfe_tx_cnt == 0) 1087 ifp->if_timer = 0; 1088 else 1089 ifp->if_timer = 5; 1090 1091 splx(s); 1092 } 1093 1094 /* Pass a received packet up the stack */ 1095 static void 1096 bfe_rxeof(struct bfe_softc *sc) 1097 { 1098 struct mbuf *m; 1099 struct ifnet *ifp; 1100 struct bfe_rxheader *rxheader; 1101 struct bfe_data *r; 1102 uint32_t cons, status, current, len, flags; 1103 int s; 1104 1105 s = splimp(); 1106 cons = sc->bfe_rx_cons; 1107 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1108 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1109 1110 ifp = &sc->arpcom.ac_if; 1111 1112 while (current != cons) { 1113 r = &sc->bfe_rx_ring[cons]; 1114 m = r->bfe_mbuf; 1115 rxheader = mtod(m, struct bfe_rxheader*); 1116 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1117 len = rxheader->len; 1118 r->bfe_mbuf = NULL; 1119 1120 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1121 flags = rxheader->flags; 1122 1123 len -= ETHER_CRC_LEN; 1124 1125 /* flag an error and try again */ 1126 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1127 ifp->if_ierrors++; 1128 if (flags & BFE_RX_FLAG_SERR) 1129 ifp->if_collisions++; 1130 bfe_list_newbuf(sc, cons, m); 1131 BFE_INC(cons, BFE_RX_LIST_CNT); 1132 continue; 1133 } 1134 1135 /* Go past the rx header */ 1136 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1137 m_adj(m, BFE_RX_OFFSET); 1138 m->m_len = m->m_pkthdr.len = len; 1139 } else { 1140 bfe_list_newbuf(sc, cons, m); 1141 BFE_INC(cons, BFE_RX_LIST_CNT); 1142 ifp->if_ierrors++; 1143 continue; 1144 } 1145 1146 ifp->if_ipackets++; 1147 m->m_pkthdr.rcvif = ifp; 1148 1149 ether_input(ifp, NULL, m); 1150 BFE_INC(cons, BFE_RX_LIST_CNT); 1151 } 1152 sc->bfe_rx_cons = cons; 1153 splx(s); 1154 } 1155 1156 static void 1157 bfe_intr(void *xsc) 1158 { 1159 struct bfe_softc *sc = xsc; 1160 struct ifnet *ifp; 1161 uint32_t istat, imask, flag; 1162 int s; 1163 1164 ifp = &sc->arpcom.ac_if; 1165 1166 s = splimp(); 1167 1168 istat = CSR_READ_4(sc, BFE_ISTAT); 1169 imask = CSR_READ_4(sc, BFE_IMASK); 1170 1171 /* 1172 * Defer unsolicited interrupts - This is necessary because setting the 1173 * chips interrupt mask register to 0 doesn't actually stop the 1174 * interrupts 1175 */ 1176 istat &= imask; 1177 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1178 CSR_READ_4(sc, BFE_ISTAT); 1179 1180 /* not expecting this interrupt, disregard it */ 1181 if (istat == 0) { 1182 splx(s); 1183 return; 1184 } 1185 1186 if (istat & BFE_ISTAT_ERRORS) { 1187 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1188 if (flag & BFE_STAT_EMASK) 1189 ifp->if_oerrors++; 1190 1191 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1192 if (flag & BFE_RX_FLAG_ERRORS) 1193 ifp->if_ierrors++; 1194 1195 ifp->if_flags &= ~IFF_RUNNING; 1196 bfe_init(sc); 1197 } 1198 1199 /* A packet was received */ 1200 if (istat & BFE_ISTAT_RX) 1201 bfe_rxeof(sc); 1202 1203 /* A packet was sent */ 1204 if (istat & BFE_ISTAT_TX) 1205 bfe_txeof(sc); 1206 1207 /* We have packets pending, fire them out */ 1208 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1209 bfe_start(ifp); 1210 1211 splx(s); 1212 } 1213 1214 static int 1215 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1216 { 1217 struct bfe_desc *d = NULL; 1218 struct bfe_data *r = NULL; 1219 struct mbuf *m; 1220 uint32_t frag, cur, cnt = 0; 1221 1222 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1223 return(ENOBUFS); 1224 1225 /* 1226 * Start packing the mbufs in this chain into 1227 * the fragment pointers. Stop when we run out 1228 * of fragments or hit the end of the mbuf chain. 1229 */ 1230 m = m_head; 1231 cur = frag = *txidx; 1232 cnt = 0; 1233 1234 for (m = m_head; m != NULL; m = m->m_next) { 1235 if (m->m_len != 0) { 1236 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1237 return(ENOBUFS); 1238 1239 d = &sc->bfe_tx_list[cur]; 1240 r = &sc->bfe_tx_ring[cur]; 1241 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1242 /* always intterupt on completion */ 1243 d->bfe_ctrl |= BFE_DESC_IOC; 1244 if (cnt == 0) 1245 /* Set start of frame */ 1246 d->bfe_ctrl |= BFE_DESC_SOF; 1247 if (cur == BFE_TX_LIST_CNT - 1) 1248 /* 1249 * Tell the chip to wrap to the start of the 1250 *descriptor list 1251 */ 1252 d->bfe_ctrl |= BFE_DESC_EOT; 1253 1254 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*), 1255 m->m_len, bfe_dma_map_desc, d, 0); 1256 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1257 BUS_DMASYNC_PREREAD); 1258 1259 frag = cur; 1260 BFE_INC(cur, BFE_TX_LIST_CNT); 1261 cnt++; 1262 } 1263 } 1264 1265 if (m != NULL) 1266 return(ENOBUFS); 1267 1268 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1269 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1270 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1271 1272 *txidx = cur; 1273 sc->bfe_tx_cnt += cnt; 1274 return(0); 1275 } 1276 1277 /* 1278 * Set up to transmit a packet 1279 */ 1280 static void 1281 bfe_start(struct ifnet *ifp) 1282 { 1283 struct bfe_softc *sc; 1284 struct mbuf *m_head = NULL; 1285 int idx; 1286 int s; 1287 1288 sc = ifp->if_softc; 1289 idx = sc->bfe_tx_prod; 1290 1291 s = splimp(); 1292 1293 /* 1294 * not much point trying to send if the link is down or we have nothing to 1295 * send 1296 */ 1297 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1298 splx(s); 1299 return; 1300 } 1301 1302 if (ifp->if_flags & IFF_OACTIVE) { 1303 splx(s); 1304 return; 1305 } 1306 1307 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1308 IF_DEQUEUE(&ifp->if_snd, m_head); 1309 if (m_head == NULL) 1310 break; 1311 1312 /* 1313 * Pack the data into the tx ring. If we dont have enough room, let 1314 * the chip drain the ring 1315 */ 1316 if (bfe_encap(sc, m_head, &idx)) { 1317 IF_PREPEND(&ifp->if_snd, m_head); 1318 ifp->if_flags |= IFF_OACTIVE; 1319 break; 1320 } 1321 1322 /* 1323 * If there's a BPF listener, bounce a copy of this frame 1324 * to him. 1325 */ 1326 BPF_MTAP(ifp, m_head); 1327 } 1328 1329 sc->bfe_tx_prod = idx; 1330 /* Transmit - twice due to apparent hardware bug */ 1331 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1332 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1333 1334 /* 1335 * Set a timeout in case the chip goes out to lunch. 1336 */ 1337 ifp->if_timer = 5; 1338 splx(s); 1339 } 1340 1341 static void 1342 bfe_init(void *xsc) 1343 { 1344 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1345 struct ifnet *ifp = &sc->arpcom.ac_if; 1346 int s; 1347 1348 s = splimp(); 1349 1350 if (ifp->if_flags & IFF_RUNNING) { 1351 splx(s); 1352 return; 1353 } 1354 1355 bfe_stop(sc); 1356 bfe_chip_reset(sc); 1357 1358 if (bfe_list_rx_init(sc) == ENOBUFS) { 1359 printf("bfe%d: bfe_init failed. Not enough memory for list buffers\n", 1360 sc->bfe_unit); 1361 bfe_stop(sc); 1362 return; 1363 } 1364 1365 bfe_set_rx_mode(sc); 1366 1367 /* Enable the chip and core */ 1368 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1369 /* Enable interrupts */ 1370 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1371 1372 bfe_ifmedia_upd(ifp); 1373 ifp->if_flags |= IFF_RUNNING; 1374 ifp->if_flags &= ~IFF_OACTIVE; 1375 1376 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1377 splx(s); 1378 } 1379 1380 /* 1381 * Set media options. 1382 */ 1383 static int 1384 bfe_ifmedia_upd(struct ifnet *ifp) 1385 { 1386 struct bfe_softc *sc; 1387 struct mii_data *mii; 1388 int s; 1389 1390 sc = ifp->if_softc; 1391 1392 s = splimp(); 1393 1394 mii = device_get_softc(sc->bfe_miibus); 1395 sc->bfe_link = 0; 1396 if (mii->mii_instance) { 1397 struct mii_softc *miisc; 1398 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1399 miisc = LIST_NEXT(miisc, mii_list)) 1400 mii_phy_reset(miisc); 1401 } 1402 mii_mediachg(mii); 1403 1404 splx(s); 1405 return(0); 1406 } 1407 1408 /* 1409 * Report current media status. 1410 */ 1411 static void 1412 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1413 { 1414 struct bfe_softc *sc = ifp->if_softc; 1415 struct mii_data *mii; 1416 int s; 1417 1418 s = splimp(); 1419 1420 mii = device_get_softc(sc->bfe_miibus); 1421 mii_pollstat(mii); 1422 ifmr->ifm_active = mii->mii_media_active; 1423 ifmr->ifm_status = mii->mii_media_status; 1424 1425 splx(s); 1426 } 1427 1428 static int 1429 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1430 { 1431 struct bfe_softc *sc = ifp->if_softc; 1432 struct ifreq *ifr = (struct ifreq *) data; 1433 struct mii_data *mii; 1434 int error = 0; 1435 int s; 1436 1437 s = splimp(); 1438 1439 switch (command) { 1440 case SIOCSIFFLAGS: 1441 if (ifp->if_flags & IFF_UP) 1442 if (ifp->if_flags & IFF_RUNNING) 1443 bfe_set_rx_mode(sc); 1444 else 1445 bfe_init(sc); 1446 else if (ifp->if_flags & IFF_RUNNING) 1447 bfe_stop(sc); 1448 break; 1449 case SIOCADDMULTI: 1450 case SIOCDELMULTI: 1451 if (ifp->if_flags & IFF_RUNNING) 1452 bfe_set_rx_mode(sc); 1453 break; 1454 case SIOCGIFMEDIA: 1455 case SIOCSIFMEDIA: 1456 mii = device_get_softc(sc->bfe_miibus); 1457 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1458 command); 1459 break; 1460 case SIOCSIFADDR: 1461 case SIOCGIFADDR: 1462 case SIOCSIFMTU: 1463 error = ether_ioctl(ifp, command, data); 1464 break; 1465 1466 default: 1467 error = EINVAL; 1468 break; 1469 } 1470 1471 splx(s); 1472 return error; 1473 } 1474 1475 static void 1476 bfe_watchdog(struct ifnet *ifp) 1477 { 1478 struct bfe_softc *sc; 1479 int s; 1480 1481 sc = ifp->if_softc; 1482 1483 s = splimp(); 1484 1485 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1486 1487 ifp->if_flags &= ~IFF_RUNNING; 1488 bfe_init(sc); 1489 1490 ifp->if_oerrors++; 1491 1492 splx(s); 1493 } 1494 1495 static void 1496 bfe_tick(void *xsc) 1497 { 1498 struct bfe_softc *sc = xsc; 1499 struct mii_data *mii; 1500 int s; 1501 1502 if (sc == NULL) 1503 return; 1504 1505 s = splimp(); 1506 1507 mii = device_get_softc(sc->bfe_miibus); 1508 1509 bfe_stats_update(sc); 1510 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1511 1512 if (sc->bfe_link) { 1513 splx(s); 1514 return; 1515 } 1516 1517 mii_tick(mii); 1518 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1519 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1520 sc->bfe_link++; 1521 1522 if (!sc->bfe_link) 1523 sc->bfe_link++; 1524 1525 splx(s); 1526 } 1527 1528 /* 1529 * Stop the adapter and free any mbufs allocated to the 1530 * RX and TX lists. 1531 */ 1532 static void 1533 bfe_stop(struct bfe_softc *sc) 1534 { 1535 struct ifnet *ifp; 1536 int s; 1537 1538 s = splimp(); 1539 1540 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1541 1542 ifp = &sc->arpcom.ac_if; 1543 1544 bfe_chip_halt(sc); 1545 bfe_tx_ring_free(sc); 1546 bfe_rx_ring_free(sc); 1547 1548 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1549 1550 splx(s); 1551 } 1552