1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.22 2003/05/11 18:00:55 ps Exp $ 34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.8 2003/11/05 05:30:29 drhodus Exp $ 35 * 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Engineer, Wind River Systems 43 */ 44 45 /* 46 * The Broadcom BCM5700 is based on technology originally developed by 47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 51 * frames, highly configurable RX filtering, and 16 RX and TX queues 52 * (which, along with RX filter rules, can be used for QOS applications). 53 * Other features, such as TCP segmentation, may be available as part 54 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 55 * firmware images can be stored in hardware and need not be compiled 56 * into the driver. 57 * 58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 60 * 61 * The BCM5701 is a single-chip solution incorporating both the BCM5700 62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 63 * does not support external SSRAM. 64 * 65 * Broadcom also produces a variation of the BCM5700 under the "Altima" 66 * brand name, which is functionally similar but lacks PCI-X support. 67 * 68 * Without external SSRAM, you can only have at most 4 TX rings, 69 * and the use of the mini RX ring is disabled. This seems to imply 70 * that these features are simply not available on the BCM5701. As a 71 * result, this driver does not implement any support for the mini RX 72 * ring. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/sockio.h> 78 #include <sys/mbuf.h> 79 #include <sys/malloc.h> 80 #include <sys/kernel.h> 81 #include <sys/socket.h> 82 #include <sys/queue.h> 83 84 #include <net/if.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #include <net/bpf.h> 91 92 #include <net/if_types.h> 93 #include <net/vlan/if_vlan_var.h> 94 95 #include <netinet/in_systm.h> 96 #include <netinet/in.h> 97 #include <netinet/ip.h> 98 99 #include <vm/vm.h> /* for vtophys */ 100 #include <vm/pmap.h> /* for vtophys */ 101 #include <machine/clock.h> /* for DELAY */ 102 #include <machine/bus_memio.h> 103 #include <machine/bus.h> 104 #include <machine/resource.h> 105 #include <sys/bus.h> 106 #include <sys/rman.h> 107 108 #include <dev/netif/mii_layer/mii.h> 109 #include <dev/netif/mii_layer/miivar.h> 110 #include <dev/netif/mii_layer/miidevs.h> 111 #include <dev/netif/mii_layer/brgphyreg.h> 112 113 #include <bus/pci/pcireg.h> 114 #include <bus/pci/pcivar.h> 115 116 #include "if_bgereg.h" 117 118 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 /* 124 * Various supported device vendors/types and their names. Note: the 125 * spec seems to indicate that the hardware still has Alteon's vendor 126 * ID burned into it, though it will always be overriden by the vendor 127 * ID in the EEPROM. Just to be safe, we cover all possibilities. 128 */ 129 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 130 131 static struct bge_type bge_devs[] = { 132 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 133 "Broadcom BCM5700 Gigabit Ethernet" }, 134 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 135 "Broadcom BCM5701 Gigabit Ethernet" }, 136 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 137 "Broadcom BCM5700 Gigabit Ethernet" }, 138 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 139 "Broadcom BCM5701 Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 141 "Broadcom BCM5702X Gigabit Ethernet" }, 142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 143 "Broadcom BCM5703X Gigabit Ethernet" }, 144 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C, 145 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 146 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S, 147 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 148 { SK_VENDORID, SK_DEVICEID_ALTIMA, 149 "SysKonnect Gigabit Ethernet" }, 150 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 151 "Altima AC1000 Gigabit Ethernet" }, 152 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 153 "Altima AC9100 Gigabit Ethernet" }, 154 { 0, 0, NULL } 155 }; 156 157 static int bge_probe (device_t); 158 static int bge_attach (device_t); 159 static int bge_detach (device_t); 160 static void bge_release_resources 161 (struct bge_softc *); 162 static void bge_txeof (struct bge_softc *); 163 static void bge_rxeof (struct bge_softc *); 164 165 static void bge_tick (void *); 166 static void bge_stats_update (struct bge_softc *); 167 static int bge_encap (struct bge_softc *, struct mbuf *, 168 u_int32_t *); 169 170 static void bge_intr (void *); 171 static void bge_start (struct ifnet *); 172 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 173 static void bge_init (void *); 174 static void bge_stop (struct bge_softc *); 175 static void bge_watchdog (struct ifnet *); 176 static void bge_shutdown (device_t); 177 static int bge_ifmedia_upd (struct ifnet *); 178 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 179 180 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, 181 int, u_int8_t *); 182 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 183 184 static u_int32_t bge_crc (caddr_t); 185 static void bge_setmulti (struct bge_softc *); 186 187 static void bge_handle_events (struct bge_softc *); 188 static int bge_alloc_jumbo_mem (struct bge_softc *); 189 static void bge_free_jumbo_mem (struct bge_softc *); 190 static void *bge_jalloc (struct bge_softc *); 191 static void bge_jfree (caddr_t, u_int); 192 static void bge_jref (caddr_t, u_int); 193 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 194 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 195 static int bge_init_rx_ring_std (struct bge_softc *); 196 static void bge_free_rx_ring_std (struct bge_softc *); 197 static int bge_init_rx_ring_jumbo (struct bge_softc *); 198 static void bge_free_rx_ring_jumbo (struct bge_softc *); 199 static void bge_free_tx_ring (struct bge_softc *); 200 static int bge_init_tx_ring (struct bge_softc *); 201 202 static int bge_chipinit (struct bge_softc *); 203 static int bge_blockinit (struct bge_softc *); 204 205 #ifdef notdef 206 static u_int8_t bge_vpd_readbyte (struct bge_softc *, int); 207 static void bge_vpd_read_res (struct bge_softc *, 208 struct vpd_res *, int); 209 static void bge_vpd_read (struct bge_softc *); 210 #endif 211 212 static u_int32_t bge_readmem_ind 213 (struct bge_softc *, int); 214 static void bge_writemem_ind (struct bge_softc *, int, int); 215 #ifdef notdef 216 static u_int32_t bge_readreg_ind 217 (struct bge_softc *, int); 218 #endif 219 static void bge_writereg_ind (struct bge_softc *, int, int); 220 221 static int bge_miibus_readreg (device_t, int, int); 222 static int bge_miibus_writereg (device_t, int, int, int); 223 static void bge_miibus_statchg (device_t); 224 225 static void bge_reset (struct bge_softc *); 226 227 static device_method_t bge_methods[] = { 228 /* Device interface */ 229 DEVMETHOD(device_probe, bge_probe), 230 DEVMETHOD(device_attach, bge_attach), 231 DEVMETHOD(device_detach, bge_detach), 232 DEVMETHOD(device_shutdown, bge_shutdown), 233 234 /* bus interface */ 235 DEVMETHOD(bus_print_child, bus_generic_print_child), 236 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 237 238 /* MII interface */ 239 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 240 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 241 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 242 243 { 0, 0 } 244 }; 245 246 static driver_t bge_driver = { 247 "bge", 248 bge_methods, 249 sizeof(struct bge_softc) 250 }; 251 252 static devclass_t bge_devclass; 253 254 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 255 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 256 257 static u_int32_t 258 bge_readmem_ind(sc, off) 259 struct bge_softc *sc; 260 int off; 261 { 262 device_t dev; 263 264 dev = sc->bge_dev; 265 266 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 267 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 268 } 269 270 static void 271 bge_writemem_ind(sc, off, val) 272 struct bge_softc *sc; 273 int off, val; 274 { 275 device_t dev; 276 277 dev = sc->bge_dev; 278 279 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 280 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 281 282 return; 283 } 284 285 #ifdef notdef 286 static u_int32_t 287 bge_readreg_ind(sc, off) 288 struct bge_softc *sc; 289 int off; 290 { 291 device_t dev; 292 293 dev = sc->bge_dev; 294 295 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 296 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 297 } 298 #endif 299 300 static void 301 bge_writereg_ind(sc, off, val) 302 struct bge_softc *sc; 303 int off, val; 304 { 305 device_t dev; 306 307 dev = sc->bge_dev; 308 309 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 310 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 311 312 return; 313 } 314 315 #ifdef notdef 316 static u_int8_t 317 bge_vpd_readbyte(sc, addr) 318 struct bge_softc *sc; 319 int addr; 320 { 321 int i; 322 device_t dev; 323 u_int32_t val; 324 325 dev = sc->bge_dev; 326 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 327 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 328 DELAY(10); 329 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 330 break; 331 } 332 333 if (i == BGE_TIMEOUT) { 334 printf("bge%d: VPD read timed out\n", sc->bge_unit); 335 return(0); 336 } 337 338 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 339 340 return((val >> ((addr % 4) * 8)) & 0xFF); 341 } 342 343 static void 344 bge_vpd_read_res(sc, res, addr) 345 struct bge_softc *sc; 346 struct vpd_res *res; 347 int addr; 348 { 349 int i; 350 u_int8_t *ptr; 351 352 ptr = (u_int8_t *)res; 353 for (i = 0; i < sizeof(struct vpd_res); i++) 354 ptr[i] = bge_vpd_readbyte(sc, i + addr); 355 356 return; 357 } 358 359 static void 360 bge_vpd_read(sc) 361 struct bge_softc *sc; 362 { 363 int pos = 0, i; 364 struct vpd_res res; 365 366 if (sc->bge_vpd_prodname != NULL) 367 free(sc->bge_vpd_prodname, M_DEVBUF); 368 if (sc->bge_vpd_readonly != NULL) 369 free(sc->bge_vpd_readonly, M_DEVBUF); 370 sc->bge_vpd_prodname = NULL; 371 sc->bge_vpd_readonly = NULL; 372 373 bge_vpd_read_res(sc, &res, pos); 374 375 if (res.vr_id != VPD_RES_ID) { 376 printf("bge%d: bad VPD resource id: expected %x got %x\n", 377 sc->bge_unit, VPD_RES_ID, res.vr_id); 378 return; 379 } 380 381 pos += sizeof(res); 382 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 383 for (i = 0; i < res.vr_len; i++) 384 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 385 sc->bge_vpd_prodname[i] = '\0'; 386 pos += i; 387 388 bge_vpd_read_res(sc, &res, pos); 389 390 if (res.vr_id != VPD_RES_READ) { 391 printf("bge%d: bad VPD resource id: expected %x got %x\n", 392 sc->bge_unit, VPD_RES_READ, res.vr_id); 393 return; 394 } 395 396 pos += sizeof(res); 397 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 398 for (i = 0; i < res.vr_len + 1; i++) 399 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 400 401 return; 402 } 403 #endif 404 405 /* 406 * Read a byte of data stored in the EEPROM at address 'addr.' The 407 * BCM570x supports both the traditional bitbang interface and an 408 * auto access interface for reading the EEPROM. We use the auto 409 * access method. 410 */ 411 static u_int8_t 412 bge_eeprom_getbyte(sc, addr, dest) 413 struct bge_softc *sc; 414 int addr; 415 u_int8_t *dest; 416 { 417 int i; 418 u_int32_t byte = 0; 419 420 /* 421 * Enable use of auto EEPROM access so we can avoid 422 * having to use the bitbang method. 423 */ 424 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 425 426 /* Reset the EEPROM, load the clock period. */ 427 CSR_WRITE_4(sc, BGE_EE_ADDR, 428 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 429 DELAY(20); 430 431 /* Issue the read EEPROM command. */ 432 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 433 434 /* Wait for completion */ 435 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 436 DELAY(10); 437 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 438 break; 439 } 440 441 if (i == BGE_TIMEOUT) { 442 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 443 return(0); 444 } 445 446 /* Get result. */ 447 byte = CSR_READ_4(sc, BGE_EE_DATA); 448 449 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 450 451 return(0); 452 } 453 454 /* 455 * Read a sequence of bytes from the EEPROM. 456 */ 457 static int 458 bge_read_eeprom(sc, dest, off, cnt) 459 struct bge_softc *sc; 460 caddr_t dest; 461 int off; 462 int cnt; 463 { 464 int err = 0, i; 465 u_int8_t byte = 0; 466 467 for (i = 0; i < cnt; i++) { 468 err = bge_eeprom_getbyte(sc, off + i, &byte); 469 if (err) 470 break; 471 *(dest + i) = byte; 472 } 473 474 return(err ? 1 : 0); 475 } 476 477 static int 478 bge_miibus_readreg(dev, phy, reg) 479 device_t dev; 480 int phy, reg; 481 { 482 struct bge_softc *sc; 483 struct ifnet *ifp; 484 u_int32_t val, autopoll; 485 int i; 486 487 sc = device_get_softc(dev); 488 ifp = &sc->arpcom.ac_if; 489 490 if (phy != 1) 491 switch(sc->bge_chipid) { 492 case BGE_CHIPID_BCM5701_B5: 493 case BGE_CHIPID_BCM5703_A2: 494 case BGE_CHIPID_BCM5704_A0: 495 return(0); 496 } 497 498 /* Reading with autopolling on may trigger PCI errors */ 499 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 500 if (autopoll & BGE_MIMODE_AUTOPOLL) { 501 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 502 DELAY(40); 503 } 504 505 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 506 BGE_MIPHY(phy)|BGE_MIREG(reg)); 507 508 for (i = 0; i < BGE_TIMEOUT; i++) { 509 val = CSR_READ_4(sc, BGE_MI_COMM); 510 if (!(val & BGE_MICOMM_BUSY)) 511 break; 512 } 513 514 if (i == BGE_TIMEOUT) { 515 printf("bge%d: PHY read timed out\n", sc->bge_unit); 516 val = 0; 517 goto done; 518 } 519 520 val = CSR_READ_4(sc, BGE_MI_COMM); 521 522 done: 523 if (autopoll & BGE_MIMODE_AUTOPOLL) { 524 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 525 DELAY(40); 526 } 527 528 if (val & BGE_MICOMM_READFAIL) 529 return(0); 530 531 return(val & 0xFFFF); 532 } 533 534 static int 535 bge_miibus_writereg(dev, phy, reg, val) 536 device_t dev; 537 int phy, reg, val; 538 { 539 struct bge_softc *sc; 540 u_int32_t autopoll; 541 int i; 542 543 sc = device_get_softc(dev); 544 545 /* Reading with autopolling on may trigger PCI errors */ 546 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 547 if (autopoll & BGE_MIMODE_AUTOPOLL) { 548 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 549 DELAY(40); 550 } 551 552 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 553 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 554 555 for (i = 0; i < BGE_TIMEOUT; i++) { 556 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 557 break; 558 } 559 560 if (autopoll & BGE_MIMODE_AUTOPOLL) { 561 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 562 DELAY(40); 563 } 564 565 if (i == BGE_TIMEOUT) { 566 printf("bge%d: PHY read timed out\n", sc->bge_unit); 567 return(0); 568 } 569 570 return(0); 571 } 572 573 static void 574 bge_miibus_statchg(dev) 575 device_t dev; 576 { 577 struct bge_softc *sc; 578 struct mii_data *mii; 579 580 sc = device_get_softc(dev); 581 mii = device_get_softc(sc->bge_miibus); 582 583 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 584 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) { 585 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 586 } else { 587 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 588 } 589 590 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 591 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 592 } else { 593 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 594 } 595 596 return; 597 } 598 599 /* 600 * Handle events that have triggered interrupts. 601 */ 602 static void 603 bge_handle_events(sc) 604 struct bge_softc *sc; 605 { 606 607 return; 608 } 609 610 /* 611 * Memory management for jumbo frames. 612 */ 613 614 static int 615 bge_alloc_jumbo_mem(sc) 616 struct bge_softc *sc; 617 { 618 caddr_t ptr; 619 int i; 620 struct bge_jpool_entry *entry; 621 622 /* Grab a big chunk o' storage. */ 623 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 624 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 625 626 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 627 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 628 return(ENOBUFS); 629 } 630 631 SLIST_INIT(&sc->bge_jfree_listhead); 632 SLIST_INIT(&sc->bge_jinuse_listhead); 633 634 /* 635 * Now divide it up into 9K pieces and save the addresses 636 * in an array. Note that we play an evil trick here by using 637 * the first few bytes in the buffer to hold the the address 638 * of the softc structure for this interface. This is because 639 * bge_jfree() needs it, but it is called by the mbuf management 640 * code which will not pass it to us explicitly. 641 */ 642 ptr = sc->bge_cdata.bge_jumbo_buf; 643 for (i = 0; i < BGE_JSLOTS; i++) { 644 u_int64_t **aptr; 645 aptr = (u_int64_t **)ptr; 646 aptr[0] = (u_int64_t *)sc; 647 ptr += sizeof(u_int64_t); 648 sc->bge_cdata.bge_jslots[i].bge_buf = ptr; 649 sc->bge_cdata.bge_jslots[i].bge_inuse = 0; 650 ptr += (BGE_JLEN - sizeof(u_int64_t)); 651 entry = malloc(sizeof(struct bge_jpool_entry), 652 M_DEVBUF, M_NOWAIT); 653 if (entry == NULL) { 654 contigfree(sc->bge_cdata.bge_jumbo_buf, 655 BGE_JMEM, M_DEVBUF); 656 sc->bge_cdata.bge_jumbo_buf = NULL; 657 printf("bge%d: no memory for jumbo " 658 "buffer queue!\n", sc->bge_unit); 659 return(ENOBUFS); 660 } 661 entry->slot = i; 662 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 663 entry, jpool_entries); 664 } 665 666 return(0); 667 } 668 669 static void 670 bge_free_jumbo_mem(sc) 671 struct bge_softc *sc; 672 { 673 int i; 674 struct bge_jpool_entry *entry; 675 676 for (i = 0; i < BGE_JSLOTS; i++) { 677 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 678 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 679 free(entry, M_DEVBUF); 680 } 681 682 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 683 684 return; 685 } 686 687 /* 688 * Allocate a jumbo buffer. 689 */ 690 static void * 691 bge_jalloc(sc) 692 struct bge_softc *sc; 693 { 694 struct bge_jpool_entry *entry; 695 696 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 697 698 if (entry == NULL) { 699 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 700 return(NULL); 701 } 702 703 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 704 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 705 sc->bge_cdata.bge_jslots[entry->slot].bge_inuse = 1; 706 return(sc->bge_cdata.bge_jslots[entry->slot].bge_buf); 707 } 708 709 /* 710 * Adjust usage count on a jumbo buffer. 711 */ 712 static void 713 bge_jref(buf, size) 714 caddr_t buf; 715 u_int size; 716 { 717 struct bge_softc *sc; 718 u_int64_t **aptr; 719 int i; 720 721 /* Extract the softc struct pointer. */ 722 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 723 sc = (struct bge_softc *)(aptr[0]); 724 725 if (sc == NULL) 726 panic("bge_jref: can't find softc pointer!"); 727 728 if (size != BGE_JUMBO_FRAMELEN) 729 panic("bge_jref: adjusting refcount of buf of wrong size!"); 730 731 /* calculate the slot this buffer belongs to */ 732 733 i = ((vm_offset_t)aptr 734 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 735 736 if ((i < 0) || (i >= BGE_JSLOTS)) 737 panic("bge_jref: asked to reference buffer " 738 "that we don't manage!"); 739 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0) 740 panic("bge_jref: buffer already free!"); 741 else 742 sc->bge_cdata.bge_jslots[i].bge_inuse++; 743 744 return; 745 } 746 747 /* 748 * Release a jumbo buffer. 749 */ 750 static void 751 bge_jfree(buf, size) 752 caddr_t buf; 753 u_int size; 754 { 755 struct bge_softc *sc; 756 u_int64_t **aptr; 757 int i; 758 struct bge_jpool_entry *entry; 759 760 /* Extract the softc struct pointer. */ 761 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 762 sc = (struct bge_softc *)(aptr[0]); 763 764 if (sc == NULL) 765 panic("bge_jfree: can't find softc pointer!"); 766 767 if (size != BGE_JUMBO_FRAMELEN) 768 panic("bge_jfree: freeing buffer of wrong size!"); 769 770 /* calculate the slot this buffer belongs to */ 771 772 i = ((vm_offset_t)aptr 773 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 774 775 if ((i < 0) || (i >= BGE_JSLOTS)) 776 panic("bge_jfree: asked to free buffer that we don't manage!"); 777 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0) 778 panic("bge_jfree: buffer already free!"); 779 else { 780 sc->bge_cdata.bge_jslots[i].bge_inuse--; 781 if(sc->bge_cdata.bge_jslots[i].bge_inuse == 0) { 782 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 783 if (entry == NULL) 784 panic("bge_jfree: buffer not in use!"); 785 entry->slot = i; 786 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, 787 jpool_entries); 788 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 789 entry, jpool_entries); 790 } 791 } 792 793 return; 794 } 795 796 797 /* 798 * Intialize a standard receive ring descriptor. 799 */ 800 static int 801 bge_newbuf_std(sc, i, m) 802 struct bge_softc *sc; 803 int i; 804 struct mbuf *m; 805 { 806 struct mbuf *m_new = NULL; 807 struct bge_rx_bd *r; 808 809 if (m == NULL) { 810 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 811 if (m_new == NULL) { 812 return(ENOBUFS); 813 } 814 815 MCLGET(m_new, M_DONTWAIT); 816 if (!(m_new->m_flags & M_EXT)) { 817 m_freem(m_new); 818 return(ENOBUFS); 819 } 820 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 821 } else { 822 m_new = m; 823 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 824 m_new->m_data = m_new->m_ext.ext_buf; 825 } 826 827 if (!sc->bge_rx_alignment_bug) 828 m_adj(m_new, ETHER_ALIGN); 829 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 830 r = &sc->bge_rdata->bge_rx_std_ring[i]; 831 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 832 r->bge_flags = BGE_RXBDFLAG_END; 833 r->bge_len = m_new->m_len; 834 r->bge_idx = i; 835 836 return(0); 837 } 838 839 /* 840 * Initialize a jumbo receive ring descriptor. This allocates 841 * a jumbo buffer from the pool managed internally by the driver. 842 */ 843 static int 844 bge_newbuf_jumbo(sc, i, m) 845 struct bge_softc *sc; 846 int i; 847 struct mbuf *m; 848 { 849 struct mbuf *m_new = NULL; 850 struct bge_rx_bd *r; 851 852 if (m == NULL) { 853 caddr_t *buf = NULL; 854 855 /* Allocate the mbuf. */ 856 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 857 if (m_new == NULL) { 858 return(ENOBUFS); 859 } 860 861 /* Allocate the jumbo buffer */ 862 buf = bge_jalloc(sc); 863 if (buf == NULL) { 864 m_freem(m_new); 865 printf("bge%d: jumbo allocation failed " 866 "-- packet dropped!\n", sc->bge_unit); 867 return(ENOBUFS); 868 } 869 870 /* Attach the buffer to the mbuf. */ 871 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 872 m_new->m_flags |= M_EXT; 873 m_new->m_len = m_new->m_pkthdr.len = 874 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 875 m_new->m_ext.ext_free = bge_jfree; 876 m_new->m_ext.ext_ref = bge_jref; 877 } else { 878 m_new = m; 879 m_new->m_data = m_new->m_ext.ext_buf; 880 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 881 } 882 883 if (!sc->bge_rx_alignment_bug) 884 m_adj(m_new, ETHER_ALIGN); 885 /* Set up the descriptor. */ 886 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 887 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 888 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 889 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 890 r->bge_len = m_new->m_len; 891 r->bge_idx = i; 892 893 return(0); 894 } 895 896 /* 897 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 898 * that's 1MB or memory, which is a lot. For now, we fill only the first 899 * 256 ring entries and hope that our CPU is fast enough to keep up with 900 * the NIC. 901 */ 902 static int 903 bge_init_rx_ring_std(sc) 904 struct bge_softc *sc; 905 { 906 int i; 907 908 for (i = 0; i < BGE_SSLOTS; i++) { 909 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 910 return(ENOBUFS); 911 }; 912 913 sc->bge_std = i - 1; 914 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 915 916 return(0); 917 } 918 919 static void 920 bge_free_rx_ring_std(sc) 921 struct bge_softc *sc; 922 { 923 int i; 924 925 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 926 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 927 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 928 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 929 } 930 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 931 sizeof(struct bge_rx_bd)); 932 } 933 934 return; 935 } 936 937 static int 938 bge_init_rx_ring_jumbo(sc) 939 struct bge_softc *sc; 940 { 941 int i; 942 struct bge_rcb *rcb; 943 944 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 945 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 946 return(ENOBUFS); 947 }; 948 949 sc->bge_jumbo = i - 1; 950 951 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 952 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 953 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 954 955 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 956 957 return(0); 958 } 959 960 static void 961 bge_free_rx_ring_jumbo(sc) 962 struct bge_softc *sc; 963 { 964 int i; 965 966 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 967 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 968 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 969 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 970 } 971 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 972 sizeof(struct bge_rx_bd)); 973 } 974 975 return; 976 } 977 978 static void 979 bge_free_tx_ring(sc) 980 struct bge_softc *sc; 981 { 982 int i; 983 984 if (sc->bge_rdata->bge_tx_ring == NULL) 985 return; 986 987 for (i = 0; i < BGE_TX_RING_CNT; i++) { 988 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 989 m_freem(sc->bge_cdata.bge_tx_chain[i]); 990 sc->bge_cdata.bge_tx_chain[i] = NULL; 991 } 992 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 993 sizeof(struct bge_tx_bd)); 994 } 995 996 return; 997 } 998 999 static int 1000 bge_init_tx_ring(sc) 1001 struct bge_softc *sc; 1002 { 1003 sc->bge_txcnt = 0; 1004 sc->bge_tx_saved_considx = 0; 1005 1006 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1007 /* 5700 b2 errata */ 1008 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1009 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1010 1011 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1012 /* 5700 b2 errata */ 1013 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1014 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1015 1016 return(0); 1017 } 1018 1019 #define BGE_POLY 0xEDB88320 1020 1021 static u_int32_t 1022 bge_crc(addr) 1023 caddr_t addr; 1024 { 1025 u_int32_t idx, bit, data, crc; 1026 1027 /* Compute CRC for the address value. */ 1028 crc = 0xFFFFFFFF; /* initial value */ 1029 1030 for (idx = 0; idx < 6; idx++) { 1031 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1032 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 1033 } 1034 1035 return(crc & 0x7F); 1036 } 1037 1038 static void 1039 bge_setmulti(sc) 1040 struct bge_softc *sc; 1041 { 1042 struct ifnet *ifp; 1043 struct ifmultiaddr *ifma; 1044 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1045 int h, i; 1046 1047 ifp = &sc->arpcom.ac_if; 1048 1049 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1050 for (i = 0; i < 4; i++) 1051 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1052 return; 1053 } 1054 1055 /* First, zot all the existing filters. */ 1056 for (i = 0; i < 4; i++) 1057 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1058 1059 /* Now program new ones. */ 1060 for (ifma = ifp->if_multiaddrs.lh_first; 1061 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1062 if (ifma->ifma_addr->sa_family != AF_LINK) 1063 continue; 1064 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1065 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1066 } 1067 1068 for (i = 0; i < 4; i++) 1069 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1070 1071 return; 1072 } 1073 1074 /* 1075 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1076 * self-test results. 1077 */ 1078 static int 1079 bge_chipinit(sc) 1080 struct bge_softc *sc; 1081 { 1082 int i; 1083 u_int32_t dma_rw_ctl; 1084 1085 /* Set endianness before we access any non-PCI registers. */ 1086 #if BYTE_ORDER == BIG_ENDIAN 1087 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1088 BGE_BIGENDIAN_INIT, 4); 1089 #else 1090 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1091 BGE_LITTLEENDIAN_INIT, 4); 1092 #endif 1093 1094 /* 1095 * Check the 'ROM failed' bit on the RX CPU to see if 1096 * self-tests passed. 1097 */ 1098 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1099 printf("bge%d: RX CPU self-diagnostics failed!\n", 1100 sc->bge_unit); 1101 return(ENODEV); 1102 } 1103 1104 /* Clear the MAC control register */ 1105 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1106 1107 /* 1108 * Clear the MAC statistics block in the NIC's 1109 * internal memory. 1110 */ 1111 for (i = BGE_STATS_BLOCK; 1112 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1113 BGE_MEMWIN_WRITE(sc, i, 0); 1114 1115 for (i = BGE_STATUS_BLOCK; 1116 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1117 BGE_MEMWIN_WRITE(sc, i, 0); 1118 1119 /* Set up the PCI DMA control register. */ 1120 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1121 BGE_PCISTATE_PCI_BUSMODE) { 1122 /* Conventional PCI bus */ 1123 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1124 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1125 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1126 (0x0F); 1127 } else { 1128 /* PCI-X bus */ 1129 /* 1130 * The 5704 uses a different encoding of read/write 1131 * watermarks. 1132 */ 1133 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1134 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1135 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1136 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1137 else 1138 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1139 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1140 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1141 (0x0F); 1142 1143 /* 1144 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1145 * for hardware bugs. 1146 */ 1147 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1148 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1149 u_int32_t tmp; 1150 1151 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1152 if (tmp == 0x6 || tmp == 0x7) 1153 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1154 } 1155 } 1156 1157 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1158 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1159 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1160 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1161 1162 /* 1163 * Set up general mode register. 1164 */ 1165 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1166 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1167 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1168 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1169 BGE_MODECTL_RX_NO_PHDR_CSUM); 1170 1171 /* 1172 * Disable memory write invalidate. Apparently it is not supported 1173 * properly by these devices. 1174 */ 1175 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1176 1177 #ifdef __brokenalpha__ 1178 /* 1179 * Must insure that we do not cross an 8K (bytes) boundary 1180 * for DMA reads. Our highest limit is 1K bytes. This is a 1181 * restriction on some ALPHA platforms with early revision 1182 * 21174 PCI chipsets, such as the AlphaPC 164lx 1183 */ 1184 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1185 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1186 #endif 1187 1188 /* Set the timer prescaler (always 66Mhz) */ 1189 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1190 1191 return(0); 1192 } 1193 1194 static int 1195 bge_blockinit(sc) 1196 struct bge_softc *sc; 1197 { 1198 struct bge_rcb *rcb; 1199 volatile struct bge_rcb *vrcb; 1200 int i; 1201 1202 /* 1203 * Initialize the memory window pointer register so that 1204 * we can access the first 32K of internal NIC RAM. This will 1205 * allow us to set up the TX send ring RCBs and the RX return 1206 * ring RCBs, plus other things which live in NIC memory. 1207 */ 1208 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1209 1210 /* Configure mbuf memory pool */ 1211 if (sc->bge_extram) { 1212 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1213 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1214 } else { 1215 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1216 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1217 } 1218 1219 /* Configure DMA resource pool */ 1220 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1221 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1222 1223 /* Configure mbuf pool watermarks */ 1224 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1225 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1226 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1227 1228 /* Configure DMA resource watermarks */ 1229 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1230 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1231 1232 /* Enable buffer manager */ 1233 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1234 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1235 1236 /* Poll for buffer manager start indication */ 1237 for (i = 0; i < BGE_TIMEOUT; i++) { 1238 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1239 break; 1240 DELAY(10); 1241 } 1242 1243 if (i == BGE_TIMEOUT) { 1244 printf("bge%d: buffer manager failed to start\n", 1245 sc->bge_unit); 1246 return(ENXIO); 1247 } 1248 1249 /* Enable flow-through queues */ 1250 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1251 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1252 1253 /* Wait until queue initialization is complete */ 1254 for (i = 0; i < BGE_TIMEOUT; i++) { 1255 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1256 break; 1257 DELAY(10); 1258 } 1259 1260 if (i == BGE_TIMEOUT) { 1261 printf("bge%d: flow-through queue init failed\n", 1262 sc->bge_unit); 1263 return(ENXIO); 1264 } 1265 1266 /* Initialize the standard RX ring control block */ 1267 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1268 BGE_HOSTADDR(rcb->bge_hostaddr) = 1269 vtophys(&sc->bge_rdata->bge_rx_std_ring); 1270 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1271 if (sc->bge_extram) 1272 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1273 else 1274 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1275 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1276 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1277 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1278 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1279 1280 /* 1281 * Initialize the jumbo RX ring control block 1282 * We set the 'ring disabled' bit in the flags 1283 * field until we're actually ready to start 1284 * using this ring (i.e. once we set the MTU 1285 * high enough to require it). 1286 */ 1287 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1288 BGE_HOSTADDR(rcb->bge_hostaddr) = 1289 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring); 1290 rcb->bge_maxlen_flags = 1291 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, BGE_RCB_FLAG_RING_DISABLED); 1292 if (sc->bge_extram) 1293 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1294 else 1295 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1296 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1297 rcb->bge_hostaddr.bge_addr_hi); 1298 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1299 rcb->bge_hostaddr.bge_addr_lo); 1300 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1301 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1302 1303 /* Set up dummy disabled mini ring RCB */ 1304 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1305 rcb->bge_maxlen_flags = 1306 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1307 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1308 1309 /* 1310 * Set the BD ring replentish thresholds. The recommended 1311 * values are 1/8th the number of descriptors allocated to 1312 * each ring. 1313 */ 1314 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1315 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1316 1317 /* 1318 * Disable all unused send rings by setting the 'ring disabled' 1319 * bit in the flags field of all the TX send ring control blocks. 1320 * These are located in NIC memory. 1321 */ 1322 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1323 BGE_SEND_RING_RCB); 1324 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1325 vrcb->bge_maxlen_flags = 1326 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1327 vrcb->bge_nicaddr = 0; 1328 vrcb++; 1329 } 1330 1331 /* Configure TX RCB 0 (we use only the first ring) */ 1332 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1333 BGE_SEND_RING_RCB); 1334 vrcb->bge_hostaddr.bge_addr_hi = 0; 1335 BGE_HOSTADDR(vrcb->bge_hostaddr) = 1336 vtophys(&sc->bge_rdata->bge_tx_ring); 1337 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1338 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1339 1340 /* Disable all unused RX return rings */ 1341 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1342 BGE_RX_RETURN_RING_RCB); 1343 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1344 vrcb->bge_hostaddr.bge_addr_hi = 0; 1345 vrcb->bge_hostaddr.bge_addr_lo = 0; 1346 vrcb->bge_maxlen_flags = 1347 BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 1348 BGE_RCB_FLAG_RING_DISABLED); 1349 vrcb->bge_nicaddr = 0; 1350 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1351 (i * (sizeof(u_int64_t))), 0); 1352 vrcb++; 1353 } 1354 1355 /* Initialize RX ring indexes */ 1356 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1357 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1358 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1359 1360 /* 1361 * Set up RX return ring 0 1362 * Note that the NIC address for RX return rings is 0x00000000. 1363 * The return rings live entirely within the host, so the 1364 * nicaddr field in the RCB isn't used. 1365 */ 1366 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1367 BGE_RX_RETURN_RING_RCB); 1368 vrcb->bge_hostaddr.bge_addr_hi = 0; 1369 BGE_HOSTADDR(vrcb->bge_hostaddr) = 1370 vtophys(&sc->bge_rdata->bge_rx_return_ring); 1371 vrcb->bge_nicaddr = 0x00000000; 1372 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 0); 1373 1374 /* Set random backoff seed for TX */ 1375 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1376 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1377 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1378 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1379 BGE_TX_BACKOFF_SEED_MASK); 1380 1381 /* Set inter-packet gap */ 1382 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1383 1384 /* 1385 * Specify which ring to use for packets that don't match 1386 * any RX rules. 1387 */ 1388 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1389 1390 /* 1391 * Configure number of RX lists. One interrupt distribution 1392 * list, sixteen active lists, one bad frames class. 1393 */ 1394 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1395 1396 /* Inialize RX list placement stats mask. */ 1397 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1398 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1399 1400 /* Disable host coalescing until we get it set up */ 1401 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1402 1403 /* Poll to make sure it's shut down. */ 1404 for (i = 0; i < BGE_TIMEOUT; i++) { 1405 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1406 break; 1407 DELAY(10); 1408 } 1409 1410 if (i == BGE_TIMEOUT) { 1411 printf("bge%d: host coalescing engine failed to idle\n", 1412 sc->bge_unit); 1413 return(ENXIO); 1414 } 1415 1416 /* Set up host coalescing defaults */ 1417 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1418 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1419 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1420 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1421 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1422 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1423 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1424 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1425 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1426 1427 /* Set up address of statistics block */ 1428 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1429 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1430 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1431 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1432 1433 /* Set up address of status block */ 1434 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1435 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1436 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1437 vtophys(&sc->bge_rdata->bge_status_block)); 1438 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1439 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1440 1441 /* Turn on host coalescing state machine */ 1442 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1443 1444 /* Turn on RX BD completion state machine and enable attentions */ 1445 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1446 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1447 1448 /* Turn on RX list placement state machine */ 1449 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1450 1451 /* Turn on RX list selector state machine. */ 1452 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1453 1454 /* Turn on DMA, clear stats */ 1455 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1456 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1457 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1458 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1459 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1460 1461 /* Set misc. local control, enable interrupts on attentions */ 1462 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1463 1464 #ifdef notdef 1465 /* Assert GPIO pins for PHY reset */ 1466 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1467 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1468 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1469 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1470 #endif 1471 1472 /* Turn on DMA completion state machine */ 1473 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1474 1475 /* Turn on write DMA state machine */ 1476 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1477 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1478 1479 /* Turn on read DMA state machine */ 1480 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1481 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1482 1483 /* Turn on RX data completion state machine */ 1484 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1485 1486 /* Turn on RX BD initiator state machine */ 1487 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1488 1489 /* Turn on RX data and RX BD initiator state machine */ 1490 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1491 1492 /* Turn on Mbuf cluster free state machine */ 1493 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1494 1495 /* Turn on send BD completion state machine */ 1496 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1497 1498 /* Turn on send data completion state machine */ 1499 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1500 1501 /* Turn on send data initiator state machine */ 1502 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1503 1504 /* Turn on send BD initiator state machine */ 1505 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1506 1507 /* Turn on send BD selector state machine */ 1508 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1509 1510 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1511 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1512 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1513 1514 /* ack/clear link change events */ 1515 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1516 BGE_MACSTAT_CFG_CHANGED); 1517 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1518 1519 /* Enable PHY auto polling (for MII/GMII only) */ 1520 if (sc->bge_tbi) { 1521 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1522 } else { 1523 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1524 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1525 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1526 BGE_EVTENB_MI_INTERRUPT); 1527 } 1528 1529 /* Enable link state change attentions. */ 1530 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1531 1532 return(0); 1533 } 1534 1535 /* 1536 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1537 * against our list and return its name if we find a match. Note 1538 * that since the Broadcom controller contains VPD support, we 1539 * can get the device name string from the controller itself instead 1540 * of the compiled-in string. This is a little slow, but it guarantees 1541 * we'll always announce the right product name. 1542 */ 1543 static int 1544 bge_probe(dev) 1545 device_t dev; 1546 { 1547 struct bge_type *t; 1548 struct bge_softc *sc; 1549 char *descbuf; 1550 1551 t = bge_devs; 1552 1553 sc = device_get_softc(dev); 1554 bzero(sc, sizeof(struct bge_softc)); 1555 sc->bge_unit = device_get_unit(dev); 1556 sc->bge_dev = dev; 1557 1558 while(t->bge_name != NULL) { 1559 if ((pci_get_vendor(dev) == t->bge_vid) && 1560 (pci_get_device(dev) == t->bge_did)) { 1561 #ifdef notdef 1562 bge_vpd_read(sc); 1563 device_set_desc(dev, sc->bge_vpd_prodname); 1564 #endif 1565 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1566 if (descbuf == NULL) 1567 return(ENOMEM); 1568 snprintf(descbuf, BGE_DEVDESC_MAX, 1569 "%s, ASIC rev. %#04x", t->bge_name, 1570 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1571 device_set_desc_copy(dev, descbuf); 1572 free(descbuf, M_TEMP); 1573 return(0); 1574 } 1575 t++; 1576 } 1577 1578 return(ENXIO); 1579 } 1580 1581 static int 1582 bge_attach(dev) 1583 device_t dev; 1584 { 1585 int s; 1586 u_int32_t command; 1587 struct ifnet *ifp; 1588 struct bge_softc *sc; 1589 u_int32_t hwcfg = 0; 1590 u_int32_t mac_addr = 0; 1591 int unit, error = 0, rid; 1592 1593 s = splimp(); 1594 1595 sc = device_get_softc(dev); 1596 unit = device_get_unit(dev); 1597 sc->bge_dev = dev; 1598 sc->bge_unit = unit; 1599 1600 /* 1601 * Map control/status registers. 1602 */ 1603 command = pci_read_config(dev, PCIR_COMMAND, 4); 1604 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1605 pci_write_config(dev, PCIR_COMMAND, command, 4); 1606 command = pci_read_config(dev, PCIR_COMMAND, 4); 1607 1608 if (!(command & PCIM_CMD_MEMEN)) { 1609 printf("bge%d: failed to enable memory mapping!\n", unit); 1610 error = ENXIO; 1611 goto fail; 1612 } 1613 1614 rid = BGE_PCI_BAR0; 1615 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1616 0, ~0, 1, RF_ACTIVE); 1617 1618 if (sc->bge_res == NULL) { 1619 printf ("bge%d: couldn't map memory\n", unit); 1620 error = ENXIO; 1621 goto fail; 1622 } 1623 1624 sc->bge_btag = rman_get_bustag(sc->bge_res); 1625 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1626 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1627 1628 /* 1629 * XXX FIXME: rman_get_virtual() on the alpha is currently 1630 * broken and returns a physical address instead of a kernel 1631 * virtual address. Consequently, we need to do a little 1632 * extra mangling of the vhandle on the alpha. This should 1633 * eventually be fixed! The whole idea here is to get rid 1634 * of platform dependencies. 1635 */ 1636 #ifdef __alpha__ 1637 if (pci_cvt_to_bwx(sc->bge_vhandle)) 1638 sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle); 1639 else 1640 sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle); 1641 sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle); 1642 #endif 1643 1644 /* Allocate interrupt */ 1645 rid = 0; 1646 1647 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1648 RF_SHAREABLE | RF_ACTIVE); 1649 1650 if (sc->bge_irq == NULL) { 1651 printf("bge%d: couldn't map interrupt\n", unit); 1652 error = ENXIO; 1653 goto fail; 1654 } 1655 1656 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1657 bge_intr, sc, &sc->bge_intrhand); 1658 1659 if (error) { 1660 bge_release_resources(sc); 1661 printf("bge%d: couldn't set up irq\n", unit); 1662 goto fail; 1663 } 1664 1665 sc->bge_unit = unit; 1666 1667 /* Try to reset the chip. */ 1668 bge_reset(sc); 1669 1670 if (bge_chipinit(sc)) { 1671 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1672 bge_release_resources(sc); 1673 error = ENXIO; 1674 goto fail; 1675 } 1676 1677 /* 1678 * Get station address from the EEPROM. 1679 */ 1680 mac_addr = bge_readmem_ind(sc, 0x0c14); 1681 if ((mac_addr >> 16) == 0x484b) { 1682 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 1683 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 1684 mac_addr = bge_readmem_ind(sc, 0x0c18); 1685 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 1686 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 1687 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 1688 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 1689 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1690 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1691 printf("bge%d: failed to read station address\n", unit); 1692 bge_release_resources(sc); 1693 error = ENXIO; 1694 goto fail; 1695 } 1696 1697 /* 1698 * A Broadcom chip was detected. Inform the world. 1699 */ 1700 printf("bge%d: Ethernet address: %6D\n", unit, 1701 sc->arpcom.ac_enaddr, ":"); 1702 1703 /* Allocate the general information block and ring buffers. */ 1704 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1705 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1706 1707 if (sc->bge_rdata == NULL) { 1708 bge_release_resources(sc); 1709 error = ENXIO; 1710 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1711 goto fail; 1712 } 1713 1714 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1715 1716 /* Try to allocate memory for jumbo buffers. */ 1717 if (bge_alloc_jumbo_mem(sc)) { 1718 printf("bge%d: jumbo buffer allocation " 1719 "failed\n", sc->bge_unit); 1720 bge_release_resources(sc); 1721 error = ENXIO; 1722 goto fail; 1723 } 1724 1725 /* Set default tuneable values. */ 1726 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1727 sc->bge_rx_coal_ticks = 150; 1728 sc->bge_tx_coal_ticks = 150; 1729 sc->bge_rx_max_coal_bds = 64; 1730 sc->bge_tx_max_coal_bds = 128; 1731 1732 /* Set up ifnet structure */ 1733 ifp = &sc->arpcom.ac_if; 1734 ifp->if_softc = sc; 1735 ifp->if_unit = sc->bge_unit; 1736 ifp->if_name = "bge"; 1737 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1738 ifp->if_ioctl = bge_ioctl; 1739 ifp->if_output = ether_output; 1740 ifp->if_start = bge_start; 1741 ifp->if_watchdog = bge_watchdog; 1742 ifp->if_init = bge_init; 1743 ifp->if_mtu = ETHERMTU; 1744 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1745 ifp->if_hwassist = BGE_CSUM_FEATURES; 1746 ifp->if_capabilities = IFCAP_HWCSUM; 1747 ifp->if_capenable = ifp->if_capabilities; 1748 1749 /* Save ASIC rev. */ 1750 1751 sc->bge_chipid = 1752 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1753 BGE_PCIMISCCTL_ASICREV; 1754 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 1755 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 1756 1757 /* 1758 * Figure out what sort of media we have by checking the 1759 * hardware config word in the first 32k of NIC internal memory, 1760 * or fall back to examining the EEPROM if necessary. 1761 * Note: on some BCM5700 cards, this value appears to be unset. 1762 * If that's the case, we have to rely on identifying the NIC 1763 * by its PCI subsystem ID, as we do below for the SysKonnect 1764 * SK-9D41. 1765 */ 1766 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 1767 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 1768 else { 1769 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1770 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1771 hwcfg = ntohl(hwcfg); 1772 } 1773 1774 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1775 sc->bge_tbi = 1; 1776 1777 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1778 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1779 sc->bge_tbi = 1; 1780 1781 if (sc->bge_tbi) { 1782 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1783 bge_ifmedia_upd, bge_ifmedia_sts); 1784 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1785 ifmedia_add(&sc->bge_ifmedia, 1786 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1787 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1788 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1789 } else { 1790 /* 1791 * Do transceiver setup. 1792 */ 1793 if (mii_phy_probe(dev, &sc->bge_miibus, 1794 bge_ifmedia_upd, bge_ifmedia_sts)) { 1795 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1796 bge_release_resources(sc); 1797 bge_free_jumbo_mem(sc); 1798 error = ENXIO; 1799 goto fail; 1800 } 1801 } 1802 1803 /* 1804 * When using the BCM5701 in PCI-X mode, data corruption has 1805 * been observed in the first few bytes of some received packets. 1806 * Aligning the packet buffer in memory eliminates the corruption. 1807 * Unfortunately, this misaligns the packet payloads. On platforms 1808 * which do not support unaligned accesses, we will realign the 1809 * payloads by copying the received packets. 1810 */ 1811 switch (sc->bge_chipid) { 1812 case BGE_CHIPID_BCM5701_A0: 1813 case BGE_CHIPID_BCM5701_B0: 1814 case BGE_CHIPID_BCM5701_B2: 1815 case BGE_CHIPID_BCM5701_B5: 1816 /* If in PCI-X mode, work around the alignment bug. */ 1817 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1818 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1819 BGE_PCISTATE_PCI_BUSSPEED) 1820 sc->bge_rx_alignment_bug = 1; 1821 break; 1822 } 1823 1824 /* 1825 * Call MI attach routine. 1826 */ 1827 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1828 callout_handle_init(&sc->bge_stat_ch); 1829 1830 fail: 1831 splx(s); 1832 1833 return(error); 1834 } 1835 1836 static int 1837 bge_detach(dev) 1838 device_t dev; 1839 { 1840 struct bge_softc *sc; 1841 struct ifnet *ifp; 1842 int s; 1843 1844 s = splimp(); 1845 1846 sc = device_get_softc(dev); 1847 ifp = &sc->arpcom.ac_if; 1848 1849 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1850 bge_stop(sc); 1851 bge_reset(sc); 1852 1853 if (sc->bge_tbi) { 1854 ifmedia_removeall(&sc->bge_ifmedia); 1855 } else { 1856 bus_generic_detach(dev); 1857 device_delete_child(dev, sc->bge_miibus); 1858 } 1859 1860 bge_release_resources(sc); 1861 bge_free_jumbo_mem(sc); 1862 1863 splx(s); 1864 1865 return(0); 1866 } 1867 1868 static void 1869 bge_release_resources(sc) 1870 struct bge_softc *sc; 1871 { 1872 device_t dev; 1873 1874 dev = sc->bge_dev; 1875 1876 if (sc->bge_vpd_prodname != NULL) 1877 free(sc->bge_vpd_prodname, M_DEVBUF); 1878 1879 if (sc->bge_vpd_readonly != NULL) 1880 free(sc->bge_vpd_readonly, M_DEVBUF); 1881 1882 if (sc->bge_intrhand != NULL) 1883 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1884 1885 if (sc->bge_irq != NULL) 1886 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1887 1888 if (sc->bge_res != NULL) 1889 bus_release_resource(dev, SYS_RES_MEMORY, 1890 BGE_PCI_BAR0, sc->bge_res); 1891 1892 if (sc->bge_rdata != NULL) 1893 contigfree(sc->bge_rdata, 1894 sizeof(struct bge_ring_data), M_DEVBUF); 1895 1896 return; 1897 } 1898 1899 static void 1900 bge_reset(sc) 1901 struct bge_softc *sc; 1902 { 1903 device_t dev; 1904 u_int32_t cachesize, command, pcistate; 1905 int i, val = 0; 1906 1907 dev = sc->bge_dev; 1908 1909 /* Save some important PCI state. */ 1910 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1911 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1912 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1913 1914 pci_write_config(dev, BGE_PCI_MISC_CTL, 1915 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1916 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1917 1918 /* Issue global reset */ 1919 bge_writereg_ind(sc, BGE_MISC_CFG, 1920 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1921 1922 DELAY(1000); 1923 1924 /* Reset some of the PCI state that got zapped by reset */ 1925 pci_write_config(dev, BGE_PCI_MISC_CTL, 1926 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1927 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1928 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1929 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1930 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1931 1932 /* 1933 * Prevent PXE restart: write a magic number to the 1934 * general communications memory at 0xB50. 1935 */ 1936 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1937 /* 1938 * Poll the value location we just wrote until 1939 * we see the 1's complement of the magic number. 1940 * This indicates that the firmware initialization 1941 * is complete. 1942 */ 1943 for (i = 0; i < BGE_TIMEOUT; i++) { 1944 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1945 if (val == ~BGE_MAGIC_NUMBER) 1946 break; 1947 DELAY(10); 1948 } 1949 1950 if (i == BGE_TIMEOUT) { 1951 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1952 return; 1953 } 1954 1955 /* 1956 * XXX Wait for the value of the PCISTATE register to 1957 * return to its original pre-reset state. This is a 1958 * fairly good indicator of reset completion. If we don't 1959 * wait for the reset to fully complete, trying to read 1960 * from the device's non-PCI registers may yield garbage 1961 * results. 1962 */ 1963 for (i = 0; i < BGE_TIMEOUT; i++) { 1964 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1965 break; 1966 DELAY(10); 1967 } 1968 1969 /* Enable memory arbiter. */ 1970 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1971 1972 /* Fix up byte swapping */ 1973 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1974 BGE_MODECTL_BYTESWAP_DATA); 1975 1976 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1977 1978 DELAY(10000); 1979 1980 return; 1981 } 1982 1983 /* 1984 * Frame reception handling. This is called if there's a frame 1985 * on the receive return list. 1986 * 1987 * Note: we have to be able to handle two possibilities here: 1988 * 1) the frame is from the jumbo recieve ring 1989 * 2) the frame is from the standard receive ring 1990 */ 1991 1992 static void 1993 bge_rxeof(sc) 1994 struct bge_softc *sc; 1995 { 1996 struct ifnet *ifp; 1997 int stdcnt = 0, jumbocnt = 0; 1998 1999 ifp = &sc->arpcom.ac_if; 2000 2001 while(sc->bge_rx_saved_considx != 2002 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2003 struct bge_rx_bd *cur_rx; 2004 u_int32_t rxidx; 2005 struct ether_header *eh; 2006 struct mbuf *m = NULL; 2007 u_int16_t vlan_tag = 0; 2008 int have_tag = 0; 2009 2010 cur_rx = 2011 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 2012 2013 rxidx = cur_rx->bge_idx; 2014 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 2015 2016 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2017 have_tag = 1; 2018 vlan_tag = cur_rx->bge_vlan_tag; 2019 } 2020 2021 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2022 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2023 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2024 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2025 jumbocnt++; 2026 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2027 ifp->if_ierrors++; 2028 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2029 continue; 2030 } 2031 if (bge_newbuf_jumbo(sc, 2032 sc->bge_jumbo, NULL) == ENOBUFS) { 2033 ifp->if_ierrors++; 2034 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2035 continue; 2036 } 2037 } else { 2038 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2039 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2040 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2041 stdcnt++; 2042 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2043 ifp->if_ierrors++; 2044 bge_newbuf_std(sc, sc->bge_std, m); 2045 continue; 2046 } 2047 if (bge_newbuf_std(sc, sc->bge_std, 2048 NULL) == ENOBUFS) { 2049 ifp->if_ierrors++; 2050 bge_newbuf_std(sc, sc->bge_std, m); 2051 continue; 2052 } 2053 } 2054 2055 ifp->if_ipackets++; 2056 #ifndef __i386__ 2057 /* 2058 * The i386 allows unaligned accesses, but for other 2059 * platforms we must make sure the payload is aligned. 2060 */ 2061 if (sc->bge_rx_alignment_bug) { 2062 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2063 cur_rx->bge_len); 2064 m->m_data += ETHER_ALIGN; 2065 } 2066 #endif 2067 eh = mtod(m, struct ether_header *); 2068 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2069 m->m_pkthdr.rcvif = ifp; 2070 2071 /* Remove header from mbuf and pass it on. */ 2072 m_adj(m, sizeof(struct ether_header)); 2073 2074 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2075 if (ifp->if_hwassist) { 2076 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2077 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2078 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2079 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2080 m->m_pkthdr.csum_data = 2081 cur_rx->bge_tcp_udp_csum; 2082 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2083 } 2084 } 2085 #endif 2086 2087 /* 2088 * If we received a packet with a vlan tag, pass it 2089 * to vlan_input() instead of ether_input(). 2090 */ 2091 if (have_tag) { 2092 VLAN_INPUT_TAG(eh, m, vlan_tag); 2093 have_tag = vlan_tag = 0; 2094 continue; 2095 } 2096 2097 ether_input(ifp, eh, m); 2098 } 2099 2100 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2101 if (stdcnt) 2102 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2103 if (jumbocnt) 2104 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2105 2106 return; 2107 } 2108 2109 static void 2110 bge_txeof(sc) 2111 struct bge_softc *sc; 2112 { 2113 struct bge_tx_bd *cur_tx = NULL; 2114 struct ifnet *ifp; 2115 2116 ifp = &sc->arpcom.ac_if; 2117 2118 /* 2119 * Go through our tx ring and free mbufs for those 2120 * frames that have been sent. 2121 */ 2122 while (sc->bge_tx_saved_considx != 2123 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2124 u_int32_t idx = 0; 2125 2126 idx = sc->bge_tx_saved_considx; 2127 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2128 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2129 ifp->if_opackets++; 2130 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2131 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2132 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2133 } 2134 sc->bge_txcnt--; 2135 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2136 ifp->if_timer = 0; 2137 } 2138 2139 if (cur_tx != NULL) 2140 ifp->if_flags &= ~IFF_OACTIVE; 2141 2142 return; 2143 } 2144 2145 static void 2146 bge_intr(xsc) 2147 void *xsc; 2148 { 2149 struct bge_softc *sc; 2150 struct ifnet *ifp; 2151 u_int32_t status; 2152 2153 sc = xsc; 2154 ifp = &sc->arpcom.ac_if; 2155 2156 #ifdef notdef 2157 /* Avoid this for now -- checking this register is expensive. */ 2158 /* Make sure this is really our interrupt. */ 2159 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2160 return; 2161 #endif 2162 /* Ack interrupt and stop others from occuring. */ 2163 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2164 2165 /* 2166 * Process link state changes. 2167 * Grrr. The link status word in the status block does 2168 * not work correctly on the BCM5700 rev AX and BX chips, 2169 * according to all avaibable information. Hence, we have 2170 * to enable MII interrupts in order to properly obtain 2171 * async link changes. Unfortunately, this also means that 2172 * we have to read the MAC status register to detect link 2173 * changes, thereby adding an additional register access to 2174 * the interrupt handler. 2175 */ 2176 2177 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2178 u_int32_t status; 2179 2180 status = CSR_READ_4(sc, BGE_MAC_STS); 2181 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2182 sc->bge_link = 0; 2183 untimeout(bge_tick, sc, sc->bge_stat_ch); 2184 bge_tick(sc); 2185 /* Clear the interrupt */ 2186 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2187 BGE_EVTENB_MI_INTERRUPT); 2188 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2189 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2190 BRGPHY_INTRS); 2191 } 2192 } else { 2193 if ((sc->bge_rdata->bge_status_block.bge_status & 2194 BGE_STATFLAG_UPDATED) && 2195 (sc->bge_rdata->bge_status_block.bge_status & 2196 BGE_STATFLAG_LINKSTATE_CHANGED)) { 2197 sc->bge_rdata->bge_status_block.bge_status &= ~(BGE_STATFLAG_UPDATED|BGE_STATFLAG_LINKSTATE_CHANGED); 2198 /* 2199 * Sometime PCS encoding errors are detected in 2200 * TBI mode (on fiber NICs), and for some reason 2201 * the chip will signal them as link changes. 2202 * If we get a link change event, but the 'PCS 2203 * encoding error' bit in the MAC status register 2204 * is set, don't bother doing a link check. 2205 * This avoids spurious "gigabit link up" messages 2206 * that sometimes appear on fiber NIC's during 2207 * periods of heavy traffic. (There should be no 2208 * effect on copper NICs.) 2209 */ 2210 status = CSR_READ_4(sc, BGE_MAC_STS); 2211 if (!(status & BGE_MACSTAT_PORT_DECODE_ERROR)) { 2212 sc->bge_link = 0; 2213 untimeout(bge_tick, sc, sc->bge_stat_ch); 2214 bge_tick(sc); 2215 } 2216 sc->bge_link = 0; 2217 untimeout(bge_tick, sc, sc->bge_stat_ch); 2218 bge_tick(sc); 2219 /* Clear the interrupt */ 2220 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2221 BGE_MACSTAT_CFG_CHANGED); 2222 2223 /* Force flush the status block cached by PCI bridge */ 2224 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2225 } 2226 } 2227 2228 if (ifp->if_flags & IFF_RUNNING) { 2229 /* Check RX return ring producer/consumer */ 2230 bge_rxeof(sc); 2231 2232 /* Check TX ring producer/consumer */ 2233 bge_txeof(sc); 2234 } 2235 2236 bge_handle_events(sc); 2237 2238 /* Re-enable interrupts. */ 2239 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2240 2241 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2242 bge_start(ifp); 2243 2244 return; 2245 } 2246 2247 static void 2248 bge_tick(xsc) 2249 void *xsc; 2250 { 2251 struct bge_softc *sc; 2252 struct mii_data *mii = NULL; 2253 struct ifmedia *ifm = NULL; 2254 struct ifnet *ifp; 2255 int s; 2256 2257 sc = xsc; 2258 ifp = &sc->arpcom.ac_if; 2259 2260 s = splimp(); 2261 2262 bge_stats_update(sc); 2263 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2264 if (sc->bge_link) { 2265 splx(s); 2266 return; 2267 } 2268 2269 if (sc->bge_tbi) { 2270 ifm = &sc->bge_ifmedia; 2271 if (CSR_READ_4(sc, BGE_MAC_STS) & 2272 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2273 sc->bge_link++; 2274 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2275 printf("bge%d: gigabit link up\n", sc->bge_unit); 2276 if (ifp->if_snd.ifq_head != NULL) 2277 bge_start(ifp); 2278 } 2279 splx(s); 2280 return; 2281 } 2282 2283 mii = device_get_softc(sc->bge_miibus); 2284 mii_tick(mii); 2285 2286 if (!sc->bge_link) { 2287 mii_pollstat(mii); 2288 if (mii->mii_media_status & IFM_ACTIVE && 2289 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2290 sc->bge_link++; 2291 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 2292 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2293 printf("bge%d: gigabit link up\n", 2294 sc->bge_unit); 2295 if (ifp->if_snd.ifq_head != NULL) 2296 bge_start(ifp); 2297 } 2298 } 2299 2300 splx(s); 2301 2302 return; 2303 } 2304 2305 static void 2306 bge_stats_update(sc) 2307 struct bge_softc *sc; 2308 { 2309 struct ifnet *ifp; 2310 struct bge_stats *stats; 2311 2312 ifp = &sc->arpcom.ac_if; 2313 2314 stats = (struct bge_stats *)(sc->bge_vhandle + 2315 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2316 2317 ifp->if_collisions += 2318 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + 2319 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + 2320 stats->dot3StatsExcessiveCollisions.bge_addr_lo + 2321 stats->dot3StatsLateCollisions.bge_addr_lo) - 2322 ifp->if_collisions; 2323 2324 #ifdef notdef 2325 ifp->if_collisions += 2326 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2327 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2328 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2329 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2330 ifp->if_collisions; 2331 #endif 2332 2333 return; 2334 } 2335 2336 /* 2337 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2338 * pointers to descriptors. 2339 */ 2340 static int 2341 bge_encap(sc, m_head, txidx) 2342 struct bge_softc *sc; 2343 struct mbuf *m_head; 2344 u_int32_t *txidx; 2345 { 2346 struct bge_tx_bd *f = NULL; 2347 struct mbuf *m; 2348 u_int32_t frag, cur, cnt = 0; 2349 u_int16_t csum_flags = 0; 2350 struct ifvlan *ifv = NULL; 2351 2352 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2353 m_head->m_pkthdr.rcvif != NULL && 2354 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 2355 ifv = m_head->m_pkthdr.rcvif->if_softc; 2356 2357 m = m_head; 2358 cur = frag = *txidx; 2359 2360 if (m_head->m_pkthdr.csum_flags) { 2361 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2362 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2363 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2364 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2365 if (m_head->m_flags & M_LASTFRAG) 2366 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2367 else if (m_head->m_flags & M_FRAG) 2368 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2369 } 2370 /* 2371 * Start packing the mbufs in this chain into 2372 * the fragment pointers. Stop when we run out 2373 * of fragments or hit the end of the mbuf chain. 2374 */ 2375 for (m = m_head; m != NULL; m = m->m_next) { 2376 if (m->m_len != 0) { 2377 f = &sc->bge_rdata->bge_tx_ring[frag]; 2378 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2379 break; 2380 BGE_HOSTADDR(f->bge_addr) = 2381 vtophys(mtod(m, vm_offset_t)); 2382 f->bge_len = m->m_len; 2383 f->bge_flags = csum_flags; 2384 if (ifv != NULL) { 2385 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2386 f->bge_vlan_tag = ifv->ifv_tag; 2387 } else { 2388 f->bge_vlan_tag = 0; 2389 } 2390 /* 2391 * Sanity check: avoid coming within 16 descriptors 2392 * of the end of the ring. 2393 */ 2394 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2395 return(ENOBUFS); 2396 cur = frag; 2397 BGE_INC(frag, BGE_TX_RING_CNT); 2398 cnt++; 2399 } 2400 } 2401 2402 if (m != NULL) 2403 return(ENOBUFS); 2404 2405 if (frag == sc->bge_tx_saved_considx) 2406 return(ENOBUFS); 2407 2408 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2409 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2410 sc->bge_txcnt += cnt; 2411 2412 *txidx = frag; 2413 2414 return(0); 2415 } 2416 2417 /* 2418 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2419 * to the mbuf data regions directly in the transmit descriptors. 2420 */ 2421 static void 2422 bge_start(ifp) 2423 struct ifnet *ifp; 2424 { 2425 struct bge_softc *sc; 2426 struct mbuf *m_head = NULL; 2427 u_int32_t prodidx = 0; 2428 2429 sc = ifp->if_softc; 2430 2431 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2432 return; 2433 2434 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2435 2436 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2437 IF_DEQUEUE(&ifp->if_snd, m_head); 2438 if (m_head == NULL) 2439 break; 2440 2441 /* 2442 * XXX 2443 * safety overkill. If this is a fragmented packet chain 2444 * with delayed TCP/UDP checksums, then only encapsulate 2445 * it if we have enough descriptors to handle the entire 2446 * chain at once. 2447 * (paranoia -- may not actually be needed) 2448 */ 2449 if (m_head->m_flags & M_FIRSTFRAG && 2450 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2451 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2452 m_head->m_pkthdr.csum_data + 16) { 2453 IF_PREPEND(&ifp->if_snd, m_head); 2454 ifp->if_flags |= IFF_OACTIVE; 2455 break; 2456 } 2457 } 2458 2459 /* 2460 * Pack the data into the transmit ring. If we 2461 * don't have room, set the OACTIVE flag and wait 2462 * for the NIC to drain the ring. 2463 */ 2464 if (bge_encap(sc, m_head, &prodidx)) { 2465 IF_PREPEND(&ifp->if_snd, m_head); 2466 ifp->if_flags |= IFF_OACTIVE; 2467 break; 2468 } 2469 2470 /* 2471 * If there's a BPF listener, bounce a copy of this frame 2472 * to him. 2473 */ 2474 if (ifp->if_bpf) 2475 bpf_mtap(ifp, m_head); 2476 } 2477 2478 /* Transmit */ 2479 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2480 /* 5700 b2 errata */ 2481 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 2482 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2483 2484 /* 2485 * Set a timeout in case the chip goes out to lunch. 2486 */ 2487 ifp->if_timer = 5; 2488 2489 return; 2490 } 2491 2492 static void 2493 bge_init(xsc) 2494 void *xsc; 2495 { 2496 struct bge_softc *sc = xsc; 2497 struct ifnet *ifp; 2498 u_int16_t *m; 2499 int s; 2500 2501 s = splimp(); 2502 2503 ifp = &sc->arpcom.ac_if; 2504 2505 if (ifp->if_flags & IFF_RUNNING) { 2506 splx(s); 2507 return; 2508 } 2509 2510 /* Cancel pending I/O and flush buffers. */ 2511 bge_stop(sc); 2512 bge_reset(sc); 2513 bge_chipinit(sc); 2514 2515 /* 2516 * Init the various state machines, ring 2517 * control blocks and firmware. 2518 */ 2519 if (bge_blockinit(sc)) { 2520 printf("bge%d: initialization failure\n", sc->bge_unit); 2521 splx(s); 2522 return; 2523 } 2524 2525 ifp = &sc->arpcom.ac_if; 2526 2527 /* Specify MTU. */ 2528 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2529 ETHER_HDR_LEN + ETHER_CRC_LEN); 2530 2531 /* Load our MAC address. */ 2532 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2533 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2534 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2535 2536 /* Enable or disable promiscuous mode as needed. */ 2537 if (ifp->if_flags & IFF_PROMISC) { 2538 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2539 } else { 2540 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2541 } 2542 2543 /* Program multicast filter. */ 2544 bge_setmulti(sc); 2545 2546 /* Init RX ring. */ 2547 bge_init_rx_ring_std(sc); 2548 2549 /* Init jumbo RX ring. */ 2550 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2551 bge_init_rx_ring_jumbo(sc); 2552 2553 /* Init our RX return ring index */ 2554 sc->bge_rx_saved_considx = 0; 2555 2556 /* Init TX ring. */ 2557 bge_init_tx_ring(sc); 2558 2559 /* Turn on transmitter */ 2560 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2561 2562 /* Turn on receiver */ 2563 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2564 2565 /* Tell firmware we're alive. */ 2566 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2567 2568 /* Enable host interrupts. */ 2569 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2570 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2571 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2572 2573 bge_ifmedia_upd(ifp); 2574 2575 ifp->if_flags |= IFF_RUNNING; 2576 ifp->if_flags &= ~IFF_OACTIVE; 2577 2578 splx(s); 2579 2580 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2581 2582 return; 2583 } 2584 2585 /* 2586 * Set media options. 2587 */ 2588 static int 2589 bge_ifmedia_upd(ifp) 2590 struct ifnet *ifp; 2591 { 2592 struct bge_softc *sc; 2593 struct mii_data *mii; 2594 struct ifmedia *ifm; 2595 2596 sc = ifp->if_softc; 2597 ifm = &sc->bge_ifmedia; 2598 2599 /* If this is a 1000baseX NIC, enable the TBI port. */ 2600 if (sc->bge_tbi) { 2601 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2602 return(EINVAL); 2603 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2604 case IFM_AUTO: 2605 break; 2606 case IFM_1000_SX: 2607 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2608 BGE_CLRBIT(sc, BGE_MAC_MODE, 2609 BGE_MACMODE_HALF_DUPLEX); 2610 } else { 2611 BGE_SETBIT(sc, BGE_MAC_MODE, 2612 BGE_MACMODE_HALF_DUPLEX); 2613 } 2614 break; 2615 default: 2616 return(EINVAL); 2617 } 2618 return(0); 2619 } 2620 2621 mii = device_get_softc(sc->bge_miibus); 2622 sc->bge_link = 0; 2623 if (mii->mii_instance) { 2624 struct mii_softc *miisc; 2625 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2626 miisc = LIST_NEXT(miisc, mii_list)) 2627 mii_phy_reset(miisc); 2628 } 2629 mii_mediachg(mii); 2630 2631 return(0); 2632 } 2633 2634 /* 2635 * Report current media status. 2636 */ 2637 static void 2638 bge_ifmedia_sts(ifp, ifmr) 2639 struct ifnet *ifp; 2640 struct ifmediareq *ifmr; 2641 { 2642 struct bge_softc *sc; 2643 struct mii_data *mii; 2644 2645 sc = ifp->if_softc; 2646 2647 if (sc->bge_tbi) { 2648 ifmr->ifm_status = IFM_AVALID; 2649 ifmr->ifm_active = IFM_ETHER; 2650 if (CSR_READ_4(sc, BGE_MAC_STS) & 2651 BGE_MACSTAT_TBI_PCS_SYNCHED) 2652 ifmr->ifm_status |= IFM_ACTIVE; 2653 ifmr->ifm_active |= IFM_1000_SX; 2654 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2655 ifmr->ifm_active |= IFM_HDX; 2656 else 2657 ifmr->ifm_active |= IFM_FDX; 2658 return; 2659 } 2660 2661 mii = device_get_softc(sc->bge_miibus); 2662 mii_pollstat(mii); 2663 ifmr->ifm_active = mii->mii_media_active; 2664 ifmr->ifm_status = mii->mii_media_status; 2665 2666 return; 2667 } 2668 2669 static int 2670 bge_ioctl(ifp, command, data) 2671 struct ifnet *ifp; 2672 u_long command; 2673 caddr_t data; 2674 { 2675 struct bge_softc *sc = ifp->if_softc; 2676 struct ifreq *ifr = (struct ifreq *) data; 2677 int s, mask, error = 0; 2678 struct mii_data *mii; 2679 2680 s = splimp(); 2681 2682 switch(command) { 2683 case SIOCSIFADDR: 2684 case SIOCGIFADDR: 2685 error = ether_ioctl(ifp, command, data); 2686 break; 2687 case SIOCSIFMTU: 2688 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2689 error = EINVAL; 2690 else { 2691 ifp->if_mtu = ifr->ifr_mtu; 2692 ifp->if_flags &= ~IFF_RUNNING; 2693 bge_init(sc); 2694 } 2695 break; 2696 case SIOCSIFFLAGS: 2697 if (ifp->if_flags & IFF_UP) { 2698 /* 2699 * If only the state of the PROMISC flag changed, 2700 * then just use the 'set promisc mode' command 2701 * instead of reinitializing the entire NIC. Doing 2702 * a full re-init means reloading the firmware and 2703 * waiting for it to start up, which may take a 2704 * second or two. 2705 */ 2706 if (ifp->if_flags & IFF_RUNNING && 2707 ifp->if_flags & IFF_PROMISC && 2708 !(sc->bge_if_flags & IFF_PROMISC)) { 2709 BGE_SETBIT(sc, BGE_RX_MODE, 2710 BGE_RXMODE_RX_PROMISC); 2711 } else if (ifp->if_flags & IFF_RUNNING && 2712 !(ifp->if_flags & IFF_PROMISC) && 2713 sc->bge_if_flags & IFF_PROMISC) { 2714 BGE_CLRBIT(sc, BGE_RX_MODE, 2715 BGE_RXMODE_RX_PROMISC); 2716 } else 2717 bge_init(sc); 2718 } else { 2719 if (ifp->if_flags & IFF_RUNNING) { 2720 bge_stop(sc); 2721 } 2722 } 2723 sc->bge_if_flags = ifp->if_flags; 2724 error = 0; 2725 break; 2726 case SIOCADDMULTI: 2727 case SIOCDELMULTI: 2728 if (ifp->if_flags & IFF_RUNNING) { 2729 bge_setmulti(sc); 2730 error = 0; 2731 } 2732 break; 2733 case SIOCSIFMEDIA: 2734 case SIOCGIFMEDIA: 2735 if (sc->bge_tbi) { 2736 error = ifmedia_ioctl(ifp, ifr, 2737 &sc->bge_ifmedia, command); 2738 } else { 2739 mii = device_get_softc(sc->bge_miibus); 2740 error = ifmedia_ioctl(ifp, ifr, 2741 &mii->mii_media, command); 2742 } 2743 break; 2744 case SIOCSIFCAP: 2745 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2746 if (mask & IFCAP_HWCSUM) { 2747 if (IFCAP_HWCSUM & ifp->if_capenable) 2748 ifp->if_capenable &= ~IFCAP_HWCSUM; 2749 else 2750 ifp->if_capenable |= IFCAP_HWCSUM; 2751 } 2752 error = 0; 2753 break; 2754 default: 2755 error = EINVAL; 2756 break; 2757 } 2758 2759 (void)splx(s); 2760 2761 return(error); 2762 } 2763 2764 static void 2765 bge_watchdog(ifp) 2766 struct ifnet *ifp; 2767 { 2768 struct bge_softc *sc; 2769 2770 sc = ifp->if_softc; 2771 2772 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2773 2774 ifp->if_flags &= ~IFF_RUNNING; 2775 bge_init(sc); 2776 2777 ifp->if_oerrors++; 2778 2779 return; 2780 } 2781 2782 /* 2783 * Stop the adapter and free any mbufs allocated to the 2784 * RX and TX lists. 2785 */ 2786 static void 2787 bge_stop(sc) 2788 struct bge_softc *sc; 2789 { 2790 struct ifnet *ifp; 2791 struct ifmedia_entry *ifm; 2792 struct mii_data *mii = NULL; 2793 int mtmp, itmp; 2794 2795 ifp = &sc->arpcom.ac_if; 2796 2797 if (!sc->bge_tbi) 2798 mii = device_get_softc(sc->bge_miibus); 2799 2800 untimeout(bge_tick, sc, sc->bge_stat_ch); 2801 2802 /* 2803 * Disable all of the receiver blocks 2804 */ 2805 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2806 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2807 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2808 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2809 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2810 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2811 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2812 2813 /* 2814 * Disable all of the transmit blocks 2815 */ 2816 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2817 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2818 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2819 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2820 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2821 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2822 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2823 2824 /* 2825 * Shut down all of the memory managers and related 2826 * state machines. 2827 */ 2828 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2829 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2830 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2831 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2832 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2833 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2834 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2835 2836 /* Disable host interrupts. */ 2837 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2838 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2839 2840 /* 2841 * Tell firmware we're shutting down. 2842 */ 2843 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2844 2845 /* Free the RX lists. */ 2846 bge_free_rx_ring_std(sc); 2847 2848 /* Free jumbo RX list. */ 2849 bge_free_rx_ring_jumbo(sc); 2850 2851 /* Free TX buffers. */ 2852 bge_free_tx_ring(sc); 2853 2854 /* 2855 * Isolate/power down the PHY, but leave the media selection 2856 * unchanged so that things will be put back to normal when 2857 * we bring the interface back up. 2858 */ 2859 if (!sc->bge_tbi) { 2860 itmp = ifp->if_flags; 2861 ifp->if_flags |= IFF_UP; 2862 ifm = mii->mii_media.ifm_cur; 2863 mtmp = ifm->ifm_media; 2864 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2865 mii_mediachg(mii); 2866 ifm->ifm_media = mtmp; 2867 ifp->if_flags = itmp; 2868 } 2869 2870 sc->bge_link = 0; 2871 2872 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2873 2874 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2875 2876 return; 2877 } 2878 2879 /* 2880 * Stop all chip I/O so that the kernel's probe routines don't 2881 * get confused by errant DMAs when rebooting. 2882 */ 2883 static void 2884 bge_shutdown(dev) 2885 device_t dev; 2886 { 2887 struct bge_softc *sc; 2888 2889 sc = device_get_softc(dev); 2890 2891 bge_stop(sc); 2892 bge_reset(sc); 2893 2894 return; 2895 } 2896