1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $ 34 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $ 35 */ 36 37 #ifndef _IF_BGEREG_H_ 38 #define _IF_BGEREG_H_ 39 40 /* 41 * BCM570x memory map. The internal memory layout varies somewhat 42 * depending on whether or not we have external SSRAM attached. 43 * The BCM5700 can have up to 16MB of external memory. The BCM5701 44 * is apparently not designed to use external SSRAM. The mappings 45 * up to the first 4 send rings are the same for both internal and 46 * external memory configurations. Note that mini RX ring space is 47 * only available with external SSRAM configurations, which means 48 * the mini RX ring is not supported on the BCM5701. 49 * 50 * The NIC's memory can be accessed by the host in one of 3 ways: 51 * 52 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 53 * registers in PCI config space can be used to read any 32-bit 54 * address within the NIC's memory. 55 * 56 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 57 * space can be used in conjunction with the memory window in the 58 * device register space at offset 0x8000 to read any 32K chunk 59 * of NIC memory. 60 * 61 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 62 * set, the device I/O mapping consumes 32MB of host address space, 63 * allowing all of the registers and internal NIC memory to be 64 * accessed directly. NIC memory addresses are offset by 0x01000000. 65 * Flat mode consumes so much host address space that it is not 66 * recommended. 67 */ 68 #define BGE_PAGE_ZERO 0x00000000 69 #define BGE_PAGE_ZERO_END 0x000000FF 70 #define BGE_SEND_RING_RCB 0x00000100 71 #define BGE_SEND_RING_RCB_END 0x000001FF 72 #define BGE_RX_RETURN_RING_RCB 0x00000200 73 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 74 #define BGE_STATS_BLOCK 0x00000300 75 #define BGE_STATS_BLOCK_END 0x00000AFF 76 #define BGE_STATUS_BLOCK 0x00000B00 77 #define BGE_STATUS_BLOCK_END 0x00000B4F 78 #define BGE_SRAM_FW_MB 0x00000B50 79 #define BGE_SRAM_DATA_SIG 0x00000B54 80 #define BGE_SRAM_DATA_CFG 0x00000B58 81 #define BGE_SRAM_FW_CMD_MB 0x00000B78 82 #define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C 83 #define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 84 #define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04 85 #define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 86 #define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 87 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 88 #define BGE_UNMAPPED 0x00001000 89 #define BGE_UNMAPPED_END 0x00001FFF 90 #define BGE_DMA_DESCRIPTORS 0x00002000 91 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 92 #define BGE_SEND_RING_5717 0x00004000 93 #define BGE_SEND_RING_1_TO_4 0x00004000 94 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 95 96 /* Firmware interface */ 97 #define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */ 98 99 #define BGE_FW_CMD_DRV_ALIVE 0x00000001 100 #define BGE_FW_CMD_PAUSE 0x00000002 101 #define BGE_FW_CMD_IPV4_ADDR_CHANGE 0x00000003 102 #define BGE_FW_CMD_IPV6_ADDR_CHANGE 0x00000004 103 #define BGE_FW_CMD_LINK_UPDATE 0x0000000C 104 #define BGE_FW_CMD_DRV_ALIVE2 0x0000000D 105 #define BGE_FW_CMD_DRV_ALIVE3 0x0000000E 106 107 #define BGE_FW_HB_TIMEOUT_SEC 3 108 109 #define BGE_FW_DRV_STATE_START 0x00000001 110 #define BGE_FW_DRV_STATE_START_DONE 0x80000001 111 #define BGE_FW_DRV_STATE_UNLOAD 0x00000002 112 #define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002 113 #define BGE_FW_DRV_STATE_WOL 0x00000003 114 #define BGE_FW_DRV_STATE_SUSPEND 0x00000004 115 116 /* Mappings for internal memory configuration */ 117 #define BGE_STD_RX_RINGS 0x00006000 118 #define BGE_STD_RX_RINGS_END 0x00006FFF 119 #define BGE_JUMBO_RX_RINGS 0x00007000 120 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 121 #define BGE_BUFFPOOL_1 0x00008000 122 #define BGE_BUFFPOOL_1_END 0x0000FFFF 123 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 124 #define BGE_BUFFPOOL_2_END 0x00017FFF 125 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 126 #define BGE_BUFFPOOL_3_END 0x0001FFFF 127 #define BGE_STD_RX_RINGS_5717 0x00040000 128 #define BGE_JUMBO_RX_RINGS_5717 0x00044400 129 130 /* Mappings for external SSRAM configurations */ 131 #define BGE_SEND_RING_5_TO_6 0x00006000 132 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 133 #define BGE_SEND_RING_7_TO_8 0x00007000 134 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 135 #define BGE_SEND_RING_9_TO_16 0x00008000 136 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 137 #define BGE_EXT_STD_RX_RINGS 0x0000C000 138 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 139 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 140 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 141 #define BGE_MINI_RX_RINGS 0x0000E000 142 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 143 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 144 #define BGE_AVAIL_REGION1_END 0x00017FFF 145 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 146 #define BGE_AVAIL_REGION2_END 0x0001FFFF 147 #define BGE_EXT_SSRAM 0x00020000 148 #define BGE_EXT_SSRAM_END 0x000FFFFF 149 150 151 /* 152 * BCM570x register offsets. These are memory mapped registers 153 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 154 * Each register must be accessed using 32 bit operations. 155 * 156 * All registers are accessed through a 32K shared memory block. 157 * The first group of registers are actually copies of the PCI 158 * configuration space registers. 159 */ 160 161 /* 162 * PCI registers defined in the PCI 2.2 spec. 163 */ 164 #define BGE_PCI_VID 0x00 165 #define BGE_PCI_DID 0x02 166 #define BGE_PCI_CMD 0x04 167 #define BGE_PCI_STS 0x06 168 #define BGE_PCI_REV 0x08 169 #define BGE_PCI_CLASS 0x09 170 #define BGE_PCI_CACHESZ 0x0C 171 #define BGE_PCI_LATTIMER 0x0D 172 #define BGE_PCI_HDRTYPE 0x0E 173 #define BGE_PCI_BIST 0x0F 174 #define BGE_PCI_BAR0 0x10 175 #define BGE_PCI_BAR1 0x14 176 #define BGE_PCI_SUBSYS 0x2C 177 #define BGE_PCI_SUBVID 0x2E 178 #define BGE_PCI_ROMBASE 0x30 179 #define BGE_PCI_CAPPTR 0x34 180 #define BGE_PCI_INTLINE 0x3C 181 #define BGE_PCI_INTPIN 0x3D 182 #define BGE_PCI_MINGNT 0x3E 183 #define BGE_PCI_MAXLAT 0x3F 184 #define BGE_PCI_PCIXCAP 0x40 185 #define BGE_PCI_NEXTPTR_PM 0x41 186 #define BGE_PCI_PCIX_CMD 0x42 187 #define BGE_PCI_PCIX_STS 0x44 188 #define BGE_PCI_PWRMGMT_CAPID 0x48 189 #define BGE_PCI_NEXTPTR_VPD 0x49 190 #define BGE_PCI_PWRMGMT_CAPS 0x4A 191 #define BGE_PCI_PWRMGMT_CMD 0x4C 192 #define BGE_PCI_PWRMGMT_STS 0x4D 193 #define BGE_PCI_PWRMGMT_DATA 0x4F 194 #define BGE_PCI_VPD_CAPID 0x50 195 #define BGE_PCI_NEXTPTR_MSI 0x51 196 #define BGE_PCI_VPD_ADDR 0x52 197 #define BGE_PCI_VPD_DATA 0x54 198 #define BGE_PCI_MSI_CAPID 0x58 199 #define BGE_PCI_NEXTPTR_NONE 0x59 200 #define BGE_PCI_MSI_CTL 0x5A 201 #define BGE_PCI_MSI_ADDR_HI 0x5C 202 #define BGE_PCI_MSI_ADDR_LO 0x60 203 #define BGE_PCI_MSI_DATA 0x64 204 205 /* PCI MSI. ??? */ 206 #define BGE_PCIE_CAPID_REG 0xD0 207 #define BGE_PCIE_CAPID 0x10 208 209 /* 210 * PCI registers specific to the BCM570x family. 211 */ 212 #define BGE_PCI_MISC_CTL 0x68 213 #define BGE_PCI_DMA_RW_CTL 0x6C 214 #define BGE_PCI_PCISTATE 0x70 215 #define BGE_PCI_CLKCTL 0x74 216 #define BGE_PCI_REG_BASEADDR 0x78 217 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 218 #define BGE_PCI_REG_DATA 0x80 219 #define BGE_PCI_MEMWIN_DATA 0x84 220 #define BGE_PCI_MODECTL 0x88 221 #define BGE_PCI_MISC_CFG 0x8C 222 #define BGE_PCI_MISC_LOCALCTL 0x90 223 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 224 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 225 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 226 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 227 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 228 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 229 #define BGE_PCI_ISR_MBX_HI 0xB0 230 #define BGE_PCI_ISR_MBX_LO 0xB4 231 #define BGE_PCI_PRODID_ASICREV 0xBC 232 #define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 233 #define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 234 235 /* PCI Misc. Host control register */ 236 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 237 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 238 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 239 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 240 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 241 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 242 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 243 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 244 #define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 245 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 246 #define BGE_PCIMISCCTL_ASICREV_SHIFT 16 247 248 #if BYTE_ORDER == LITTLE_ENDIAN 249 #define BGE_DMA_SWAP_OPTIONS (BGE_MODECTL_WORDSWAP_NONFRAME |\ 250 BGE_MODECTL_BYTESWAP_DATA | \ 251 BGE_MODECTL_WORDSWAP_DATA) 252 #else 253 #define BGE_DMA_SWAP_OPTIONS (BGE_MODECTL_WORDSWAP_NONFRAME |\ 254 BGE_MODECTL_BYTESWAP_NONFRAME |\ 255 BGE_MODECTL_BYTESWAP_DATA | 256 BGE_MODECTL_WORDSWAP_DATA) 257 #endif 258 259 #define BGE_HIF_SWAP_OPTIONS BGE_PCIMISCCTL_ENDIAN_WORDSWAP 260 #define BGE_INIT (BGE_HIF_SWAP_OPTIONS | \ 261 BGE_PCIMISCCTL_CLEAR_INTA | \ 262 BGE_PCIMISCCTL_MASK_PCI_INTR | \ 263 BGE_PCIMISCCTL_INDIRECT_ACCESS) 264 265 #define BGE_PCISTAT_INTR_NOTACT 0x2 266 267 #define BGE_CHIPID_TIGON_I 0x4000 268 #define BGE_CHIPID_TIGON_II 0x6000 269 #define BGE_CHIPID_BCM5700_A0 0x7000 270 #define BGE_CHIPID_BCM5700_A1 0x7001 271 #define BGE_CHIPID_BCM5700_B0 0x7100 272 #define BGE_CHIPID_BCM5700_B1 0x7101 273 #define BGE_CHIPID_BCM5700_B2 0x7102 274 #define BGE_CHIPID_BCM5700_B3 0x7103 275 #define BGE_CHIPID_BCM5700_ALTIMA 0x7104 276 #define BGE_CHIPID_BCM5700_C0 0x7200 277 #define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 278 #define BGE_CHIPID_BCM5701_B0 0x0100 279 #define BGE_CHIPID_BCM5701_B2 0x0102 280 #define BGE_CHIPID_BCM5701_B5 0x0105 281 #define BGE_CHIPID_BCM5703_A0 0x1000 282 #define BGE_CHIPID_BCM5703_A1 0x1001 283 #define BGE_CHIPID_BCM5703_A2 0x1002 284 #define BGE_CHIPID_BCM5703_A3 0x1003 285 #define BGE_CHIPID_BCM5703_B0 0x1100 286 #define BGE_CHIPID_BCM5704_A0 0x2000 287 #define BGE_CHIPID_BCM5704_A1 0x2001 288 #define BGE_CHIPID_BCM5704_A2 0x2002 289 #define BGE_CHIPID_BCM5704_A3 0x2003 290 #define BGE_CHIPID_BCM5704_B0 0x2100 291 #define BGE_CHIPID_BCM5705_A0 0x3000 292 #define BGE_CHIPID_BCM5705_A1 0x3001 293 #define BGE_CHIPID_BCM5705_A2 0x3002 294 #define BGE_CHIPID_BCM5705_A3 0x3003 295 #define BGE_CHIPID_BCM5750_A0 0x4000 296 #define BGE_CHIPID_BCM5750_A1 0x4001 297 #define BGE_CHIPID_BCM5750_A3 0x4003 298 #define BGE_CHIPID_BCM5750_B0 0x4100 299 #define BGE_CHIPID_BCM5750_B1 0x4101 300 #define BGE_CHIPID_BCM5750_C0 0x4200 301 #define BGE_CHIPID_BCM5750_C1 0x4201 302 #define BGE_CHIPID_BCM5750_C2 0x4202 303 #define BGE_CHIPID_BCM5714_A0 0x5000 304 #define BGE_CHIPID_BCM5752_A0 0x6000 305 #define BGE_CHIPID_BCM5752_A1 0x6001 306 #define BGE_CHIPID_BCM5752_A2 0x6002 307 #define BGE_CHIPID_BCM5714_B0 0x8000 308 #define BGE_CHIPID_BCM5714_B3 0x8003 309 #define BGE_CHIPID_BCM5715_A0 0x9000 310 #define BGE_CHIPID_BCM5715_A1 0x9001 311 #define BGE_CHIPID_BCM5715_A3 0x9003 312 #define BGE_CHIPID_BCM5722_A0 0xa200 313 #define BGE_CHIPID_BCM5755_A0 0xa000 314 #define BGE_CHIPID_BCM5755_A1 0xa001 315 #define BGE_CHIPID_BCM5755_A2 0xa002 316 #define BGE_CHIPID_BCM5754_A0 0xb000 317 #define BGE_CHIPID_BCM5754_A1 0xb001 318 #define BGE_CHIPID_BCM5754_A2 0xb002 319 #define BGE_CHIPID_BCM5761_A0 0x5761000 320 #define BGE_CHIPID_BCM5761_A1 0x5761100 321 #define BGE_CHIPID_BCM5784_A0 0x5784000 322 #define BGE_CHIPID_BCM5784_A1 0x5784100 323 #define BGE_CHIPID_BCM5787_A0 0xb000 324 #define BGE_CHIPID_BCM5787_A1 0xb001 325 #define BGE_CHIPID_BCM5787_A2 0xb002 326 #define BGE_CHIPID_BCM5906_A0 0xc000 327 #define BGE_CHIPID_BCM5906_A1 0xc001 328 #define BGE_CHIPID_BCM5906_A2 0xc002 329 #define BGE_CHIPID_BCM57780_A0 0x57780000 330 #define BGE_CHIPID_BCM57780_A1 0x57780001 331 #define BGE_CHIPID_BCM5717_A0 0x05717000 332 #define BGE_CHIPID_BCM5717_B0 0x05717100 333 #define BGE_CHIPID_BCM5717_C0 0x05717200 334 #define BGE_CHIPID_BCM5719_A0 0x05719000 335 #define BGE_CHIPID_BCM5720_A0 0x05720000 336 #define BGE_CHIPID_BCM5762_A0 0x05762000 337 #define BGE_CHIPID_BCM57765_A0 0x57785000 338 #define BGE_CHIPID_BCM57765_B0 0x57785100 339 340 /* shorthand one */ 341 #define BGE_ASICREV(x) ((x) >> 12) 342 #define BGE_ASICREV_BCM5701 0x00 343 #define BGE_ASICREV_BCM5703 0x01 344 #define BGE_ASICREV_BCM5704 0x02 345 #define BGE_ASICREV_BCM5705 0x03 346 #define BGE_ASICREV_BCM5750 0x04 347 #define BGE_ASICREV_BCM5714_A0 0x05 348 #define BGE_ASICREV_BCM5752 0x06 349 #define BGE_ASICREV_BCM5700 0x07 350 #define BGE_ASICREV_BCM5780 0x08 351 #define BGE_ASICREV_BCM5714 0x09 352 #define BGE_ASICREV_BCM5755 0x0a 353 #define BGE_ASICREV_BCM5754 0x0b 354 #define BGE_ASICREV_BCM5787 0x0b 355 #define BGE_ASICREV_BCM5906 0x0c 356 357 /* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 358 #define BGE_ASICREV_USE_PRODID_REG 0x0f 359 /* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 360 #define BGE_ASICREV_BCM5717 0x5717 361 #define BGE_ASICREV_BCM5719 0x5719 362 #define BGE_ASICREV_BCM5720 0x5720 363 #define BGE_ASICREV_BCM5761 0x5761 364 #define BGE_ASICREV_BCM5762 0x5762 365 #define BGE_ASICREV_BCM5784 0x5784 366 #define BGE_ASICREV_BCM5785 0x5785 367 #define BGE_ASICREV_BCM57765 0x57785 368 #define BGE_ASICREV_BCM57766 0x57766 369 #define BGE_ASICREV_BCM57780 0x57780 370 371 /* chip revisions */ 372 #define BGE_CHIPREV(x) ((x) >> 8) 373 #define BGE_CHIPREV_5700_AX 0x70 374 #define BGE_CHIPREV_5700_BX 0x71 375 #define BGE_CHIPREV_5700_CX 0x72 376 #define BGE_CHIPREV_5701_AX 0x00 377 #define BGE_CHIPREV_5703_AX 0x10 378 #define BGE_CHIPREV_5704_AX 0x20 379 #define BGE_CHIPREV_5704_BX 0x21 380 #define BGE_CHIPREV_5750_AX 0x40 381 #define BGE_CHIPREV_5750_BX 0x41 382 /* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 383 #define BGE_CHIPREV_5717_AX 0x57170 384 #define BGE_CHIPREV_5717_BX 0x57171 385 #define BGE_CHIPREV_5761_AX 0x57611 386 #define BGE_CHIPREV_5784_AX 0x57841 387 #define BGE_CHIPREV_57765_AX 0x577850 388 389 /* PCI DMA Read/Write Control register */ 390 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 391 #define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 392 #define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 393 #define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 394 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 395 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 396 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 397 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 398 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 399 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 400 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 401 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 402 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 403 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 404 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 405 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 406 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 407 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 408 409 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 410 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 411 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 412 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 413 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 414 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 415 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 416 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 417 418 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 419 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 420 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 421 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 422 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 423 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 424 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 425 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 426 427 /* 428 * PCI state register -- note, this register is read only 429 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 430 * register is set. 431 */ 432 #define BGE_PCISTATE_FORCE_RESET 0x00000001 433 #define BGE_PCISTATE_INTR_STATE 0x00000002 434 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 435 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 436 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 437 #define BGE_PCISTATE_ROM_ENABLE 0x00000020 438 #define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 439 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 440 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 441 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 442 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 443 #define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 444 #define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 445 #define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 446 #define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 447 448 /* 449 * PCI Clock Control register -- note, this register is read only 450 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 451 * register is set. 452 */ 453 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 454 #define BGE_PCICLOCKCTL_M66EN 0x00000080 455 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 456 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 457 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 458 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 459 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 460 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 461 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 462 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 463 464 /* BAR0 (MAC) Register Definitions */ 465 466 /* 467 * High priority mailbox registers 468 * Each mailbox is 64-bits wide, though we only use the 469 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 470 * first. The NIC will load the mailbox after the lower 32 bit word 471 * has been updated. 472 */ 473 #define BGE_MBX_IRQ0_HI 0x0200 474 #define BGE_MBX_IRQ0_LO 0x0204 475 #define BGE_MBX_IRQ1_HI 0x0208 476 #define BGE_MBX_IRQ1_LO 0x020C 477 #define BGE_MBX_IRQ2_HI 0x0210 478 #define BGE_MBX_IRQ2_LO 0x0214 479 #define BGE_MBX_IRQ3_HI 0x0218 480 #define BGE_MBX_IRQ3_LO 0x021C 481 #define BGE_MBX_GEN0_HI 0x0220 482 #define BGE_MBX_GEN0_LO 0x0224 483 #define BGE_MBX_GEN1_HI 0x0228 484 #define BGE_MBX_GEN1_LO 0x022C 485 #define BGE_MBX_GEN2_HI 0x0230 486 #define BGE_MBX_GEN2_LO 0x0234 487 #define BGE_MBX_GEN3_HI 0x0228 488 #define BGE_MBX_GEN3_LO 0x022C 489 #define BGE_MBX_GEN4_HI 0x0240 490 #define BGE_MBX_GEN4_LO 0x0244 491 #define BGE_MBX_GEN5_HI 0x0248 492 #define BGE_MBX_GEN5_LO 0x024C 493 #define BGE_MBX_GEN6_HI 0x0250 494 #define BGE_MBX_GEN6_LO 0x0254 495 #define BGE_MBX_GEN7_HI 0x0258 496 #define BGE_MBX_GEN7_LO 0x025C 497 #define BGE_MBX_RELOAD_STATS_HI 0x0260 498 #define BGE_MBX_RELOAD_STATS_LO 0x0264 499 #define BGE_MBX_RX_STD_PROD_HI 0x0268 500 #define BGE_MBX_RX_STD_PROD_LO 0x026C 501 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 502 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 503 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 504 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 505 #define BGE_MBX_RX_CONS0_HI 0x0280 506 #define BGE_MBX_RX_CONS0_LO 0x0284 507 #define BGE_MBX_RX_CONS1_HI 0x0288 508 #define BGE_MBX_RX_CONS1_LO 0x028C 509 #define BGE_MBX_RX_CONS2_HI 0x0290 510 #define BGE_MBX_RX_CONS2_LO 0x0294 511 #define BGE_MBX_RX_CONS3_HI 0x0298 512 #define BGE_MBX_RX_CONS3_LO 0x029C 513 #define BGE_MBX_RX_CONS4_HI 0x02A0 514 #define BGE_MBX_RX_CONS4_LO 0x02A4 515 #define BGE_MBX_RX_CONS5_HI 0x02A8 516 #define BGE_MBX_RX_CONS5_LO 0x02AC 517 #define BGE_MBX_RX_CONS6_HI 0x02B0 518 #define BGE_MBX_RX_CONS6_LO 0x02B4 519 #define BGE_MBX_RX_CONS7_HI 0x02B8 520 #define BGE_MBX_RX_CONS7_LO 0x02BC 521 #define BGE_MBX_RX_CONS8_HI 0x02C0 522 #define BGE_MBX_RX_CONS8_LO 0x02C4 523 #define BGE_MBX_RX_CONS9_HI 0x02C8 524 #define BGE_MBX_RX_CONS9_LO 0x02CC 525 #define BGE_MBX_RX_CONS10_HI 0x02D0 526 #define BGE_MBX_RX_CONS10_LO 0x02D4 527 #define BGE_MBX_RX_CONS11_HI 0x02D8 528 #define BGE_MBX_RX_CONS11_LO 0x02DC 529 #define BGE_MBX_RX_CONS12_HI 0x02E0 530 #define BGE_MBX_RX_CONS12_LO 0x02E4 531 #define BGE_MBX_RX_CONS13_HI 0x02E8 532 #define BGE_MBX_RX_CONS13_LO 0x02EC 533 #define BGE_MBX_RX_CONS14_HI 0x02F0 534 #define BGE_MBX_RX_CONS14_LO 0x02F4 535 #define BGE_MBX_RX_CONS15_HI 0x02F8 536 #define BGE_MBX_RX_CONS15_LO 0x02FC 537 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 538 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 539 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 540 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 541 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 542 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 543 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 544 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 545 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 546 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 547 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 548 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 549 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 550 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 551 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 552 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 553 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 554 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 555 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 556 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 557 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 558 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 559 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 560 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 561 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 562 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 563 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 564 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 565 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 566 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 567 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 568 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 569 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 570 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 571 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 572 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 573 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 574 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 575 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 576 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 577 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 578 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 579 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 580 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 581 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 582 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 583 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 584 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 585 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 586 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 587 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 588 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 589 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 590 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 591 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 592 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 593 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 594 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 595 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 596 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 597 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 598 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 599 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 600 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 601 602 #define BGE_TX_RINGS_MAX 4 603 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 604 #define BGE_RX_RINGS_MAX 16 605 #define BGE_RX_RINGS_MAX_5717 17 606 607 /* Ethernet MAC control registers */ 608 #define BGE_MAC_MODE 0x0400 609 #define BGE_MAC_STS 0x0404 610 #define BGE_MAC_EVT_ENB 0x0408 611 #define BGE_MAC_LED_CTL 0x040C 612 #define BGE_MAC_ADDR1_LO 0x0410 613 #define BGE_MAC_ADDR1_HI 0x0414 614 #define BGE_MAC_ADDR2_LO 0x0418 615 #define BGE_MAC_ADDR2_HI 0x041C 616 #define BGE_MAC_ADDR3_LO 0x0420 617 #define BGE_MAC_ADDR3_HI 0x0424 618 #define BGE_MAC_ADDR4_LO 0x0428 619 #define BGE_MAC_ADDR4_HI 0x042C 620 #define BGE_WOL_PATPTR 0x0430 621 #define BGE_WOL_PATCFG 0x0434 622 #define BGE_TX_RANDOM_BACKOFF 0x0438 623 #define BGE_RX_MTU 0x043C 624 #define BGE_GBIT_PCS_TEST 0x0440 625 #define BGE_TX_TBI_AUTONEG 0x0444 626 #define BGE_RX_TBI_AUTONEG 0x0448 627 #define BGE_MI_COMM 0x044C 628 #define BGE_MI_STS 0x0450 629 #define BGE_MI_MODE 0x0454 630 #define BGE_AUTOPOLL_STS 0x0458 631 #define BGE_TX_MODE 0x045C 632 #define BGE_TX_STS 0x0460 633 #define BGE_TX_LENGTHS 0x0464 634 #define BGE_RX_MODE 0x0468 635 #define BGE_RX_STS 0x046C 636 #define BGE_MAR0 0x0470 637 #define BGE_MAR1 0x0474 638 #define BGE_MAR2 0x0478 639 #define BGE_MAR3 0x047C 640 #define BGE_RX_BD_RULES_CTL0 0x0480 641 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 642 #define BGE_RX_BD_RULES_CTL1 0x0488 643 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 644 #define BGE_RX_BD_RULES_CTL2 0x0490 645 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 646 #define BGE_RX_BD_RULES_CTL3 0x0498 647 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 648 #define BGE_RX_BD_RULES_CTL4 0x04A0 649 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 650 #define BGE_RX_BD_RULES_CTL5 0x04A8 651 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 652 #define BGE_RX_BD_RULES_CTL6 0x04B0 653 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 654 #define BGE_RX_BD_RULES_CTL7 0x04B8 655 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 656 #define BGE_RX_BD_RULES_CTL8 0x04C0 657 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 658 #define BGE_RX_BD_RULES_CTL9 0x04C8 659 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 660 #define BGE_RX_BD_RULES_CTL10 0x04D0 661 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 662 #define BGE_RX_BD_RULES_CTL11 0x04D8 663 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 664 #define BGE_RX_BD_RULES_CTL12 0x04E0 665 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 666 #define BGE_RX_BD_RULES_CTL13 0x04E8 667 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 668 #define BGE_RX_BD_RULES_CTL14 0x04F0 669 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 670 #define BGE_RX_BD_RULES_CTL15 0x04F8 671 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 672 #define BGE_RX_RULES_CFG 0x0500 673 #define BGE_MAX_RX_FRAME_LOWAT 0x0504 674 #define BGE_SERDES_CFG 0x0590 675 #define BGE_SERDES_STS 0x0594 676 #define BGE_SGDIG_CFG 0x05B0 677 #define BGE_SGDIG_STS 0x05B4 678 #define BGE_RSS_INDIR_TBL0 0x0630 679 #define BGE_RSS_KEYREG0 0x0670 680 #define BGE_RX_STATS 0x0800 681 #define BGE_TX_STATS 0x0880 682 683 /* Ethernet MAC Mode register */ 684 #define BGE_MACMODE_RESET 0x00000001 685 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 686 #define BGE_MACMODE_PORTMODE 0x0000000C 687 #define BGE_MACMODE_LOOPBACK 0x00000010 688 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 689 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 690 #define BGE_MACMODE_MAX_DEFER 0x00000200 691 #define BGE_MACMODE_LINK_POLARITY 0x00000400 692 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 693 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 694 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 695 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 696 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 697 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 698 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 699 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 700 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 701 #define BGE_MACMODE_MIP_ENB 0x00100000 702 #define BGE_MACMODE_TXDMA_ENB 0x00200000 703 #define BGE_MACMODE_RXDMA_ENB 0x00400000 704 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 705 #define BGE_MACMODE_APE_RX_EN 0x08000000 706 #define BGE_MACMODE_APE_TX_EN 0x10000000 707 708 #define BGE_PORTMODE_NONE 0x00000000 709 #define BGE_PORTMODE_MII 0x00000004 710 #define BGE_PORTMODE_GMII 0x00000008 711 #define BGE_PORTMODE_TBI 0x0000000C 712 713 /* MAC Status register */ 714 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 715 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 716 #define BGE_MACSTAT_RX_CFG 0x00000004 717 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 718 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 719 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 720 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 721 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 722 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 723 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 724 #define BGE_MACSTAT_ODI_ERROR 0x02000000 725 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 726 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 727 728 /* MAC Event Enable Register */ 729 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 730 #define BGE_EVTENB_LINK_CHANGED 0x00001000 731 #define BGE_EVTENB_MI_COMPLETE 0x00400000 732 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 733 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 734 #define BGE_EVTENB_ODI_ERROR 0x02000000 735 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 736 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 737 738 /* LED Control Register */ 739 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 740 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 741 #define BGE_LEDCTL_100MBPS_LED 0x00000004 742 #define BGE_LEDCTL_10MBPS_LED 0x00000008 743 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 744 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 745 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 746 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 747 #define BGE_LEDCTL_100MBPS_STS 0x00000100 748 #define BGE_LEDCTL_10MBPS_STS 0x00000200 749 #define BGE_LEDCTL_TRADLED_STS 0x00000400 750 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 751 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 752 753 /* TX backoff seed register */ 754 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 755 756 /* Autopoll status register */ 757 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 758 759 /* Transmit MAC mode register */ 760 #define BGE_TXMODE_RESET 0x00000001 761 #define BGE_TXMODE_ENABLE 0x00000002 762 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 763 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 764 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 765 #define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 766 #define BGE_TXMODE_JMB_FRM_LEN 0x00400000 767 #define BGE_TXMODE_CNT_DN_MODE 0x00800000 768 769 /* Transmit MAC status register */ 770 #define BGE_TXSTAT_RX_XOFFED 0x00000001 771 #define BGE_TXSTAT_SENT_XOFF 0x00000002 772 #define BGE_TXSTAT_SENT_XON 0x00000004 773 #define BGE_TXSTAT_LINK_UP 0x00000008 774 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 775 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 776 777 /* Transmit MAC lengths register */ 778 #define BGE_TXLEN_SLOTTIME 0x000000FF 779 #define BGE_TXLEN_IPG 0x00000F00 780 #define BGE_TXLEN_CRS 0x00003000 781 #define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 782 #define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 783 784 /* Receive MAC mode register */ 785 #define BGE_RXMODE_RESET 0x00000001 786 #define BGE_RXMODE_ENABLE 0x00000002 787 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 788 #define BGE_RXMODE_RX_GIANTS 0x00000020 789 #define BGE_RXMODE_RX_RUNTS 0x00000040 790 #define BGE_RXMODE_8022_LENCHECK 0x00000080 791 #define BGE_RXMODE_RX_PROMISC 0x00000100 792 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 793 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 794 #define BGE_RXMODE_RSS_IPV4_HASH 0x00010000 795 #define BGE_RXMODE_RSS_TCP_IPV4_HASH 0x00020000 796 #define BGE_RXMODE_RSS_IPV6_HASH 0x00040000 797 #define BGE_RXMODE_RSS_TCP_IPV6_HASH 0x00080000 798 #define BGE_RXMODE_RSS_HASH_MASK_BITS 0x00700000 799 #define BGE_RXMODE_RSS_ENABLE 0x00800000 800 #define BGE_RXMODE_IPV6_ENABLE 0x01000000 801 802 /* Receive MAC status register */ 803 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 804 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 805 #define BGE_RXSTAT_RCVD_XON 0x00000004 806 807 /* Receive Rules Control register */ 808 #define BGE_RXRULECTL_OFFSET 0x000000FF 809 #define BGE_RXRULECTL_CLASS 0x00001F00 810 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 811 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 812 #define BGE_RXRULECTL_MAP 0x01000000 813 #define BGE_RXRULECTL_DISCARD 0x02000000 814 #define BGE_RXRULECTL_MASK 0x04000000 815 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 816 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 817 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 818 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 819 820 /* Receive Rules Mask register */ 821 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 822 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 823 824 /* SERDES configuration register */ 825 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 826 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 827 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 828 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 829 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 830 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 831 #define BGE_SERDESCFG_TXMODE 0x00001000 832 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 833 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 834 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 835 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 836 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 837 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 838 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 839 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 840 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 841 842 /* SERDES status register */ 843 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 844 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 845 846 /* SGDIG config (not documented) */ 847 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 848 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 849 #define BGE_SGDIGCFG_SEND 0x40000000 850 #define BGE_SGDIGCFG_AUTO 0x80000000 851 852 /* SGDIG status (not documented) */ 853 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 854 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 855 #define BGE_SGDIGSTS_DONE 0x00000002 856 #define BGE_SGDIGSTS_IS_SERDES 0x00000100 857 858 /* MI communication register */ 859 #define BGE_MICOMM_DATA 0x0000FFFF 860 #define BGE_MICOMM_REG 0x001F0000 861 #define BGE_MICOMM_PHY 0x03E00000 862 #define BGE_MICOMM_CMD 0x0C000000 863 #define BGE_MICOMM_READFAIL 0x10000000 864 #define BGE_MICOMM_BUSY 0x20000000 865 866 #define BGE_MIREG(x) ((x & 0x1F) << 16) 867 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 868 #define BGE_MICMD_WRITE 0x04000000 869 #define BGE_MICMD_READ 0x08000000 870 871 /* MI status register */ 872 #define BGE_MISTS_LINK 0x00000001 873 #define BGE_MISTS_10MBPS 0x00000002 874 875 #define BGE_MIMODE_CLK_10MHZ 0x00000001 876 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 877 #define BGE_MIMODE_AUTOPOLL 0x00000010 878 #define BGE_MIMODE_CLKCNT 0x001F0000 879 #define BGE_MIMODE_500KHZ_CONST 0x00008000 880 #define BGE_MIMODE_BASE 0x000C0000 881 882 /* RSS key registers */ 883 #define BGE_RSS_KEYREG_CNT 10 884 #define BGE_RSS_KEYREG_SIZE 4 885 #define BGE_RSS_KEYREG(i) (BGE_RSS_KEYREG0 + \ 886 ((i) * BGE_RSS_KEYREG_SIZE)) 887 #define BGE_RSS_KEYREG_VAL(k, x) \ 888 (k[(x) * BGE_RSS_KEYREG_SIZE] << 24 | \ 889 k[(x) * BGE_RSS_KEYREG_SIZE + 1] << 16 | \ 890 k[(x) * BGE_RSS_KEYREG_SIZE + 2] << 8 | \ 891 k[(x) * BGE_RSS_KEYREG_SIZE + 3]) 892 893 /* RSS indirect table registers */ 894 #define BGE_RSS_INDIR_TBLENT_CNT 8 895 #define BGE_RSS_INDIR_TBLENT_SHIFT 4 896 #define BGE_RSS_INDIR_TBL_CNT 16 897 #define BGE_RSS_INDIR_TBL_SIZE 4 898 #define BGE_RSS_INDIR_TBL(i) (BGE_RSS_INDIR_TBL0 + \ 899 ((i) * BGE_RSS_INDIR_TBL_SIZE)) 900 901 /* 902 * Send data initiator control registers. 903 */ 904 #define BGE_SDI_MODE 0x0C00 905 #define BGE_SDI_STATUS 0x0C04 906 #define BGE_SDI_STATS_CTL 0x0C08 907 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 908 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 909 #define BGE_ISO_PKT_TX 0x0C20 910 #define BGE_LOCSTATS_COS0 0x0C80 911 #define BGE_LOCSTATS_COS1 0x0C84 912 #define BGE_LOCSTATS_COS2 0x0C88 913 #define BGE_LOCSTATS_COS3 0x0C8C 914 #define BGE_LOCSTATS_COS4 0x0C90 915 #define BGE_LOCSTATS_COS5 0x0C84 916 #define BGE_LOCSTATS_COS6 0x0C98 917 #define BGE_LOCSTATS_COS7 0x0C9C 918 #define BGE_LOCSTATS_COS8 0x0CA0 919 #define BGE_LOCSTATS_COS9 0x0CA4 920 #define BGE_LOCSTATS_COS10 0x0CA8 921 #define BGE_LOCSTATS_COS11 0x0CAC 922 #define BGE_LOCSTATS_COS12 0x0CB0 923 #define BGE_LOCSTATS_COS13 0x0CB4 924 #define BGE_LOCSTATS_COS14 0x0CB8 925 #define BGE_LOCSTATS_COS15 0x0CBC 926 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 927 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 928 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 929 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 930 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 931 #define BGE_LOCSTATS_IRQS 0x0CD4 932 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 933 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 934 935 /* Send Data Initiator mode register */ 936 #define BGE_SDIMODE_RESET 0x00000001 937 #define BGE_SDIMODE_ENABLE 0x00000002 938 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 939 #define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 940 941 /* Send Data Initiator stats register */ 942 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 943 944 /* Send Data Initiator stats control register */ 945 #define BGE_SDISTATSCTL_ENABLE 0x00000001 946 #define BGE_SDISTATSCTL_FASTER 0x00000002 947 #define BGE_SDISTATSCTL_CLEAR 0x00000004 948 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 949 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 950 951 /* 952 * Send Data Completion Control registers 953 */ 954 #define BGE_SDC_MODE 0x1000 955 #define BGE_SDC_STATUS 0x1004 956 957 /* Send Data completion mode register */ 958 #define BGE_SDCMODE_RESET 0x00000001 959 #define BGE_SDCMODE_ENABLE 0x00000002 960 #define BGE_SDCMODE_ATTN 0x00000004 961 #define BGE_SDCMODE_CDELAY 0x00000010 962 963 /* Send Data completion status register */ 964 #define BGE_SDCSTAT_ATTN 0x00000004 965 966 /* 967 * Send BD Ring Selector Control registers 968 */ 969 #define BGE_SRS_MODE 0x1400 970 #define BGE_SRS_STATUS 0x1404 971 #define BGE_SRS_HWDIAG 0x1408 972 #define BGE_SRS_LOC_NIC_CONS0 0x1440 973 #define BGE_SRS_LOC_NIC_CONS1 0x1444 974 #define BGE_SRS_LOC_NIC_CONS2 0x1448 975 #define BGE_SRS_LOC_NIC_CONS3 0x144C 976 #define BGE_SRS_LOC_NIC_CONS4 0x1450 977 #define BGE_SRS_LOC_NIC_CONS5 0x1454 978 #define BGE_SRS_LOC_NIC_CONS6 0x1458 979 #define BGE_SRS_LOC_NIC_CONS7 0x145C 980 #define BGE_SRS_LOC_NIC_CONS8 0x1460 981 #define BGE_SRS_LOC_NIC_CONS9 0x1464 982 #define BGE_SRS_LOC_NIC_CONS10 0x1468 983 #define BGE_SRS_LOC_NIC_CONS11 0x146C 984 #define BGE_SRS_LOC_NIC_CONS12 0x1470 985 #define BGE_SRS_LOC_NIC_CONS13 0x1474 986 #define BGE_SRS_LOC_NIC_CONS14 0x1478 987 #define BGE_SRS_LOC_NIC_CONS15 0x147C 988 989 /* Send BD Ring Selector Mode register */ 990 #define BGE_SRSMODE_RESET 0x00000001 991 #define BGE_SRSMODE_ENABLE 0x00000002 992 #define BGE_SRSMODE_ATTN 0x00000004 993 994 /* Send BD Ring Selector Status register */ 995 #define BGE_SRSSTAT_ERROR 0x00000004 996 997 /* Send BD Ring Selector HW Diagnostics register */ 998 #define BGE_SRSHWDIAG_STATE 0x0000000F 999 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1000 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1001 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1002 1003 /* 1004 * Send BD Initiator Selector Control registers 1005 */ 1006 #define BGE_SBDI_MODE 0x1800 1007 #define BGE_SBDI_STATUS 0x1804 1008 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 1009 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 1010 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 1011 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 1012 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 1013 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 1014 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 1015 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 1016 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 1017 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 1018 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 1019 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 1020 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 1021 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 1022 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 1023 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 1024 1025 /* Send BD Initiator Mode register */ 1026 #define BGE_SBDIMODE_RESET 0x00000001 1027 #define BGE_SBDIMODE_ENABLE 0x00000002 1028 #define BGE_SBDIMODE_ATTN 0x00000004 1029 #define BGE_SBDIMODE_MULTI_TXR 0x00000020 1030 1031 /* Send BD Initiator Status register */ 1032 #define BGE_SBDISTAT_ERROR 0x00000004 1033 1034 /* 1035 * Send BD Completion Control registers 1036 */ 1037 #define BGE_SBDC_MODE 0x1C00 1038 #define BGE_SBDC_STATUS 0x1C04 1039 1040 /* Send BD Completion Control Mode register */ 1041 #define BGE_SBDCMODE_RESET 0x00000001 1042 #define BGE_SBDCMODE_ENABLE 0x00000002 1043 #define BGE_SBDCMODE_ATTN 0x00000004 1044 1045 /* Send BD Completion Control Status register */ 1046 #define BGE_SBDCSTAT_ATTN 0x00000004 1047 1048 /* 1049 * Receive List Placement Control registers 1050 */ 1051 #define BGE_RXLP_MODE 0x2000 1052 #define BGE_RXLP_STATUS 0x2004 1053 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 1054 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1055 #define BGE_RXLP_CFG 0x2010 1056 #define BGE_RXLP_STATS_CTL 0x2014 1057 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1058 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1059 #define BGE_RXLP_HEAD0 0x2100 1060 #define BGE_RXLP_TAIL0 0x2104 1061 #define BGE_RXLP_COUNT0 0x2108 1062 #define BGE_RXLP_HEAD1 0x2110 1063 #define BGE_RXLP_TAIL1 0x2114 1064 #define BGE_RXLP_COUNT1 0x2118 1065 #define BGE_RXLP_HEAD2 0x2120 1066 #define BGE_RXLP_TAIL2 0x2124 1067 #define BGE_RXLP_COUNT2 0x2128 1068 #define BGE_RXLP_HEAD3 0x2130 1069 #define BGE_RXLP_TAIL3 0x2134 1070 #define BGE_RXLP_COUNT3 0x2138 1071 #define BGE_RXLP_HEAD4 0x2140 1072 #define BGE_RXLP_TAIL4 0x2144 1073 #define BGE_RXLP_COUNT4 0x2148 1074 #define BGE_RXLP_HEAD5 0x2150 1075 #define BGE_RXLP_TAIL5 0x2154 1076 #define BGE_RXLP_COUNT5 0x2158 1077 #define BGE_RXLP_HEAD6 0x2160 1078 #define BGE_RXLP_TAIL6 0x2164 1079 #define BGE_RXLP_COUNT6 0x2168 1080 #define BGE_RXLP_HEAD7 0x2170 1081 #define BGE_RXLP_TAIL7 0x2174 1082 #define BGE_RXLP_COUNT7 0x2178 1083 #define BGE_RXLP_HEAD8 0x2180 1084 #define BGE_RXLP_TAIL8 0x2184 1085 #define BGE_RXLP_COUNT8 0x2188 1086 #define BGE_RXLP_HEAD9 0x2190 1087 #define BGE_RXLP_TAIL9 0x2194 1088 #define BGE_RXLP_COUNT9 0x2198 1089 #define BGE_RXLP_HEAD10 0x21A0 1090 #define BGE_RXLP_TAIL10 0x21A4 1091 #define BGE_RXLP_COUNT10 0x21A8 1092 #define BGE_RXLP_HEAD11 0x21B0 1093 #define BGE_RXLP_TAIL11 0x21B4 1094 #define BGE_RXLP_COUNT11 0x21B8 1095 #define BGE_RXLP_HEAD12 0x21C0 1096 #define BGE_RXLP_TAIL12 0x21C4 1097 #define BGE_RXLP_COUNT12 0x21C8 1098 #define BGE_RXLP_HEAD13 0x21D0 1099 #define BGE_RXLP_TAIL13 0x21D4 1100 #define BGE_RXLP_COUNT13 0x21D8 1101 #define BGE_RXLP_HEAD14 0x21E0 1102 #define BGE_RXLP_TAIL14 0x21E4 1103 #define BGE_RXLP_COUNT14 0x21E8 1104 #define BGE_RXLP_HEAD15 0x21F0 1105 #define BGE_RXLP_TAIL15 0x21F4 1106 #define BGE_RXLP_COUNT15 0x21F8 1107 #define BGE_RXLP_LOCSTAT_COS0 0x2200 1108 #define BGE_RXLP_LOCSTAT_COS1 0x2204 1109 #define BGE_RXLP_LOCSTAT_COS2 0x2208 1110 #define BGE_RXLP_LOCSTAT_COS3 0x220C 1111 #define BGE_RXLP_LOCSTAT_COS4 0x2210 1112 #define BGE_RXLP_LOCSTAT_COS5 0x2214 1113 #define BGE_RXLP_LOCSTAT_COS6 0x2218 1114 #define BGE_RXLP_LOCSTAT_COS7 0x221C 1115 #define BGE_RXLP_LOCSTAT_COS8 0x2220 1116 #define BGE_RXLP_LOCSTAT_COS9 0x2224 1117 #define BGE_RXLP_LOCSTAT_COS10 0x2228 1118 #define BGE_RXLP_LOCSTAT_COS11 0x222C 1119 #define BGE_RXLP_LOCSTAT_COS12 0x2230 1120 #define BGE_RXLP_LOCSTAT_COS13 0x2234 1121 #define BGE_RXLP_LOCSTAT_COS14 0x2238 1122 #define BGE_RXLP_LOCSTAT_COS15 0x223C 1123 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1124 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1125 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1126 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1127 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1128 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1129 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1130 1131 1132 /* Receive List Placement mode register */ 1133 #define BGE_RXLPMODE_RESET 0x00000001 1134 #define BGE_RXLPMODE_ENABLE 0x00000002 1135 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1136 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1137 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1138 1139 /* Receive List Placement Status register */ 1140 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1141 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1142 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1143 1144 /* 1145 * Receive Data and Receive BD Initiator Control Registers 1146 */ 1147 #define BGE_RDBDI_MODE 0x2400 1148 #define BGE_RDBDI_STATUS 0x2404 1149 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1150 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1151 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1152 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1153 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 1154 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 1155 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1156 #define BGE_RX_STD_RCB_NICADDR 0x245C 1157 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1158 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1159 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1160 #define BGE_RX_MINI_RCB_NICADDR 0x246C 1161 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1162 #define BGE_RDBDI_STD_RX_CONS 0x2474 1163 #define BGE_RDBDI_MINI_RX_CONS 0x2478 1164 #define BGE_RDBDI_RETURN_PROD0 0x2480 1165 #define BGE_RDBDI_RETURN_PROD1 0x2484 1166 #define BGE_RDBDI_RETURN_PROD2 0x2488 1167 #define BGE_RDBDI_RETURN_PROD3 0x248C 1168 #define BGE_RDBDI_RETURN_PROD4 0x2490 1169 #define BGE_RDBDI_RETURN_PROD5 0x2494 1170 #define BGE_RDBDI_RETURN_PROD6 0x2498 1171 #define BGE_RDBDI_RETURN_PROD7 0x249C 1172 #define BGE_RDBDI_RETURN_PROD8 0x24A0 1173 #define BGE_RDBDI_RETURN_PROD9 0x24A4 1174 #define BGE_RDBDI_RETURN_PROD10 0x24A8 1175 #define BGE_RDBDI_RETURN_PROD11 0x24AC 1176 #define BGE_RDBDI_RETURN_PROD12 0x24B0 1177 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1178 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1179 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1180 #define BGE_RDBDI_HWDIAG 0x24C0 1181 1182 1183 /* Receive Data and Receive BD Initiator Mode register */ 1184 #define BGE_RDBDIMODE_RESET 0x00000001 1185 #define BGE_RDBDIMODE_ENABLE 0x00000002 1186 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1187 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1188 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1189 1190 /* Receive Data and Receive BD Initiator Status register */ 1191 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1192 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1193 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1194 1195 1196 /* 1197 * Receive Data Completion Control registers 1198 */ 1199 #define BGE_RDC_MODE 0x2800 1200 1201 /* Receive Data Completion Mode register */ 1202 #define BGE_RDCMODE_RESET 0x00000001 1203 #define BGE_RDCMODE_ENABLE 0x00000002 1204 #define BGE_RDCMODE_ATTN 0x00000004 1205 1206 /* 1207 * Receive BD Initiator Control registers 1208 */ 1209 #define BGE_RBDI_MODE 0x2C00 1210 #define BGE_RBDI_STATUS 0x2C04 1211 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1212 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1213 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1214 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1215 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1216 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1217 1218 #define BGE_STD_REPLENISH_LWM 0x2D00 1219 #define BGE_JMB_REPLENISH_LWM 0x2D04 1220 1221 /* Receive BD Initiator Mode register */ 1222 #define BGE_RBDIMODE_RESET 0x00000001 1223 #define BGE_RBDIMODE_ENABLE 0x00000002 1224 #define BGE_RBDIMODE_ATTN 0x00000004 1225 1226 /* Receive BD Initiator Status register */ 1227 #define BGE_RBDISTAT_ATTN 0x00000004 1228 1229 /* 1230 * Receive BD Completion Control registers 1231 */ 1232 #define BGE_RBDC_MODE 0x3000 1233 #define BGE_RBDC_STATUS 0x3004 1234 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1235 #define BGE_RBDC_STD_BD_PROD 0x300C 1236 #define BGE_RBDC_MINI_BD_PROD 0x3010 1237 1238 /* Receive BD completion mode register */ 1239 #define BGE_RBDCMODE_RESET 0x00000001 1240 #define BGE_RBDCMODE_ENABLE 0x00000002 1241 #define BGE_RBDCMODE_ATTN 0x00000004 1242 1243 /* Receive BD completion status register */ 1244 #define BGE_RBDCSTAT_ERROR 0x00000004 1245 1246 /* 1247 * Receive List Selector Control registers 1248 */ 1249 #define BGE_RXLS_MODE 0x3400 1250 #define BGE_RXLS_STATUS 0x3404 1251 1252 /* Receive List Selector Mode register */ 1253 #define BGE_RXLSMODE_RESET 0x00000001 1254 #define BGE_RXLSMODE_ENABLE 0x00000002 1255 #define BGE_RXLSMODE_ATTN 0x00000004 1256 1257 /* Receive List Selector Status register */ 1258 #define BGE_RXLSSTAT_ERROR 0x00000004 1259 1260 #define BGE_CPMU_CTRL 0x3600 1261 #define BGE_CPMU_LSPD_10MB_CLK 0x3604 1262 #define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1263 #define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1264 #define BGE_CPMU_HST_ACC 0x361C 1265 #define BGE_CPMU_CLCK_STAT 0x3630 1266 #define BGE_CPMU_CLCK_ORIDE 0x3624 1267 #define BGE_CPMU_MUTEX_REQ 0x365C 1268 #define BGE_CPMU_MUTEX_GNT 0x3660 1269 #define BGE_CPMU_PHY_STRAP 0x3664 1270 #define BGE_CPMU_PADRNG_CTL 0x3668 1271 1272 /* Central Power Management Unit (CPMU) register */ 1273 #define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1274 #define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1275 #define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1276 #define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1277 1278 /* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1279 #define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1280 #define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1281 1282 /* Link Speed 1000MB Power Mode Clock Policy register */ 1283 #define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1284 #define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1285 #define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1286 1287 /* Link Aware Power Mode Clock Policy register */ 1288 #define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1289 #define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1290 1291 #define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1292 #define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1293 1294 /* Clock Speed Override Policy register */ 1295 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1296 1297 /* CPMU Clock Status register */ 1298 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1299 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1300 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1301 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1302 1303 /* CPMU Mutex Request register */ 1304 #define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1305 #define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1306 1307 /* CPMU GPHY Strap register */ 1308 #define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1309 1310 /* CPMU Padring Control register */ 1311 #define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000 1312 1313 /* 1314 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1315 */ 1316 #define BGE_MBCF_MODE 0x3800 1317 #define BGE_MBCF_STATUS 0x3804 1318 1319 /* Mbuf Cluster Free mode register */ 1320 #define BGE_MBCFMODE_RESET 0x00000001 1321 #define BGE_MBCFMODE_ENABLE 0x00000002 1322 #define BGE_MBCFMODE_ATTN 0x00000004 1323 1324 /* Mbuf Cluster Free status register */ 1325 #define BGE_MBCFSTAT_ERROR 0x00000004 1326 1327 /* 1328 * Host Coalescing Control registers 1329 */ 1330 #define BGE_HCC_MODE 0x3C00 1331 #define BGE_HCC_STATUS 0x3C04 1332 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1333 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1334 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1335 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1336 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1337 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1338 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1339 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1340 #define BGE_HCC_STATS_TICKS 0x3C28 1341 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1342 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1343 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1344 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1345 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1346 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1347 #define BGE_FLOW_ATTN 0x3C48 1348 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1349 #define BGE_HCC_STD_BD_CONS 0x3C54 1350 #define BGE_HCC_MINI_BD_CONS 0x3C58 1351 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1352 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1353 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1354 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1355 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1356 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1357 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1358 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1359 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1360 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1361 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1362 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1363 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1364 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1365 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1366 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1367 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1368 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1369 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1370 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1371 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1372 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1373 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1374 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1375 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1376 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1377 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1378 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1379 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1380 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1381 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1382 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1383 1384 1385 /* Host coalescing mode register */ 1386 #define BGE_HCCMODE_RESET 0x00000001 1387 #define BGE_HCCMODE_ENABLE 0x00000002 1388 #define BGE_HCCMODE_ATTN 0x00000004 1389 #define BGE_HCCMODE_COAL_NOW 0x00000008 1390 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1391 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1392 #define BGE_HCCMODE_CLRTICK_RX 0x00000200 1393 #define BGE_HCCMODE_CLRTICK_TX 0x00000400 1394 1395 #define BGE_STATBLKSZ_FULL 0x00000000 1396 #define BGE_STATBLKSZ_64BYTE 0x00000080 1397 #define BGE_STATBLKSZ_32BYTE 0x00000100 1398 1399 /* Host coalescing status register */ 1400 #define BGE_HCCSTAT_ERROR 0x00000004 1401 1402 /* Flow attention register */ 1403 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1404 #define BGE_FLOWATTN_MEMARB 0x00000080 1405 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1406 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1407 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1408 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1409 #define BGE_FLOWATTN_RDBDI 0x00080000 1410 #define BGE_FLOWATTN_RXLS 0x00100000 1411 #define BGE_FLOWATTN_RXLP 0x00200000 1412 #define BGE_FLOWATTN_RBDC 0x00400000 1413 #define BGE_FLOWATTN_RBDI 0x00800000 1414 #define BGE_FLOWATTN_SDC 0x08000000 1415 #define BGE_FLOWATTN_SDI 0x10000000 1416 #define BGE_FLOWATTN_SRS 0x20000000 1417 #define BGE_FLOWATTN_SBDC 0x40000000 1418 #define BGE_FLOWATTN_SBDI 0x80000000 1419 1420 #define BGE_VEC1_STATUSBLK_ADDR_HI 0x3D00 1421 #define BGE_VEC1_STATUSBLK_ADDR_LO 0x3D04 1422 1423 #define BGE_VEC1_RX_COAL_TICKS 0x3D80 1424 #define BGE_VEC1_TX_COAL_TICKS 0x3D84 1425 #define BGE_VEC1_RX_MAX_COAL_BDS 0x3D88 1426 #define BGE_VEC1_TX_MAX_COAL_BDS 0x3D8C 1427 #define BGE_VEC1_RX_MAX_COAL_BDS_INT 0x3D90 /* BDs during interrupt */ 1428 #define BGE_VEC1_TX_MAX_COAL_BDS_INT 0x3D94 /* BDs during interrupt */ 1429 1430 #define BGE_VEC_COALSET_SIZE 24 1431 1432 /* 1433 * Memory arbiter registers 1434 */ 1435 #define BGE_MARB_MODE 0x4000 1436 #define BGE_MARB_STATUS 0x4004 1437 #define BGE_MARB_TRAPADDR_HI 0x4008 1438 #define BGE_MARB_TRAPADDR_LO 0x400C 1439 1440 /* Memory arbiter mode register */ 1441 #define BGE_MARBMODE_RESET 0x00000001 1442 #define BGE_MARBMODE_ENABLE 0x00000002 1443 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1444 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1445 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1446 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1447 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1448 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1449 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1450 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1451 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1452 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1453 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1454 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1455 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1456 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1457 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1458 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1459 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1460 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1461 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1462 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1463 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1464 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1465 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1466 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1467 1468 /* Memory arbiter status register */ 1469 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1470 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1471 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1472 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1473 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1474 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1475 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1476 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1477 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1478 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1479 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1480 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1481 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1482 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1483 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1484 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1485 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1486 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1487 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1488 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1489 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1490 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1491 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1492 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1493 1494 /* 1495 * Buffer manager control registers 1496 */ 1497 #define BGE_BMAN_MODE 0x4400 1498 #define BGE_BMAN_STATUS 0x4404 1499 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1500 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1501 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1502 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1503 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1504 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1505 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1506 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1507 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1508 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1509 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1510 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1511 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1512 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1513 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1514 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1515 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1516 #define BGE_BMAN_HWDIAG_1 0x444C 1517 #define BGE_BMAN_HWDIAG_2 0x4450 1518 #define BGE_BMAN_HWDIAG_3 0x4454 1519 1520 /* Buffer manager mode register */ 1521 #define BGE_BMANMODE_RESET 0x00000001 1522 #define BGE_BMANMODE_ENABLE 0x00000002 1523 #define BGE_BMANMODE_ATTN 0x00000004 1524 #define BGE_BMANMODE_TESTMODE 0x00000008 1525 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1526 #define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 1527 1528 /* Buffer manager status register */ 1529 #define BGE_BMANSTAT_ERRO 0x00000004 1530 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1531 1532 1533 /* 1534 * Read DMA Control registers 1535 */ 1536 #define BGE_RDMA_MODE 0x4800 1537 #define BGE_RDMA_STATUS 0x4804 1538 #define BGE_RDMA_RSRVCTRL2 0x4890 1539 #define BGE_RDMA_LSO_CRPTEN_CTRL2 0x48a0 1540 #define BGE_RDMA_RSRVCTRL 0x4900 1541 #define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 1542 1543 /* Read DMA mode register */ 1544 #define BGE_RDMAMODE_RESET 0x00000001 1545 #define BGE_RDMAMODE_ENABLE 0x00000002 1546 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1547 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1548 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1549 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1550 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1551 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1552 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1553 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1554 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1555 #define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1556 #define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1557 #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1558 #define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1559 #define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1560 #define BGE_RDMAMODE_JMB_2K_MMRR 0x00800000 1561 #define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1562 #define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1563 #define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 1564 1565 /* Read DMA status register */ 1566 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1567 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1568 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1569 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1570 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1571 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1572 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1573 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1574 1575 /* Read DMA Reserved Control register */ 1576 #define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1577 #define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1578 #define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1579 #define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1580 #define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1581 #define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1582 #define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1583 1584 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1585 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1586 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1587 1588 /* BD Read DMA Mode register */ 1589 #define BGE_RDMA_BD_MODE 0x4A00 1590 /* BD Read DMA Mode status register */ 1591 #define BGE_RDMA_BD_STATUS 0x4A04 1592 1593 #define BGE_RDMA_BD_MODE_RESET 0x00000001 1594 #define BGE_RDMA_BD_MODE_ENABLE 0x00000002 1595 1596 /* Non-LSO Read DMA Mode register */ 1597 #define BGE_RDMA_NON_LSO_MODE 0x4B00 1598 /* Non-LSO Read DMA Mode status register */ 1599 #define BGE_RDMA_NON_LSO_STATUS 0x4B04 1600 1601 #define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001 1602 #define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002 1603 1604 /* 1605 * Write DMA control registers 1606 */ 1607 #define BGE_WDMA_MODE 0x4C00 1608 #define BGE_WDMA_STATUS 0x4C04 1609 1610 /* Write DMA mode register */ 1611 #define BGE_WDMAMODE_RESET 0x00000001 1612 #define BGE_WDMAMODE_ENABLE 0x00000002 1613 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1614 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1615 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1616 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1617 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1618 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1619 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1620 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1621 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1622 #define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1623 #define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1624 1625 /* Write DMA status register */ 1626 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1627 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1628 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1629 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1630 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1631 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1632 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1633 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1634 1635 1636 /* 1637 * RX CPU registers 1638 */ 1639 #define BGE_RXCPU_MODE 0x5000 1640 #define BGE_RXCPU_STATUS 0x5004 1641 #define BGE_RXCPU_PC 0x501C 1642 1643 /* RX CPU mode register */ 1644 #define BGE_RXCPUMODE_RESET 0x00000001 1645 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1646 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1647 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1648 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1649 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1650 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1651 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1652 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1653 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1654 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1655 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1656 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1657 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1658 1659 /* RX CPU status register */ 1660 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1661 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1662 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1663 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1664 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1665 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1666 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1667 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1668 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1669 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1670 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1671 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1672 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1673 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1674 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1675 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1676 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1677 1678 /* 1679 * V? CPU registers 1680 */ 1681 #define BGE_VCPU_STATUS 0x5100 1682 #define BGE_VCPU_EXT_CTRL 0x6890 1683 1684 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1685 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1686 1687 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1688 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1689 1690 1691 /* 1692 * TX CPU registers 1693 */ 1694 #define BGE_TXCPU_MODE 0x5400 1695 #define BGE_TXCPU_STATUS 0x5404 1696 #define BGE_TXCPU_PC 0x541C 1697 1698 /* TX CPU mode register */ 1699 #define BGE_TXCPUMODE_RESET 0x00000001 1700 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1701 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1702 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1703 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1704 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1705 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1706 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1707 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1708 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1709 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1710 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1711 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1712 1713 /* TX CPU status register */ 1714 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1715 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1716 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1717 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1718 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1719 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1720 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1721 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1722 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1723 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1724 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1725 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1726 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1727 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1728 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1729 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1730 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1731 1732 1733 /* 1734 * Low priority mailbox registers 1735 */ 1736 #define BGE_LPMBX_IRQ0_HI 0x5800 1737 #define BGE_LPMBX_IRQ0_LO 0x5804 1738 #define BGE_LPMBX_IRQ1_HI 0x5808 1739 #define BGE_LPMBX_IRQ1_LO 0x580C 1740 #define BGE_LPMBX_IRQ2_HI 0x5810 1741 #define BGE_LPMBX_IRQ2_LO 0x5814 1742 #define BGE_LPMBX_IRQ3_HI 0x5818 1743 #define BGE_LPMBX_IRQ3_LO 0x581C 1744 #define BGE_LPMBX_GEN0_HI 0x5820 1745 #define BGE_LPMBX_GEN0_LO 0x5824 1746 #define BGE_LPMBX_GEN1_HI 0x5828 1747 #define BGE_LPMBX_GEN1_LO 0x582C 1748 #define BGE_LPMBX_GEN2_HI 0x5830 1749 #define BGE_LPMBX_GEN2_LO 0x5834 1750 #define BGE_LPMBX_GEN3_HI 0x5828 1751 #define BGE_LPMBX_GEN3_LO 0x582C 1752 #define BGE_LPMBX_GEN4_HI 0x5840 1753 #define BGE_LPMBX_GEN4_LO 0x5844 1754 #define BGE_LPMBX_GEN5_HI 0x5848 1755 #define BGE_LPMBX_GEN5_LO 0x584C 1756 #define BGE_LPMBX_GEN6_HI 0x5850 1757 #define BGE_LPMBX_GEN6_LO 0x5854 1758 #define BGE_LPMBX_GEN7_HI 0x5858 1759 #define BGE_LPMBX_GEN7_LO 0x585C 1760 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1761 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1762 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1763 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1764 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1765 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1766 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1767 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1768 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1769 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1770 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1771 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1772 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1773 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1774 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1775 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1776 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1777 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1778 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1779 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1780 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1781 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1782 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1783 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1784 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1785 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1786 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1787 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1788 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1789 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1790 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1791 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1792 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1793 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1794 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1795 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1796 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1797 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1798 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1799 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1800 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1801 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1802 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1803 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1804 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1805 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1806 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1807 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1808 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1809 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1810 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1811 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1812 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1813 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1814 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1815 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1816 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1817 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1818 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1819 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1820 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1821 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1822 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1823 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1824 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1825 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1826 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1827 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1828 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1829 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1830 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1831 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1832 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1833 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1834 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1835 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1836 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1837 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1838 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1839 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1840 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1841 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1842 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1843 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1844 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1845 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1846 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1847 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1848 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1849 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1850 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1851 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1852 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1853 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1854 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1855 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1856 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1857 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1858 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1859 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1860 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1861 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1862 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1863 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1864 1865 /* 1866 * Flow throw Queue reset register 1867 */ 1868 #define BGE_FTQ_RESET 0x5C00 1869 1870 #define BGE_FTQRESET_DMAREAD 0x00000002 1871 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1872 #define BGE_FTQRESET_DMADONE 0x00000010 1873 #define BGE_FTQRESET_SBDC 0x00000020 1874 #define BGE_FTQRESET_SDI 0x00000040 1875 #define BGE_FTQRESET_WDMA 0x00000080 1876 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1877 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1878 #define BGE_FTQRESET_SDC 0x00000400 1879 #define BGE_FTQRESET_HCC 0x00000800 1880 #define BGE_FTQRESET_TXFIFO 0x00001000 1881 #define BGE_FTQRESET_MBC 0x00002000 1882 #define BGE_FTQRESET_RBDC 0x00004000 1883 #define BGE_FTQRESET_RXLP 0x00008000 1884 #define BGE_FTQRESET_RDBDI 0x00010000 1885 #define BGE_FTQRESET_RDC 0x00020000 1886 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1887 1888 /* 1889 * Message Signaled Interrupt registers 1890 */ 1891 #define BGE_MSI_MODE 0x6000 1892 #define BGE_MSI_STATUS 0x6004 1893 #define BGE_MSI_FIFOACCESS 0x6008 1894 1895 /* MSI mode register */ 1896 #define BGE_MSIMODE_RESET 0x00000001 1897 #define BGE_MSIMODE_ENABLE 0x00000002 1898 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1899 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1900 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1901 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1902 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1903 #define BGE_MSIMODE_MSIX_MULTIMODE 0x00000080 1904 /* 1905 * Duplicate MSI_FIFOUFLOW_ATTN, only applies to BCM57785 and BCM5718 1906 * families. See 5718-PG105-R. 1907 */ 1908 #define BGE_MSIMODE_ONESHOT_DISABLE 0x00000020 1909 1910 /* MSI status register */ 1911 #define BGE_MSISTAT_MSI_PCI_REQ 0x00000001 1912 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1913 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1914 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1915 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1916 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1917 1918 1919 /* 1920 * DMA Completion registers 1921 */ 1922 #define BGE_DMAC_MODE 0x6400 1923 1924 /* DMA Completion mode register */ 1925 #define BGE_DMACMODE_RESET 0x00000001 1926 #define BGE_DMACMODE_ENABLE 0x00000002 1927 1928 1929 /* 1930 * General control registers. 1931 */ 1932 #define BGE_MODE_CTL 0x6800 1933 #define BGE_MISC_CFG 0x6804 1934 #define BGE_MISC_LOCAL_CTL 0x6808 1935 #define BGE_RX_CPU_EVENT 0x6810 1936 #define BGE_EE_ADDR 0x6838 1937 #define BGE_EE_DATA 0x683C 1938 #define BGE_EE_CTL 0x6840 1939 #define BGE_MDI_CTL 0x6844 1940 #define BGE_EE_DELAY 0x6848 1941 #define BGE_FASTBOOT_PC 0x6894 1942 1943 #define BGE_RX_CPU_DRV_EVENT 0x00004000 1944 1945 /* 1946 * NVRAM Control registers 1947 */ 1948 #define BGE_NVRAM_CMD 0x7000 1949 #define BGE_NVRAM_STAT 0x7004 1950 #define BGE_NVRAM_WRDATA 0x7008 1951 #define BGE_NVRAM_ADDR 0x700c 1952 #define BGE_NVRAM_RDDATA 0x7010 1953 #define BGE_NVRAM_CFG1 0x7014 1954 #define BGE_NVRAM_CFG2 0x7018 1955 #define BGE_NVRAM_CFG3 0x701c 1956 #define BGE_NVRAM_SWARB 0x7020 1957 #define BGE_NVRAM_ACCESS 0x7024 1958 #define BGE_NVRAM_WRITE1 0x7028 1959 1960 #define BGE_NVRAMCMD_RESET 0x00000001 1961 #define BGE_NVRAMCMD_DONE 0x00000008 1962 #define BGE_NVRAMCMD_START 0x00000010 1963 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1964 #define BGE_NVRAMCMD_ERASE 0x00000040 1965 #define BGE_NVRAMCMD_FIRST 0x00000080 1966 #define BGE_NVRAMCMD_LAST 0x00000100 1967 1968 #define BGE_NVRAM_READCMD \ 1969 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1970 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1971 #define BGE_NVRAM_WRITECMD \ 1972 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1973 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1974 1975 #define BGE_NVRAMSWARB_SET0 0x00000001 1976 #define BGE_NVRAMSWARB_SET1 0x00000002 1977 #define BGE_NVRAMSWARB_SET2 0x00000003 1978 #define BGE_NVRAMSWARB_SET3 0x00000004 1979 #define BGE_NVRAMSWARB_CLR0 0x00000010 1980 #define BGE_NVRAMSWARB_CLR1 0x00000020 1981 #define BGE_NVRAMSWARB_CLR2 0x00000040 1982 #define BGE_NVRAMSWARB_CLR3 0x00000080 1983 #define BGE_NVRAMSWARB_GNT0 0x00000100 1984 #define BGE_NVRAMSWARB_GNT1 0x00000200 1985 #define BGE_NVRAMSWARB_GNT2 0x00000400 1986 #define BGE_NVRAMSWARB_GNT3 0x00000800 1987 #define BGE_NVRAMSWARB_REQ0 0x00001000 1988 #define BGE_NVRAMSWARB_REQ1 0x00002000 1989 #define BGE_NVRAMSWARB_REQ2 0x00004000 1990 #define BGE_NVRAMSWARB_REQ3 0x00008000 1991 1992 #define BGE_NVRAMACC_ENABLE 0x00000001 1993 #define BGE_NVRAMACC_WRENABLE 0x00000002 1994 1995 /* Mode control register */ 1996 #define BGE_MODECTL_PCIE_TL_SEL 0x00000000 1997 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1998 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1999 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 2000 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 2001 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 2002 #define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 2003 #define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 2004 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 2005 #define BGE_MODECTL_NO_RX_CRC 0x00000400 2006 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 2007 #define BGE_MODECTL_NO_TX_INTR 0x00002000 2008 #define BGE_MODECTL_NO_RX_INTR 0x00004000 2009 #define BGE_MODECTL_FORCE_PCI32 0x00008000 2010 #define BGE_MODECTL_B2HRX_ENABLE 0x00008000 2011 #define BGE_MODECTL_STACKUP 0x00010000 2012 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 2013 #define BGE_MODECTL_HTX2B_ENABLE 0x00040000 2014 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 2015 #define BGE_MODECTL_PCIE_PL_SEL 0x00400000 2016 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 2017 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 2018 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 2019 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 2020 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 2021 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 2022 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 2023 #define BGE_MODECTL_PCIE_DL_SEL 0x20000000 2024 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 2025 #define BGE_MODECTL_PCIE_HI1K_EN 0x80000000 2026 #define BGE_MODECTL_PCIE_PORTS \ 2027 (BGE_MODECTL_PCIE_HI1K_EN | \ 2028 BGE_MODECTL_PCIE_TL_SEL | \ 2029 BGE_MODECTL_PCIE_PL_SEL | \ 2030 BGE_MODECTL_PCIE_DL_SEL) 2031 2032 /* Misc. config register */ 2033 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 2034 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 2035 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000 2036 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 2037 #define BGE_MISCCFG_BOARD_ID_MASK 0x0001e000 2038 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000 2039 #define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 2040 2041 #define BGE_32BITTIME_66MHZ (0x41 << 1) 2042 2043 /* Misc. Local Control */ 2044 #define BGE_MLC_INTR_STATE 0x00000001 2045 #define BGE_MLC_INTR_CLR 0x00000002 2046 #define BGE_MLC_INTR_SET 0x00000004 2047 #define BGE_MLC_INTR_ONATTN 0x00000008 2048 #define BGE_MLC_MISCIO_IN0 0x00000100 2049 #define BGE_MLC_MISCIO_IN1 0x00000200 2050 #define BGE_MLC_MISCIO_IN2 0x00000400 2051 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 2052 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 2053 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 2054 #define BGE_MLC_MISCIO_OUT0 0x00004000 2055 #define BGE_MLC_MISCIO_OUT1 0x00008000 2056 #define BGE_MLC_MISCIO_OUT2 0x00010000 2057 #define BGE_MLC_EXTRAM_ENB 0x00020000 2058 #define BGE_MLC_SRAM_SIZE 0x001C0000 2059 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 2060 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 2061 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2062 #define BGE_MLC_AUTO_EEPROM 0x01000000 2063 2064 #define BGE_SSRAMSIZE_256KB 0x00000000 2065 #define BGE_SSRAMSIZE_512KB 0x00040000 2066 #define BGE_SSRAMSIZE_1MB 0x00080000 2067 #define BGE_SSRAMSIZE_2MB 0x000C0000 2068 #define BGE_SSRAMSIZE_4MB 0x00100000 2069 #define BGE_SSRAMSIZE_8MB 0x00140000 2070 #define BGE_SSRAMSIZE_16M 0x00180000 2071 2072 /* EEPROM address register */ 2073 #define BGE_EEADDR_ADDRESS 0x0000FFFC 2074 #define BGE_EEADDR_HALFCLK 0x01FF0000 2075 #define BGE_EEADDR_START 0x02000000 2076 #define BGE_EEADDR_DEVID 0x1C000000 2077 #define BGE_EEADDR_RESET 0x20000000 2078 #define BGE_EEADDR_DONE 0x40000000 2079 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 2080 2081 #define BGE_EEDEVID(x) ((x & 7) << 26) 2082 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2083 #define BGE_HALFCLK_384SCL 0x60 2084 #define BGE_EE_READCMD \ 2085 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2086 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2087 #define BGE_EE_WRCMD \ 2088 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2089 BGE_EEADDR_START|BGE_EEADDR_DONE) 2090 2091 /* EEPROM Control register */ 2092 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2093 #define BGE_EECTL_CLKOUT 0x00000002 2094 #define BGE_EECTL_CLKIN 0x00000004 2095 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2096 #define BGE_EECTL_DATAOUT 0x00000010 2097 #define BGE_EECTL_DATAIN 0x00000020 2098 2099 /* MDI (MII/GMII) access register */ 2100 #define BGE_MDI_DATA 0x00000001 2101 #define BGE_MDI_DIR 0x00000002 2102 #define BGE_MDI_SEL 0x00000004 2103 #define BGE_MDI_CLK 0x00000008 2104 2105 #define BGE_MEMWIN_START 0x00008000 2106 #define BGE_MEMWIN_END 0x0000FFFF 2107 2108 /* BAR1 (APE) Register Definitions */ 2109 2110 #define BGE_APE_GPIO_MSG 0x0008 2111 #define BGE_APE_EVENT 0x000C 2112 #define BGE_APE_LOCK_REQ 0x002C 2113 #define BGE_APE_LOCK_GRANT 0x004C 2114 2115 #define BGE_APE_GPIO_MSG_SHIFT 4 2116 2117 #define BGE_APE_EVENT_1 0x00000001 2118 2119 #define BGE_APE_LOCK_REQ_DRIVER0 0x00001000 2120 2121 #define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000 2122 2123 /* APE Shared Memory block (writable by APE only) */ 2124 #define BGE_APE_SEG_SIG 0x4000 2125 #define BGE_APE_FW_STATUS 0x400C 2126 #define BGE_APE_FW_FEATURES 0x4010 2127 #define BGE_APE_FW_BEHAVIOR 0x4014 2128 #define BGE_APE_FW_VERSION 0x4018 2129 #define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024 2130 #define BGE_APE_FW_HEARTBEAT 0x4028 2131 #define BGE_APE_FW_ERROR_FLAGS 0x4074 2132 2133 #define BGE_APE_SEG_SIG_MAGIC 0x41504521 2134 2135 #define BGE_APE_FW_STATUS_READY 0x00000100 2136 2137 #define BGE_APE_FW_FEATURE_DASH 0x00000001 2138 #define BGE_APE_FW_FEATURE_NCSI 0x00000002 2139 2140 #define BGE_APE_FW_VERSION_MAJMSK 0xFF000000 2141 #define BGE_APE_FW_VERSION_MAJSFT 24 2142 #define BGE_APE_FW_VERSION_MINMSK 0x00FF0000 2143 #define BGE_APE_FW_VERSION_MINSFT 16 2144 #define BGE_APE_FW_VERSION_REVMSK 0x0000FF00 2145 #define BGE_APE_FW_VERSION_REVSFT 8 2146 #define BGE_APE_FW_VERSION_BLDMSK 0x000000FF 2147 2148 /* Host Shared Memory block (writable by host only) */ 2149 #define BGE_APE_HOST_SEG_SIG 0x4200 2150 #define BGE_APE_HOST_SEG_LEN 0x4204 2151 #define BGE_APE_HOST_INIT_COUNT 0x4208 2152 #define BGE_APE_HOST_DRIVER_ID 0x420C 2153 #define BGE_APE_HOST_BEHAVIOR 0x4210 2154 #define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 2155 #define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 2156 #define BGE_APE_HOST_DRVR_STATE 0x421C 2157 #define BGE_APE_HOST_WOL_SPEED 0x4224 2158 2159 #define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354 2160 2161 #define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020 2162 2163 #define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000 2164 #define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2165 (BGE_APE_HOST_DRIVER_ID_FBSD | \ 2166 ((maj) & 0xffd) << 16 | ((min) & 0xff) << 8) 2167 2168 #define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2169 2170 #define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0 2171 #define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000 2172 2173 #define BGE_APE_HOST_DRVR_STATE_START 0x00000001 2174 #define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2175 #define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 2176 #define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004 2177 2178 #define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 2179 2180 #define BGE_APE_EVENT_STATUS 0x4300 2181 2182 #define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2183 #define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2184 #define BGE_APE_EVENT_STATUS_STATE_START 0x00010000 2185 #define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2186 #define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000 2187 #define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2188 #define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2189 2190 #define BGE_APE_DEBUG_LOG 0x4E00 2191 #define BGE_APE_DEBUG_LOG_LEN 0x0100 2192 2193 #define BGE_APE_PER_LOCK_REQ 0x8400 2194 #define BGE_APE_PER_LOCK_GRANT 0x8420 2195 2196 #define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000 2197 #define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002 2198 #define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004 2199 #define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008 2200 2201 #define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000 2202 #define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002 2203 #define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004 2204 #define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008 2205 2206 /* APE Mutex Resources */ 2207 #define BGE_APE_LOCK_PHY0 0 2208 #define BGE_APE_LOCK_GRC 1 2209 #define BGE_APE_LOCK_PHY1 2 2210 #define BGE_APE_LOCK_PHY2 3 2211 #define BGE_APE_LOCK_MEM 4 2212 #define BGE_APE_LOCK_PHY3 5 2213 #define BGE_APE_LOCK_GPIO 7 2214 2215 /* 2216 * PCI-E Core Private Register Access to TL, DL & PL 2217 */ 2218 #define BGE_PCIE_TLDLPL_PORT 0x7c00 2219 #define BGE_PCIE_PL_LO_PHYCTL5 0x7c14 2220 #define BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000 2221 #define BGE_PCIE_DL_LO_FTSMAX 0x7c0c 2222 #define BGE_PCIE_DL_LO_FTSMAX_MASK 0x000000ff 2223 #define BGE_PCIE_DL_LO_FTSMAX_VAL 0x0000002c 2224 2225 /* 2226 * PCI-E transaction configure register. 2227 * Applies to BCM5906 and BCM5755+. See 5722-PG101-R. 2228 * 2229 * Earlier PCI-E chips, e.g. 5750, call it TLP workaround, 2230 * and there are no interesting bits in it. 2231 */ 2232 #define BGE_PCIE_TRANSACT 0x7c04 2233 #define BGE_PCIE_TRANSACT_ONESHOT_MSI 0x20000000 2234 2235 /* PCI-E PHY test control register */ 2236 #define BGE_PCIE_PHY_TSTCTL 0x7e2c 2237 #define BGE_PCIE_PHY_TSTCTL_PSCRAM 0x00000020 2238 #define BGE_PCIE_PHY_TSTCTL_PCIE10 0x00000040 2239 2240 #define PCI_SETBIT(dev, reg, x, s) \ 2241 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s) 2242 #define PCI_CLRBIT(dev, reg, x, s) \ 2243 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s) 2244 2245 /* 2246 * This magic number is written to the firmware mailbox at 0xb50 2247 * before a software reset is issued. After the internal firmware 2248 * has completed its initialization it will write the opposite of 2249 * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location, allowing 2250 * the driver to synchronize with the firmware. 2251 */ 2252 #define BGE_SRAM_FW_MB_MAGIC 0x4B657654 2253 2254 typedef struct { 2255 uint32_t bge_addr_hi; 2256 uint32_t bge_addr_lo; 2257 } bge_hostaddr; 2258 2259 #define BGE_HOSTADDR(x, y) \ 2260 do { \ 2261 (x).bge_addr_lo = ((uint64_t)(y) & 0xffffffff); \ 2262 (x).bge_addr_hi = ((uint64_t)(y) >> 32); \ 2263 } while(0) 2264 2265 #define BGE_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF) 2266 #define BGE_ADDR_HI(y) ((uint64_t)(y) >> 32) 2267 2268 /* Ring control block structure */ 2269 struct bge_rcb { 2270 bge_hostaddr bge_hostaddr; 2271 uint32_t bge_maxlen_flags; 2272 uint32_t bge_nicaddr; 2273 }; 2274 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2275 2276 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2277 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 2278 2279 struct bge_tx_bd { 2280 bge_hostaddr bge_addr; 2281 #if BYTE_ORDER == LITTLE_ENDIAN 2282 uint16_t bge_flags; 2283 uint16_t bge_len; 2284 uint16_t bge_vlan_tag; 2285 uint16_t bge_mss; 2286 #else 2287 uint16_t bge_len; 2288 uint16_t bge_flags; 2289 uint16_t bge_mss; 2290 uint16_t bge_vlan_tag; 2291 #endif 2292 }; 2293 2294 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2295 #define BGE_TXBDFLAG_IP_CSUM 0x0002 2296 #define BGE_TXBDFLAG_END 0x0004 2297 #define BGE_TXBDFLAG_IP_FRAG 0x0008 2298 #define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2299 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2300 #define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2301 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 2302 #define BGE_TXBDFLAG_COAL_NOW 0x0080 2303 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2304 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2305 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2306 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2307 #define BGE_TXBDFLAG_NO_CRC 0x8000 2308 2309 #define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2310 /* Bits [1:0] of the MSS header length. */ 2311 #define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2312 2313 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 2314 BGE_SEND_RING_1_TO_4 + \ 2315 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2316 2317 struct bge_rx_bd { 2318 bge_hostaddr bge_addr; 2319 #if BYTE_ORDER == LITTLE_ENDIAN 2320 uint16_t bge_len; 2321 uint16_t bge_idx; 2322 uint16_t bge_flags; 2323 uint16_t bge_type; 2324 uint16_t bge_tcp_udp_csum; 2325 uint16_t bge_ip_csum; 2326 uint16_t bge_vlan_tag; 2327 uint16_t bge_error_flag; 2328 #else 2329 uint16_t bge_idx; 2330 uint16_t bge_len; 2331 uint16_t bge_type; 2332 uint16_t bge_flags; 2333 uint16_t bge_ip_csum; 2334 uint16_t bge_tcp_udp_csum; 2335 uint16_t bge_error_flag; 2336 uint16_t bge_vlan_tag; 2337 #endif 2338 uint32_t bge_hash; 2339 uint32_t bge_opaque; 2340 }; 2341 2342 #define BGE_RXBDFLAG_END 0x0004 2343 #define BGE_RXBDFLAG_RSS_HASH 0x0008 2344 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 2345 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 2346 #define BGE_RXBDFLAG_ERROR 0x0400 2347 #define BGE_RXBDFLAG_MINI_RING 0x0800 2348 #define BGE_RXBDFLAG_IP_CSUM 0x1000 2349 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2350 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2351 #define BGE_RXBDFLAG_IPV6 0x8000 2352 2353 #define BGE_RXERRFLAG_BAD_CRC 0x0001 2354 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 2355 #define BGE_RXERRFLAG_LINK_LOST 0x0004 2356 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2357 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 2358 #define BGE_RXERRFLAG_RUNT 0x0020 2359 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2360 #define BGE_RXERRFLAG_GIANT 0x0080 2361 #define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 2362 2363 struct bge_sts_idx { 2364 #if BYTE_ORDER == LITTLE_ENDIAN 2365 uint16_t bge_rx_prod_idx; 2366 uint16_t bge_tx_cons_idx; 2367 #else 2368 uint16_t bge_tx_cons_idx; 2369 uint16_t bge_rx_prod_idx; 2370 #endif 2371 }; 2372 2373 struct bge_status_block { 2374 uint32_t bge_status; 2375 uint32_t bge_status_tag; 2376 #if BYTE_ORDER == LITTLE_ENDIAN 2377 uint16_t bge_rx_jumbo_cons_idx; 2378 uint16_t bge_rx_std_cons_idx; 2379 uint16_t bge_rx_mini_cons_idx; 2380 uint16_t bge_rsvd1; 2381 #else 2382 uint16_t bge_rx_std_cons_idx; 2383 uint16_t bge_rx_jumbo_cons_idx; 2384 uint16_t bge_rsvd1; 2385 uint16_t bge_rx_mini_cons_idx; 2386 #endif 2387 struct bge_sts_idx bge_idx[16]; 2388 }; 2389 #define BGE_STATUS_BLK_SZ sizeof(struct bge_status_block) 2390 2391 #define BGE_STATFLAG_UPDATED 0x00000001 2392 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2393 #define BGE_STATFLAG_ERROR 0x00000004 2394 2395 /* 2396 * Offset of MAC address inside EEPROM. 2397 */ 2398 #define BGE_EE_MAC_OFFSET 0x7C 2399 #define BGE_EE_MAC_OFFSET_5906 0x10 2400 #define BGE_EE_HWCFG_OFFSET 0xC8 2401 #define BGE_EE_MAC_OFFSET_5717 0xCC 2402 #define BGE_EE_MAC_OFFSET_5717_OFF 0x18C 2403 2404 #define BGE_HWCFG_VOLTAGE 0x00000003 2405 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 2406 #define BGE_HWCFG_MEDIA 0x00000030 2407 #define BGE_HWCFG_ASF 0x00000080 2408 2409 #define BGE_VOLTAGE_1POINT3 0x00000000 2410 #define BGE_VOLTAGE_1POINT8 0x00000001 2411 2412 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 2413 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2414 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 2415 2416 #define BGE_MEDIA_UNSPEC 0x00000000 2417 #define BGE_MEDIA_COPPER 0x00000010 2418 #define BGE_MEDIA_FIBER 0x00000020 2419 2420 #define BGE_PCI_READ_CMD 0x06000000 2421 #define BGE_PCI_WRITE_CMD 0x70000000 2422 2423 #define BGE_TICKS_PER_SEC 1000000 2424 2425 /* 2426 * Ring size constants. 2427 */ 2428 #define BGE_EVENT_RING_CNT 256 2429 #define BGE_CMD_RING_CNT 64 2430 #define BGE_STD_RX_RING_CNT 512 2431 #define BGE_JUMBO_RX_RING_CNT 256 2432 #define BGE_MINI_RX_RING_CNT 1024 2433 #define BGE_RETURN_RING_CNT 1024 2434 2435 /* 5705 has smaller return ring size */ 2436 2437 #define BGE_RETURN_RING_CNT_5705 512 2438 2439 /* 2440 * Possible TX ring sizes. 2441 */ 2442 #define BGE_TX_RING_CNT_128 128 2443 #define BGE_TX_RING_BASE_128 0x3800 2444 2445 #define BGE_TX_RING_CNT_256 256 2446 #define BGE_TX_RING_BASE_256 0x3000 2447 2448 #define BGE_TX_RING_CNT_512 512 2449 #define BGE_TX_RING_BASE_512 0x2000 2450 2451 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2452 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2453 2454 /* 2455 * Tigon III statistics counters. 2456 */ 2457 /* Statistics maintained MAC Receive block. */ 2458 struct bge_rx_mac_stats { 2459 bge_hostaddr ifHCInOctets; 2460 bge_hostaddr Reserved1; 2461 bge_hostaddr etherStatsFragments; 2462 bge_hostaddr ifHCInUcastPkts; 2463 bge_hostaddr ifHCInMulticastPkts; 2464 bge_hostaddr ifHCInBroadcastPkts; 2465 bge_hostaddr dot3StatsFCSErrors; 2466 bge_hostaddr dot3StatsAlignmentErrors; 2467 bge_hostaddr xonPauseFramesReceived; 2468 bge_hostaddr xoffPauseFramesReceived; 2469 bge_hostaddr macControlFramesReceived; 2470 bge_hostaddr xoffStateEntered; 2471 bge_hostaddr dot3StatsFramesTooLong; 2472 bge_hostaddr etherStatsJabbers; 2473 bge_hostaddr etherStatsUndersizePkts; 2474 bge_hostaddr inRangeLengthError; 2475 bge_hostaddr outRangeLengthError; 2476 bge_hostaddr etherStatsPkts64Octets; 2477 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2478 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2479 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2480 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2481 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2482 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2483 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2484 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2485 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2486 }; 2487 2488 2489 /* Statistics maintained MAC Transmit block. */ 2490 struct bge_tx_mac_stats { 2491 bge_hostaddr ifHCOutOctets; 2492 bge_hostaddr Reserved2; 2493 bge_hostaddr etherStatsCollisions; 2494 bge_hostaddr outXonSent; 2495 bge_hostaddr outXoffSent; 2496 bge_hostaddr flowControlDone; 2497 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2498 bge_hostaddr dot3StatsSingleCollisionFrames; 2499 bge_hostaddr dot3StatsMultipleCollisionFrames; 2500 bge_hostaddr dot3StatsDeferredTransmissions; 2501 bge_hostaddr Reserved3; 2502 bge_hostaddr dot3StatsExcessiveCollisions; 2503 bge_hostaddr dot3StatsLateCollisions; 2504 bge_hostaddr dot3Collided2Times; 2505 bge_hostaddr dot3Collided3Times; 2506 bge_hostaddr dot3Collided4Times; 2507 bge_hostaddr dot3Collided5Times; 2508 bge_hostaddr dot3Collided6Times; 2509 bge_hostaddr dot3Collided7Times; 2510 bge_hostaddr dot3Collided8Times; 2511 bge_hostaddr dot3Collided9Times; 2512 bge_hostaddr dot3Collided10Times; 2513 bge_hostaddr dot3Collided11Times; 2514 bge_hostaddr dot3Collided12Times; 2515 bge_hostaddr dot3Collided13Times; 2516 bge_hostaddr dot3Collided14Times; 2517 bge_hostaddr dot3Collided15Times; 2518 bge_hostaddr ifHCOutUcastPkts; 2519 bge_hostaddr ifHCOutMulticastPkts; 2520 bge_hostaddr ifHCOutBroadcastPkts; 2521 bge_hostaddr dot3StatsCarrierSenseErrors; 2522 bge_hostaddr ifOutDiscards; 2523 bge_hostaddr ifOutErrors; 2524 }; 2525 2526 /* Stats counters access through registers */ 2527 struct bge_mac_stats_regs { 2528 uint32_t ifHCOutOctets; 2529 uint32_t Reserved0; 2530 uint32_t etherStatsCollisions; 2531 uint32_t outXonSent; 2532 uint32_t outXoffSent; 2533 uint32_t Reserved1; 2534 uint32_t dot3StatsInternalMacTransmitErrors; 2535 uint32_t dot3StatsSingleCollisionFrames; 2536 uint32_t dot3StatsMultipleCollisionFrames; 2537 uint32_t dot3StatsDeferredTransmissions; 2538 uint32_t Reserved2; 2539 uint32_t dot3StatsExcessiveCollisions; 2540 uint32_t dot3StatsLateCollisions; 2541 uint32_t Reserved3[14]; 2542 uint32_t ifHCOutUcastPkts; 2543 uint32_t ifHCOutMulticastPkts; 2544 uint32_t ifHCOutBroadcastPkts; 2545 uint32_t Reserved4[2]; 2546 uint32_t ifHCInOctets; 2547 uint32_t Reserved5; 2548 uint32_t etherStatsFragments; 2549 uint32_t ifHCInUcastPkts; 2550 uint32_t ifHCInMulticastPkts; 2551 uint32_t ifHCInBroadcastPkts; 2552 uint32_t dot3StatsFCSErrors; 2553 uint32_t dot3StatsAlignmentErrors; 2554 uint32_t xonPauseFramesReceived; 2555 uint32_t xoffPauseFramesReceived; 2556 uint32_t macControlFramesReceived; 2557 uint32_t xoffStateEntered; 2558 uint32_t dot3StatsFramesTooLong; 2559 uint32_t etherStatsJabbers; 2560 uint32_t etherStatsUndersizePkts; 2561 }; 2562 2563 struct bge_stats { 2564 uint8_t Reserved0[256]; 2565 2566 /* Statistics maintained by Receive MAC. */ 2567 struct bge_rx_mac_stats rxstats; 2568 2569 bge_hostaddr Unused1[37]; 2570 2571 /* Statistics maintained by Transmit MAC. */ 2572 struct bge_tx_mac_stats txstats; 2573 2574 bge_hostaddr Unused2[31]; 2575 2576 /* Statistics maintained by Receive List Placement. */ 2577 bge_hostaddr COSIfHCInPkts[16]; 2578 bge_hostaddr COSFramesDroppedDueToFilters; 2579 bge_hostaddr nicDmaWriteQueueFull; 2580 bge_hostaddr nicDmaWriteHighPriQueueFull; 2581 bge_hostaddr nicNoMoreRxBDs; 2582 bge_hostaddr ifInDiscards; 2583 bge_hostaddr ifInErrors; 2584 bge_hostaddr nicRecvThresholdHit; 2585 2586 bge_hostaddr Unused3[9]; 2587 2588 /* Statistics maintained by Send Data Initiator. */ 2589 bge_hostaddr COSIfHCOutPkts[16]; 2590 bge_hostaddr nicDmaReadQueueFull; 2591 bge_hostaddr nicDmaReadHighPriQueueFull; 2592 bge_hostaddr nicSendDataCompQueueFull; 2593 2594 /* Statistics maintained by Host Coalescing. */ 2595 bge_hostaddr nicRingSetSendProdIndex; 2596 bge_hostaddr nicRingStatusUpdate; 2597 bge_hostaddr nicInterrupts; 2598 bge_hostaddr nicAvoidedInterrupts; 2599 bge_hostaddr nicSendThresholdHit; 2600 2601 uint8_t Reserved4[320]; 2602 }; 2603 #define BGE_STATS_SZ sizeof(struct bge_stats) 2604 2605 #if (BUS_SPACE_MAXADDR != BUS_SPACE_MAXADDR_32BIT) 2606 #define BGE_DMA_MAXADDR_40BIT 0xFFFFFFFFFF 2607 #define BGE_DMA_BOUNDARY_4G 0x100000000ULL 2608 #else 2609 #define BGE_DMA_MAXADDR_40BIT BUS_SPACE_MAXADDR 2610 #define BGE_DMA_BOUNDARY_4G 0 2611 #endif 2612 2613 #define BGE_STD_RX_RING_SZ \ 2614 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2615 #define BGE_JUMBO_RX_RING_SZ \ 2616 (sizeof(struct bge_rx_bd) * BGE_JUMBO_RX_RING_CNT) 2617 #define BGE_TX_RING_SZ \ 2618 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2619 #define BGE_RX_RTN_RING_SZ(cnt) \ 2620 (sizeof(struct bge_rx_bd) * (cnt)) 2621 2622 #endif /* !_IF_BGEREG_H_ */ 2623