1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $ 34 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $ 35 */ 36 37 #ifndef _IF_BNXVAR_H_ 38 #define _IF_BNXVAR_H_ 39 40 /* 41 * Tigon general information block. This resides in host memory 42 * and contains the status counters, ring control blocks and 43 * producer pointers. 44 */ 45 46 struct bnx_gib { 47 struct bge_stats bnx_stats; 48 struct bge_rcb bnx_tx_rcb[16]; 49 struct bge_rcb bnx_std_rx_rcb; 50 struct bge_rcb bnx_jumbo_rx_rcb; 51 struct bge_rcb bnx_mini_rx_rcb; 52 struct bge_rcb bnx_return_rcb; 53 }; 54 55 #define BNX_MIN_FRAMELEN 60 56 #define BNX_MAX_FRAMELEN 1536 57 #define BNX_JUMBO_FRAMELEN 9018 58 #define BNX_JUMBO_MTU (BNX_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 59 60 #define BNX_TIMEOUT 5000 61 #define BNX_FIRMWARE_TIMEOUT 100000 62 #define BNX_TXCONS_UNSET 0xFFFF /* impossible value */ 63 64 /* 65 * Other utility macros. 66 */ 67 #define BNX_INC(x, y) (x) = ((x) + 1) % (y) 68 69 /* 70 * Register access macros. The Tigon always uses memory mapped register 71 * accesses and all registers must be accessed with 32 bit operations. 72 */ 73 74 #define CSR_WRITE_4(sc, reg, val) \ 75 bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val) 76 77 #define CSR_READ_4(sc, reg) \ 78 bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg) 79 80 #define BNX_SETBIT(sc, reg, x) \ 81 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 82 83 #define BNX_CLRBIT(sc, reg, x) \ 84 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 85 86 #define BNX_MEMWIN_READ(sc, x, val) \ 87 do { \ 88 pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \ 89 (0xFFFF0000 & x), 4); \ 90 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 91 } while(0) 92 93 #define BNX_MEMWIN_WRITE(sc, x, val) \ 94 do { \ 95 pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \ 96 (0xFFFF0000 & x), 4); \ 97 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 98 } while(0) 99 100 #define RCB_WRITE_4(sc, rcb, offset, val) \ 101 bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, \ 102 rcb + offsetof(struct bge_rcb, offset), val) 103 104 /* 105 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 106 * values are tuneable. They control the actual amount of buffers 107 * allocated for the standard, mini and jumbo receive rings. 108 */ 109 110 #define BNX_SSLOTS 256 111 #define BNX_MSLOTS 256 112 #define BNX_JSLOTS 384 113 114 #define BNX_JRAWLEN (BNX_JUMBO_FRAMELEN + ETHER_ALIGN) 115 #define BNX_JLEN (BNX_JRAWLEN + \ 116 (sizeof(uint64_t) - BNX_JRAWLEN % sizeof(uint64_t))) 117 #define BNX_JPAGESZ PAGE_SIZE 118 #define BNX_RESID (BNX_JPAGESZ - (BNX_JLEN * BNX_JSLOTS) % BNX_JPAGESZ) 119 #define BNX_JMEM ((BNX_JLEN * BNX_JSLOTS) + BNX_RESID) 120 121 struct bnx_softc; 122 struct bnx_tx_ring; 123 124 struct bnx_jslot { 125 struct bnx_softc *bnx_sc; 126 void *bnx_buf; 127 bus_addr_t bnx_paddr; 128 int bnx_inuse; 129 int bnx_slot; 130 SLIST_ENTRY(bnx_jslot) jslot_link; 131 }; 132 133 /* 134 * Ring structures. Most of these reside in host memory and we tell 135 * the NIC where they are via the ring control blocks. The exceptions 136 * are the tx and command rings, which live in NIC memory and which 137 * we access via the shared memory window. 138 */ 139 struct bnx_ring_data { 140 struct bge_rx_bd *bnx_rx_jumbo_ring; 141 bus_addr_t bnx_rx_jumbo_ring_paddr; 142 void *bnx_jumbo_buf; 143 struct bnx_gib bnx_info; 144 }; 145 146 struct bnx_rx_buf { 147 bus_dmamap_t bnx_rx_dmamap; 148 struct mbuf *bnx_rx_mbuf; 149 bus_addr_t bnx_rx_paddr; 150 int bnx_rx_len; 151 int bnx_rx_refilled; 152 } __cachealign; 153 154 struct bnx_rx_std_ring { 155 struct lwkt_serialize bnx_rx_std_serialize; 156 struct bnx_softc *bnx_sc; 157 158 uint16_t bnx_rx_std_stop; 159 uint16_t bnx_rx_std; /* current prod ring head */ 160 struct bge_rx_bd *bnx_rx_std_ring; 161 162 int bnx_rx_std_refill __cachealign; 163 u_int bnx_rx_std_running; 164 struct thread bnx_rx_std_ithread; 165 166 struct bnx_rx_buf bnx_rx_std_buf[BGE_STD_RX_RING_CNT]; 167 168 bus_dma_tag_t bnx_rx_mtag; /* RX mbuf DMA tag */ 169 170 bus_dma_tag_t bnx_rx_std_ring_tag; 171 bus_dmamap_t bnx_rx_std_ring_map; 172 bus_addr_t bnx_rx_std_ring_paddr; 173 } __cachealign; 174 175 struct bnx_rx_ret_ring { 176 struct lwkt_serialize bnx_rx_ret_serialize; 177 int bnx_rx_mbx; 178 uint32_t bnx_saved_status_tag; 179 volatile uint32_t *bnx_hw_status_tag; 180 int bnx_msix_mbx; 181 struct bnx_softc *bnx_sc; 182 struct bnx_rx_std_ring *bnx_std; 183 struct bnx_tx_ring *bnx_txr; 184 185 /* Shadow of bnx_rx_std_ring's bnx_rx_mtag */ 186 bus_dma_tag_t bnx_rx_mtag; 187 188 volatile uint16_t *bnx_rx_considx; 189 uint16_t bnx_rx_saved_considx; 190 uint16_t bnx_rx_cnt; 191 uint16_t bnx_rx_cntmax; 192 uint16_t bnx_rx_mask; 193 struct bge_rx_bd *bnx_rx_ret_ring; 194 bus_dmamap_t bnx_rx_tmpmap; 195 196 u_long bnx_rx_pkt; 197 bus_dma_tag_t bnx_rx_ret_ring_tag; 198 bus_dmamap_t bnx_rx_ret_ring_map; 199 bus_addr_t bnx_rx_ret_ring_paddr; 200 } __cachealign; 201 202 /* 203 * Mbuf pointers. We need these to keep track of the virtual addresses 204 * of our mbuf chains since we can only convert from physical to virtual, 205 * not the other way around. 206 */ 207 struct bnx_chain_data { 208 bus_dma_tag_t bnx_parent_tag; 209 bus_dma_tag_t bnx_rx_jumbo_ring_tag; 210 bus_dma_tag_t bnx_jumbo_tag; 211 bus_dmamap_t bnx_rx_jumbo_ring_map; 212 bus_dmamap_t bnx_jumbo_map; 213 struct bnx_rx_buf bnx_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 214 /* Stick the jumbo mem management stuff here too. */ 215 struct bnx_jslot bnx_jslots[BNX_JSLOTS]; 216 }; 217 218 struct bnx_tx_buf { 219 bus_dmamap_t bnx_tx_dmamap; 220 struct mbuf *bnx_tx_mbuf; 221 }; 222 223 struct bnx_tx_ring { 224 struct lwkt_serialize bnx_tx_serialize; 225 volatile uint32_t *bnx_hw_status_tag; 226 uint32_t bnx_saved_status_tag; 227 struct bnx_softc *bnx_sc; 228 struct ifaltq_subque *bnx_ifsq; 229 volatile uint16_t *bnx_tx_considx; 230 uint16_t bnx_tx_flags; 231 #define BNX_TX_FLAG_SHORTDMA 0x0001 232 #define BNX_TX_FLAG_FORCE_DEFRAG 0x0002 233 uint16_t bnx_tx_saved_considx; 234 int bnx_tx_cnt; 235 uint32_t bnx_tx_prodidx; 236 int bnx_tx_wreg; 237 int bnx_tx_mbx; 238 struct ifsubq_watchdog bnx_tx_watchdog; 239 240 struct bge_tx_bd *bnx_tx_ring; 241 242 bus_dma_tag_t bnx_tx_mtag; /* TX mbuf DMA tag */ 243 struct bnx_tx_buf bnx_tx_buf[BGE_TX_RING_CNT]; 244 245 bus_dma_tag_t bnx_tx_ring_tag; 246 bus_dmamap_t bnx_tx_ring_map; 247 bus_addr_t bnx_tx_ring_paddr; 248 int bnx_tx_cpuid; 249 250 u_long bnx_tx_pkt; 251 } __cachealign; 252 253 struct bnx_intr_data { 254 struct bnx_softc *bnx_sc; 255 struct bnx_rx_ret_ring *bnx_ret; 256 struct bnx_tx_ring *bnx_txr; 257 258 int bnx_intr_cpuid; 259 struct lwkt_serialize *bnx_intr_serialize; 260 struct callout bnx_intr_timer; 261 void (*bnx_intr_check)(void *); 262 uint16_t bnx_rx_check_considx; 263 uint16_t bnx_tx_check_considx; 264 boolean_t bnx_intr_maylose; 265 266 void *bnx_intr_arg; 267 driver_intr_t *bnx_intr_func; 268 void *bnx_intr_hand; 269 struct resource *bnx_intr_res; 270 int bnx_intr_rid; 271 int bnx_intr_mbx; 272 const uint32_t *bnx_saved_status_tag; 273 274 const char *bnx_intr_desc; 275 char bnx_intr_desc0[64]; 276 277 bus_dma_tag_t bnx_status_tag; 278 bus_dmamap_t bnx_status_map; 279 struct bge_status_block *bnx_status_block; 280 bus_addr_t bnx_status_block_paddr; 281 } __cachealign; 282 283 #define BNX_RX_RING_MAX 4 284 #define BNX_TX_RING_MAX 4 285 #define BNX_INTR_MAX 5 286 287 struct bnx_softc { 288 struct arpcom arpcom; /* interface info */ 289 device_t bnx_dev; 290 device_t bnx_miibus; 291 bus_space_handle_t bnx_bhandle; 292 bus_space_tag_t bnx_btag; 293 struct resource *bnx_res; 294 struct ifmedia bnx_ifmedia; /* TBI media info */ 295 int bnx_pciecap; 296 uint32_t bnx_flags; /* BNX_FLAG_ */ 297 #define BNX_FLAG_TBI 0x00000001 298 #define BNX_FLAG_JUMBO 0x00000002 299 #define BNX_FLAG_5717_PLUS 0x00000008 300 #define BNX_FLAG_MII_SERDES 0x00000010 301 #define BNX_FLAG_CPMU 0x00000020 302 #define BNX_FLAG_57765_PLUS 0x00000040 303 #define BNX_FLAG_57765_FAMILY 0x00000080 304 #define BNX_FLAG_STATUSTAG_BUG 0x00000100 305 #define BNX_FLAG_TSO 0x00000200 306 #define BNX_FLAG_NO_EEPROM 0x10000000 307 #define BNX_FLAG_RXTX_BUNDLE 0x20000000 308 #define BNX_FLAG_STD_THREAD 0x40000000 309 #define BNX_FLAG_STATUS_HASTAG 0x80000000 310 311 uint32_t bnx_chipid; 312 uint32_t bnx_asicrev; 313 uint32_t bnx_chiprev; 314 struct bnx_ring_data bnx_ldata; /* rings */ 315 struct bnx_chain_data bnx_cdata; /* mbufs */ 316 317 struct lwkt_serialize bnx_main_serialize; 318 volatile uint32_t *bnx_hw_status; 319 volatile uint32_t *bnx_hw_status_tag; 320 uint32_t bnx_saved_status_tag; 321 int bnx_link_evt; 322 u_long bnx_errors; 323 u_long bnx_norxbds; 324 325 int bnx_serialize_cnt; 326 struct lwkt_serialize **bnx_serialize; 327 328 int bnx_tx_ringcnt; 329 struct bnx_tx_ring *bnx_tx_ring; 330 int bnx_rx_retcnt; 331 struct bnx_rx_ret_ring *bnx_rx_ret_ring; 332 struct bnx_rx_std_ring bnx_rx_std_ring; 333 334 uint16_t bnx_jumbo; /* current jumo ring head */ 335 SLIST_HEAD(__bnx_jfreehead, bnx_jslot) bnx_jfree_listhead; 336 struct lwkt_serialize bnx_jslot_serializer; 337 uint32_t bnx_rx_coal_ticks; 338 uint32_t bnx_tx_coal_ticks; 339 uint32_t bnx_rx_coal_bds; 340 uint32_t bnx_tx_coal_bds; 341 uint32_t bnx_rx_coal_bds_int; 342 uint32_t bnx_tx_coal_bds_int; 343 uint32_t bnx_mi_mode; 344 int bnx_if_flags; 345 int bnx_link; 346 int bnx_tick_cpuid; 347 struct callout bnx_tick_timer; 348 349 int bnx_npoll_rxoff; 350 int bnx_npoll_txoff; 351 352 int bnx_msix_mem_rid; 353 struct resource *bnx_msix_mem_res; 354 int bnx_intr_type; 355 int bnx_intr_cnt; 356 struct bnx_intr_data bnx_intr_data[BNX_INTR_MAX]; 357 358 struct sysctl_ctx_list bnx_sysctl_ctx; 359 struct sysctl_oid *bnx_sysctl_tree; 360 361 int bnx_phyno; 362 uint32_t bnx_coal_chg; 363 #define BNX_RX_COAL_TICKS_CHG 0x01 364 #define BNX_TX_COAL_TICKS_CHG 0x02 365 #define BNX_RX_COAL_BDS_CHG 0x04 366 #define BNX_TX_COAL_BDS_CHG 0x08 367 #define BNX_RX_COAL_BDS_INT_CHG 0x40 368 #define BNX_TX_COAL_BDS_INT_CHG 0x80 369 370 void (*bnx_link_upd)(struct bnx_softc *, uint32_t); 371 uint32_t bnx_link_chg; 372 373 int bnx_rss_debug; 374 #define BNX_TSO_NSTATS 45 375 u_long bnx_tsosegs[BNX_TSO_NSTATS]; 376 }; 377 378 #define BNX_NSEG_NEW 40 379 #define BNX_NSEG_SPARE 33 /* enough for 64K TSO segment */ 380 #define BNX_NSEG_RSVD 4 381 382 /* RX coalesce ticks, unit: us */ 383 #define BNX_RX_COAL_TICKS_MIN 0 384 #define BNX_RX_COAL_TICKS_DEF 160 385 #define BNX_RX_COAL_TICKS_MAX 1023 386 387 /* TX coalesce ticks, unit: us */ 388 #define BNX_TX_COAL_TICKS_MIN 0 389 #define BNX_TX_COAL_TICKS_DEF 1023 390 #define BNX_TX_COAL_TICKS_MAX 1023 391 392 /* RX coalesce BDs */ 393 #define BNX_RX_COAL_BDS_MIN 0 394 #define BNX_RX_COAL_BDS_DEF 0 395 #define BNX_RX_COAL_BDS_INT_DEF 80 396 #define BNX_RX_COAL_BDS_MAX 255 397 398 /* TX coalesce BDs */ 399 #define BNX_TX_COAL_BDS_MIN 0 400 #define BNX_TX_COAL_BDS_DEF 64 401 #define BNX_TX_COAL_BDS_INT_DEF 64 402 #define BNX_TX_COAL_BDS_MAX 255 403 404 /* Number of segments sent before writing to TX related registers */ 405 #define BNX_TX_WREG_NSEGS 8 406 407 /* Return ring descriptor count */ 408 #define BNX_RETURN_RING_CNT 512 409 410 #define BNX_TX_RING_MAX 4 411 412 #define BNX_RSS_ENABLED(sc) ((sc)->bnx_rx_retcnt > 1) 413 414 #endif /* !_IF_BNXVAR_H_ */ 415