1 /* 2 * 3 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 2001-2006, Intel Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * 3. Neither the name of the Intel Corporation nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * 35 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 36 * 37 * This code is derived from software contributed to The DragonFly Project 38 * by Matthew Dillon <dillon@backplane.com> 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * 3. Neither the name of The DragonFly Project nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific, prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 57 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 58 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 60 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 61 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 62 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 64 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * $DragonFly: src/sys/dev/netif/em/if_em.c,v 1.80 2008/09/17 08:51:29 sephe Exp $ 68 * $FreeBSD$ 69 */ 70 /* 71 * SERIALIZATION API RULES: 72 * 73 * - If the driver uses the same serializer for the interrupt as for the 74 * ifnet, most of the serialization will be done automatically for the 75 * driver. 76 * 77 * - ifmedia entry points will be serialized by the ifmedia code using the 78 * ifnet serializer. 79 * 80 * - if_* entry points except for if_input will be serialized by the IF 81 * and protocol layers. 82 * 83 * - The device driver must be sure to serialize access from timeout code 84 * installed by the device driver. 85 * 86 * - The device driver typically holds the serializer at the time it wishes 87 * to call if_input. If so, it should pass the serializer to if_input and 88 * note that the serializer might be dropped temporarily by if_input 89 * (e.g. in case it has to bridge the packet to another interface). 90 * 91 * NOTE! Since callers into the device driver hold the ifnet serializer, 92 * the device driver may be holding a serializer at the time it calls 93 * if_input even if it is not serializer-aware. 94 */ 95 96 #include "opt_polling.h" 97 #include "opt_inet.h" 98 #include "opt_serializer.h" 99 100 #include <sys/param.h> 101 #include <sys/bus.h> 102 #include <sys/endian.h> 103 #include <sys/interrupt.h> 104 #include <sys/kernel.h> 105 #include <sys/ktr.h> 106 #include <sys/malloc.h> 107 #include <sys/mbuf.h> 108 #include <sys/module.h> 109 #include <sys/rman.h> 110 #include <sys/serialize.h> 111 #include <sys/socket.h> 112 #include <sys/sockio.h> 113 #include <sys/sysctl.h> 114 115 #include <net/bpf.h> 116 #include <net/ethernet.h> 117 #include <net/if.h> 118 #include <net/if_arp.h> 119 #include <net/if_dl.h> 120 #include <net/if_media.h> 121 #include <net/if_types.h> 122 #include <net/ifq_var.h> 123 #include <net/vlan/if_vlan_var.h> 124 #include <net/vlan/if_vlan_ether.h> 125 126 #ifdef INET 127 #include <netinet/in.h> 128 #include <netinet/in_systm.h> 129 #include <netinet/in_var.h> 130 #include <netinet/ip.h> 131 #include <netinet/tcp.h> 132 #include <netinet/udp.h> 133 #endif 134 135 #include <dev/netif/em/if_em_hw.h> 136 #include <dev/netif/em/if_em.h> 137 138 #define EM_X60_WORKAROUND 139 140 /********************************************************************* 141 * Set this to one to display debug statistics 142 *********************************************************************/ 143 int em_display_debug_stats = 0; 144 145 /********************************************************************* 146 * Driver version 147 *********************************************************************/ 148 149 char em_driver_version[] = "6.2.9"; 150 151 152 /********************************************************************* 153 * PCI Device ID Table 154 * 155 * Used by probe to select devices to load on 156 * Last field stores an index into em_strings 157 * Last entry must be all 0s 158 * 159 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 160 *********************************************************************/ 161 162 static em_vendor_info_t em_vendor_info_array[] = 163 { 164 /* Intel(R) PRO/1000 Network Connection */ 165 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 166 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 167 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 168 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 169 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 170 171 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 172 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 173 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 174 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 175 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 176 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 177 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 178 179 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 180 181 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 182 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 183 184 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 185 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 186 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 187 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 188 189 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 190 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 191 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 192 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 193 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 194 195 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 196 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 197 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 198 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 199 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 200 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 201 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 202 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 203 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 204 PCI_ANY_ID, PCI_ANY_ID, 0}, 205 206 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 207 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 208 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 209 210 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 211 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 212 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 213 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 214 PCI_ANY_ID, PCI_ANY_ID, 0}, 215 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE, 216 PCI_ANY_ID, PCI_ANY_ID, 0}, 217 218 { 0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 219 PCI_ANY_ID, PCI_ANY_ID, 0}, 220 { 0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, 221 PCI_ANY_ID, PCI_ANY_ID, 0}, 222 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 223 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 224 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 225 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 226 227 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 228 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 229 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 230 231 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 232 PCI_ANY_ID, PCI_ANY_ID, 0}, 233 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 234 PCI_ANY_ID, PCI_ANY_ID, 0}, 235 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 236 PCI_ANY_ID, PCI_ANY_ID, 0}, 237 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 238 PCI_ANY_ID, PCI_ANY_ID, 0}, 239 240 { 0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 241 { 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 242 { 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 243 { 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 244 { 0x8086, E1000_DEV_ID_ICH8_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 245 { 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 246 { 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0}, 247 248 { 0x8086, E1000_DEV_ID_ICH9_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 249 { 0x8086, E1000_DEV_ID_ICH9_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 250 { 0x8086, E1000_DEV_ID_ICH9_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 251 { 0x8086, E1000_DEV_ID_ICH9_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 252 { 0x8086, E1000_DEV_ID_ICH9_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 253 254 { 0x8086, E1000_DEV_ID_82575EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 255 { 0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, 256 PCI_ANY_ID, PCI_ANY_ID, 0}, 257 { 0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, 258 PCI_ANY_ID, PCI_ANY_ID, 0}, 259 { 0x8086, 0x101A, PCI_ANY_ID, PCI_ANY_ID, 0}, 260 { 0x8086, 0x1014, PCI_ANY_ID, PCI_ANY_ID, 0}, 261 /* required last entry */ 262 { 0, 0, 0, 0, 0} 263 }; 264 265 /********************************************************************* 266 * Table of branding strings for all supported NICs. 267 *********************************************************************/ 268 269 static const char *em_strings[] = { 270 "Intel(R) PRO/1000 Network Connection" 271 }; 272 273 /********************************************************************* 274 * Function prototypes 275 *********************************************************************/ 276 static int em_probe(device_t); 277 static int em_attach(device_t); 278 static int em_detach(device_t); 279 static int em_shutdown(device_t); 280 static void em_intr(void *); 281 static int em_suspend(device_t); 282 static int em_resume(device_t); 283 static void em_start(struct ifnet *); 284 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 285 static void em_watchdog(struct ifnet *); 286 static void em_init(void *); 287 static void em_stop(void *); 288 static void em_media_status(struct ifnet *, struct ifmediareq *); 289 static int em_media_change(struct ifnet *); 290 static void em_identify_hardware(struct adapter *); 291 static int em_allocate_pci_resources(device_t); 292 static void em_free_pci_resources(device_t); 293 static void em_local_timer(void *); 294 static int em_hardware_init(struct adapter *); 295 static void em_setup_interface(device_t, struct adapter *); 296 static int em_setup_transmit_structures(struct adapter *); 297 static void em_initialize_transmit_unit(struct adapter *); 298 static int em_setup_receive_structures(struct adapter *); 299 static void em_initialize_receive_unit(struct adapter *); 300 static void em_enable_intr(struct adapter *); 301 static void em_disable_intr(struct adapter *); 302 static void em_free_transmit_structures(struct adapter *); 303 static void em_free_receive_structures(struct adapter *); 304 static void em_update_stats_counters(struct adapter *); 305 static void em_txeof(struct adapter *); 306 static int em_allocate_receive_structures(struct adapter *); 307 static void em_rxeof(struct adapter *, int); 308 static void em_receive_checksum(struct adapter *, struct em_rx_desc *, 309 struct mbuf *); 310 static void em_transmit_checksum_setup(struct adapter *, struct mbuf *, 311 uint32_t *, uint32_t *); 312 static void em_set_promisc(struct adapter *); 313 static void em_disable_promisc(struct adapter *); 314 static void em_set_multi(struct adapter *); 315 static void em_print_hw_stats(struct adapter *); 316 static void em_update_link_status(struct adapter *); 317 static int em_get_buf(int i, struct adapter *, struct mbuf *, int how); 318 static void em_enable_vlans(struct adapter *); 319 static void em_disable_vlans(struct adapter *) __unused; 320 static int em_encap(struct adapter *, struct mbuf *); 321 static void em_smartspeed(struct adapter *); 322 static int em_82547_fifo_workaround(struct adapter *, int); 323 static void em_82547_update_fifo_head(struct adapter *, int); 324 static int em_82547_tx_fifo_reset(struct adapter *); 325 static void em_82547_move_tail(void *); 326 static void em_82547_move_tail_serialized(struct adapter *); 327 static int em_dma_malloc(struct adapter *, bus_size_t, 328 struct em_dma_alloc *); 329 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 330 static void em_print_debug_info(struct adapter *); 331 static int em_is_valid_ether_addr(uint8_t *); 332 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 333 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 334 static uint32_t em_fill_descriptors(bus_addr_t address, uint32_t length, 335 PDESC_ARRAY desc_array); 336 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 337 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 338 static void em_add_int_delay_sysctl(struct adapter *, const char *, 339 const char *, 340 struct em_int_delay_info *, int, int); 341 342 /********************************************************************* 343 * FreeBSD Device Interface Entry Points 344 *********************************************************************/ 345 346 static device_method_t em_methods[] = { 347 /* Device interface */ 348 DEVMETHOD(device_probe, em_probe), 349 DEVMETHOD(device_attach, em_attach), 350 DEVMETHOD(device_detach, em_detach), 351 DEVMETHOD(device_shutdown, em_shutdown), 352 DEVMETHOD(device_suspend, em_suspend), 353 DEVMETHOD(device_resume, em_resume), 354 {0, 0} 355 }; 356 357 static driver_t em_driver = { 358 "em", em_methods, sizeof(struct adapter), 359 }; 360 361 static devclass_t em_devclass; 362 363 DECLARE_DUMMY_MODULE(if_em); 364 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, 0, 0); 365 366 /********************************************************************* 367 * Tunable default values. 368 *********************************************************************/ 369 370 #define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 371 #define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 372 373 static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV); 374 static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR); 375 static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV); 376 static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV); 377 static int em_int_throttle_ceil = 10000; 378 static int em_rxd = EM_DEFAULT_RXD; 379 static int em_txd = EM_DEFAULT_TXD; 380 static int em_smart_pwr_down = FALSE; 381 382 TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 383 TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 384 TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 385 TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 386 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil); 387 TUNABLE_INT("hw.em.rxd", &em_rxd); 388 TUNABLE_INT("hw.em.txd", &em_txd); 389 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 390 391 /* 392 * Kernel trace for characterization of operations 393 */ 394 #if !defined(KTR_IF_EM) 395 #define KTR_IF_EM KTR_ALL 396 #endif 397 KTR_INFO_MASTER(if_em); 398 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin", 0); 399 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end", 0); 400 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet", 0); 401 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet", 0); 402 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean", 0); 403 #define logif(name) KTR_LOG(if_em_ ## name) 404 405 /********************************************************************* 406 * Device identification routine 407 * 408 * em_probe determines if the driver should be loaded on 409 * adapter based on PCI vendor/device id of the adapter. 410 * 411 * return 0 on success, positive on failure 412 *********************************************************************/ 413 414 static int 415 em_probe(device_t dev) 416 { 417 em_vendor_info_t *ent; 418 419 uint16_t pci_vendor_id = 0; 420 uint16_t pci_device_id = 0; 421 uint16_t pci_subvendor_id = 0; 422 uint16_t pci_subdevice_id = 0; 423 char adapter_name[60]; 424 425 INIT_DEBUGOUT("em_probe: begin"); 426 427 pci_vendor_id = pci_get_vendor(dev); 428 if (pci_vendor_id != EM_VENDOR_ID) 429 return (ENXIO); 430 431 pci_device_id = pci_get_device(dev); 432 pci_subvendor_id = pci_get_subvendor(dev); 433 pci_subdevice_id = pci_get_subdevice(dev); 434 435 ent = em_vendor_info_array; 436 while (ent->vendor_id != 0) { 437 if ((pci_vendor_id == ent->vendor_id) && 438 (pci_device_id == ent->device_id) && 439 440 ((pci_subvendor_id == ent->subvendor_id) || 441 (ent->subvendor_id == PCI_ANY_ID)) && 442 443 ((pci_subdevice_id == ent->subdevice_id) || 444 (ent->subdevice_id == PCI_ANY_ID))) { 445 ksnprintf(adapter_name, sizeof(adapter_name), 446 "%s, Version - %s", em_strings[ent->index], 447 em_driver_version); 448 device_set_desc_copy(dev, adapter_name); 449 device_set_async_attach(dev, TRUE); 450 return (0); 451 } 452 ent++; 453 } 454 455 return (ENXIO); 456 } 457 458 /********************************************************************* 459 * Device initialization routine 460 * 461 * The attach entry point is called when the driver is being loaded. 462 * This routine identifies the type of hardware, allocates all resources 463 * and initializes the hardware. 464 * 465 * return 0 on success, positive on failure 466 *********************************************************************/ 467 468 static int 469 em_attach(device_t dev) 470 { 471 struct adapter *adapter; 472 struct ifnet *ifp; 473 int tsize, rsize; 474 int error = 0; 475 476 INIT_DEBUGOUT("em_attach: begin"); 477 478 adapter = device_get_softc(dev); 479 ifp = &adapter->interface_data.ac_if; 480 481 callout_init(&adapter->timer); 482 callout_init(&adapter->tx_fifo_timer); 483 484 adapter->dev = dev; 485 adapter->osdep.dev = dev; 486 487 /* SYSCTL stuff */ 488 sysctl_ctx_init(&adapter->sysctl_ctx); 489 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx, 490 SYSCTL_STATIC_CHILDREN(_hw), 491 OID_AUTO, 492 device_get_nameunit(dev), 493 CTLFLAG_RD, 494 0, ""); 495 496 if (adapter->sysctl_tree == NULL) { 497 device_printf(dev, "Unable to create sysctl tree\n"); 498 return EIO; 499 } 500 501 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 502 SYSCTL_CHILDREN(adapter->sysctl_tree), 503 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, 504 (void *)adapter, 0, 505 em_sysctl_debug_info, "I", "Debug Information"); 506 507 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 508 SYSCTL_CHILDREN(adapter->sysctl_tree), 509 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, 510 (void *)adapter, 0, 511 em_sysctl_stats, "I", "Statistics"); 512 513 /* Determine hardware revision */ 514 em_identify_hardware(adapter); 515 516 /* Set up some sysctls for the tunable interrupt delays */ 517 em_add_int_delay_sysctl(adapter, "rx_int_delay", 518 "receive interrupt delay in usecs", 519 &adapter->rx_int_delay, 520 E1000_REG_OFFSET(&adapter->hw, RDTR), 521 em_rx_int_delay_dflt); 522 em_add_int_delay_sysctl(adapter, "tx_int_delay", 523 "transmit interrupt delay in usecs", 524 &adapter->tx_int_delay, 525 E1000_REG_OFFSET(&adapter->hw, TIDV), 526 em_tx_int_delay_dflt); 527 if (adapter->hw.mac_type >= em_82540) { 528 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 529 "receive interrupt delay limit in usecs", 530 &adapter->rx_abs_int_delay, 531 E1000_REG_OFFSET(&adapter->hw, RADV), 532 em_rx_abs_int_delay_dflt); 533 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 534 "transmit interrupt delay limit in usecs", 535 &adapter->tx_abs_int_delay, 536 E1000_REG_OFFSET(&adapter->hw, TADV), 537 em_tx_abs_int_delay_dflt); 538 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 539 SYSCTL_CHILDREN(adapter->sysctl_tree), 540 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, 541 adapter, 0, em_sysctl_int_throttle, "I", NULL); 542 } 543 544 /* 545 * Validate number of transmit and receive descriptors. It 546 * must not exceed hardware maximum, and must be multiple 547 * of EM_DBA_ALIGN. 548 */ 549 if (((em_txd * sizeof(struct em_tx_desc)) % EM_DBA_ALIGN) != 0 || 550 (adapter->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) || 551 (adapter->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) || 552 (em_txd < EM_MIN_TXD)) { 553 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 554 EM_DEFAULT_TXD, em_txd); 555 adapter->num_tx_desc = EM_DEFAULT_TXD; 556 } else { 557 adapter->num_tx_desc = em_txd; 558 } 559 560 if (((em_rxd * sizeof(struct em_rx_desc)) % EM_DBA_ALIGN) != 0 || 561 (adapter->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) || 562 (adapter->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) || 563 (em_rxd < EM_MIN_RXD)) { 564 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 565 EM_DEFAULT_RXD, em_rxd); 566 adapter->num_rx_desc = EM_DEFAULT_RXD; 567 } else { 568 adapter->num_rx_desc = em_rxd; 569 } 570 571 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 572 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, "rxd", 573 CTLFLAG_RD, &adapter->num_rx_desc, 0, NULL); 574 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 575 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, "txd", 576 CTLFLAG_RD, &adapter->num_tx_desc, 0, NULL); 577 578 adapter->hw.autoneg = DO_AUTO_NEG; 579 adapter->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 580 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 581 adapter->hw.tbi_compatibility_en = TRUE; 582 adapter->rx_buffer_len = EM_RXBUFFER_2048; 583 584 adapter->hw.phy_init_script = 1; 585 adapter->hw.phy_reset_disable = FALSE; 586 587 #ifndef EM_MASTER_SLAVE 588 adapter->hw.master_slave = em_ms_hw_default; 589 #else 590 adapter->hw.master_slave = EM_MASTER_SLAVE; 591 #endif 592 593 /* 594 * Set the max frame size assuming standard ethernet 595 * sized frames. 596 */ 597 adapter->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 598 599 adapter->hw.min_frame_size = 600 MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN; 601 602 /* 603 * This controls when hardware reports transmit completion 604 * status. 605 */ 606 adapter->hw.report_tx_early = 1; 607 608 error = em_allocate_pci_resources(dev); 609 if (error) 610 goto fail; 611 612 /* Initialize eeprom parameters */ 613 em_init_eeprom_params(&adapter->hw); 614 615 tsize = roundup2(adapter->num_tx_desc * sizeof(struct em_tx_desc), 616 EM_DBA_ALIGN); 617 618 /* Allocate Transmit Descriptor ring */ 619 error = em_dma_malloc(adapter, tsize, &adapter->txdma); 620 if (error) { 621 device_printf(dev, "Unable to allocate TxDescriptor memory\n"); 622 goto fail; 623 } 624 adapter->tx_desc_base = (struct em_tx_desc *)adapter->txdma.dma_vaddr; 625 626 rsize = roundup2(adapter->num_rx_desc * sizeof(struct em_rx_desc), 627 EM_DBA_ALIGN); 628 629 /* Allocate Receive Descriptor ring */ 630 error = em_dma_malloc(adapter, rsize, &adapter->rxdma); 631 if (error) { 632 device_printf(dev, "Unable to allocate rx_desc memory\n"); 633 goto fail; 634 } 635 adapter->rx_desc_base = (struct em_rx_desc *)adapter->rxdma.dma_vaddr; 636 637 /* Initialize the hardware */ 638 if (em_hardware_init(adapter)) { 639 device_printf(dev, "Unable to initialize the hardware\n"); 640 error = EIO; 641 goto fail; 642 } 643 644 /* Copy the permanent MAC address out of the EEPROM */ 645 if (em_read_mac_addr(&adapter->hw) < 0) { 646 device_printf(dev, 647 "EEPROM read error while reading MAC address\n"); 648 error = EIO; 649 goto fail; 650 } 651 652 if (!em_is_valid_ether_addr(adapter->hw.mac_addr)) { 653 device_printf(dev, "Invalid MAC address\n"); 654 error = EIO; 655 goto fail; 656 } 657 658 /* Setup OS specific network interface */ 659 em_setup_interface(dev, adapter); 660 661 /* Initialize statistics */ 662 em_clear_hw_cntrs(&adapter->hw); 663 em_update_stats_counters(adapter); 664 adapter->hw.get_link_status = 1; 665 em_update_link_status(adapter); 666 667 /* Indicate SOL/IDER usage */ 668 if (em_check_phy_reset_block(&adapter->hw)) { 669 device_printf(dev, "PHY reset is blocked due to " 670 "SOL/IDER session.\n"); 671 } 672 673 /* Identify 82544 on PCIX */ 674 em_get_bus_info(&adapter->hw); 675 if (adapter->hw.bus_type == em_bus_type_pcix && 676 adapter->hw.mac_type == em_82544) 677 adapter->pcix_82544 = TRUE; 678 else 679 adapter->pcix_82544 = FALSE; 680 681 error = bus_setup_intr(dev, adapter->res_interrupt, INTR_MPSAFE, 682 em_intr, adapter, 683 &adapter->int_handler_tag, ifp->if_serializer); 684 if (error) { 685 device_printf(dev, "Error registering interrupt handler!\n"); 686 ether_ifdetach(ifp); 687 goto fail; 688 } 689 690 ifp->if_cpuid = ithread_cpuid(rman_get_start(adapter->res_interrupt)); 691 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 692 INIT_DEBUGOUT("em_attach: end"); 693 return(0); 694 695 fail: 696 em_detach(dev); 697 return(error); 698 } 699 700 /********************************************************************* 701 * Device removal routine 702 * 703 * The detach entry point is called when the driver is being removed. 704 * This routine stops the adapter and deallocates all the resources 705 * that were allocated for driver operation. 706 * 707 * return 0 on success, positive on failure 708 *********************************************************************/ 709 710 static int 711 em_detach(device_t dev) 712 { 713 struct adapter *adapter = device_get_softc(dev); 714 715 INIT_DEBUGOUT("em_detach: begin"); 716 717 if (device_is_attached(dev)) { 718 struct ifnet *ifp = &adapter->interface_data.ac_if; 719 720 lwkt_serialize_enter(ifp->if_serializer); 721 adapter->in_detach = 1; 722 em_stop(adapter); 723 em_phy_hw_reset(&adapter->hw); 724 bus_teardown_intr(dev, adapter->res_interrupt, 725 adapter->int_handler_tag); 726 lwkt_serialize_exit(ifp->if_serializer); 727 728 ether_ifdetach(ifp); 729 } 730 bus_generic_detach(dev); 731 732 em_free_pci_resources(dev); 733 734 /* Free Transmit Descriptor ring */ 735 if (adapter->tx_desc_base != NULL) { 736 em_dma_free(adapter, &adapter->txdma); 737 adapter->tx_desc_base = NULL; 738 } 739 740 /* Free Receive Descriptor ring */ 741 if (adapter->rx_desc_base != NULL) { 742 em_dma_free(adapter, &adapter->rxdma); 743 adapter->rx_desc_base = NULL; 744 } 745 746 /* Free sysctl tree */ 747 if (adapter->sysctl_tree != NULL) { 748 adapter->sysctl_tree = NULL; 749 sysctl_ctx_free(&adapter->sysctl_ctx); 750 } 751 752 return (0); 753 } 754 755 /********************************************************************* 756 * 757 * Shutdown entry point 758 * 759 **********************************************************************/ 760 761 static int 762 em_shutdown(device_t dev) 763 { 764 struct adapter *adapter = device_get_softc(dev); 765 struct ifnet *ifp = &adapter->interface_data.ac_if; 766 767 lwkt_serialize_enter(ifp->if_serializer); 768 em_stop(adapter); 769 lwkt_serialize_exit(ifp->if_serializer); 770 771 return (0); 772 } 773 774 /* 775 * Suspend/resume device methods. 776 */ 777 static int 778 em_suspend(device_t dev) 779 { 780 struct adapter *adapter = device_get_softc(dev); 781 struct ifnet *ifp = &adapter->interface_data.ac_if; 782 783 lwkt_serialize_enter(ifp->if_serializer); 784 em_stop(adapter); 785 lwkt_serialize_exit(ifp->if_serializer); 786 return (0); 787 } 788 789 static int 790 em_resume(device_t dev) 791 { 792 struct adapter *adapter = device_get_softc(dev); 793 struct ifnet *ifp = &adapter->interface_data.ac_if; 794 795 lwkt_serialize_enter(ifp->if_serializer); 796 ifp->if_flags &= ~IFF_RUNNING; 797 em_init(adapter); 798 if_devstart(ifp); 799 lwkt_serialize_exit(ifp->if_serializer); 800 801 return bus_generic_resume(dev); 802 } 803 804 /********************************************************************* 805 * Transmit entry point 806 * 807 * em_start is called by the stack to initiate a transmit. 808 * The driver will remain in this routine as long as there are 809 * packets to transmit and transmit resources are available. 810 * In case resources are not available stack is notified and 811 * the packet is requeued. 812 **********************************************************************/ 813 814 static void 815 em_start(struct ifnet *ifp) 816 { 817 struct mbuf *m_head; 818 struct adapter *adapter = ifp->if_softc; 819 820 ASSERT_SERIALIZED(ifp->if_serializer); 821 822 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 823 return; 824 if (!adapter->link_active) { 825 ifq_purge(&ifp->if_snd); 826 return; 827 } 828 while (!ifq_is_empty(&ifp->if_snd)) { 829 m_head = ifq_dequeue(&ifp->if_snd, NULL); 830 if (m_head == NULL) 831 break; 832 833 logif(pkt_txqueue); 834 if (em_encap(adapter, m_head)) { 835 ifp->if_flags |= IFF_OACTIVE; 836 ifq_prepend(&ifp->if_snd, m_head); 837 break; 838 } 839 840 /* Send a copy of the frame to the BPF listener */ 841 ETHER_BPF_MTAP(ifp, m_head); 842 843 /* Set timeout in case hardware has problems transmitting. */ 844 ifp->if_timer = EM_TX_TIMEOUT; 845 } 846 } 847 848 /********************************************************************* 849 * Ioctl entry point 850 * 851 * em_ioctl is called when the user wants to configure the 852 * interface. 853 * 854 * return 0 on success, positive on failure 855 **********************************************************************/ 856 857 static int 858 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 859 { 860 int max_frame_size, mask, error = 0, reinit = 0; 861 struct ifreq *ifr = (struct ifreq *) data; 862 struct adapter *adapter = ifp->if_softc; 863 uint16_t eeprom_data = 0; 864 865 ASSERT_SERIALIZED(ifp->if_serializer); 866 867 if (adapter->in_detach) 868 return 0; 869 870 switch (command) { 871 case SIOCSIFMTU: 872 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 873 switch (adapter->hw.mac_type) { 874 case em_82573: 875 /* 876 * 82573 only supports jumbo frames 877 * if ASPM is disabled. 878 */ 879 em_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 880 1, &eeprom_data); 881 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 882 max_frame_size = ETHER_MAX_LEN; 883 break; 884 } 885 /* Allow Jumbo frames */ 886 /* FALLTHROUGH */ 887 case em_82571: 888 case em_82572: 889 case em_ich9lan: 890 case em_80003es2lan: /* Limit Jumbo Frame size */ 891 max_frame_size = 9234; 892 break; 893 case em_ich8lan: 894 /* ICH8 does not support jumbo frames */ 895 max_frame_size = ETHER_MAX_LEN; 896 break; 897 default: 898 max_frame_size = MAX_JUMBO_FRAME_SIZE; 899 break; 900 } 901 if (ifr->ifr_mtu > 902 max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 903 error = EINVAL; 904 } else { 905 ifp->if_mtu = ifr->ifr_mtu; 906 adapter->hw.max_frame_size = 907 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 908 ifp->if_flags &= ~IFF_RUNNING; 909 em_init(adapter); 910 } 911 break; 912 case SIOCSIFFLAGS: 913 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS " 914 "(Set Interface Flags)"); 915 if (ifp->if_flags & IFF_UP) { 916 if (!(ifp->if_flags & IFF_RUNNING)) { 917 em_init(adapter); 918 } else if ((ifp->if_flags ^ adapter->if_flags) & 919 (IFF_PROMISC | IFF_ALLMULTI)) { 920 em_disable_promisc(adapter); 921 em_set_promisc(adapter); 922 } 923 } else { 924 if (ifp->if_flags & IFF_RUNNING) 925 em_stop(adapter); 926 } 927 adapter->if_flags = ifp->if_flags; 928 break; 929 case SIOCADDMULTI: 930 case SIOCDELMULTI: 931 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 932 if (ifp->if_flags & IFF_RUNNING) { 933 em_disable_intr(adapter); 934 em_set_multi(adapter); 935 if (adapter->hw.mac_type == em_82542_rev2_0) 936 em_initialize_receive_unit(adapter); 937 #ifdef DEVICE_POLLING 938 /* Do not enable interrupt if polling(4) is enabled */ 939 if ((ifp->if_flags & IFF_POLLING) == 0) 940 #endif 941 em_enable_intr(adapter); 942 } 943 break; 944 case SIOCSIFMEDIA: 945 /* Check SOL/IDER usage */ 946 if (em_check_phy_reset_block(&adapter->hw)) { 947 if_printf(ifp, "Media change is blocked due to " 948 "SOL/IDER session.\n"); 949 break; 950 } 951 /* FALLTHROUGH */ 952 case SIOCGIFMEDIA: 953 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA " 954 "(Get/Set Interface Media)"); 955 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 956 break; 957 case SIOCSIFCAP: 958 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 959 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 960 if (mask & IFCAP_HWCSUM) { 961 ifp->if_capenable ^= IFCAP_HWCSUM; 962 reinit = 1; 963 } 964 if (mask & IFCAP_VLAN_HWTAGGING) { 965 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 966 reinit = 1; 967 } 968 if (reinit && (ifp->if_flags & IFF_RUNNING)) { 969 ifp->if_flags &= ~IFF_RUNNING; 970 em_init(adapter); 971 } 972 break; 973 default: 974 error = ether_ioctl(ifp, command, data); 975 break; 976 } 977 978 return (error); 979 } 980 981 /********************************************************************* 982 * Watchdog entry point 983 * 984 * This routine is called whenever hardware quits transmitting. 985 * 986 **********************************************************************/ 987 988 static void 989 em_watchdog(struct ifnet *ifp) 990 { 991 struct adapter *adapter = ifp->if_softc; 992 993 /* 994 * If we are in this routine because of pause frames, then 995 * don't reset the hardware. 996 */ 997 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF) { 998 ifp->if_timer = EM_TX_TIMEOUT; 999 return; 1000 } 1001 1002 if (em_check_for_link(&adapter->hw) == 0) 1003 if_printf(ifp, "watchdog timeout -- resetting\n"); 1004 1005 ifp->if_flags &= ~IFF_RUNNING; 1006 em_init(adapter); 1007 1008 adapter->watchdog_timeouts++; 1009 } 1010 1011 /********************************************************************* 1012 * Init entry point 1013 * 1014 * This routine is used in two ways. It is used by the stack as 1015 * init entry point in network interface structure. It is also used 1016 * by the driver as a hw/sw initialization routine to get to a 1017 * consistent state. 1018 * 1019 * return 0 on success, positive on failure 1020 **********************************************************************/ 1021 1022 static void 1023 em_init(void *arg) 1024 { 1025 struct adapter *adapter = arg; 1026 uint32_t pba; 1027 struct ifnet *ifp = &adapter->interface_data.ac_if; 1028 1029 ASSERT_SERIALIZED(ifp->if_serializer); 1030 1031 INIT_DEBUGOUT("em_init: begin"); 1032 1033 if (ifp->if_flags & IFF_RUNNING) 1034 return; 1035 1036 em_stop(adapter); 1037 1038 /* 1039 * Packet Buffer Allocation (PBA) 1040 * Writing PBA sets the receive portion of the buffer 1041 * the remainder is used for the transmit buffer. 1042 * 1043 * Devices before the 82547 had a Packet Buffer of 64K. 1044 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 1045 * After the 82547 the buffer was reduced to 40K. 1046 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 1047 * Note: default does not leave enough room for Jumbo Frame >10k. 1048 */ 1049 switch (adapter->hw.mac_type) { 1050 case em_82547: 1051 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 1052 if (adapter->hw.max_frame_size > EM_RXBUFFER_8192) 1053 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1054 else 1055 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1056 1057 adapter->tx_fifo_head = 0; 1058 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 1059 adapter->tx_fifo_size = 1060 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 1061 break; 1062 /* Total Packet Buffer on these is 48K */ 1063 case em_82571: 1064 case em_82572: 1065 case em_80003es2lan: 1066 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1067 break; 1068 case em_82573: /* 82573: Total Packet Buffer is 32K */ 1069 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1070 break; 1071 case em_ich8lan: 1072 pba = E1000_PBA_8K; 1073 break; 1074 case em_ich9lan: 1075 #define E1000_PBA_10K 0x000A 1076 pba = E1000_PBA_10K; 1077 break; 1078 default: 1079 /* Devices before 82547 had a Packet Buffer of 64K. */ 1080 if(adapter->hw.max_frame_size > EM_RXBUFFER_8192) 1081 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1082 else 1083 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1084 } 1085 1086 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 1087 E1000_WRITE_REG(&adapter->hw, PBA, pba); 1088 1089 /* Get the latest mac address, User can use a LAA */ 1090 bcopy(adapter->interface_data.ac_enaddr, adapter->hw.mac_addr, 1091 ETHER_ADDR_LEN); 1092 1093 /* Initialize the hardware */ 1094 if (em_hardware_init(adapter)) { 1095 if_printf(ifp, "Unable to initialize the hardware\n"); 1096 return; 1097 } 1098 em_update_link_status(adapter); 1099 1100 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1101 em_enable_vlans(adapter); 1102 1103 /* Set hardware offload abilities */ 1104 if (adapter->hw.mac_type >= em_82543) { 1105 if (ifp->if_capenable & IFCAP_TXCSUM) 1106 ifp->if_hwassist = EM_CHECKSUM_FEATURES; 1107 else 1108 ifp->if_hwassist = 0; 1109 } 1110 1111 /* Prepare transmit descriptors and buffers */ 1112 if (em_setup_transmit_structures(adapter)) { 1113 if_printf(ifp, "Could not setup transmit structures\n"); 1114 em_stop(adapter); 1115 return; 1116 } 1117 em_initialize_transmit_unit(adapter); 1118 1119 /* Setup Multicast table */ 1120 em_set_multi(adapter); 1121 1122 /* Prepare receive descriptors and buffers */ 1123 if (em_setup_receive_structures(adapter)) { 1124 if_printf(ifp, "Could not setup receive structures\n"); 1125 em_stop(adapter); 1126 return; 1127 } 1128 em_initialize_receive_unit(adapter); 1129 1130 /* Don't lose promiscuous settings */ 1131 em_set_promisc(adapter); 1132 1133 ifp->if_flags |= IFF_RUNNING; 1134 ifp->if_flags &= ~IFF_OACTIVE; 1135 1136 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1137 em_clear_hw_cntrs(&adapter->hw); 1138 1139 #ifdef DEVICE_POLLING 1140 /* Do not enable interrupt if polling(4) is enabled */ 1141 if (ifp->if_flags & IFF_POLLING) 1142 em_disable_intr(adapter); 1143 else 1144 #endif 1145 em_enable_intr(adapter); 1146 1147 /* Don't reset the phy next time init gets called */ 1148 adapter->hw.phy_reset_disable = TRUE; 1149 } 1150 1151 #ifdef DEVICE_POLLING 1152 1153 static void 1154 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1155 { 1156 struct adapter *adapter = ifp->if_softc; 1157 uint32_t reg_icr; 1158 1159 ASSERT_SERIALIZED(ifp->if_serializer); 1160 1161 switch(cmd) { 1162 case POLL_REGISTER: 1163 em_disable_intr(adapter); 1164 break; 1165 case POLL_DEREGISTER: 1166 em_enable_intr(adapter); 1167 break; 1168 case POLL_AND_CHECK_STATUS: 1169 reg_icr = E1000_READ_REG(&adapter->hw, ICR); 1170 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1171 callout_stop(&adapter->timer); 1172 adapter->hw.get_link_status = 1; 1173 em_check_for_link(&adapter->hw); 1174 em_update_link_status(adapter); 1175 callout_reset(&adapter->timer, hz, em_local_timer, 1176 adapter); 1177 } 1178 /* fall through */ 1179 case POLL_ONLY: 1180 if (ifp->if_flags & IFF_RUNNING) { 1181 em_rxeof(adapter, count); 1182 em_txeof(adapter); 1183 1184 if (!ifq_is_empty(&ifp->if_snd)) 1185 if_devstart(ifp); 1186 } 1187 break; 1188 } 1189 } 1190 1191 #endif /* DEVICE_POLLING */ 1192 1193 /********************************************************************* 1194 * 1195 * Interrupt Service routine 1196 * 1197 *********************************************************************/ 1198 static void 1199 em_intr(void *arg) 1200 { 1201 uint32_t reg_icr; 1202 struct ifnet *ifp; 1203 struct adapter *adapter = arg; 1204 1205 ifp = &adapter->interface_data.ac_if; 1206 1207 logif(intr_beg); 1208 ASSERT_SERIALIZED(ifp->if_serializer); 1209 1210 reg_icr = E1000_READ_REG(&adapter->hw, ICR); 1211 if ((adapter->hw.mac_type >= em_82571 && 1212 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1213 reg_icr == 0) { 1214 logif(intr_end); 1215 return; 1216 } 1217 1218 /* 1219 * XXX: some laptops trigger several spurious interrupts on em(4) 1220 * when in the resume cycle. The ICR register reports all-ones 1221 * value in this case. Processing such interrupts would lead to 1222 * a freeze. I don't know why. 1223 */ 1224 if (reg_icr == 0xffffffff) { 1225 logif(intr_end); 1226 return; 1227 } 1228 1229 /* 1230 * note: do not attempt to improve efficiency by looping. This 1231 * only results in unnecessary piecemeal collection of received 1232 * packets and unnecessary piecemeal cleanups of the transmit ring. 1233 */ 1234 if (ifp->if_flags & IFF_RUNNING) { 1235 em_rxeof(adapter, -1); 1236 em_txeof(adapter); 1237 } 1238 1239 /* Link status change */ 1240 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1241 callout_stop(&adapter->timer); 1242 adapter->hw.get_link_status = 1; 1243 em_check_for_link(&adapter->hw); 1244 em_update_link_status(adapter); 1245 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1246 } 1247 1248 if (reg_icr & E1000_ICR_RXO) 1249 adapter->rx_overruns++; 1250 1251 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1252 if_devstart(ifp); 1253 1254 logif(intr_end); 1255 } 1256 1257 /********************************************************************* 1258 * 1259 * Media Ioctl callback 1260 * 1261 * This routine is called whenever the user queries the status of 1262 * the interface using ifconfig. 1263 * 1264 **********************************************************************/ 1265 static void 1266 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1267 { 1268 struct adapter *adapter = ifp->if_softc; 1269 u_char fiber_type = IFM_1000_SX; 1270 1271 INIT_DEBUGOUT("em_media_status: begin"); 1272 1273 ASSERT_SERIALIZED(ifp->if_serializer); 1274 1275 em_check_for_link(&adapter->hw); 1276 em_update_link_status(adapter); 1277 1278 ifmr->ifm_status = IFM_AVALID; 1279 ifmr->ifm_active = IFM_ETHER; 1280 1281 if (!adapter->link_active) 1282 return; 1283 1284 ifmr->ifm_status |= IFM_ACTIVE; 1285 1286 if (adapter->hw.media_type == em_media_type_fiber || 1287 adapter->hw.media_type == em_media_type_internal_serdes) { 1288 if (adapter->hw.mac_type == em_82545) 1289 fiber_type = IFM_1000_LX; 1290 ifmr->ifm_active |= fiber_type | IFM_FDX; 1291 } else { 1292 switch (adapter->link_speed) { 1293 case 10: 1294 ifmr->ifm_active |= IFM_10_T; 1295 break; 1296 case 100: 1297 ifmr->ifm_active |= IFM_100_TX; 1298 break; 1299 case 1000: 1300 ifmr->ifm_active |= IFM_1000_T; 1301 break; 1302 } 1303 if (adapter->link_duplex == FULL_DUPLEX) 1304 ifmr->ifm_active |= IFM_FDX; 1305 else 1306 ifmr->ifm_active |= IFM_HDX; 1307 } 1308 } 1309 1310 /********************************************************************* 1311 * 1312 * Media Ioctl callback 1313 * 1314 * This routine is called when the user changes speed/duplex using 1315 * media/mediopt option with ifconfig. 1316 * 1317 **********************************************************************/ 1318 static int 1319 em_media_change(struct ifnet *ifp) 1320 { 1321 struct adapter *adapter = ifp->if_softc; 1322 struct ifmedia *ifm = &adapter->media; 1323 1324 INIT_DEBUGOUT("em_media_change: begin"); 1325 1326 ASSERT_SERIALIZED(ifp->if_serializer); 1327 1328 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1329 return (EINVAL); 1330 1331 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1332 case IFM_AUTO: 1333 adapter->hw.autoneg = DO_AUTO_NEG; 1334 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1335 break; 1336 case IFM_1000_LX: 1337 case IFM_1000_SX: 1338 case IFM_1000_T: 1339 adapter->hw.autoneg = DO_AUTO_NEG; 1340 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1341 break; 1342 case IFM_100_TX: 1343 adapter->hw.autoneg = FALSE; 1344 adapter->hw.autoneg_advertised = 0; 1345 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1346 adapter->hw.forced_speed_duplex = em_100_full; 1347 else 1348 adapter->hw.forced_speed_duplex = em_100_half; 1349 break; 1350 case IFM_10_T: 1351 adapter->hw.autoneg = FALSE; 1352 adapter->hw.autoneg_advertised = 0; 1353 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1354 adapter->hw.forced_speed_duplex = em_10_full; 1355 else 1356 adapter->hw.forced_speed_duplex = em_10_half; 1357 break; 1358 default: 1359 if_printf(ifp, "Unsupported media type\n"); 1360 } 1361 /* 1362 * As the speed/duplex settings may have changed we need to 1363 * reset the PHY. 1364 */ 1365 adapter->hw.phy_reset_disable = FALSE; 1366 1367 ifp->if_flags &= ~IFF_RUNNING; 1368 em_init(adapter); 1369 1370 return(0); 1371 } 1372 1373 static void 1374 em_tx_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, 1375 int error) 1376 { 1377 struct em_q *q = arg; 1378 1379 if (error) 1380 return; 1381 KASSERT(nsegs <= EM_MAX_SCATTER, 1382 ("Too many DMA segments returned when mapping tx packet")); 1383 q->nsegs = nsegs; 1384 bcopy(seg, q->segs, nsegs * sizeof(seg[0])); 1385 } 1386 1387 /********************************************************************* 1388 * 1389 * This routine maps the mbufs to tx descriptors. 1390 * 1391 * return 0 on success, positive on failure 1392 **********************************************************************/ 1393 static int 1394 em_encap(struct adapter *adapter, struct mbuf *m_head) 1395 { 1396 uint32_t txd_upper = 0, txd_lower = 0, txd_used = 0, txd_saved = 0; 1397 int i, j, error, last = 0; 1398 1399 struct em_q q; 1400 struct em_buffer *tx_buffer = NULL, *tx_buffer_first; 1401 bus_dmamap_t map; 1402 struct em_tx_desc *current_tx_desc = NULL; 1403 struct ifnet *ifp = &adapter->interface_data.ac_if; 1404 1405 /* 1406 * Force a cleanup if number of TX descriptors 1407 * available hits the threshold 1408 */ 1409 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1410 em_txeof(adapter); 1411 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1412 adapter->no_tx_desc_avail1++; 1413 return (ENOBUFS); 1414 } 1415 } 1416 1417 /* 1418 * Capture the first descriptor index, this descriptor will have 1419 * the index of the EOP which is the only one that now gets a 1420 * DONE bit writeback. 1421 */ 1422 tx_buffer_first = &adapter->tx_buffer_area[adapter->next_avail_tx_desc]; 1423 1424 /* 1425 * Map the packet for DMA. 1426 */ 1427 map = tx_buffer_first->map; 1428 error = bus_dmamap_load_mbuf(adapter->txtag, map, m_head, em_tx_cb, 1429 &q, BUS_DMA_NOWAIT); 1430 if (error != 0) { 1431 adapter->no_tx_dma_setup++; 1432 return (error); 1433 } 1434 KASSERT(q.nsegs != 0, ("em_encap: empty packet")); 1435 1436 if (q.nsegs > (adapter->num_tx_desc_avail - 2)) { 1437 adapter->no_tx_desc_avail2++; 1438 error = ENOBUFS; 1439 goto fail; 1440 } 1441 1442 if (ifp->if_hwassist > 0) { 1443 em_transmit_checksum_setup(adapter, m_head, 1444 &txd_upper, &txd_lower); 1445 } 1446 1447 i = adapter->next_avail_tx_desc; 1448 if (adapter->pcix_82544) 1449 txd_saved = i; 1450 1451 /* Set up our transmit descriptors */ 1452 for (j = 0; j < q.nsegs; j++) { 1453 /* If adapter is 82544 and on PCIX bus */ 1454 if(adapter->pcix_82544) { 1455 DESC_ARRAY desc_array; 1456 uint32_t array_elements, counter; 1457 1458 /* 1459 * Check the Address and Length combination and 1460 * split the data accordingly 1461 */ 1462 array_elements = em_fill_descriptors(q.segs[j].ds_addr, 1463 q.segs[j].ds_len, &desc_array); 1464 for (counter = 0; counter < array_elements; counter++) { 1465 if (txd_used == adapter->num_tx_desc_avail) { 1466 adapter->next_avail_tx_desc = txd_saved; 1467 adapter->no_tx_desc_avail2++; 1468 error = ENOBUFS; 1469 goto fail; 1470 } 1471 tx_buffer = &adapter->tx_buffer_area[i]; 1472 current_tx_desc = &adapter->tx_desc_base[i]; 1473 current_tx_desc->buffer_addr = htole64( 1474 desc_array.descriptor[counter].address); 1475 current_tx_desc->lower.data = htole32( 1476 adapter->txd_cmd | txd_lower | 1477 (uint16_t)desc_array.descriptor[counter].length); 1478 current_tx_desc->upper.data = htole32(txd_upper); 1479 1480 last = i; 1481 if (++i == adapter->num_tx_desc) 1482 i = 0; 1483 1484 tx_buffer->m_head = NULL; 1485 tx_buffer->next_eop = -1; 1486 txd_used++; 1487 } 1488 } else { 1489 tx_buffer = &adapter->tx_buffer_area[i]; 1490 current_tx_desc = &adapter->tx_desc_base[i]; 1491 1492 current_tx_desc->buffer_addr = htole64(q.segs[j].ds_addr); 1493 current_tx_desc->lower.data = htole32( 1494 adapter->txd_cmd | txd_lower | q.segs[j].ds_len); 1495 current_tx_desc->upper.data = htole32(txd_upper); 1496 1497 last = i; 1498 if (++i == adapter->num_tx_desc) 1499 i = 0; 1500 1501 tx_buffer->m_head = NULL; 1502 tx_buffer->next_eop = -1; 1503 } 1504 } 1505 1506 adapter->next_avail_tx_desc = i; 1507 if (adapter->pcix_82544) 1508 adapter->num_tx_desc_avail -= txd_used; 1509 else 1510 adapter->num_tx_desc_avail -= q.nsegs; 1511 1512 /* Find out if we are in vlan mode */ 1513 if (m_head->m_flags & M_VLANTAG) { 1514 /* Set the vlan id */ 1515 current_tx_desc->upper.fields.special = 1516 htole16(m_head->m_pkthdr.ether_vlantag); 1517 1518 /* Tell hardware to add tag */ 1519 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1520 } 1521 1522 tx_buffer->m_head = m_head; 1523 tx_buffer_first->map = tx_buffer->map; 1524 tx_buffer->map = map; 1525 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1526 1527 /* 1528 * Last Descriptor of Packet needs End Of Packet (EOP) 1529 * and Report Status (RS) 1530 */ 1531 current_tx_desc->lower.data |= 1532 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1533 1534 /* 1535 * Keep track in the first buffer which descriptor will be 1536 * written back. 1537 */ 1538 tx_buffer_first->next_eop = last; 1539 1540 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 1541 BUS_DMASYNC_PREWRITE); 1542 1543 /* 1544 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000 1545 * that this frame is available to transmit. 1546 */ 1547 if (adapter->hw.mac_type == em_82547 && 1548 adapter->link_duplex == HALF_DUPLEX) { 1549 em_82547_move_tail_serialized(adapter); 1550 } else { 1551 E1000_WRITE_REG(&adapter->hw, TDT, i); 1552 if (adapter->hw.mac_type == em_82547) { 1553 em_82547_update_fifo_head(adapter, 1554 m_head->m_pkthdr.len); 1555 } 1556 } 1557 1558 return (0); 1559 fail: 1560 bus_dmamap_unload(adapter->txtag, map); 1561 return error; 1562 } 1563 1564 /********************************************************************* 1565 * 1566 * 82547 workaround to avoid controller hang in half-duplex environment. 1567 * The workaround is to avoid queuing a large packet that would span 1568 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1569 * in this case. We do that only when FIFO is quiescent. 1570 * 1571 **********************************************************************/ 1572 static void 1573 em_82547_move_tail(void *arg) 1574 { 1575 struct adapter *adapter = arg; 1576 struct ifnet *ifp = &adapter->interface_data.ac_if; 1577 1578 lwkt_serialize_enter(ifp->if_serializer); 1579 em_82547_move_tail_serialized(adapter); 1580 lwkt_serialize_exit(ifp->if_serializer); 1581 } 1582 1583 static void 1584 em_82547_move_tail_serialized(struct adapter *adapter) 1585 { 1586 uint16_t hw_tdt; 1587 uint16_t sw_tdt; 1588 struct em_tx_desc *tx_desc; 1589 uint16_t length = 0; 1590 boolean_t eop = 0; 1591 1592 hw_tdt = E1000_READ_REG(&adapter->hw, TDT); 1593 sw_tdt = adapter->next_avail_tx_desc; 1594 1595 while (hw_tdt != sw_tdt) { 1596 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1597 length += tx_desc->lower.flags.length; 1598 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1599 if (++hw_tdt == adapter->num_tx_desc) 1600 hw_tdt = 0; 1601 1602 if (eop) { 1603 if (em_82547_fifo_workaround(adapter, length)) { 1604 adapter->tx_fifo_wrk_cnt++; 1605 callout_reset(&adapter->tx_fifo_timer, 1, 1606 em_82547_move_tail, adapter); 1607 break; 1608 } 1609 E1000_WRITE_REG(&adapter->hw, TDT, hw_tdt); 1610 em_82547_update_fifo_head(adapter, length); 1611 length = 0; 1612 } 1613 } 1614 } 1615 1616 static int 1617 em_82547_fifo_workaround(struct adapter *adapter, int len) 1618 { 1619 int fifo_space, fifo_pkt_len; 1620 1621 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1622 1623 if (adapter->link_duplex == HALF_DUPLEX) { 1624 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 1625 1626 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1627 if (em_82547_tx_fifo_reset(adapter)) 1628 return (0); 1629 else 1630 return (1); 1631 } 1632 } 1633 1634 return (0); 1635 } 1636 1637 static void 1638 em_82547_update_fifo_head(struct adapter *adapter, int len) 1639 { 1640 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1641 1642 /* tx_fifo_head is always 16 byte aligned */ 1643 adapter->tx_fifo_head += fifo_pkt_len; 1644 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) 1645 adapter->tx_fifo_head -= adapter->tx_fifo_size; 1646 } 1647 1648 static int 1649 em_82547_tx_fifo_reset(struct adapter *adapter) 1650 { 1651 uint32_t tctl; 1652 1653 if (E1000_READ_REG(&adapter->hw, TDT) == E1000_READ_REG(&adapter->hw, TDH) && 1654 E1000_READ_REG(&adapter->hw, TDFT) == E1000_READ_REG(&adapter->hw, TDFH) && 1655 E1000_READ_REG(&adapter->hw, TDFTS) == E1000_READ_REG(&adapter->hw, TDFHS) && 1656 E1000_READ_REG(&adapter->hw, TDFPC) == 0) { 1657 /* Disable TX unit */ 1658 tctl = E1000_READ_REG(&adapter->hw, TCTL); 1659 E1000_WRITE_REG(&adapter->hw, TCTL, tctl & ~E1000_TCTL_EN); 1660 1661 /* Reset FIFO pointers */ 1662 E1000_WRITE_REG(&adapter->hw, TDFT, adapter->tx_head_addr); 1663 E1000_WRITE_REG(&adapter->hw, TDFH, adapter->tx_head_addr); 1664 E1000_WRITE_REG(&adapter->hw, TDFTS, adapter->tx_head_addr); 1665 E1000_WRITE_REG(&adapter->hw, TDFHS, adapter->tx_head_addr); 1666 1667 /* Re-enable TX unit */ 1668 E1000_WRITE_REG(&adapter->hw, TCTL, tctl); 1669 E1000_WRITE_FLUSH(&adapter->hw); 1670 1671 adapter->tx_fifo_head = 0; 1672 adapter->tx_fifo_reset_cnt++; 1673 1674 return (TRUE); 1675 } else { 1676 return (FALSE); 1677 } 1678 } 1679 1680 static void 1681 em_set_promisc(struct adapter *adapter) 1682 { 1683 uint32_t reg_rctl; 1684 struct ifnet *ifp = &adapter->interface_data.ac_if; 1685 1686 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1687 1688 if (ifp->if_flags & IFF_PROMISC) { 1689 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1690 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1691 } else if (ifp->if_flags & IFF_ALLMULTI) { 1692 reg_rctl |= E1000_RCTL_MPE; 1693 reg_rctl &= ~E1000_RCTL_UPE; 1694 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1695 } 1696 } 1697 1698 static void 1699 em_disable_promisc(struct adapter *adapter) 1700 { 1701 uint32_t reg_rctl; 1702 1703 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1704 1705 reg_rctl &= (~E1000_RCTL_UPE); 1706 reg_rctl &= (~E1000_RCTL_MPE); 1707 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1708 } 1709 1710 /********************************************************************* 1711 * Multicast Update 1712 * 1713 * This routine is called whenever multicast address list is updated. 1714 * 1715 **********************************************************************/ 1716 1717 static void 1718 em_set_multi(struct adapter *adapter) 1719 { 1720 uint32_t reg_rctl = 0; 1721 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1722 struct ifmultiaddr *ifma; 1723 int mcnt = 0; 1724 struct ifnet *ifp = &adapter->interface_data.ac_if; 1725 1726 IOCTL_DEBUGOUT("em_set_multi: begin"); 1727 1728 if (adapter->hw.mac_type == em_82542_rev2_0) { 1729 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1730 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1731 em_pci_clear_mwi(&adapter->hw); 1732 reg_rctl |= E1000_RCTL_RST; 1733 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1734 msec_delay(5); 1735 } 1736 1737 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1738 if (ifma->ifma_addr->sa_family != AF_LINK) 1739 continue; 1740 1741 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1742 break; 1743 1744 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1745 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS); 1746 mcnt++; 1747 } 1748 1749 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1750 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1751 reg_rctl |= E1000_RCTL_MPE; 1752 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1753 } else { 1754 em_mc_addr_list_update(&adapter->hw, mta, mcnt, 0, 1); 1755 } 1756 1757 if (adapter->hw.mac_type == em_82542_rev2_0) { 1758 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1759 reg_rctl &= ~E1000_RCTL_RST; 1760 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1761 msec_delay(5); 1762 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1763 em_pci_set_mwi(&adapter->hw); 1764 } 1765 } 1766 1767 /********************************************************************* 1768 * Timer routine 1769 * 1770 * This routine checks for link status and updates statistics. 1771 * 1772 **********************************************************************/ 1773 1774 static void 1775 em_local_timer(void *arg) 1776 { 1777 struct ifnet *ifp; 1778 struct adapter *adapter = arg; 1779 ifp = &adapter->interface_data.ac_if; 1780 1781 lwkt_serialize_enter(ifp->if_serializer); 1782 1783 em_check_for_link(&adapter->hw); 1784 em_update_link_status(adapter); 1785 em_update_stats_counters(adapter); 1786 if (em_display_debug_stats && ifp->if_flags & IFF_RUNNING) 1787 em_print_hw_stats(adapter); 1788 em_smartspeed(adapter); 1789 1790 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1791 1792 lwkt_serialize_exit(ifp->if_serializer); 1793 } 1794 1795 static void 1796 em_update_link_status(struct adapter *adapter) 1797 { 1798 struct ifnet *ifp; 1799 ifp = &adapter->interface_data.ac_if; 1800 1801 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) { 1802 if (adapter->link_active == 0) { 1803 em_get_speed_and_duplex(&adapter->hw, 1804 &adapter->link_speed, 1805 &adapter->link_duplex); 1806 /* Check if we may set SPEED_MODE bit on PCI-E */ 1807 if (adapter->link_speed == SPEED_1000 && 1808 (adapter->hw.mac_type == em_82571 || 1809 adapter->hw.mac_type == em_82572)) { 1810 int tarc0; 1811 1812 tarc0 = E1000_READ_REG(&adapter->hw, TARC0); 1813 tarc0 |= SPEED_MODE_BIT; 1814 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0); 1815 } 1816 if (bootverbose) { 1817 if_printf(&adapter->interface_data.ac_if, 1818 "Link is up %d Mbps %s\n", 1819 adapter->link_speed, 1820 adapter->link_duplex == FULL_DUPLEX ? 1821 "Full Duplex" : "Half Duplex"); 1822 } 1823 adapter->link_active = 1; 1824 adapter->smartspeed = 0; 1825 ifp->if_baudrate = adapter->link_speed * 1000000; 1826 ifp->if_link_state = LINK_STATE_UP; 1827 if_link_state_change(ifp); 1828 } 1829 } else { 1830 if (adapter->link_active == 1) { 1831 ifp->if_baudrate = 0; 1832 adapter->link_speed = 0; 1833 adapter->link_duplex = 0; 1834 if (bootverbose) { 1835 if_printf(&adapter->interface_data.ac_if, 1836 "Link is Down\n"); 1837 } 1838 adapter->link_active = 0; 1839 ifp->if_link_state = LINK_STATE_DOWN; 1840 if_link_state_change(ifp); 1841 } 1842 } 1843 } 1844 1845 /********************************************************************* 1846 * 1847 * This routine disables all traffic on the adapter by issuing a 1848 * global reset on the MAC and deallocates TX/RX buffers. 1849 * 1850 **********************************************************************/ 1851 1852 static void 1853 em_stop(void *arg) 1854 { 1855 struct ifnet *ifp; 1856 struct adapter * adapter = arg; 1857 ifp = &adapter->interface_data.ac_if; 1858 1859 ASSERT_SERIALIZED(ifp->if_serializer); 1860 1861 INIT_DEBUGOUT("em_stop: begin"); 1862 em_disable_intr(adapter); 1863 em_reset_hw(&adapter->hw); 1864 callout_stop(&adapter->timer); 1865 callout_stop(&adapter->tx_fifo_timer); 1866 em_free_transmit_structures(adapter); 1867 em_free_receive_structures(adapter); 1868 1869 /* Tell the stack that the interface is no longer active */ 1870 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1871 ifp->if_timer = 0; 1872 } 1873 1874 /********************************************************************* 1875 * 1876 * Determine hardware revision. 1877 * 1878 **********************************************************************/ 1879 static void 1880 em_identify_hardware(struct adapter *adapter) 1881 { 1882 device_t dev = adapter->dev; 1883 1884 /* Make sure our PCI config space has the necessary stuff set */ 1885 adapter->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1886 if (!((adapter->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) && 1887 (adapter->hw.pci_cmd_word & PCIM_CMD_MEMEN))) { 1888 device_printf(dev, "Memory Access and/or Bus Master bits " 1889 "were not set!\n"); 1890 adapter->hw.pci_cmd_word |= PCIM_CMD_BUSMASTEREN | 1891 PCIM_CMD_MEMEN; 1892 pci_write_config(dev, PCIR_COMMAND, 1893 adapter->hw.pci_cmd_word, 2); 1894 } 1895 1896 /* Save off the information about this board */ 1897 adapter->hw.vendor_id = pci_get_vendor(dev); 1898 adapter->hw.device_id = pci_get_device(dev); 1899 adapter->hw.revision_id = pci_get_revid(dev); 1900 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev); 1901 adapter->hw.subsystem_id = pci_get_subdevice(dev); 1902 1903 /* Identify the MAC */ 1904 if (em_set_mac_type(&adapter->hw)) 1905 device_printf(dev, "Unknown MAC Type\n"); 1906 1907 if (adapter->hw.mac_type == em_82541 || 1908 adapter->hw.mac_type == em_82541_rev_2 || 1909 adapter->hw.mac_type == em_82547 || 1910 adapter->hw.mac_type == em_82547_rev_2) 1911 adapter->hw.phy_init_script = TRUE; 1912 } 1913 1914 static int 1915 em_allocate_pci_resources(device_t dev) 1916 { 1917 struct adapter *adapter = device_get_softc(dev); 1918 int rid; 1919 1920 rid = PCIR_BAR(0); 1921 adapter->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1922 &rid, RF_ACTIVE); 1923 if (adapter->res_memory == NULL) { 1924 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1925 return ENXIO; 1926 } 1927 adapter->osdep.mem_bus_space_tag = 1928 rman_get_bustag(adapter->res_memory); 1929 adapter->osdep.mem_bus_space_handle = 1930 rman_get_bushandle(adapter->res_memory); 1931 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 1932 1933 if (adapter->hw.mac_type > em_82543) { 1934 /* Figure our where our IO BAR is ? */ 1935 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1936 uint32_t val; 1937 1938 val = pci_read_config(dev, rid, 4); 1939 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1940 adapter->io_rid = rid; 1941 break; 1942 } 1943 rid += 4; 1944 /* check for 64bit BAR */ 1945 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1946 rid += 4; 1947 } 1948 if (rid >= PCIR_CIS) { 1949 device_printf(dev, "Unable to locate IO BAR\n"); 1950 return (ENXIO); 1951 } 1952 1953 adapter->res_ioport = bus_alloc_resource_any(dev, 1954 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1955 if (!(adapter->res_ioport)) { 1956 device_printf(dev, "Unable to allocate bus resource: " 1957 "ioport\n"); 1958 return ENXIO; 1959 } 1960 adapter->hw.io_base = 0; 1961 adapter->osdep.io_bus_space_tag = 1962 rman_get_bustag(adapter->res_ioport); 1963 adapter->osdep.io_bus_space_handle = 1964 rman_get_bushandle(adapter->res_ioport); 1965 } 1966 1967 /* For ICH8 we need to find the flash memory. */ 1968 if ((adapter->hw.mac_type == em_ich8lan) || 1969 (adapter->hw.mac_type == em_ich9lan)) { 1970 rid = EM_FLASH; 1971 adapter->flash_mem = bus_alloc_resource_any(dev, 1972 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1973 if (adapter->flash_mem == NULL) { 1974 device_printf(dev, "Unable to allocate bus resource: " 1975 "flash memory\n"); 1976 return ENXIO; 1977 } 1978 adapter->osdep.flash_bus_space_tag = 1979 rman_get_bustag(adapter->flash_mem); 1980 adapter->osdep.flash_bus_space_handle = 1981 rman_get_bushandle(adapter->flash_mem); 1982 } 1983 1984 rid = 0x0; 1985 adapter->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1986 &rid, RF_SHAREABLE | RF_ACTIVE); 1987 if (adapter->res_interrupt == NULL) { 1988 device_printf(dev, "Unable to allocate bus resource: " 1989 "interrupt\n"); 1990 return ENXIO; 1991 } 1992 1993 adapter->hw.back = &adapter->osdep; 1994 1995 return 0; 1996 } 1997 1998 static void 1999 em_free_pci_resources(device_t dev) 2000 { 2001 struct adapter *adapter = device_get_softc(dev); 2002 2003 if (adapter->res_interrupt != NULL) { 2004 bus_release_resource(dev, SYS_RES_IRQ, 0, 2005 adapter->res_interrupt); 2006 } 2007 if (adapter->res_memory != NULL) { 2008 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2009 adapter->res_memory); 2010 } 2011 2012 if (adapter->res_ioport != NULL) { 2013 bus_release_resource(dev, SYS_RES_IOPORT, adapter->io_rid, 2014 adapter->res_ioport); 2015 } 2016 2017 if (adapter->flash_mem != NULL) { 2018 bus_release_resource(dev, SYS_RES_MEMORY, EM_FLASH, 2019 adapter->flash_mem); 2020 } 2021 } 2022 2023 /********************************************************************* 2024 * 2025 * Initialize the hardware to a configuration as specified by the 2026 * adapter structure. The controller is reset, the EEPROM is 2027 * verified, the MAC address is set, then the shared initialization 2028 * routines are called. 2029 * 2030 **********************************************************************/ 2031 static int 2032 em_hardware_init(struct adapter *adapter) 2033 { 2034 uint16_t rx_buffer_size; 2035 2036 INIT_DEBUGOUT("em_hardware_init: begin"); 2037 /* Issue a global reset */ 2038 em_reset_hw(&adapter->hw); 2039 2040 /* When hardware is reset, fifo_head is also reset */ 2041 adapter->tx_fifo_head = 0; 2042 2043 /* Make sure we have a good EEPROM before we read from it */ 2044 if (em_validate_eeprom_checksum(&adapter->hw) < 0) { 2045 if (em_validate_eeprom_checksum(&adapter->hw) < 0) { 2046 device_printf(adapter->dev, 2047 "The EEPROM Checksum Is Not Valid\n"); 2048 return (EIO); 2049 } 2050 } 2051 2052 if (em_read_part_num(&adapter->hw, &(adapter->part_num)) < 0) { 2053 device_printf(adapter->dev, 2054 "EEPROM read error while reading part number\n"); 2055 return (EIO); 2056 } 2057 2058 /* Set up smart power down as default off on newer adapters. */ 2059 if (!em_smart_pwr_down && 2060 (adapter->hw.mac_type == em_82571 || 2061 adapter->hw.mac_type == em_82572)) { 2062 uint16_t phy_tmp = 0; 2063 2064 /* Speed up time to link by disabling smart power down. */ 2065 em_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT, 2066 &phy_tmp); 2067 phy_tmp &= ~IGP02E1000_PM_SPD; 2068 em_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT, 2069 phy_tmp); 2070 } 2071 2072 /* 2073 * These parameters control the automatic generation (Tx) and 2074 * response (Rx) to Ethernet PAUSE frames. 2075 * - High water mark should allow for at least two frames to be 2076 * received after sending an XOFF. 2077 * - Low water mark works best when it is very near the high water mark. 2078 * This allows the receiver to restart by sending XON when it has 2079 * drained a bit. Here we use an arbitary value of 1500 which will 2080 * restart after one full frame is pulled from the buffer. There 2081 * could be several smaller frames in the buffer and if so they will 2082 * not trigger the XON until their total number reduces the buffer 2083 * by 1500. 2084 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2085 */ 2086 rx_buffer_size = ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff) << 10); 2087 2088 adapter->hw.fc_high_water = 2089 rx_buffer_size - roundup2(adapter->hw.max_frame_size, 1024); 2090 adapter->hw.fc_low_water = adapter->hw.fc_high_water - 1500; 2091 if (adapter->hw.mac_type == em_80003es2lan) 2092 adapter->hw.fc_pause_time = 0xFFFF; 2093 else 2094 adapter->hw.fc_pause_time = 1000; 2095 adapter->hw.fc_send_xon = TRUE; 2096 adapter->hw.fc = E1000_FC_FULL; 2097 2098 if (em_init_hw(&adapter->hw) < 0) { 2099 device_printf(adapter->dev, "Hardware Initialization Failed"); 2100 return (EIO); 2101 } 2102 2103 em_check_for_link(&adapter->hw); 2104 2105 return (0); 2106 } 2107 2108 /********************************************************************* 2109 * 2110 * Setup networking device structure and register an interface. 2111 * 2112 **********************************************************************/ 2113 static void 2114 em_setup_interface(device_t dev, struct adapter *adapter) 2115 { 2116 struct ifnet *ifp; 2117 u_char fiber_type = IFM_1000_SX; /* default type */ 2118 INIT_DEBUGOUT("em_setup_interface: begin"); 2119 2120 ifp = &adapter->interface_data.ac_if; 2121 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2122 ifp->if_mtu = ETHERMTU; 2123 ifp->if_baudrate = 1000000000; 2124 ifp->if_init = em_init; 2125 ifp->if_softc = adapter; 2126 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2127 ifp->if_ioctl = em_ioctl; 2128 ifp->if_start = em_start; 2129 #ifdef DEVICE_POLLING 2130 ifp->if_poll = em_poll; 2131 #endif 2132 ifp->if_watchdog = em_watchdog; 2133 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1); 2134 ifq_set_ready(&ifp->if_snd); 2135 2136 if (adapter->hw.mac_type >= em_82543) 2137 ifp->if_capabilities |= IFCAP_HWCSUM; 2138 2139 ifp->if_capenable = ifp->if_capabilities; 2140 2141 ether_ifattach(ifp, adapter->hw.mac_addr, NULL); 2142 2143 #ifdef PROFILE_SERIALIZER 2144 SYSCTL_ADD_UINT(&adapter->sysctl_ctx, 2145 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, 2146 "serializer_sleep", CTLFLAG_RW, 2147 &ifp->if_serializer->sleep_cnt, 0, NULL); 2148 SYSCTL_ADD_UINT(&adapter->sysctl_ctx, 2149 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, 2150 "serializer_tryfail", CTLFLAG_RW, 2151 &ifp->if_serializer->tryfail_cnt, 0, NULL); 2152 SYSCTL_ADD_UINT(&adapter->sysctl_ctx, 2153 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, 2154 "serializer_enter", CTLFLAG_RW, 2155 &ifp->if_serializer->enter_cnt, 0, NULL); 2156 SYSCTL_ADD_UINT(&adapter->sysctl_ctx, 2157 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, 2158 "serializer_try", CTLFLAG_RW, 2159 &ifp->if_serializer->try_cnt, 0, NULL); 2160 #endif 2161 2162 /* 2163 * Tell the upper layer(s) we support long frames. 2164 */ 2165 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2166 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2167 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2168 2169 /* 2170 * Specify the media types supported by this adapter and register 2171 * callbacks to update media and link information 2172 */ 2173 ifmedia_init(&adapter->media, IFM_IMASK, em_media_change, 2174 em_media_status); 2175 if (adapter->hw.media_type == em_media_type_fiber || 2176 adapter->hw.media_type == em_media_type_internal_serdes) { 2177 if (adapter->hw.mac_type == em_82545) 2178 fiber_type = IFM_1000_LX; 2179 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2180 0, NULL); 2181 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2182 } else { 2183 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2184 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2185 0, NULL); 2186 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2187 0, NULL); 2188 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2189 0, NULL); 2190 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 2191 0, NULL); 2192 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2193 } 2194 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2195 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2196 } 2197 2198 /********************************************************************* 2199 * 2200 * Workaround for SmartSpeed on 82541 and 82547 controllers 2201 * 2202 **********************************************************************/ 2203 static void 2204 em_smartspeed(struct adapter *adapter) 2205 { 2206 uint16_t phy_tmp; 2207 2208 if (adapter->link_active || (adapter->hw.phy_type != em_phy_igp) || 2209 !adapter->hw.autoneg || 2210 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL)) 2211 return; 2212 2213 if (adapter->smartspeed == 0) { 2214 /* 2215 * If Master/Slave config fault is asserted twice, 2216 * we assume back-to-back. 2217 */ 2218 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2219 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2220 return; 2221 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2222 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2223 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2224 if (phy_tmp & CR_1000T_MS_ENABLE) { 2225 phy_tmp &= ~CR_1000T_MS_ENABLE; 2226 em_write_phy_reg(&adapter->hw, 2227 PHY_1000T_CTRL, phy_tmp); 2228 adapter->smartspeed++; 2229 if (adapter->hw.autoneg && 2230 !em_phy_setup_autoneg(&adapter->hw) && 2231 !em_read_phy_reg(&adapter->hw, PHY_CTRL, 2232 &phy_tmp)) { 2233 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2234 MII_CR_RESTART_AUTO_NEG); 2235 em_write_phy_reg(&adapter->hw, 2236 PHY_CTRL, phy_tmp); 2237 } 2238 } 2239 } 2240 return; 2241 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2242 /* If still no link, perhaps using 2/3 pair cable */ 2243 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2244 phy_tmp |= CR_1000T_MS_ENABLE; 2245 em_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2246 if (adapter->hw.autoneg && 2247 !em_phy_setup_autoneg(&adapter->hw) && 2248 !em_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_tmp)) { 2249 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2250 MII_CR_RESTART_AUTO_NEG); 2251 em_write_phy_reg(&adapter->hw, PHY_CTRL, phy_tmp); 2252 } 2253 } 2254 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2255 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2256 adapter->smartspeed = 0; 2257 } 2258 2259 /* 2260 * Manage DMA'able memory. 2261 */ 2262 static void 2263 em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2264 { 2265 if (error) 2266 return; 2267 *(bus_addr_t *)arg = segs->ds_addr; 2268 } 2269 2270 static int 2271 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2272 struct em_dma_alloc *dma) 2273 { 2274 device_t dev = adapter->dev; 2275 int error; 2276 2277 error = bus_dma_tag_create(NULL, /* parent */ 2278 EM_DBA_ALIGN, 0, /* alignment, bounds */ 2279 BUS_SPACE_MAXADDR, /* lowaddr */ 2280 BUS_SPACE_MAXADDR, /* highaddr */ 2281 NULL, NULL, /* filter, filterarg */ 2282 size, /* maxsize */ 2283 1, /* nsegments */ 2284 size, /* maxsegsize */ 2285 0, /* flags */ 2286 &dma->dma_tag); 2287 if (error) { 2288 device_printf(dev, "%s: bus_dma_tag_create failed; error %d\n", 2289 __func__, error); 2290 return error; 2291 } 2292 2293 error = bus_dmamem_alloc(dma->dma_tag, (void**)&dma->dma_vaddr, 2294 BUS_DMA_WAITOK, &dma->dma_map); 2295 if (error) { 2296 device_printf(dev, "%s: bus_dmammem_alloc failed; " 2297 "size %llu, error %d\n", 2298 __func__, (uintmax_t)size, error); 2299 goto fail; 2300 } 2301 2302 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, 2303 dma->dma_vaddr, size, 2304 em_dmamap_cb, &dma->dma_paddr, 2305 BUS_DMA_WAITOK); 2306 if (error) { 2307 device_printf(dev, "%s: bus_dmamap_load failed; error %u\n", 2308 __func__, error); 2309 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2310 goto fail; 2311 } 2312 2313 return 0; 2314 fail: 2315 bus_dma_tag_destroy(dma->dma_tag); 2316 dma->dma_tag = NULL; 2317 return error; 2318 } 2319 2320 static void 2321 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2322 { 2323 if (dma->dma_tag != NULL) { 2324 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2325 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2326 bus_dma_tag_destroy(dma->dma_tag); 2327 dma->dma_tag = NULL; 2328 } 2329 } 2330 2331 /********************************************************************* 2332 * 2333 * Allocate and initialize transmit structures. 2334 * 2335 **********************************************************************/ 2336 static int 2337 em_setup_transmit_structures(struct adapter *adapter) 2338 { 2339 struct em_buffer *tx_buffer; 2340 bus_size_t size; 2341 int error, i; 2342 2343 /* 2344 * Setup DMA descriptor areas. 2345 */ 2346 size = roundup2(adapter->hw.max_frame_size, MCLBYTES); 2347 if (bus_dma_tag_create(NULL, /* parent */ 2348 1, 0, /* alignment, bounds */ 2349 BUS_SPACE_MAXADDR, /* lowaddr */ 2350 BUS_SPACE_MAXADDR, /* highaddr */ 2351 NULL, NULL, /* filter, filterarg */ 2352 size, /* maxsize */ 2353 EM_MAX_SCATTER, /* nsegments */ 2354 size, /* maxsegsize */ 2355 0, /* flags */ 2356 &adapter->txtag)) { 2357 device_printf(adapter->dev, "Unable to allocate TX DMA tag\n"); 2358 return(ENOMEM); 2359 } 2360 2361 adapter->tx_buffer_area = 2362 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc, 2363 M_DEVBUF, M_WAITOK | M_ZERO); 2364 2365 bzero(adapter->tx_desc_base, 2366 sizeof(struct em_tx_desc) * adapter->num_tx_desc); 2367 tx_buffer = adapter->tx_buffer_area; 2368 for (i = 0; i < adapter->num_tx_desc; i++) { 2369 error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map); 2370 if (error) { 2371 device_printf(adapter->dev, 2372 "Unable to create TX DMA map\n"); 2373 goto fail; 2374 } 2375 tx_buffer++; 2376 } 2377 2378 adapter->next_avail_tx_desc = 0; 2379 adapter->next_tx_to_clean = 0; 2380 2381 /* Set number of descriptors available */ 2382 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2383 2384 /* Set checksum context */ 2385 adapter->active_checksum_context = OFFLOAD_NONE; 2386 2387 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2388 BUS_DMASYNC_PREWRITE); 2389 2390 return (0); 2391 fail: 2392 em_free_transmit_structures(adapter); 2393 return (error); 2394 } 2395 2396 /********************************************************************* 2397 * 2398 * Enable transmit unit. 2399 * 2400 **********************************************************************/ 2401 static void 2402 em_initialize_transmit_unit(struct adapter *adapter) 2403 { 2404 uint32_t reg_tctl; 2405 uint32_t reg_tipg = 0; 2406 uint64_t bus_addr; 2407 2408 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2409 2410 /* Setup the Base and Length of the Tx Descriptor Ring */ 2411 bus_addr = adapter->txdma.dma_paddr; 2412 E1000_WRITE_REG(&adapter->hw, TDLEN, 2413 adapter->num_tx_desc * sizeof(struct em_tx_desc)); 2414 E1000_WRITE_REG(&adapter->hw, TDBAH, (uint32_t)(bus_addr >> 32)); 2415 E1000_WRITE_REG(&adapter->hw, TDBAL, (uint32_t)bus_addr); 2416 2417 /* Setup the HW Tx Head and Tail descriptor pointers */ 2418 E1000_WRITE_REG(&adapter->hw, TDT, 0); 2419 E1000_WRITE_REG(&adapter->hw, TDH, 0); 2420 2421 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2422 E1000_READ_REG(&adapter->hw, TDBAL), 2423 E1000_READ_REG(&adapter->hw, TDLEN)); 2424 2425 /* Set the default values for the Tx Inter Packet Gap timer */ 2426 switch (adapter->hw.mac_type) { 2427 case em_82542_rev2_0: 2428 case em_82542_rev2_1: 2429 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2430 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2431 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2432 break; 2433 case em_80003es2lan: 2434 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2435 reg_tipg |= 2436 DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2437 break; 2438 default: 2439 if (adapter->hw.media_type == em_media_type_fiber || 2440 adapter->hw.media_type == em_media_type_internal_serdes) 2441 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2442 else 2443 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2444 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2445 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2446 } 2447 2448 E1000_WRITE_REG(&adapter->hw, TIPG, reg_tipg); 2449 E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay.value); 2450 if (adapter->hw.mac_type >= em_82540) { 2451 E1000_WRITE_REG(&adapter->hw, TADV, 2452 adapter->tx_abs_int_delay.value); 2453 } 2454 2455 /* Program the Transmit Control Register */ 2456 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2457 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2458 if (adapter->hw.mac_type >= em_82571) 2459 reg_tctl |= E1000_TCTL_MULR; 2460 if (adapter->link_duplex == 1) 2461 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2462 else 2463 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2464 2465 /* This write will effectively turn on the transmit unit. */ 2466 E1000_WRITE_REG(&adapter->hw, TCTL, reg_tctl); 2467 2468 /* Setup Transmit Descriptor Base Settings */ 2469 adapter->txd_cmd = E1000_TXD_CMD_IFCS; 2470 2471 if (adapter->tx_int_delay.value > 0) 2472 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2473 } 2474 2475 /********************************************************************* 2476 * 2477 * Free all transmit related data structures. 2478 * 2479 **********************************************************************/ 2480 static void 2481 em_free_transmit_structures(struct adapter *adapter) 2482 { 2483 struct em_buffer *tx_buffer; 2484 int i; 2485 2486 INIT_DEBUGOUT("free_transmit_structures: begin"); 2487 2488 if (adapter->tx_buffer_area != NULL) { 2489 tx_buffer = adapter->tx_buffer_area; 2490 for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) { 2491 if (tx_buffer->m_head != NULL) { 2492 bus_dmamap_unload(adapter->txtag, 2493 tx_buffer->map); 2494 m_freem(tx_buffer->m_head); 2495 } 2496 2497 if (tx_buffer->map != NULL) { 2498 bus_dmamap_destroy(adapter->txtag, tx_buffer->map); 2499 tx_buffer->map = NULL; 2500 } 2501 tx_buffer->m_head = NULL; 2502 } 2503 } 2504 if (adapter->tx_buffer_area != NULL) { 2505 kfree(adapter->tx_buffer_area, M_DEVBUF); 2506 adapter->tx_buffer_area = NULL; 2507 } 2508 if (adapter->txtag != NULL) { 2509 bus_dma_tag_destroy(adapter->txtag); 2510 adapter->txtag = NULL; 2511 } 2512 } 2513 2514 /********************************************************************* 2515 * 2516 * The offload context needs to be set when we transfer the first 2517 * packet of a particular protocol (TCP/UDP). We change the 2518 * context only if the protocol type changes. 2519 * 2520 **********************************************************************/ 2521 static void 2522 em_transmit_checksum_setup(struct adapter *adapter, 2523 struct mbuf *mp, 2524 uint32_t *txd_upper, 2525 uint32_t *txd_lower) 2526 { 2527 struct em_context_desc *TXD; 2528 struct em_buffer *tx_buffer; 2529 int curr_txd; 2530 2531 if (mp->m_pkthdr.csum_flags) { 2532 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 2533 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2534 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2535 if (adapter->active_checksum_context == OFFLOAD_TCP_IP) 2536 return; 2537 else 2538 adapter->active_checksum_context = OFFLOAD_TCP_IP; 2539 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 2540 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2541 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2542 if (adapter->active_checksum_context == OFFLOAD_UDP_IP) 2543 return; 2544 else 2545 adapter->active_checksum_context = OFFLOAD_UDP_IP; 2546 } else { 2547 *txd_upper = 0; 2548 *txd_lower = 0; 2549 return; 2550 } 2551 } else { 2552 *txd_upper = 0; 2553 *txd_lower = 0; 2554 return; 2555 } 2556 2557 /* 2558 * If we reach this point, the checksum offload context 2559 * needs to be reset. 2560 */ 2561 curr_txd = adapter->next_avail_tx_desc; 2562 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 2563 TXD = (struct em_context_desc *) &adapter->tx_desc_base[curr_txd]; 2564 2565 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2566 TXD->lower_setup.ip_fields.ipcso = 2567 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2568 TXD->lower_setup.ip_fields.ipcse = 2569 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2570 2571 TXD->upper_setup.tcp_fields.tucss = 2572 ETHER_HDR_LEN + sizeof(struct ip); 2573 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2574 2575 if (adapter->active_checksum_context == OFFLOAD_TCP_IP) { 2576 TXD->upper_setup.tcp_fields.tucso = 2577 ETHER_HDR_LEN + sizeof(struct ip) + 2578 offsetof(struct tcphdr, th_sum); 2579 } else if (adapter->active_checksum_context == OFFLOAD_UDP_IP) { 2580 TXD->upper_setup.tcp_fields.tucso = 2581 ETHER_HDR_LEN + sizeof(struct ip) + 2582 offsetof(struct udphdr, uh_sum); 2583 } 2584 2585 TXD->tcp_seg_setup.data = htole32(0); 2586 TXD->cmd_and_length = htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT); 2587 2588 tx_buffer->m_head = NULL; 2589 tx_buffer->next_eop = -1; 2590 2591 if (++curr_txd == adapter->num_tx_desc) 2592 curr_txd = 0; 2593 2594 adapter->num_tx_desc_avail--; 2595 adapter->next_avail_tx_desc = curr_txd; 2596 } 2597 2598 /********************************************************************** 2599 * 2600 * Examine each tx_buffer in the used queue. If the hardware is done 2601 * processing the packet then free associated resources. The 2602 * tx_buffer is put back on the free queue. 2603 * 2604 **********************************************************************/ 2605 2606 static void 2607 em_txeof(struct adapter *adapter) 2608 { 2609 int first, last, done, num_avail; 2610 struct em_buffer *tx_buffer; 2611 struct em_tx_desc *tx_desc, *eop_desc; 2612 struct ifnet *ifp = &adapter->interface_data.ac_if; 2613 2614 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2615 return; 2616 2617 num_avail = adapter->num_tx_desc_avail; 2618 first = adapter->next_tx_to_clean; 2619 tx_desc = &adapter->tx_desc_base[first]; 2620 tx_buffer = &adapter->tx_buffer_area[first]; 2621 last = tx_buffer->next_eop; 2622 KKASSERT(last >= 0 && last < adapter->num_tx_desc); 2623 eop_desc = &adapter->tx_desc_base[last]; 2624 2625 /* 2626 * Now caculate the terminating index for the cleanup loop below 2627 */ 2628 if (++last == adapter->num_tx_desc) 2629 last = 0; 2630 done = last; 2631 2632 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2633 BUS_DMASYNC_POSTREAD); 2634 2635 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2636 while (first != done) { 2637 tx_desc->upper.data = 0; 2638 tx_desc->lower.data = 0; 2639 num_avail++; 2640 2641 logif(pkt_txclean); 2642 2643 if (tx_buffer->m_head) { 2644 ifp->if_opackets++; 2645 bus_dmamap_sync(adapter->txtag, tx_buffer->map, 2646 BUS_DMASYNC_POSTWRITE); 2647 bus_dmamap_unload(adapter->txtag, 2648 tx_buffer->map); 2649 2650 m_freem(tx_buffer->m_head); 2651 tx_buffer->m_head = NULL; 2652 } 2653 tx_buffer->next_eop = -1; 2654 2655 if (++first == adapter->num_tx_desc) 2656 first = 0; 2657 2658 tx_buffer = &adapter->tx_buffer_area[first]; 2659 tx_desc = &adapter->tx_desc_base[first]; 2660 } 2661 /* See if we can continue to the next packet */ 2662 last = tx_buffer->next_eop; 2663 if (last != -1) { 2664 KKASSERT(last >= 0 && last < adapter->num_tx_desc); 2665 eop_desc = &adapter->tx_desc_base[last]; 2666 if (++last == adapter->num_tx_desc) 2667 last = 0; 2668 done = last; 2669 } else { 2670 break; 2671 } 2672 } 2673 2674 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2675 BUS_DMASYNC_PREWRITE); 2676 2677 adapter->next_tx_to_clean = first; 2678 2679 /* 2680 * If we have enough room, clear IFF_OACTIVE to tell the stack 2681 * that it is OK to send packets. 2682 * If there are no pending descriptors, clear the timeout. Otherwise, 2683 * if some descriptors have been freed, restart the timeout. 2684 */ 2685 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 2686 ifp->if_flags &= ~IFF_OACTIVE; 2687 if (num_avail == adapter->num_tx_desc) 2688 ifp->if_timer = 0; 2689 else if (num_avail == adapter->num_tx_desc_avail) 2690 ifp->if_timer = EM_TX_TIMEOUT; 2691 } 2692 adapter->num_tx_desc_avail = num_avail; 2693 } 2694 2695 /********************************************************************* 2696 * 2697 * Get a buffer from system mbuf buffer pool. 2698 * 2699 **********************************************************************/ 2700 static int 2701 em_get_buf(int i, struct adapter *adapter, struct mbuf *nmp, int how) 2702 { 2703 struct mbuf *mp = nmp; 2704 struct em_buffer *rx_buffer; 2705 struct ifnet *ifp; 2706 bus_addr_t paddr; 2707 int error; 2708 2709 ifp = &adapter->interface_data.ac_if; 2710 2711 if (mp == NULL) { 2712 mp = m_getcl(how, MT_DATA, M_PKTHDR); 2713 if (mp == NULL) { 2714 adapter->mbuf_cluster_failed++; 2715 return (ENOBUFS); 2716 } 2717 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2718 } else { 2719 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2720 mp->m_data = mp->m_ext.ext_buf; 2721 mp->m_next = NULL; 2722 } 2723 2724 if (ifp->if_mtu <= ETHERMTU) 2725 m_adj(mp, ETHER_ALIGN); 2726 2727 rx_buffer = &adapter->rx_buffer_area[i]; 2728 2729 /* 2730 * Using memory from the mbuf cluster pool, invoke the 2731 * bus_dma machinery to arrange the memory mapping. 2732 */ 2733 error = bus_dmamap_load(adapter->rxtag, rx_buffer->map, 2734 mtod(mp, void *), mp->m_len, 2735 em_dmamap_cb, &paddr, 0); 2736 if (error) { 2737 m_freem(mp); 2738 return (error); 2739 } 2740 rx_buffer->m_head = mp; 2741 adapter->rx_desc_base[i].buffer_addr = htole64(paddr); 2742 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 2743 2744 return (0); 2745 } 2746 2747 /********************************************************************* 2748 * 2749 * Allocate memory for rx_buffer structures. Since we use one 2750 * rx_buffer per received packet, the maximum number of rx_buffer's 2751 * that we'll need is equal to the number of receive descriptors 2752 * that we've allocated. 2753 * 2754 **********************************************************************/ 2755 static int 2756 em_allocate_receive_structures(struct adapter *adapter) 2757 { 2758 int i, error, size; 2759 struct em_buffer *rx_buffer; 2760 2761 size = adapter->num_rx_desc * sizeof(struct em_buffer); 2762 adapter->rx_buffer_area = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 2763 2764 error = bus_dma_tag_create(NULL, /* parent */ 2765 1, 0, /* alignment, bounds */ 2766 BUS_SPACE_MAXADDR, /* lowaddr */ 2767 BUS_SPACE_MAXADDR, /* highaddr */ 2768 NULL, NULL, /* filter, filterarg */ 2769 MCLBYTES, /* maxsize */ 2770 1, /* nsegments */ 2771 MCLBYTES, /* maxsegsize */ 2772 0, /* flags */ 2773 &adapter->rxtag); 2774 if (error) { 2775 device_printf(adapter->dev, "%s: bus_dma_tag_create failed; " 2776 "error %u\n", __func__, error); 2777 goto fail; 2778 } 2779 2780 rx_buffer = adapter->rx_buffer_area; 2781 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 2782 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 2783 &rx_buffer->map); 2784 if (error) { 2785 device_printf(adapter->dev, 2786 "%s: bus_dmamap_create failed; " 2787 "error %u\n", __func__, error); 2788 goto fail; 2789 } 2790 } 2791 2792 for (i = 0; i < adapter->num_rx_desc; i++) { 2793 error = em_get_buf(i, adapter, NULL, MB_DONTWAIT); 2794 if (error) 2795 goto fail; 2796 } 2797 2798 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 2799 BUS_DMASYNC_PREWRITE); 2800 2801 return (0); 2802 fail: 2803 em_free_receive_structures(adapter); 2804 return (error); 2805 } 2806 2807 /********************************************************************* 2808 * 2809 * Allocate and initialize receive structures. 2810 * 2811 **********************************************************************/ 2812 static int 2813 em_setup_receive_structures(struct adapter *adapter) 2814 { 2815 int error; 2816 2817 bzero(adapter->rx_desc_base, 2818 sizeof(struct em_rx_desc) * adapter->num_rx_desc); 2819 2820 error = em_allocate_receive_structures(adapter); 2821 if (error) 2822 return (error); 2823 2824 /* Setup our descriptor pointers */ 2825 adapter->next_rx_desc_to_check = 0; 2826 2827 return (0); 2828 } 2829 2830 /********************************************************************* 2831 * 2832 * Enable receive unit. 2833 * 2834 **********************************************************************/ 2835 static void 2836 em_initialize_receive_unit(struct adapter *adapter) 2837 { 2838 uint32_t reg_rctl; 2839 uint32_t reg_rxcsum; 2840 struct ifnet *ifp; 2841 uint64_t bus_addr; 2842 2843 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2844 2845 ifp = &adapter->interface_data.ac_if; 2846 2847 /* 2848 * Make sure receives are disabled while setting 2849 * up the descriptor ring 2850 */ 2851 E1000_WRITE_REG(&adapter->hw, RCTL, 0); 2852 2853 /* Set the Receive Delay Timer Register */ 2854 E1000_WRITE_REG(&adapter->hw, RDTR, 2855 adapter->rx_int_delay.value | E1000_RDT_FPDB); 2856 2857 if(adapter->hw.mac_type >= em_82540) { 2858 E1000_WRITE_REG(&adapter->hw, RADV, 2859 adapter->rx_abs_int_delay.value); 2860 2861 /* Set the interrupt throttling rate in 256ns increments */ 2862 if (em_int_throttle_ceil) { 2863 E1000_WRITE_REG(&adapter->hw, ITR, 2864 1000000000 / 256 / em_int_throttle_ceil); 2865 } else { 2866 E1000_WRITE_REG(&adapter->hw, ITR, 0); 2867 } 2868 } 2869 2870 /* Setup the Base and Length of the Rx Descriptor Ring */ 2871 bus_addr = adapter->rxdma.dma_paddr; 2872 E1000_WRITE_REG(&adapter->hw, RDLEN, adapter->num_rx_desc * 2873 sizeof(struct em_rx_desc)); 2874 E1000_WRITE_REG(&adapter->hw, RDBAH, (uint32_t)(bus_addr >> 32)); 2875 E1000_WRITE_REG(&adapter->hw, RDBAL, (uint32_t)bus_addr); 2876 2877 /* Setup the Receive Control Register */ 2878 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2879 E1000_RCTL_RDMTS_HALF | 2880 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2881 2882 if (adapter->hw.tbi_compatibility_on == TRUE) 2883 reg_rctl |= E1000_RCTL_SBP; 2884 2885 switch (adapter->rx_buffer_len) { 2886 default: 2887 case EM_RXBUFFER_2048: 2888 reg_rctl |= E1000_RCTL_SZ_2048; 2889 break; 2890 case EM_RXBUFFER_4096: 2891 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | 2892 E1000_RCTL_LPE; 2893 break; 2894 case EM_RXBUFFER_8192: 2895 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | 2896 E1000_RCTL_LPE; 2897 break; 2898 case EM_RXBUFFER_16384: 2899 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | 2900 E1000_RCTL_LPE; 2901 break; 2902 } 2903 2904 if (ifp->if_mtu > ETHERMTU) 2905 reg_rctl |= E1000_RCTL_LPE; 2906 2907 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2908 if ((adapter->hw.mac_type >= em_82543) && 2909 (ifp->if_capenable & IFCAP_RXCSUM)) { 2910 reg_rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM); 2911 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2912 E1000_WRITE_REG(&adapter->hw, RXCSUM, reg_rxcsum); 2913 } 2914 2915 #ifdef EM_X60_WORKAROUND 2916 if (adapter->hw.mac_type == em_82573) 2917 E1000_WRITE_REG(&adapter->hw, RDTR, 32); 2918 #endif 2919 2920 /* Enable Receives */ 2921 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 2922 2923 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2924 E1000_WRITE_REG(&adapter->hw, RDH, 0); 2925 E1000_WRITE_REG(&adapter->hw, RDT, adapter->num_rx_desc - 1); 2926 } 2927 2928 /********************************************************************* 2929 * 2930 * Free receive related data structures. 2931 * 2932 **********************************************************************/ 2933 static void 2934 em_free_receive_structures(struct adapter *adapter) 2935 { 2936 struct em_buffer *rx_buffer; 2937 int i; 2938 2939 INIT_DEBUGOUT("free_receive_structures: begin"); 2940 2941 if (adapter->rx_buffer_area != NULL) { 2942 rx_buffer = adapter->rx_buffer_area; 2943 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 2944 if (rx_buffer->m_head != NULL) { 2945 bus_dmamap_unload(adapter->rxtag, 2946 rx_buffer->map); 2947 m_freem(rx_buffer->m_head); 2948 rx_buffer->m_head = NULL; 2949 } 2950 if (rx_buffer->map != NULL) { 2951 bus_dmamap_destroy(adapter->rxtag, 2952 rx_buffer->map); 2953 rx_buffer->map = NULL; 2954 } 2955 } 2956 } 2957 if (adapter->rx_buffer_area != NULL) { 2958 kfree(adapter->rx_buffer_area, M_DEVBUF); 2959 adapter->rx_buffer_area = NULL; 2960 } 2961 if (adapter->rxtag != NULL) { 2962 bus_dma_tag_destroy(adapter->rxtag); 2963 adapter->rxtag = NULL; 2964 } 2965 } 2966 2967 /********************************************************************* 2968 * 2969 * This routine executes in interrupt context. It replenishes 2970 * the mbufs in the descriptor and sends data which has been 2971 * dma'ed into host memory to upper layer. 2972 * 2973 * We loop at most count times if count is > 0, or until done if 2974 * count < 0. 2975 * 2976 *********************************************************************/ 2977 static void 2978 em_rxeof(struct adapter *adapter, int count) 2979 { 2980 struct ifnet *ifp; 2981 struct mbuf *mp; 2982 uint8_t accept_frame = 0; 2983 uint8_t eop = 0; 2984 uint16_t len, desc_len, prev_len_adj; 2985 int i; 2986 struct mbuf_chain chain[MAXCPU]; 2987 2988 /* Pointer to the receive descriptor being examined. */ 2989 struct em_rx_desc *current_desc; 2990 2991 ifp = &adapter->interface_data.ac_if; 2992 i = adapter->next_rx_desc_to_check; 2993 current_desc = &adapter->rx_desc_base[i]; 2994 2995 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 2996 BUS_DMASYNC_POSTREAD); 2997 2998 if (!(current_desc->status & E1000_RXD_STAT_DD)) 2999 return; 3000 3001 ether_input_chain_init(chain); 3002 3003 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) { 3004 logif(pkt_receive); 3005 mp = adapter->rx_buffer_area[i].m_head; 3006 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3007 BUS_DMASYNC_POSTREAD); 3008 bus_dmamap_unload(adapter->rxtag, 3009 adapter->rx_buffer_area[i].map); 3010 3011 accept_frame = 1; 3012 prev_len_adj = 0; 3013 desc_len = le16toh(current_desc->length); 3014 if (current_desc->status & E1000_RXD_STAT_EOP) { 3015 count--; 3016 eop = 1; 3017 if (desc_len < ETHER_CRC_LEN) { 3018 len = 0; 3019 prev_len_adj = ETHER_CRC_LEN - desc_len; 3020 } else { 3021 len = desc_len - ETHER_CRC_LEN; 3022 } 3023 } else { 3024 eop = 0; 3025 len = desc_len; 3026 } 3027 3028 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3029 uint8_t last_byte; 3030 uint32_t pkt_len = desc_len; 3031 3032 if (adapter->fmp != NULL) 3033 pkt_len += adapter->fmp->m_pkthdr.len; 3034 3035 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3036 3037 if (TBI_ACCEPT(&adapter->hw, current_desc->status, 3038 current_desc->errors, 3039 pkt_len, last_byte)) { 3040 em_tbi_adjust_stats(&adapter->hw, 3041 &adapter->stats, 3042 pkt_len, 3043 adapter->hw.mac_addr); 3044 if (len > 0) 3045 len--; 3046 } else { 3047 accept_frame = 0; 3048 } 3049 } 3050 3051 if (accept_frame) { 3052 if (em_get_buf(i, adapter, NULL, MB_DONTWAIT) == ENOBUFS) { 3053 adapter->dropped_pkts++; 3054 em_get_buf(i, adapter, mp, MB_DONTWAIT); 3055 if (adapter->fmp != NULL) 3056 m_freem(adapter->fmp); 3057 adapter->fmp = NULL; 3058 adapter->lmp = NULL; 3059 goto skip; 3060 } 3061 3062 /* Assign correct length to the current fragment */ 3063 mp->m_len = len; 3064 3065 if (adapter->fmp == NULL) { 3066 mp->m_pkthdr.len = len; 3067 adapter->fmp = mp; /* Store the first mbuf */ 3068 adapter->lmp = mp; 3069 } else { 3070 /* Chain mbuf's together */ 3071 /* 3072 * Adjust length of previous mbuf in chain if 3073 * we received less than 4 bytes in the last 3074 * descriptor. 3075 */ 3076 if (prev_len_adj > 0) { 3077 adapter->lmp->m_len -= prev_len_adj; 3078 adapter->fmp->m_pkthdr.len -= prev_len_adj; 3079 } 3080 adapter->lmp->m_next = mp; 3081 adapter->lmp = adapter->lmp->m_next; 3082 adapter->fmp->m_pkthdr.len += len; 3083 } 3084 3085 if (eop) { 3086 adapter->fmp->m_pkthdr.rcvif = ifp; 3087 ifp->if_ipackets++; 3088 3089 em_receive_checksum(adapter, current_desc, 3090 adapter->fmp); 3091 if (current_desc->status & E1000_RXD_STAT_VP) { 3092 adapter->fmp->m_flags |= M_VLANTAG; 3093 adapter->fmp->m_pkthdr.ether_vlantag = 3094 (current_desc->special & 3095 E1000_RXD_SPC_VLAN_MASK); 3096 } 3097 ether_input_chain(ifp, adapter->fmp, chain); 3098 adapter->fmp = NULL; 3099 adapter->lmp = NULL; 3100 } 3101 } else { 3102 adapter->dropped_pkts++; 3103 em_get_buf(i, adapter, mp, MB_DONTWAIT); 3104 if (adapter->fmp != NULL) 3105 m_freem(adapter->fmp); 3106 adapter->fmp = NULL; 3107 adapter->lmp = NULL; 3108 } 3109 3110 skip: 3111 /* Zero out the receive descriptors status. */ 3112 current_desc->status = 0; 3113 3114 /* Advance our pointers to the next descriptor. */ 3115 if (++i == adapter->num_rx_desc) { 3116 i = 0; 3117 current_desc = adapter->rx_desc_base; 3118 } else { 3119 current_desc++; 3120 } 3121 } 3122 3123 ether_input_dispatch(chain); 3124 3125 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 3126 BUS_DMASYNC_PREWRITE); 3127 3128 adapter->next_rx_desc_to_check = i; 3129 3130 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3131 if (--i < 0) 3132 i = adapter->num_rx_desc - 1; 3133 3134 E1000_WRITE_REG(&adapter->hw, RDT, i); 3135 } 3136 3137 /********************************************************************* 3138 * 3139 * Verify that the hardware indicated that the checksum is valid. 3140 * Inform the stack about the status of checksum so that stack 3141 * doesn't spend time verifying the checksum. 3142 * 3143 *********************************************************************/ 3144 static void 3145 em_receive_checksum(struct adapter *adapter, 3146 struct em_rx_desc *rx_desc, 3147 struct mbuf *mp) 3148 { 3149 /* 82543 or newer only */ 3150 if ((adapter->hw.mac_type < em_82543) || 3151 /* Ignore Checksum bit is set */ 3152 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 3153 mp->m_pkthdr.csum_flags = 0; 3154 return; 3155 } 3156 3157 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 3158 /* Did it pass? */ 3159 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3160 /* IP Checksum Good */ 3161 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3162 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3163 } else { 3164 mp->m_pkthdr.csum_flags = 0; 3165 } 3166 } 3167 3168 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 3169 /* Did it pass? */ 3170 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3171 mp->m_pkthdr.csum_flags |= 3172 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR | 3173 CSUM_FRAG_NOT_CHECKED); 3174 mp->m_pkthdr.csum_data = htons(0xffff); 3175 } 3176 } 3177 } 3178 3179 3180 static void 3181 em_enable_vlans(struct adapter *adapter) 3182 { 3183 uint32_t ctrl; 3184 3185 E1000_WRITE_REG(&adapter->hw, VET, ETHERTYPE_VLAN); 3186 3187 ctrl = E1000_READ_REG(&adapter->hw, CTRL); 3188 ctrl |= E1000_CTRL_VME; 3189 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 3190 } 3191 3192 static void 3193 em_disable_vlans(struct adapter *adapter) 3194 { 3195 uint32_t ctrl; 3196 3197 ctrl = E1000_READ_REG(&adapter->hw, CTRL); 3198 ctrl &= ~E1000_CTRL_VME; 3199 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 3200 } 3201 3202 /* 3203 * note: we must call bus_enable_intr() prior to enabling the hardware 3204 * interrupt and bus_disable_intr() after disabling the hardware interrupt 3205 * in order to avoid handler execution races from scheduled interrupt 3206 * threads. 3207 */ 3208 static void 3209 em_enable_intr(struct adapter *adapter) 3210 { 3211 struct ifnet *ifp = &adapter->interface_data.ac_if; 3212 3213 if ((ifp->if_flags & IFF_POLLING) == 0) { 3214 lwkt_serialize_handler_enable(ifp->if_serializer); 3215 E1000_WRITE_REG(&adapter->hw, IMS, (IMS_ENABLE_MASK)); 3216 } 3217 } 3218 3219 static void 3220 em_disable_intr(struct adapter *adapter) 3221 { 3222 /* 3223 * The first version of 82542 had an errata where when link was forced 3224 * it would stay up even up even if the cable was disconnected. 3225 * Sequence errors were used to detect the disconnect and then the 3226 * driver would unforce the link. This code in the in the ISR. For 3227 * this to work correctly the Sequence error interrupt had to be 3228 * enabled all the time. 3229 */ 3230 if (adapter->hw.mac_type == em_82542_rev2_0) { 3231 E1000_WRITE_REG(&adapter->hw, IMC, 3232 (0xffffffff & ~E1000_IMC_RXSEQ)); 3233 } else { 3234 E1000_WRITE_REG(&adapter->hw, IMC, 0xffffffff); 3235 } 3236 3237 lwkt_serialize_handler_disable(adapter->interface_data.ac_if.if_serializer); 3238 } 3239 3240 static int 3241 em_is_valid_ether_addr(uint8_t *addr) 3242 { 3243 static const char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3244 3245 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3246 return (FALSE); 3247 else 3248 return (TRUE); 3249 } 3250 3251 void 3252 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3253 { 3254 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2); 3255 } 3256 3257 void 3258 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3259 { 3260 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2); 3261 } 3262 3263 void 3264 em_pci_set_mwi(struct em_hw *hw) 3265 { 3266 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3267 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 3268 } 3269 3270 void 3271 em_pci_clear_mwi(struct em_hw *hw) 3272 { 3273 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3274 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 3275 } 3276 3277 uint32_t 3278 em_io_read(struct em_hw *hw, unsigned long port) 3279 { 3280 struct em_osdep *io = hw->back; 3281 3282 return bus_space_read_4(io->io_bus_space_tag, 3283 io->io_bus_space_handle, port); 3284 } 3285 3286 void 3287 em_io_write(struct em_hw *hw, unsigned long port, uint32_t value) 3288 { 3289 struct em_osdep *io = hw->back; 3290 3291 bus_space_write_4(io->io_bus_space_tag, 3292 io->io_bus_space_handle, port, value); 3293 } 3294 3295 /* 3296 * We may eventually really do this, but its unnecessary 3297 * for now so we just return unsupported. 3298 */ 3299 int32_t 3300 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3301 { 3302 return (0); 3303 } 3304 3305 3306 /********************************************************************* 3307 * 82544 Coexistence issue workaround. 3308 * There are 2 issues. 3309 * 1. Transmit Hang issue. 3310 * To detect this issue, following equation can be used... 3311 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3312 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3313 * 3314 * 2. DAC issue. 3315 * To detect this issue, following equation can be used... 3316 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3317 * If SUM[3:0] is in between 9 to c, we will have this issue. 3318 * 3319 * 3320 * WORKAROUND: 3321 * Make sure we do not have ending address as 1,2,3,4(Hang) or 3322 * 9,a,b,c (DAC) 3323 * 3324 *************************************************************************/ 3325 static uint32_t 3326 em_fill_descriptors(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array) 3327 { 3328 /* Since issue is sensitive to length and address.*/ 3329 /* Let us first check the address...*/ 3330 uint32_t safe_terminator; 3331 if (length <= 4) { 3332 desc_array->descriptor[0].address = address; 3333 desc_array->descriptor[0].length = length; 3334 desc_array->elements = 1; 3335 return (desc_array->elements); 3336 } 3337 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3338 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3339 if (safe_terminator == 0 || 3340 (safe_terminator > 4 && safe_terminator < 9) || 3341 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 3342 desc_array->descriptor[0].address = address; 3343 desc_array->descriptor[0].length = length; 3344 desc_array->elements = 1; 3345 return (desc_array->elements); 3346 } 3347 3348 desc_array->descriptor[0].address = address; 3349 desc_array->descriptor[0].length = length - 4; 3350 desc_array->descriptor[1].address = address + (length - 4); 3351 desc_array->descriptor[1].length = 4; 3352 desc_array->elements = 2; 3353 return (desc_array->elements); 3354 } 3355 3356 /********************************************************************** 3357 * 3358 * Update the board statistics counters. 3359 * 3360 **********************************************************************/ 3361 static void 3362 em_update_stats_counters(struct adapter *adapter) 3363 { 3364 struct ifnet *ifp; 3365 3366 if (adapter->hw.media_type == em_media_type_copper || 3367 (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) { 3368 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, SYMERRS); 3369 adapter->stats.sec += E1000_READ_REG(&adapter->hw, SEC); 3370 } 3371 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, CRCERRS); 3372 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, MPC); 3373 adapter->stats.scc += E1000_READ_REG(&adapter->hw, SCC); 3374 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, ECOL); 3375 3376 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, MCC); 3377 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, LATECOL); 3378 adapter->stats.colc += E1000_READ_REG(&adapter->hw, COLC); 3379 adapter->stats.dc += E1000_READ_REG(&adapter->hw, DC); 3380 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, RLEC); 3381 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, XONRXC); 3382 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, XONTXC); 3383 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, XOFFRXC); 3384 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, XOFFTXC); 3385 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, FCRUC); 3386 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, PRC64); 3387 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, PRC127); 3388 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, PRC255); 3389 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, PRC511); 3390 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, PRC1023); 3391 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, PRC1522); 3392 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, GPRC); 3393 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, BPRC); 3394 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, MPRC); 3395 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, GPTC); 3396 3397 /* For the 64-bit byte counters the low dword must be read first. */ 3398 /* Both registers clear on the read of the high dword */ 3399 3400 adapter->stats.gorcl += E1000_READ_REG(&adapter->hw, GORCL); 3401 adapter->stats.gorch += E1000_READ_REG(&adapter->hw, GORCH); 3402 adapter->stats.gotcl += E1000_READ_REG(&adapter->hw, GOTCL); 3403 adapter->stats.gotch += E1000_READ_REG(&adapter->hw, GOTCH); 3404 3405 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, RNBC); 3406 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, RUC); 3407 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, RFC); 3408 adapter->stats.roc += E1000_READ_REG(&adapter->hw, ROC); 3409 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, RJC); 3410 3411 adapter->stats.torl += E1000_READ_REG(&adapter->hw, TORL); 3412 adapter->stats.torh += E1000_READ_REG(&adapter->hw, TORH); 3413 adapter->stats.totl += E1000_READ_REG(&adapter->hw, TOTL); 3414 adapter->stats.toth += E1000_READ_REG(&adapter->hw, TOTH); 3415 3416 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, TPR); 3417 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, TPT); 3418 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, PTC64); 3419 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, PTC127); 3420 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, PTC255); 3421 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, PTC511); 3422 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, PTC1023); 3423 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, PTC1522); 3424 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, MPTC); 3425 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, BPTC); 3426 3427 if (adapter->hw.mac_type >= em_82543) { 3428 adapter->stats.algnerrc += 3429 E1000_READ_REG(&adapter->hw, ALGNERRC); 3430 adapter->stats.rxerrc += 3431 E1000_READ_REG(&adapter->hw, RXERRC); 3432 adapter->stats.tncrs += 3433 E1000_READ_REG(&adapter->hw, TNCRS); 3434 adapter->stats.cexterr += 3435 E1000_READ_REG(&adapter->hw, CEXTERR); 3436 adapter->stats.tsctc += 3437 E1000_READ_REG(&adapter->hw, TSCTC); 3438 adapter->stats.tsctfc += 3439 E1000_READ_REG(&adapter->hw, TSCTFC); 3440 } 3441 ifp = &adapter->interface_data.ac_if; 3442 3443 /* Fill out the OS statistics structure */ 3444 ifp->if_collisions = adapter->stats.colc; 3445 3446 /* Rx Errors */ 3447 ifp->if_ierrors = 3448 adapter->dropped_pkts + 3449 adapter->stats.rxerrc + 3450 adapter->stats.crcerrs + 3451 adapter->stats.algnerrc + 3452 adapter->stats.ruc + adapter->stats.roc + 3453 adapter->stats.mpc + adapter->stats.cexterr + 3454 adapter->rx_overruns; 3455 3456 /* Tx Errors */ 3457 ifp->if_oerrors = adapter->stats.ecol + adapter->stats.latecol + 3458 adapter->watchdog_timeouts; 3459 } 3460 3461 3462 /********************************************************************** 3463 * 3464 * This routine is called only when em_display_debug_stats is enabled. 3465 * This routine provides a way to take a look at important statistics 3466 * maintained by the driver and hardware. 3467 * 3468 **********************************************************************/ 3469 static void 3470 em_print_debug_info(struct adapter *adapter) 3471 { 3472 device_t dev= adapter->dev; 3473 uint8_t *hw_addr = adapter->hw.hw_addr; 3474 3475 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3476 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x\n", 3477 E1000_READ_REG(&adapter->hw, CTRL), 3478 E1000_READ_REG(&adapter->hw, RCTL)); 3479 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk\n", 3480 ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff0000) >> 16), 3481 (E1000_READ_REG(&adapter->hw, PBA) & 0xffff)); 3482 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3483 adapter->hw.fc_high_water, adapter->hw.fc_low_water); 3484 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3485 E1000_READ_REG(&adapter->hw, TIDV), 3486 E1000_READ_REG(&adapter->hw, TADV)); 3487 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3488 E1000_READ_REG(&adapter->hw, RDTR), 3489 E1000_READ_REG(&adapter->hw, RADV)); 3490 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3491 (long long)adapter->tx_fifo_wrk_cnt, 3492 (long long)adapter->tx_fifo_reset_cnt); 3493 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3494 E1000_READ_REG(&adapter->hw, TDH), 3495 E1000_READ_REG(&adapter->hw, TDT)); 3496 device_printf(dev, "Num Tx descriptors avail = %d\n", 3497 adapter->num_tx_desc_avail); 3498 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3499 adapter->no_tx_desc_avail1); 3500 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3501 adapter->no_tx_desc_avail2); 3502 device_printf(dev, "Std mbuf failed = %ld\n", 3503 adapter->mbuf_alloc_failed); 3504 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3505 adapter->mbuf_cluster_failed); 3506 device_printf(dev, "Driver dropped packets = %ld\n", 3507 adapter->dropped_pkts); 3508 } 3509 3510 static void 3511 em_print_hw_stats(struct adapter *adapter) 3512 { 3513 device_t dev= adapter->dev; 3514 3515 device_printf(dev, "Excessive collisions = %lld\n", 3516 (long long)adapter->stats.ecol); 3517 device_printf(dev, "Symbol errors = %lld\n", 3518 (long long)adapter->stats.symerrs); 3519 device_printf(dev, "Sequence errors = %lld\n", 3520 (long long)adapter->stats.sec); 3521 device_printf(dev, "Defer count = %lld\n", 3522 (long long)adapter->stats.dc); 3523 3524 device_printf(dev, "Missed Packets = %lld\n", 3525 (long long)adapter->stats.mpc); 3526 device_printf(dev, "Receive No Buffers = %lld\n", 3527 (long long)adapter->stats.rnbc); 3528 /* RLEC is inaccurate on some hardware, calculate our own. */ 3529 device_printf(dev, "Receive Length errors = %lld\n", 3530 (long long)adapter->stats.roc + 3531 (long long)adapter->stats.ruc); 3532 device_printf(dev, "Receive errors = %lld\n", 3533 (long long)adapter->stats.rxerrc); 3534 device_printf(dev, "Crc errors = %lld\n", 3535 (long long)adapter->stats.crcerrs); 3536 device_printf(dev, "Alignment errors = %lld\n", 3537 (long long)adapter->stats.algnerrc); 3538 device_printf(dev, "Carrier extension errors = %lld\n", 3539 (long long)adapter->stats.cexterr); 3540 device_printf(dev, "RX overruns = %lu\n", adapter->rx_overruns); 3541 device_printf(dev, "Watchdog timeouts = %lu\n", 3542 adapter->watchdog_timeouts); 3543 3544 device_printf(dev, "XON Rcvd = %lld\n", 3545 (long long)adapter->stats.xonrxc); 3546 device_printf(dev, "XON Xmtd = %lld\n", 3547 (long long)adapter->stats.xontxc); 3548 device_printf(dev, "XOFF Rcvd = %lld\n", 3549 (long long)adapter->stats.xoffrxc); 3550 device_printf(dev, "XOFF Xmtd = %lld\n", 3551 (long long)adapter->stats.xofftxc); 3552 3553 device_printf(dev, "Good Packets Rcvd = %lld\n", 3554 (long long)adapter->stats.gprc); 3555 device_printf(dev, "Good Packets Xmtd = %lld\n", 3556 (long long)adapter->stats.gptc); 3557 } 3558 3559 static int 3560 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3561 { 3562 int error; 3563 int result; 3564 struct adapter *adapter; 3565 3566 result = -1; 3567 error = sysctl_handle_int(oidp, &result, 0, req); 3568 3569 if (error || !req->newptr) 3570 return (error); 3571 3572 if (result == 1) { 3573 adapter = (struct adapter *)arg1; 3574 em_print_debug_info(adapter); 3575 } 3576 3577 return (error); 3578 } 3579 3580 static int 3581 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3582 { 3583 int error; 3584 int result; 3585 struct adapter *adapter; 3586 3587 result = -1; 3588 error = sysctl_handle_int(oidp, &result, 0, req); 3589 3590 if (error || !req->newptr) 3591 return (error); 3592 3593 if (result == 1) { 3594 adapter = (struct adapter *)arg1; 3595 em_print_hw_stats(adapter); 3596 } 3597 3598 return (error); 3599 } 3600 3601 static int 3602 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3603 { 3604 struct em_int_delay_info *info; 3605 struct adapter *adapter; 3606 uint32_t regval; 3607 int error; 3608 int usecs; 3609 int ticks; 3610 3611 info = (struct em_int_delay_info *)arg1; 3612 adapter = info->adapter; 3613 usecs = info->value; 3614 error = sysctl_handle_int(oidp, &usecs, 0, req); 3615 if (error != 0 || req->newptr == NULL) 3616 return (error); 3617 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535)) 3618 return (EINVAL); 3619 info->value = usecs; 3620 ticks = E1000_USECS_TO_TICKS(usecs); 3621 3622 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer); 3623 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 3624 regval = (regval & ~0xffff) | (ticks & 0xffff); 3625 /* Handle a few special cases. */ 3626 switch (info->offset) { 3627 case E1000_RDTR: 3628 case E1000_82542_RDTR: 3629 regval |= E1000_RDT_FPDB; 3630 break; 3631 case E1000_TIDV: 3632 case E1000_82542_TIDV: 3633 if (ticks == 0) { 3634 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 3635 /* Don't write 0 into the TIDV register. */ 3636 regval++; 3637 } else 3638 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3639 break; 3640 } 3641 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 3642 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer); 3643 return (0); 3644 } 3645 3646 static void 3647 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 3648 const char *description, struct em_int_delay_info *info, 3649 int offset, int value) 3650 { 3651 info->adapter = adapter; 3652 info->offset = offset; 3653 info->value = value; 3654 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 3655 SYSCTL_CHILDREN(adapter->sysctl_tree), 3656 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 3657 info, 0, em_sysctl_int_delay, "I", description); 3658 } 3659 3660 static int 3661 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 3662 { 3663 struct adapter *adapter = (void *)arg1; 3664 int error; 3665 int throttle; 3666 3667 throttle = em_int_throttle_ceil; 3668 error = sysctl_handle_int(oidp, &throttle, 0, req); 3669 if (error || req->newptr == NULL) 3670 return error; 3671 if (throttle < 0 || throttle > 1000000000 / 256) 3672 return EINVAL; 3673 if (throttle) { 3674 /* 3675 * Set the interrupt throttling rate in 256ns increments, 3676 * recalculate sysctl value assignment to get exact frequency. 3677 */ 3678 throttle = 1000000000 / 256 / throttle; 3679 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer); 3680 em_int_throttle_ceil = 1000000000 / 256 / throttle; 3681 E1000_WRITE_REG(&adapter->hw, ITR, throttle); 3682 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer); 3683 } else { 3684 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer); 3685 em_int_throttle_ceil = 0; 3686 E1000_WRITE_REG(&adapter->hw, ITR, 0); 3687 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer); 3688 } 3689 device_printf(adapter->dev, "Interrupt moderation set to %d/sec\n", 3690 em_int_throttle_ceil); 3691 return 0; 3692 } 3693