1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include "opt_ifpoll.h" 68 #include "opt_rss.h" 69 #include "opt_emx.h" 70 71 #include <sys/param.h> 72 #include <sys/bus.h> 73 #include <sys/endian.h> 74 #include <sys/interrupt.h> 75 #include <sys/kernel.h> 76 #include <sys/ktr.h> 77 #include <sys/malloc.h> 78 #include <sys/mbuf.h> 79 #include <sys/proc.h> 80 #include <sys/rman.h> 81 #include <sys/serialize.h> 82 #include <sys/serialize2.h> 83 #include <sys/socket.h> 84 #include <sys/sockio.h> 85 #include <sys/sysctl.h> 86 #include <sys/systm.h> 87 88 #include <net/bpf.h> 89 #include <net/ethernet.h> 90 #include <net/if.h> 91 #include <net/if_arp.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/ifq_var.h> 95 #include <net/toeplitz.h> 96 #include <net/toeplitz2.h> 97 #include <net/vlan/if_vlan_var.h> 98 #include <net/vlan/if_vlan_ether.h> 99 #include <net/if_poll.h> 100 101 #include <netinet/in_systm.h> 102 #include <netinet/in.h> 103 #include <netinet/ip.h> 104 #include <netinet/tcp.h> 105 #include <netinet/udp.h> 106 107 #include <bus/pci/pcivar.h> 108 #include <bus/pci/pcireg.h> 109 110 #include <dev/netif/ig_hal/e1000_api.h> 111 #include <dev/netif/ig_hal/e1000_82571.h> 112 #include <dev/netif/emx/if_emx.h> 113 114 #ifdef EMX_RSS_DEBUG 115 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \ 116 do { \ 117 if (sc->rss_debug >= lvl) \ 118 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \ 119 } while (0) 120 #else /* !EMX_RSS_DEBUG */ 121 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 122 #endif /* EMX_RSS_DEBUG */ 123 124 #define EMX_NAME "Intel(R) PRO/1000 " 125 126 #define EMX_DEVICE(id) \ 127 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id } 128 #define EMX_DEVICE_NULL { 0, 0, NULL } 129 130 static const struct emx_device { 131 uint16_t vid; 132 uint16_t did; 133 const char *desc; 134 } emx_devices[] = { 135 EMX_DEVICE(82571EB_COPPER), 136 EMX_DEVICE(82571EB_FIBER), 137 EMX_DEVICE(82571EB_SERDES), 138 EMX_DEVICE(82571EB_SERDES_DUAL), 139 EMX_DEVICE(82571EB_SERDES_QUAD), 140 EMX_DEVICE(82571EB_QUAD_COPPER), 141 EMX_DEVICE(82571EB_QUAD_COPPER_BP), 142 EMX_DEVICE(82571EB_QUAD_COPPER_LP), 143 EMX_DEVICE(82571EB_QUAD_FIBER), 144 EMX_DEVICE(82571PT_QUAD_COPPER), 145 146 EMX_DEVICE(82572EI_COPPER), 147 EMX_DEVICE(82572EI_FIBER), 148 EMX_DEVICE(82572EI_SERDES), 149 EMX_DEVICE(82572EI), 150 151 EMX_DEVICE(82573E), 152 EMX_DEVICE(82573E_IAMT), 153 EMX_DEVICE(82573L), 154 155 EMX_DEVICE(80003ES2LAN_COPPER_SPT), 156 EMX_DEVICE(80003ES2LAN_SERDES_SPT), 157 EMX_DEVICE(80003ES2LAN_COPPER_DPT), 158 EMX_DEVICE(80003ES2LAN_SERDES_DPT), 159 160 EMX_DEVICE(82574L), 161 162 /* required last entry */ 163 EMX_DEVICE_NULL 164 }; 165 166 static int emx_probe(device_t); 167 static int emx_attach(device_t); 168 static int emx_detach(device_t); 169 static int emx_shutdown(device_t); 170 static int emx_suspend(device_t); 171 static int emx_resume(device_t); 172 173 static void emx_init(void *); 174 static void emx_stop(struct emx_softc *); 175 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 176 static void emx_start(struct ifnet *); 177 #ifdef IFPOLL_ENABLE 178 static void emx_qpoll(struct ifnet *, struct ifpoll_info *); 179 #endif 180 static void emx_watchdog(struct ifnet *); 181 static void emx_media_status(struct ifnet *, struct ifmediareq *); 182 static int emx_media_change(struct ifnet *); 183 static void emx_timer(void *); 184 static void emx_serialize(struct ifnet *, enum ifnet_serialize); 185 static void emx_deserialize(struct ifnet *, enum ifnet_serialize); 186 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize); 187 #ifdef INVARIANTS 188 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize, 189 boolean_t); 190 #endif 191 192 static void emx_intr(void *); 193 static void emx_rxeof(struct emx_softc *, int, int); 194 static void emx_txeof(struct emx_softc *); 195 static void emx_tx_collect(struct emx_softc *); 196 static void emx_tx_purge(struct emx_softc *); 197 static void emx_enable_intr(struct emx_softc *); 198 static void emx_disable_intr(struct emx_softc *); 199 200 static int emx_dma_alloc(struct emx_softc *); 201 static void emx_dma_free(struct emx_softc *); 202 static void emx_init_tx_ring(struct emx_softc *); 203 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *); 204 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *); 205 static int emx_create_tx_ring(struct emx_softc *); 206 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *); 207 static void emx_destroy_tx_ring(struct emx_softc *, int); 208 static void emx_destroy_rx_ring(struct emx_softc *, 209 struct emx_rxdata *, int); 210 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int); 211 static int emx_encap(struct emx_softc *, struct mbuf **); 212 static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **); 213 static int emx_txcsum(struct emx_softc *, struct mbuf *, 214 uint32_t *, uint32_t *); 215 216 static int emx_is_valid_eaddr(const uint8_t *); 217 static int emx_hw_init(struct emx_softc *); 218 static void emx_setup_ifp(struct emx_softc *); 219 static void emx_init_tx_unit(struct emx_softc *); 220 static void emx_init_rx_unit(struct emx_softc *); 221 static void emx_update_stats(struct emx_softc *); 222 static void emx_set_promisc(struct emx_softc *); 223 static void emx_disable_promisc(struct emx_softc *); 224 static void emx_set_multi(struct emx_softc *); 225 static void emx_update_link_status(struct emx_softc *); 226 static void emx_smartspeed(struct emx_softc *); 227 228 static void emx_print_debug_info(struct emx_softc *); 229 static void emx_print_nvm_info(struct emx_softc *); 230 static void emx_print_hw_stats(struct emx_softc *); 231 232 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS); 233 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 234 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 235 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 236 static void emx_add_sysctl(struct emx_softc *); 237 238 static void emx_serialize_skipmain(struct emx_softc *); 239 static void emx_deserialize_skipmain(struct emx_softc *); 240 241 /* Management and WOL Support */ 242 static void emx_get_mgmt(struct emx_softc *); 243 static void emx_rel_mgmt(struct emx_softc *); 244 static void emx_get_hw_control(struct emx_softc *); 245 static void emx_rel_hw_control(struct emx_softc *); 246 static void emx_enable_wol(device_t); 247 248 static device_method_t emx_methods[] = { 249 /* Device interface */ 250 DEVMETHOD(device_probe, emx_probe), 251 DEVMETHOD(device_attach, emx_attach), 252 DEVMETHOD(device_detach, emx_detach), 253 DEVMETHOD(device_shutdown, emx_shutdown), 254 DEVMETHOD(device_suspend, emx_suspend), 255 DEVMETHOD(device_resume, emx_resume), 256 { 0, 0 } 257 }; 258 259 static driver_t emx_driver = { 260 "emx", 261 emx_methods, 262 sizeof(struct emx_softc), 263 }; 264 265 static devclass_t emx_devclass; 266 267 DECLARE_DUMMY_MODULE(if_emx); 268 MODULE_DEPEND(emx, ig_hal, 1, 1, 1); 269 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, 0, 0); 270 271 /* 272 * Tunables 273 */ 274 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR; 275 static int emx_rxd = EMX_DEFAULT_RXD; 276 static int emx_txd = EMX_DEFAULT_TXD; 277 static int emx_smart_pwr_down = FALSE; 278 279 /* Controls whether promiscuous also shows bad packets */ 280 static int emx_debug_sbp = FALSE; 281 282 static int emx_82573_workaround = TRUE; 283 284 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil); 285 TUNABLE_INT("hw.emx.rxd", &emx_rxd); 286 TUNABLE_INT("hw.emx.txd", &emx_txd); 287 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down); 288 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp); 289 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround); 290 291 /* Global used in WOL setup with multiport cards */ 292 static int emx_global_quad_port_a = 0; 293 294 /* Set this to one to display debug statistics */ 295 static int emx_display_debug_stats = 0; 296 297 #if !defined(KTR_IF_EMX) 298 #define KTR_IF_EMX KTR_ALL 299 #endif 300 KTR_INFO_MASTER(if_emx); 301 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin", 0); 302 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end", 0); 303 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet", 0); 304 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet", 0); 305 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean", 0); 306 #define logif(name) KTR_LOG(if_emx_ ## name) 307 308 static __inline void 309 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf) 310 { 311 rxd->rxd_bufaddr = htole64(rxbuf->paddr); 312 /* DD bit must be cleared */ 313 rxd->rxd_staterr = 0; 314 } 315 316 static __inline void 317 emx_rxcsum(uint32_t staterr, struct mbuf *mp) 318 { 319 /* Ignore Checksum bit is set */ 320 if (staterr & E1000_RXD_STAT_IXSM) 321 return; 322 323 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) == 324 E1000_RXD_STAT_IPCS) 325 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 326 327 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 328 E1000_RXD_STAT_TCPCS) { 329 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 330 CSUM_PSEUDO_HDR | 331 CSUM_FRAG_NOT_CHECKED; 332 mp->m_pkthdr.csum_data = htons(0xffff); 333 } 334 } 335 336 static __inline struct pktinfo * 337 emx_rssinfo(struct mbuf *m, struct pktinfo *pi, 338 uint32_t mrq, uint32_t hash, uint32_t staterr) 339 { 340 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) { 341 case EMX_RXDMRQ_IPV4_TCP: 342 pi->pi_netisr = NETISR_IP; 343 pi->pi_flags = 0; 344 pi->pi_l3proto = IPPROTO_TCP; 345 break; 346 347 case EMX_RXDMRQ_IPV6_TCP: 348 pi->pi_netisr = NETISR_IPV6; 349 pi->pi_flags = 0; 350 pi->pi_l3proto = IPPROTO_TCP; 351 break; 352 353 case EMX_RXDMRQ_IPV4: 354 if (staterr & E1000_RXD_STAT_IXSM) 355 return NULL; 356 357 if ((staterr & 358 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 359 E1000_RXD_STAT_TCPCS) { 360 pi->pi_netisr = NETISR_IP; 361 pi->pi_flags = 0; 362 pi->pi_l3proto = IPPROTO_UDP; 363 break; 364 } 365 /* FALL THROUGH */ 366 default: 367 return NULL; 368 } 369 370 m->m_flags |= M_HASH; 371 m->m_pkthdr.hash = toeplitz_hash(hash); 372 return pi; 373 } 374 375 static int 376 emx_probe(device_t dev) 377 { 378 const struct emx_device *d; 379 uint16_t vid, did; 380 381 vid = pci_get_vendor(dev); 382 did = pci_get_device(dev); 383 384 for (d = emx_devices; d->desc != NULL; ++d) { 385 if (vid == d->vid && did == d->did) { 386 device_set_desc(dev, d->desc); 387 device_set_async_attach(dev, TRUE); 388 return 0; 389 } 390 } 391 return ENXIO; 392 } 393 394 static int 395 emx_attach(device_t dev) 396 { 397 struct emx_softc *sc = device_get_softc(dev); 398 struct ifnet *ifp = &sc->arpcom.ac_if; 399 int error = 0, i; 400 uint16_t eeprom_data, device_id; 401 402 lwkt_serialize_init(&sc->main_serialize); 403 lwkt_serialize_init(&sc->tx_serialize); 404 for (i = 0; i < EMX_NRX_RING; ++i) 405 lwkt_serialize_init(&sc->rx_data[i].rx_serialize); 406 407 i = 0; 408 sc->serializes[i++] = &sc->main_serialize; 409 sc->serializes[i++] = &sc->tx_serialize; 410 sc->serializes[i++] = &sc->rx_data[0].rx_serialize; 411 sc->serializes[i++] = &sc->rx_data[1].rx_serialize; 412 KKASSERT(i == EMX_NSERIALIZE); 413 414 callout_init(&sc->timer); 415 416 sc->dev = sc->osdep.dev = dev; 417 418 /* 419 * Determine hardware and mac type 420 */ 421 sc->hw.vendor_id = pci_get_vendor(dev); 422 sc->hw.device_id = pci_get_device(dev); 423 sc->hw.revision_id = pci_get_revid(dev); 424 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev); 425 sc->hw.subsystem_device_id = pci_get_subdevice(dev); 426 427 if (e1000_set_mac_type(&sc->hw)) 428 return ENXIO; 429 430 /* Enable bus mastering */ 431 pci_enable_busmaster(dev); 432 433 /* 434 * Allocate IO memory 435 */ 436 sc->memory_rid = EMX_BAR_MEM; 437 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 438 &sc->memory_rid, RF_ACTIVE); 439 if (sc->memory == NULL) { 440 device_printf(dev, "Unable to allocate bus resource: memory\n"); 441 error = ENXIO; 442 goto fail; 443 } 444 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 445 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 446 447 /* XXX This is quite goofy, it is not actually used */ 448 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 449 450 /* 451 * Allocate interrupt 452 */ 453 sc->intr_rid = 0; 454 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, 455 RF_SHAREABLE | RF_ACTIVE); 456 if (sc->intr_res == NULL) { 457 device_printf(dev, "Unable to allocate bus resource: " 458 "interrupt\n"); 459 error = ENXIO; 460 goto fail; 461 } 462 463 /* Save PCI command register for Shared Code */ 464 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 465 sc->hw.back = &sc->osdep; 466 467 /* Do Shared Code initialization */ 468 if (e1000_setup_init_funcs(&sc->hw, TRUE)) { 469 device_printf(dev, "Setup of Shared code failed\n"); 470 error = ENXIO; 471 goto fail; 472 } 473 e1000_get_bus_info(&sc->hw); 474 475 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 476 sc->hw.phy.autoneg_wait_to_complete = FALSE; 477 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 478 479 /* 480 * Interrupt throttle rate 481 */ 482 if (emx_int_throttle_ceil == 0) { 483 sc->int_throttle_ceil = 0; 484 } else { 485 int throttle = emx_int_throttle_ceil; 486 487 if (throttle < 0) 488 throttle = EMX_DEFAULT_ITR; 489 490 /* Recalculate the tunable value to get the exact frequency. */ 491 throttle = 1000000000 / 256 / throttle; 492 493 /* Upper 16bits of ITR is reserved and should be zero */ 494 if (throttle & 0xffff0000) 495 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR; 496 497 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 498 } 499 500 e1000_init_script_state_82541(&sc->hw, TRUE); 501 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE); 502 503 /* Copper options */ 504 if (sc->hw.phy.media_type == e1000_media_type_copper) { 505 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES; 506 sc->hw.phy.disable_polarity_correction = FALSE; 507 sc->hw.phy.ms_type = EMX_MASTER_SLAVE; 508 } 509 510 /* Set the frame limits assuming standard ethernet sized frames. */ 511 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 512 sc->min_frame_size = ETHER_MIN_LEN; 513 514 /* This controls when hardware reports transmit completion status. */ 515 sc->hw.mac.report_tx_early = 1; 516 517 /* Calculate # of RX rings */ 518 if (ncpus > 1) 519 sc->rx_ring_cnt = EMX_NRX_RING; 520 else 521 sc->rx_ring_cnt = 1; 522 sc->rx_ring_inuse = sc->rx_ring_cnt; 523 524 /* Allocate RX/TX rings' busdma(9) stuffs */ 525 error = emx_dma_alloc(sc); 526 if (error) 527 goto fail; 528 529 /* Make sure we have a good EEPROM before we read from it */ 530 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 531 /* 532 * Some PCI-E parts fail the first check due to 533 * the link being in sleep state, call it again, 534 * if it fails a second time its a real issue. 535 */ 536 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 537 device_printf(dev, 538 "The EEPROM Checksum Is Not Valid\n"); 539 error = EIO; 540 goto fail; 541 } 542 } 543 544 /* Initialize the hardware */ 545 error = emx_hw_init(sc); 546 if (error) { 547 device_printf(dev, "Unable to initialize the hardware\n"); 548 goto fail; 549 } 550 551 /* Copy the permanent MAC address out of the EEPROM */ 552 if (e1000_read_mac_addr(&sc->hw) < 0) { 553 device_printf(dev, "EEPROM read error while reading MAC" 554 " address\n"); 555 error = EIO; 556 goto fail; 557 } 558 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) { 559 device_printf(dev, "Invalid MAC address\n"); 560 error = EIO; 561 goto fail; 562 } 563 564 /* Manually turn off all interrupts */ 565 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 566 567 /* Setup OS specific network interface */ 568 emx_setup_ifp(sc); 569 570 /* Add sysctl tree, must after emx_setup_ifp() */ 571 emx_add_sysctl(sc); 572 573 /* Initialize statistics */ 574 emx_update_stats(sc); 575 576 sc->hw.mac.get_link_status = 1; 577 emx_update_link_status(sc); 578 579 /* Indicate SOL/IDER usage */ 580 if (e1000_check_reset_block(&sc->hw)) { 581 device_printf(dev, 582 "PHY reset is blocked due to SOL/IDER session.\n"); 583 } 584 585 /* Determine if we have to control management hardware */ 586 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 587 588 /* 589 * Setup Wake-on-Lan 590 */ 591 switch (sc->hw.mac.type) { 592 case e1000_82571: 593 case e1000_80003es2lan: 594 if (sc->hw.bus.func == 1) { 595 e1000_read_nvm(&sc->hw, 596 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 597 } else { 598 e1000_read_nvm(&sc->hw, 599 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 600 } 601 eeprom_data &= EMX_EEPROM_APME; 602 break; 603 604 default: 605 /* APME bit in EEPROM is mapped to WUC.APME */ 606 eeprom_data = 607 E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME; 608 break; 609 } 610 if (eeprom_data) 611 sc->wol = E1000_WUFC_MAG; 612 /* 613 * We have the eeprom settings, now apply the special cases 614 * where the eeprom may be wrong or the board won't support 615 * wake on lan on a particular port 616 */ 617 device_id = pci_get_device(dev); 618 switch (device_id) { 619 case E1000_DEV_ID_82571EB_FIBER: 620 /* 621 * Wake events only supported on port A for dual fiber 622 * regardless of eeprom setting 623 */ 624 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 625 E1000_STATUS_FUNC_1) 626 sc->wol = 0; 627 break; 628 629 case E1000_DEV_ID_82571EB_QUAD_COPPER: 630 case E1000_DEV_ID_82571EB_QUAD_FIBER: 631 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 632 /* if quad port sc, disable WoL on all but port A */ 633 if (emx_global_quad_port_a != 0) 634 sc->wol = 0; 635 /* Reset for multiple quad port adapters */ 636 if (++emx_global_quad_port_a == 4) 637 emx_global_quad_port_a = 0; 638 break; 639 } 640 641 /* XXX disable wol */ 642 sc->wol = 0; 643 644 sc->spare_tx_desc = EMX_TX_SPARE; 645 646 /* 647 * Keep following relationship between spare_tx_desc, oact_tx_desc 648 * and tx_int_nsegs: 649 * (spare_tx_desc + EMX_TX_RESERVED) <= 650 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs 651 */ 652 sc->oact_tx_desc = sc->num_tx_desc / 8; 653 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX) 654 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX; 655 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED) 656 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED; 657 658 sc->tx_int_nsegs = sc->num_tx_desc / 16; 659 if (sc->tx_int_nsegs < sc->oact_tx_desc) 660 sc->tx_int_nsegs = sc->oact_tx_desc; 661 662 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc, 663 &sc->intr_tag, &sc->main_serialize); 664 if (error) { 665 device_printf(dev, "Failed to register interrupt handler"); 666 ether_ifdetach(&sc->arpcom.ac_if); 667 goto fail; 668 } 669 670 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->intr_res)); 671 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 672 return (0); 673 fail: 674 emx_detach(dev); 675 return (error); 676 } 677 678 static int 679 emx_detach(device_t dev) 680 { 681 struct emx_softc *sc = device_get_softc(dev); 682 683 if (device_is_attached(dev)) { 684 struct ifnet *ifp = &sc->arpcom.ac_if; 685 686 ifnet_serialize_all(ifp); 687 688 emx_stop(sc); 689 690 e1000_phy_hw_reset(&sc->hw); 691 692 emx_rel_mgmt(sc); 693 694 if (sc->hw.mac.type == e1000_82573 && 695 e1000_check_mng_mode(&sc->hw)) 696 emx_rel_hw_control(sc); 697 698 if (sc->wol) { 699 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 700 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 701 emx_enable_wol(dev); 702 } 703 704 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag); 705 706 ifnet_deserialize_all(ifp); 707 708 ether_ifdetach(ifp); 709 } 710 bus_generic_detach(dev); 711 712 if (sc->intr_res != NULL) { 713 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, 714 sc->intr_res); 715 } 716 717 if (sc->memory != NULL) { 718 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid, 719 sc->memory); 720 } 721 722 emx_dma_free(sc); 723 724 /* Free sysctl tree */ 725 if (sc->sysctl_tree != NULL) 726 sysctl_ctx_free(&sc->sysctl_ctx); 727 728 return (0); 729 } 730 731 static int 732 emx_shutdown(device_t dev) 733 { 734 return emx_suspend(dev); 735 } 736 737 static int 738 emx_suspend(device_t dev) 739 { 740 struct emx_softc *sc = device_get_softc(dev); 741 struct ifnet *ifp = &sc->arpcom.ac_if; 742 743 ifnet_serialize_all(ifp); 744 745 emx_stop(sc); 746 747 emx_rel_mgmt(sc); 748 749 if (sc->hw.mac.type == e1000_82573 && 750 e1000_check_mng_mode(&sc->hw)) 751 emx_rel_hw_control(sc); 752 753 if (sc->wol) { 754 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 755 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 756 emx_enable_wol(dev); 757 } 758 759 ifnet_deserialize_all(ifp); 760 761 return bus_generic_suspend(dev); 762 } 763 764 static int 765 emx_resume(device_t dev) 766 { 767 struct emx_softc *sc = device_get_softc(dev); 768 struct ifnet *ifp = &sc->arpcom.ac_if; 769 770 ifnet_serialize_all(ifp); 771 772 emx_init(sc); 773 emx_get_mgmt(sc); 774 if_devstart(ifp); 775 776 ifnet_deserialize_all(ifp); 777 778 return bus_generic_resume(dev); 779 } 780 781 static void 782 emx_start(struct ifnet *ifp) 783 { 784 struct emx_softc *sc = ifp->if_softc; 785 struct mbuf *m_head; 786 787 ASSERT_SERIALIZED(&sc->tx_serialize); 788 789 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 790 return; 791 792 if (!sc->link_active) { 793 ifq_purge(&ifp->if_snd); 794 return; 795 } 796 797 while (!ifq_is_empty(&ifp->if_snd)) { 798 /* Now do we at least have a minimal? */ 799 if (EMX_IS_OACTIVE(sc)) { 800 emx_tx_collect(sc); 801 if (EMX_IS_OACTIVE(sc)) { 802 ifp->if_flags |= IFF_OACTIVE; 803 sc->no_tx_desc_avail1++; 804 break; 805 } 806 } 807 808 logif(pkt_txqueue); 809 m_head = ifq_dequeue(&ifp->if_snd, NULL); 810 if (m_head == NULL) 811 break; 812 813 if (emx_encap(sc, &m_head)) { 814 ifp->if_oerrors++; 815 emx_tx_collect(sc); 816 continue; 817 } 818 819 /* Send a copy of the frame to the BPF listener */ 820 ETHER_BPF_MTAP(ifp, m_head); 821 822 /* Set timeout in case hardware has problems transmitting. */ 823 ifp->if_timer = EMX_TX_TIMEOUT; 824 } 825 } 826 827 static int 828 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 829 { 830 struct emx_softc *sc = ifp->if_softc; 831 struct ifreq *ifr = (struct ifreq *)data; 832 uint16_t eeprom_data = 0; 833 int max_frame_size, mask, reinit; 834 int error = 0; 835 836 ASSERT_IFNET_SERIALIZED_ALL(ifp); 837 838 switch (command) { 839 case SIOCSIFMTU: 840 switch (sc->hw.mac.type) { 841 case e1000_82573: 842 /* 843 * 82573 only supports jumbo frames 844 * if ASPM is disabled. 845 */ 846 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1, 847 &eeprom_data); 848 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 849 max_frame_size = ETHER_MAX_LEN; 850 break; 851 } 852 /* FALL THROUGH */ 853 854 /* Limit Jumbo Frame size */ 855 case e1000_82571: 856 case e1000_82572: 857 case e1000_82574: 858 case e1000_80003es2lan: 859 max_frame_size = 9234; 860 break; 861 862 default: 863 max_frame_size = MAX_JUMBO_FRAME_SIZE; 864 break; 865 } 866 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 867 ETHER_CRC_LEN) { 868 error = EINVAL; 869 break; 870 } 871 872 ifp->if_mtu = ifr->ifr_mtu; 873 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + 874 ETHER_CRC_LEN; 875 876 if (ifp->if_flags & IFF_RUNNING) 877 emx_init(sc); 878 break; 879 880 case SIOCSIFFLAGS: 881 if (ifp->if_flags & IFF_UP) { 882 if ((ifp->if_flags & IFF_RUNNING)) { 883 if ((ifp->if_flags ^ sc->if_flags) & 884 (IFF_PROMISC | IFF_ALLMULTI)) { 885 emx_disable_promisc(sc); 886 emx_set_promisc(sc); 887 } 888 } else { 889 emx_init(sc); 890 } 891 } else if (ifp->if_flags & IFF_RUNNING) { 892 emx_stop(sc); 893 } 894 sc->if_flags = ifp->if_flags; 895 break; 896 897 case SIOCADDMULTI: 898 case SIOCDELMULTI: 899 if (ifp->if_flags & IFF_RUNNING) { 900 emx_disable_intr(sc); 901 emx_set_multi(sc); 902 #ifdef IFPOLL_ENABLE 903 if (!(ifp->if_flags & IFF_NPOLLING)) 904 #endif 905 emx_enable_intr(sc); 906 } 907 break; 908 909 case SIOCSIFMEDIA: 910 /* Check SOL/IDER usage */ 911 if (e1000_check_reset_block(&sc->hw)) { 912 device_printf(sc->dev, "Media change is" 913 " blocked due to SOL/IDER session.\n"); 914 break; 915 } 916 /* FALL THROUGH */ 917 918 case SIOCGIFMEDIA: 919 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 920 break; 921 922 case SIOCSIFCAP: 923 reinit = 0; 924 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 925 if (mask & IFCAP_HWCSUM) { 926 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 927 reinit = 1; 928 } 929 if (mask & IFCAP_VLAN_HWTAGGING) { 930 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 931 reinit = 1; 932 } 933 if (mask & IFCAP_RSS) { 934 ifp->if_capenable ^= IFCAP_RSS; 935 reinit = 1; 936 } 937 if (reinit && (ifp->if_flags & IFF_RUNNING)) 938 emx_init(sc); 939 break; 940 941 default: 942 error = ether_ioctl(ifp, command, data); 943 break; 944 } 945 return (error); 946 } 947 948 static void 949 emx_watchdog(struct ifnet *ifp) 950 { 951 struct emx_softc *sc = ifp->if_softc; 952 953 ASSERT_IFNET_SERIALIZED_ALL(ifp); 954 955 /* 956 * The timer is set to 5 every time start queues a packet. 957 * Then txeof keeps resetting it as long as it cleans at 958 * least one descriptor. 959 * Finally, anytime all descriptors are clean the timer is 960 * set to 0. 961 */ 962 963 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) == 964 E1000_READ_REG(&sc->hw, E1000_TDH(0))) { 965 /* 966 * If we reach here, all TX jobs are completed and 967 * the TX engine should have been idled for some time. 968 * We don't need to call if_devstart() here. 969 */ 970 ifp->if_flags &= ~IFF_OACTIVE; 971 ifp->if_timer = 0; 972 return; 973 } 974 975 /* 976 * If we are in this routine because of pause frames, then 977 * don't reset the hardware. 978 */ 979 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) { 980 ifp->if_timer = EMX_TX_TIMEOUT; 981 return; 982 } 983 984 if (e1000_check_for_link(&sc->hw) == 0) 985 if_printf(ifp, "watchdog timeout -- resetting\n"); 986 987 ifp->if_oerrors++; 988 sc->watchdog_events++; 989 990 emx_init(sc); 991 992 if (!ifq_is_empty(&ifp->if_snd)) 993 if_devstart(ifp); 994 } 995 996 static void 997 emx_init(void *xsc) 998 { 999 struct emx_softc *sc = xsc; 1000 struct ifnet *ifp = &sc->arpcom.ac_if; 1001 device_t dev = sc->dev; 1002 uint32_t pba; 1003 int i; 1004 1005 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1006 1007 emx_stop(sc); 1008 1009 /* 1010 * Packet Buffer Allocation (PBA) 1011 * Writing PBA sets the receive portion of the buffer 1012 * the remainder is used for the transmit buffer. 1013 */ 1014 switch (sc->hw.mac.type) { 1015 /* Total Packet Buffer on these is 48K */ 1016 case e1000_82571: 1017 case e1000_82572: 1018 case e1000_80003es2lan: 1019 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1020 break; 1021 1022 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1023 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1024 break; 1025 1026 case e1000_82574: 1027 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1028 break; 1029 1030 default: 1031 /* Devices before 82547 had a Packet Buffer of 64K. */ 1032 if (sc->max_frame_size > 8192) 1033 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1034 else 1035 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1036 } 1037 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba); 1038 1039 /* Get the latest mac address, User can use a LAA */ 1040 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1041 1042 /* Put the address into the Receive Address Array */ 1043 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1044 1045 /* 1046 * With the 82571 sc, RAR[0] may be overwritten 1047 * when the other port is reset, we make a duplicate 1048 * in RAR[14] for that eventuality, this assures 1049 * the interface continues to function. 1050 */ 1051 if (sc->hw.mac.type == e1000_82571) { 1052 e1000_set_laa_state_82571(&sc->hw, TRUE); 1053 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1054 E1000_RAR_ENTRIES - 1); 1055 } 1056 1057 /* Initialize the hardware */ 1058 if (emx_hw_init(sc)) { 1059 device_printf(dev, "Unable to initialize the hardware\n"); 1060 /* XXX emx_stop()? */ 1061 return; 1062 } 1063 emx_update_link_status(sc); 1064 1065 /* Setup VLAN support, basic and offload if available */ 1066 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1067 1068 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1069 uint32_t ctrl; 1070 1071 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 1072 ctrl |= E1000_CTRL_VME; 1073 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 1074 } 1075 1076 /* Set hardware offload abilities */ 1077 if (ifp->if_capenable & IFCAP_TXCSUM) 1078 ifp->if_hwassist = EMX_CSUM_FEATURES; 1079 else 1080 ifp->if_hwassist = 0; 1081 1082 /* Configure for OS presence */ 1083 emx_get_mgmt(sc); 1084 1085 /* Prepare transmit descriptors and buffers */ 1086 emx_init_tx_ring(sc); 1087 emx_init_tx_unit(sc); 1088 1089 /* Setup Multicast table */ 1090 emx_set_multi(sc); 1091 1092 /* 1093 * Adjust # of RX ring to be used based on IFCAP_RSS 1094 */ 1095 if (ifp->if_capenable & IFCAP_RSS) 1096 sc->rx_ring_inuse = sc->rx_ring_cnt; 1097 else 1098 sc->rx_ring_inuse = 1; 1099 1100 /* Prepare receive descriptors and buffers */ 1101 for (i = 0; i < sc->rx_ring_inuse; ++i) { 1102 if (emx_init_rx_ring(sc, &sc->rx_data[i])) { 1103 device_printf(dev, 1104 "Could not setup receive structures\n"); 1105 emx_stop(sc); 1106 return; 1107 } 1108 } 1109 emx_init_rx_unit(sc); 1110 1111 /* Don't lose promiscuous settings */ 1112 emx_set_promisc(sc); 1113 1114 ifp->if_flags |= IFF_RUNNING; 1115 ifp->if_flags &= ~IFF_OACTIVE; 1116 1117 callout_reset(&sc->timer, hz, emx_timer, sc); 1118 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1119 1120 /* MSI/X configuration for 82574 */ 1121 if (sc->hw.mac.type == e1000_82574) { 1122 int tmp; 1123 1124 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1125 tmp |= E1000_CTRL_EXT_PBA_CLR; 1126 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1127 /* 1128 * Set the IVAR - interrupt vector routing. 1129 * Each nibble represents a vector, high bit 1130 * is enable, other 3 bits are the MSIX table 1131 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1132 * Link (other) to 2, hence the magic number. 1133 */ 1134 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908); 1135 } 1136 1137 #ifdef IFPOLL_ENABLE 1138 /* 1139 * Only enable interrupts if we are not polling, make sure 1140 * they are off otherwise. 1141 */ 1142 if (ifp->if_flags & IFF_NPOLLING) 1143 emx_disable_intr(sc); 1144 else 1145 #endif /* IFPOLL_ENABLE */ 1146 emx_enable_intr(sc); 1147 1148 /* Don't reset the phy next time init gets called */ 1149 sc->hw.phy.reset_disable = TRUE; 1150 } 1151 1152 static void 1153 emx_intr(void *xsc) 1154 { 1155 struct emx_softc *sc = xsc; 1156 struct ifnet *ifp = &sc->arpcom.ac_if; 1157 uint32_t reg_icr; 1158 1159 logif(intr_beg); 1160 ASSERT_SERIALIZED(&sc->main_serialize); 1161 1162 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1163 1164 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) { 1165 logif(intr_end); 1166 return; 1167 } 1168 1169 /* 1170 * XXX: some laptops trigger several spurious interrupts 1171 * on emx(4) when in the resume cycle. The ICR register 1172 * reports all-ones value in this case. Processing such 1173 * interrupts would lead to a freeze. I don't know why. 1174 */ 1175 if (reg_icr == 0xffffffff) { 1176 logif(intr_end); 1177 return; 1178 } 1179 1180 if (ifp->if_flags & IFF_RUNNING) { 1181 if (reg_icr & 1182 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) { 1183 int i; 1184 1185 for (i = 0; i < sc->rx_ring_inuse; ++i) { 1186 lwkt_serialize_enter( 1187 &sc->rx_data[i].rx_serialize); 1188 emx_rxeof(sc, i, -1); 1189 lwkt_serialize_exit( 1190 &sc->rx_data[i].rx_serialize); 1191 } 1192 } 1193 if (reg_icr & E1000_ICR_TXDW) { 1194 lwkt_serialize_enter(&sc->tx_serialize); 1195 emx_txeof(sc); 1196 if (!ifq_is_empty(&ifp->if_snd)) 1197 if_devstart(ifp); 1198 lwkt_serialize_exit(&sc->tx_serialize); 1199 } 1200 } 1201 1202 /* Link status change */ 1203 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1204 emx_serialize_skipmain(sc); 1205 1206 callout_stop(&sc->timer); 1207 sc->hw.mac.get_link_status = 1; 1208 emx_update_link_status(sc); 1209 1210 /* Deal with TX cruft when link lost */ 1211 emx_tx_purge(sc); 1212 1213 callout_reset(&sc->timer, hz, emx_timer, sc); 1214 1215 emx_deserialize_skipmain(sc); 1216 } 1217 1218 if (reg_icr & E1000_ICR_RXO) 1219 sc->rx_overruns++; 1220 1221 logif(intr_end); 1222 } 1223 1224 static void 1225 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1226 { 1227 struct emx_softc *sc = ifp->if_softc; 1228 1229 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1230 1231 emx_update_link_status(sc); 1232 1233 ifmr->ifm_status = IFM_AVALID; 1234 ifmr->ifm_active = IFM_ETHER; 1235 1236 if (!sc->link_active) 1237 return; 1238 1239 ifmr->ifm_status |= IFM_ACTIVE; 1240 1241 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1242 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1243 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1244 } else { 1245 switch (sc->link_speed) { 1246 case 10: 1247 ifmr->ifm_active |= IFM_10_T; 1248 break; 1249 case 100: 1250 ifmr->ifm_active |= IFM_100_TX; 1251 break; 1252 1253 case 1000: 1254 ifmr->ifm_active |= IFM_1000_T; 1255 break; 1256 } 1257 if (sc->link_duplex == FULL_DUPLEX) 1258 ifmr->ifm_active |= IFM_FDX; 1259 else 1260 ifmr->ifm_active |= IFM_HDX; 1261 } 1262 } 1263 1264 static int 1265 emx_media_change(struct ifnet *ifp) 1266 { 1267 struct emx_softc *sc = ifp->if_softc; 1268 struct ifmedia *ifm = &sc->media; 1269 1270 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1271 1272 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1273 return (EINVAL); 1274 1275 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1276 case IFM_AUTO: 1277 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1278 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 1279 break; 1280 1281 case IFM_1000_LX: 1282 case IFM_1000_SX: 1283 case IFM_1000_T: 1284 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1285 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1286 break; 1287 1288 case IFM_100_TX: 1289 sc->hw.mac.autoneg = FALSE; 1290 sc->hw.phy.autoneg_advertised = 0; 1291 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1292 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1293 else 1294 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1295 break; 1296 1297 case IFM_10_T: 1298 sc->hw.mac.autoneg = FALSE; 1299 sc->hw.phy.autoneg_advertised = 0; 1300 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1301 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1302 else 1303 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1304 break; 1305 1306 default: 1307 if_printf(ifp, "Unsupported media type\n"); 1308 break; 1309 } 1310 1311 /* 1312 * As the speed/duplex settings my have changed we need to 1313 * reset the PHY. 1314 */ 1315 sc->hw.phy.reset_disable = FALSE; 1316 1317 emx_init(sc); 1318 1319 return (0); 1320 } 1321 1322 static int 1323 emx_encap(struct emx_softc *sc, struct mbuf **m_headp) 1324 { 1325 bus_dma_segment_t segs[EMX_MAX_SCATTER]; 1326 bus_dmamap_t map; 1327 struct emx_txbuf *tx_buffer, *tx_buffer_mapped; 1328 struct e1000_tx_desc *ctxd = NULL; 1329 struct mbuf *m_head = *m_headp; 1330 uint32_t txd_upper, txd_lower, cmd = 0; 1331 int maxsegs, nsegs, i, j, first, last = 0, error; 1332 1333 if (m_head->m_len < EMX_TXCSUM_MINHL && 1334 (m_head->m_flags & EMX_CSUM_FEATURES)) { 1335 /* 1336 * Make sure that ethernet header and ip.ip_hl are in 1337 * contiguous memory, since if TXCSUM is enabled, later 1338 * TX context descriptor's setup need to access ip.ip_hl. 1339 */ 1340 error = emx_txcsum_pullup(sc, m_headp); 1341 if (error) { 1342 KKASSERT(*m_headp == NULL); 1343 return error; 1344 } 1345 m_head = *m_headp; 1346 } 1347 1348 txd_upper = txd_lower = 0; 1349 1350 /* 1351 * Capture the first descriptor index, this descriptor 1352 * will have the index of the EOP which is the only one 1353 * that now gets a DONE bit writeback. 1354 */ 1355 first = sc->next_avail_tx_desc; 1356 tx_buffer = &sc->tx_buf[first]; 1357 tx_buffer_mapped = tx_buffer; 1358 map = tx_buffer->map; 1359 1360 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED; 1361 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc\n")); 1362 if (maxsegs > EMX_MAX_SCATTER) 1363 maxsegs = EMX_MAX_SCATTER; 1364 1365 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp, 1366 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1367 if (error) { 1368 if (error == ENOBUFS) 1369 sc->mbuf_alloc_failed++; 1370 else 1371 sc->no_tx_dma_setup++; 1372 1373 m_freem(*m_headp); 1374 *m_headp = NULL; 1375 return error; 1376 } 1377 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1378 1379 m_head = *m_headp; 1380 sc->tx_nsegs += nsegs; 1381 1382 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) { 1383 /* TX csum offloading will consume one TX desc */ 1384 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower); 1385 } 1386 i = sc->next_avail_tx_desc; 1387 1388 /* Set up our transmit descriptors */ 1389 for (j = 0; j < nsegs; j++) { 1390 tx_buffer = &sc->tx_buf[i]; 1391 ctxd = &sc->tx_desc_base[i]; 1392 1393 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1394 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1395 txd_lower | segs[j].ds_len); 1396 ctxd->upper.data = htole32(txd_upper); 1397 1398 last = i; 1399 if (++i == sc->num_tx_desc) 1400 i = 0; 1401 } 1402 1403 sc->next_avail_tx_desc = i; 1404 1405 KKASSERT(sc->num_tx_desc_avail > nsegs); 1406 sc->num_tx_desc_avail -= nsegs; 1407 1408 /* Handle VLAN tag */ 1409 if (m_head->m_flags & M_VLANTAG) { 1410 /* Set the vlan id. */ 1411 ctxd->upper.fields.special = 1412 htole16(m_head->m_pkthdr.ether_vlantag); 1413 1414 /* Tell hardware to add tag */ 1415 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1416 } 1417 1418 tx_buffer->m_head = m_head; 1419 tx_buffer_mapped->map = tx_buffer->map; 1420 tx_buffer->map = map; 1421 1422 if (sc->tx_nsegs >= sc->tx_int_nsegs) { 1423 sc->tx_nsegs = 0; 1424 1425 /* 1426 * Report Status (RS) is turned on 1427 * every tx_int_nsegs descriptors. 1428 */ 1429 cmd = E1000_TXD_CMD_RS; 1430 1431 /* 1432 * Keep track of the descriptor, which will 1433 * be written back by hardware. 1434 */ 1435 sc->tx_dd[sc->tx_dd_tail] = last; 1436 EMX_INC_TXDD_IDX(sc->tx_dd_tail); 1437 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head); 1438 } 1439 1440 /* 1441 * Last Descriptor of Packet needs End Of Packet (EOP) 1442 */ 1443 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1444 1445 /* 1446 * Advance the Transmit Descriptor Tail (TDT), this tells 1447 * the E1000 that this frame is available to transmit. 1448 */ 1449 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i); 1450 1451 return (0); 1452 } 1453 1454 static void 1455 emx_set_promisc(struct emx_softc *sc) 1456 { 1457 struct ifnet *ifp = &sc->arpcom.ac_if; 1458 uint32_t reg_rctl; 1459 1460 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1461 1462 if (ifp->if_flags & IFF_PROMISC) { 1463 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1464 /* Turn this on if you want to see bad packets */ 1465 if (emx_debug_sbp) 1466 reg_rctl |= E1000_RCTL_SBP; 1467 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1468 } else if (ifp->if_flags & IFF_ALLMULTI) { 1469 reg_rctl |= E1000_RCTL_MPE; 1470 reg_rctl &= ~E1000_RCTL_UPE; 1471 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1472 } 1473 } 1474 1475 static void 1476 emx_disable_promisc(struct emx_softc *sc) 1477 { 1478 uint32_t reg_rctl; 1479 1480 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1481 1482 reg_rctl &= ~E1000_RCTL_UPE; 1483 reg_rctl &= ~E1000_RCTL_MPE; 1484 reg_rctl &= ~E1000_RCTL_SBP; 1485 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1486 } 1487 1488 static void 1489 emx_set_multi(struct emx_softc *sc) 1490 { 1491 struct ifnet *ifp = &sc->arpcom.ac_if; 1492 struct ifmultiaddr *ifma; 1493 uint32_t reg_rctl = 0; 1494 uint8_t mta[512]; /* Largest MTS is 4096 bits */ 1495 int mcnt = 0; 1496 1497 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1498 if (ifma->ifma_addr->sa_family != AF_LINK) 1499 continue; 1500 1501 if (mcnt == EMX_MCAST_ADDR_MAX) 1502 break; 1503 1504 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1505 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1506 mcnt++; 1507 } 1508 1509 if (mcnt >= EMX_MCAST_ADDR_MAX) { 1510 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1511 reg_rctl |= E1000_RCTL_MPE; 1512 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1513 } else { 1514 e1000_update_mc_addr_list(&sc->hw, mta, 1515 mcnt, 1, sc->hw.mac.rar_entry_count); 1516 } 1517 } 1518 1519 /* 1520 * This routine checks for link status and updates statistics. 1521 */ 1522 static void 1523 emx_timer(void *xsc) 1524 { 1525 struct emx_softc *sc = xsc; 1526 struct ifnet *ifp = &sc->arpcom.ac_if; 1527 1528 ifnet_serialize_all(ifp); 1529 1530 emx_update_link_status(sc); 1531 emx_update_stats(sc); 1532 1533 /* Reset LAA into RAR[0] on 82571 */ 1534 if (e1000_get_laa_state_82571(&sc->hw) == TRUE) 1535 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1536 1537 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1538 emx_print_hw_stats(sc); 1539 1540 emx_smartspeed(sc); 1541 1542 callout_reset(&sc->timer, hz, emx_timer, sc); 1543 1544 ifnet_deserialize_all(ifp); 1545 } 1546 1547 static void 1548 emx_update_link_status(struct emx_softc *sc) 1549 { 1550 struct e1000_hw *hw = &sc->hw; 1551 struct ifnet *ifp = &sc->arpcom.ac_if; 1552 device_t dev = sc->dev; 1553 uint32_t link_check = 0; 1554 1555 /* Get the cached link value or read phy for real */ 1556 switch (hw->phy.media_type) { 1557 case e1000_media_type_copper: 1558 if (hw->mac.get_link_status) { 1559 /* Do the work to read phy */ 1560 e1000_check_for_link(hw); 1561 link_check = !hw->mac.get_link_status; 1562 if (link_check) /* ESB2 fix */ 1563 e1000_cfg_on_link_up(hw); 1564 } else { 1565 link_check = TRUE; 1566 } 1567 break; 1568 1569 case e1000_media_type_fiber: 1570 e1000_check_for_link(hw); 1571 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 1572 break; 1573 1574 case e1000_media_type_internal_serdes: 1575 e1000_check_for_link(hw); 1576 link_check = sc->hw.mac.serdes_has_link; 1577 break; 1578 1579 case e1000_media_type_unknown: 1580 default: 1581 break; 1582 } 1583 1584 /* Now check for a transition */ 1585 if (link_check && sc->link_active == 0) { 1586 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1587 &sc->link_duplex); 1588 1589 /* 1590 * Check if we should enable/disable SPEED_MODE bit on 1591 * 82571EB/82572EI 1592 */ 1593 if (hw->mac.type == e1000_82571 || 1594 hw->mac.type == e1000_82572) { 1595 int tarc0; 1596 1597 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1598 if (sc->link_speed != SPEED_1000) 1599 tarc0 &= ~EMX_TARC_SPEED_MODE; 1600 else 1601 tarc0 |= EMX_TARC_SPEED_MODE; 1602 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1603 } 1604 if (bootverbose) { 1605 device_printf(dev, "Link is up %d Mbps %s\n", 1606 sc->link_speed, 1607 ((sc->link_duplex == FULL_DUPLEX) ? 1608 "Full Duplex" : "Half Duplex")); 1609 } 1610 sc->link_active = 1; 1611 sc->smartspeed = 0; 1612 ifp->if_baudrate = sc->link_speed * 1000000; 1613 ifp->if_link_state = LINK_STATE_UP; 1614 if_link_state_change(ifp); 1615 } else if (!link_check && sc->link_active == 1) { 1616 ifp->if_baudrate = sc->link_speed = 0; 1617 sc->link_duplex = 0; 1618 if (bootverbose) 1619 device_printf(dev, "Link is Down\n"); 1620 sc->link_active = 0; 1621 #if 0 1622 /* Link down, disable watchdog */ 1623 if->if_timer = 0; 1624 #endif 1625 ifp->if_link_state = LINK_STATE_DOWN; 1626 if_link_state_change(ifp); 1627 } 1628 } 1629 1630 static void 1631 emx_stop(struct emx_softc *sc) 1632 { 1633 struct ifnet *ifp = &sc->arpcom.ac_if; 1634 int i; 1635 1636 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1637 1638 emx_disable_intr(sc); 1639 1640 callout_stop(&sc->timer); 1641 1642 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1643 ifp->if_timer = 0; 1644 1645 /* 1646 * Disable multiple receive queues. 1647 * 1648 * NOTE: 1649 * We should disable multiple receive queues before 1650 * resetting the hardware. 1651 */ 1652 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0); 1653 1654 e1000_reset_hw(&sc->hw); 1655 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1656 1657 for (i = 0; i < sc->num_tx_desc; i++) { 1658 struct emx_txbuf *tx_buffer = &sc->tx_buf[i]; 1659 1660 if (tx_buffer->m_head != NULL) { 1661 bus_dmamap_unload(sc->txtag, tx_buffer->map); 1662 m_freem(tx_buffer->m_head); 1663 tx_buffer->m_head = NULL; 1664 } 1665 } 1666 1667 for (i = 0; i < sc->rx_ring_inuse; ++i) 1668 emx_free_rx_ring(sc, &sc->rx_data[i]); 1669 1670 sc->csum_flags = 0; 1671 sc->csum_ehlen = 0; 1672 sc->csum_iphlen = 0; 1673 1674 sc->tx_dd_head = 0; 1675 sc->tx_dd_tail = 0; 1676 sc->tx_nsegs = 0; 1677 } 1678 1679 static int 1680 emx_hw_init(struct emx_softc *sc) 1681 { 1682 device_t dev = sc->dev; 1683 uint16_t rx_buffer_size; 1684 1685 /* Issue a global reset */ 1686 e1000_reset_hw(&sc->hw); 1687 1688 /* Get control from any management/hw control */ 1689 if (sc->hw.mac.type == e1000_82573 && 1690 e1000_check_mng_mode(&sc->hw)) 1691 emx_get_hw_control(sc); 1692 1693 /* Set up smart power down as default off on newer adapters. */ 1694 if (!emx_smart_pwr_down && 1695 (sc->hw.mac.type == e1000_82571 || 1696 sc->hw.mac.type == e1000_82572)) { 1697 uint16_t phy_tmp = 0; 1698 1699 /* Speed up time to link by disabling smart power down. */ 1700 e1000_read_phy_reg(&sc->hw, 1701 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1702 phy_tmp &= ~IGP02E1000_PM_SPD; 1703 e1000_write_phy_reg(&sc->hw, 1704 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1705 } 1706 1707 /* 1708 * These parameters control the automatic generation (Tx) and 1709 * response (Rx) to Ethernet PAUSE frames. 1710 * - High water mark should allow for at least two frames to be 1711 * received after sending an XOFF. 1712 * - Low water mark works best when it is very near the high water mark. 1713 * This allows the receiver to restart by sending XON when it has 1714 * drained a bit. Here we use an arbitary value of 1500 which will 1715 * restart after one full frame is pulled from the buffer. There 1716 * could be several smaller frames in the buffer and if so they will 1717 * not trigger the XON until their total number reduces the buffer 1718 * by 1500. 1719 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1720 */ 1721 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10; 1722 1723 sc->hw.fc.high_water = rx_buffer_size - 1724 roundup2(sc->max_frame_size, 1024); 1725 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500; 1726 1727 if (sc->hw.mac.type == e1000_80003es2lan) 1728 sc->hw.fc.pause_time = 0xFFFF; 1729 else 1730 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME; 1731 sc->hw.fc.send_xon = TRUE; 1732 sc->hw.fc.requested_mode = e1000_fc_full; 1733 1734 if (e1000_init_hw(&sc->hw) < 0) { 1735 device_printf(dev, "Hardware Initialization Failed\n"); 1736 return (EIO); 1737 } 1738 1739 e1000_check_for_link(&sc->hw); 1740 1741 return (0); 1742 } 1743 1744 static void 1745 emx_setup_ifp(struct emx_softc *sc) 1746 { 1747 struct ifnet *ifp = &sc->arpcom.ac_if; 1748 1749 if_initname(ifp, device_get_name(sc->dev), 1750 device_get_unit(sc->dev)); 1751 ifp->if_softc = sc; 1752 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1753 ifp->if_init = emx_init; 1754 ifp->if_ioctl = emx_ioctl; 1755 ifp->if_start = emx_start; 1756 #ifdef IFPOLL_ENABLE 1757 ifp->if_qpoll = emx_qpoll; 1758 #endif 1759 ifp->if_watchdog = emx_watchdog; 1760 ifp->if_serialize = emx_serialize; 1761 ifp->if_deserialize = emx_deserialize; 1762 ifp->if_tryserialize = emx_tryserialize; 1763 #ifdef INVARIANTS 1764 ifp->if_serialize_assert = emx_serialize_assert; 1765 #endif 1766 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1); 1767 ifq_set_ready(&ifp->if_snd); 1768 1769 ether_ifattach(ifp, sc->hw.mac.addr, NULL); 1770 1771 ifp->if_capabilities = IFCAP_HWCSUM | 1772 IFCAP_VLAN_HWTAGGING | 1773 IFCAP_VLAN_MTU; 1774 if (sc->rx_ring_cnt > 1) 1775 ifp->if_capabilities |= IFCAP_RSS; 1776 ifp->if_capenable = ifp->if_capabilities; 1777 ifp->if_hwassist = EMX_CSUM_FEATURES; 1778 1779 /* 1780 * Tell the upper layer(s) we support long frames. 1781 */ 1782 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1783 1784 /* 1785 * Specify the media types supported by this sc and register 1786 * callbacks to update media and link information 1787 */ 1788 ifmedia_init(&sc->media, IFM_IMASK, 1789 emx_media_change, emx_media_status); 1790 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1791 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1792 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 1793 0, NULL); 1794 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1795 } else { 1796 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1797 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1798 0, NULL); 1799 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1800 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1801 0, NULL); 1802 if (sc->hw.phy.type != e1000_phy_ife) { 1803 ifmedia_add(&sc->media, 1804 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1805 ifmedia_add(&sc->media, 1806 IFM_ETHER | IFM_1000_T, 0, NULL); 1807 } 1808 } 1809 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1810 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1811 } 1812 1813 /* 1814 * Workaround for SmartSpeed on 82541 and 82547 controllers 1815 */ 1816 static void 1817 emx_smartspeed(struct emx_softc *sc) 1818 { 1819 uint16_t phy_tmp; 1820 1821 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp || 1822 sc->hw.mac.autoneg == 0 || 1823 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 1824 return; 1825 1826 if (sc->smartspeed == 0) { 1827 /* 1828 * If Master/Slave config fault is asserted twice, 1829 * we assume back-to-back 1830 */ 1831 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1832 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 1833 return; 1834 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1835 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 1836 e1000_read_phy_reg(&sc->hw, 1837 PHY_1000T_CTRL, &phy_tmp); 1838 if (phy_tmp & CR_1000T_MS_ENABLE) { 1839 phy_tmp &= ~CR_1000T_MS_ENABLE; 1840 e1000_write_phy_reg(&sc->hw, 1841 PHY_1000T_CTRL, phy_tmp); 1842 sc->smartspeed++; 1843 if (sc->hw.mac.autoneg && 1844 !e1000_phy_setup_autoneg(&sc->hw) && 1845 !e1000_read_phy_reg(&sc->hw, 1846 PHY_CONTROL, &phy_tmp)) { 1847 phy_tmp |= MII_CR_AUTO_NEG_EN | 1848 MII_CR_RESTART_AUTO_NEG; 1849 e1000_write_phy_reg(&sc->hw, 1850 PHY_CONTROL, phy_tmp); 1851 } 1852 } 1853 } 1854 return; 1855 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) { 1856 /* If still no link, perhaps using 2/3 pair cable */ 1857 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 1858 phy_tmp |= CR_1000T_MS_ENABLE; 1859 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 1860 if (sc->hw.mac.autoneg && 1861 !e1000_phy_setup_autoneg(&sc->hw) && 1862 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 1863 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 1864 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 1865 } 1866 } 1867 1868 /* Restart process after EMX_SMARTSPEED_MAX iterations */ 1869 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX) 1870 sc->smartspeed = 0; 1871 } 1872 1873 static int 1874 emx_create_tx_ring(struct emx_softc *sc) 1875 { 1876 device_t dev = sc->dev; 1877 struct emx_txbuf *tx_buffer; 1878 int error, i, tsize; 1879 1880 /* 1881 * Validate number of transmit descriptors. It must not exceed 1882 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 1883 */ 1884 if ((emx_txd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 || 1885 emx_txd > EMX_MAX_TXD || emx_txd < EMX_MIN_TXD) { 1886 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 1887 EMX_DEFAULT_TXD, emx_txd); 1888 sc->num_tx_desc = EMX_DEFAULT_TXD; 1889 } else { 1890 sc->num_tx_desc = emx_txd; 1891 } 1892 1893 /* 1894 * Allocate Transmit Descriptor ring 1895 */ 1896 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc), 1897 EMX_DBA_ALIGN); 1898 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag, 1899 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK, 1900 &sc->tx_desc_dtag, &sc->tx_desc_dmap, 1901 &sc->tx_desc_paddr); 1902 if (sc->tx_desc_base == NULL) { 1903 device_printf(dev, "Unable to allocate tx_desc memory\n"); 1904 return ENOMEM; 1905 } 1906 1907 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc, 1908 M_DEVBUF, M_WAITOK | M_ZERO); 1909 1910 /* 1911 * Create DMA tags for tx buffers 1912 */ 1913 error = bus_dma_tag_create(sc->parent_dtag, /* parent */ 1914 1, 0, /* alignment, bounds */ 1915 BUS_SPACE_MAXADDR, /* lowaddr */ 1916 BUS_SPACE_MAXADDR, /* highaddr */ 1917 NULL, NULL, /* filter, filterarg */ 1918 EMX_TSO_SIZE, /* maxsize */ 1919 EMX_MAX_SCATTER, /* nsegments */ 1920 EMX_MAX_SEGSIZE, /* maxsegsize */ 1921 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 1922 BUS_DMA_ONEBPAGE, /* flags */ 1923 &sc->txtag); 1924 if (error) { 1925 device_printf(dev, "Unable to allocate TX DMA tag\n"); 1926 kfree(sc->tx_buf, M_DEVBUF); 1927 sc->tx_buf = NULL; 1928 return error; 1929 } 1930 1931 /* 1932 * Create DMA maps for tx buffers 1933 */ 1934 for (i = 0; i < sc->num_tx_desc; i++) { 1935 tx_buffer = &sc->tx_buf[i]; 1936 1937 error = bus_dmamap_create(sc->txtag, 1938 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1939 &tx_buffer->map); 1940 if (error) { 1941 device_printf(dev, "Unable to create TX DMA map\n"); 1942 emx_destroy_tx_ring(sc, i); 1943 return error; 1944 } 1945 } 1946 return (0); 1947 } 1948 1949 static void 1950 emx_init_tx_ring(struct emx_softc *sc) 1951 { 1952 /* Clear the old ring contents */ 1953 bzero(sc->tx_desc_base, 1954 sizeof(struct e1000_tx_desc) * sc->num_tx_desc); 1955 1956 /* Reset state */ 1957 sc->next_avail_tx_desc = 0; 1958 sc->next_tx_to_clean = 0; 1959 sc->num_tx_desc_avail = sc->num_tx_desc; 1960 } 1961 1962 static void 1963 emx_init_tx_unit(struct emx_softc *sc) 1964 { 1965 uint32_t tctl, tarc, tipg = 0; 1966 uint64_t bus_addr; 1967 1968 /* Setup the Base and Length of the Tx Descriptor Ring */ 1969 bus_addr = sc->tx_desc_paddr; 1970 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0), 1971 sc->num_tx_desc * sizeof(struct e1000_tx_desc)); 1972 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0), 1973 (uint32_t)(bus_addr >> 32)); 1974 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0), 1975 (uint32_t)bus_addr); 1976 /* Setup the HW Tx Head and Tail descriptor pointers */ 1977 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0); 1978 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0); 1979 1980 /* Set the default values for the Tx Inter Packet Gap timer */ 1981 switch (sc->hw.mac.type) { 1982 case e1000_80003es2lan: 1983 tipg = DEFAULT_82543_TIPG_IPGR1; 1984 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 1985 E1000_TIPG_IPGR2_SHIFT; 1986 break; 1987 1988 default: 1989 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1990 sc->hw.phy.media_type == e1000_media_type_internal_serdes) 1991 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 1992 else 1993 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 1994 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 1995 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 1996 break; 1997 } 1998 1999 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg); 2000 2001 /* NOTE: 0 is not allowed for TIDV */ 2002 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1); 2003 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0); 2004 2005 if (sc->hw.mac.type == e1000_82571 || 2006 sc->hw.mac.type == e1000_82572) { 2007 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2008 tarc |= EMX_TARC_SPEED_MODE; 2009 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2010 } else if (sc->hw.mac.type == e1000_80003es2lan) { 2011 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2012 tarc |= 1; 2013 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2014 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2015 tarc |= 1; 2016 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2017 } 2018 2019 /* Program the Transmit Control Register */ 2020 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL); 2021 tctl &= ~E1000_TCTL_CT; 2022 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2023 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2024 tctl |= E1000_TCTL_MULR; 2025 2026 /* This write will effectively turn on the transmit unit. */ 2027 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl); 2028 } 2029 2030 static void 2031 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc) 2032 { 2033 struct emx_txbuf *tx_buffer; 2034 int i; 2035 2036 /* Free Transmit Descriptor ring */ 2037 if (sc->tx_desc_base) { 2038 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap); 2039 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base, 2040 sc->tx_desc_dmap); 2041 bus_dma_tag_destroy(sc->tx_desc_dtag); 2042 2043 sc->tx_desc_base = NULL; 2044 } 2045 2046 if (sc->tx_buf == NULL) 2047 return; 2048 2049 for (i = 0; i < ndesc; i++) { 2050 tx_buffer = &sc->tx_buf[i]; 2051 2052 KKASSERT(tx_buffer->m_head == NULL); 2053 bus_dmamap_destroy(sc->txtag, tx_buffer->map); 2054 } 2055 bus_dma_tag_destroy(sc->txtag); 2056 2057 kfree(sc->tx_buf, M_DEVBUF); 2058 sc->tx_buf = NULL; 2059 } 2060 2061 /* 2062 * The offload context needs to be set when we transfer the first 2063 * packet of a particular protocol (TCP/UDP). This routine has been 2064 * enhanced to deal with inserted VLAN headers. 2065 * 2066 * If the new packet's ether header length, ip header length and 2067 * csum offloading type are same as the previous packet, we should 2068 * avoid allocating a new csum context descriptor; mainly to take 2069 * advantage of the pipeline effect of the TX data read request. 2070 * 2071 * This function returns number of TX descrptors allocated for 2072 * csum context. 2073 */ 2074 static int 2075 emx_txcsum(struct emx_softc *sc, struct mbuf *mp, 2076 uint32_t *txd_upper, uint32_t *txd_lower) 2077 { 2078 struct e1000_context_desc *TXD; 2079 struct emx_txbuf *tx_buffer; 2080 struct ether_vlan_header *eh; 2081 struct ip *ip; 2082 int curr_txd, ehdrlen, csum_flags; 2083 uint32_t cmd, hdr_len, ip_hlen; 2084 uint16_t etype; 2085 2086 /* 2087 * Determine where frame payload starts. 2088 * Jump over vlan headers if already present, 2089 * helpful for QinQ too. 2090 */ 2091 KASSERT(mp->m_len >= ETHER_HDR_LEN, 2092 ("emx_txcsum_pullup is not called (eh)?\n")); 2093 eh = mtod(mp, struct ether_vlan_header *); 2094 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2095 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN, 2096 ("emx_txcsum_pullup is not called (evh)?\n")); 2097 etype = ntohs(eh->evl_proto); 2098 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN; 2099 } else { 2100 etype = ntohs(eh->evl_encap_proto); 2101 ehdrlen = ETHER_HDR_LEN; 2102 } 2103 2104 /* 2105 * We only support TCP/UDP for IPv4 for the moment. 2106 * TODO: Support SCTP too when it hits the tree. 2107 */ 2108 if (etype != ETHERTYPE_IP) 2109 return 0; 2110 2111 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE, 2112 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n")); 2113 2114 /* NOTE: We could only safely access ip.ip_vhl part */ 2115 ip = (struct ip *)(mp->m_data + ehdrlen); 2116 ip_hlen = ip->ip_hl << 2; 2117 2118 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES; 2119 2120 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen && 2121 sc->csum_flags == csum_flags) { 2122 /* 2123 * Same csum offload context as the previous packets; 2124 * just return. 2125 */ 2126 *txd_upper = sc->csum_txd_upper; 2127 *txd_lower = sc->csum_txd_lower; 2128 return 0; 2129 } 2130 2131 /* 2132 * Setup a new csum offload context. 2133 */ 2134 2135 curr_txd = sc->next_avail_tx_desc; 2136 tx_buffer = &sc->tx_buf[curr_txd]; 2137 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd]; 2138 2139 cmd = 0; 2140 2141 /* Setup of IP header checksum. */ 2142 if (csum_flags & CSUM_IP) { 2143 /* 2144 * Start offset for header checksum calculation. 2145 * End offset for header checksum calculation. 2146 * Offset of place to put the checksum. 2147 */ 2148 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2149 TXD->lower_setup.ip_fields.ipcse = 2150 htole16(ehdrlen + ip_hlen - 1); 2151 TXD->lower_setup.ip_fields.ipcso = 2152 ehdrlen + offsetof(struct ip, ip_sum); 2153 cmd |= E1000_TXD_CMD_IP; 2154 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2155 } 2156 hdr_len = ehdrlen + ip_hlen; 2157 2158 if (csum_flags & CSUM_TCP) { 2159 /* 2160 * Start offset for payload checksum calculation. 2161 * End offset for payload checksum calculation. 2162 * Offset of place to put the checksum. 2163 */ 2164 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2165 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2166 TXD->upper_setup.tcp_fields.tucso = 2167 hdr_len + offsetof(struct tcphdr, th_sum); 2168 cmd |= E1000_TXD_CMD_TCP; 2169 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2170 } else if (csum_flags & CSUM_UDP) { 2171 /* 2172 * Start offset for header checksum calculation. 2173 * End offset for header checksum calculation. 2174 * Offset of place to put the checksum. 2175 */ 2176 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2177 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2178 TXD->upper_setup.tcp_fields.tucso = 2179 hdr_len + offsetof(struct udphdr, uh_sum); 2180 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2181 } 2182 2183 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2184 E1000_TXD_DTYP_D; /* Data descr */ 2185 2186 /* Save the information for this csum offloading context */ 2187 sc->csum_ehlen = ehdrlen; 2188 sc->csum_iphlen = ip_hlen; 2189 sc->csum_flags = csum_flags; 2190 sc->csum_txd_upper = *txd_upper; 2191 sc->csum_txd_lower = *txd_lower; 2192 2193 TXD->tcp_seg_setup.data = htole32(0); 2194 TXD->cmd_and_length = 2195 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2196 2197 if (++curr_txd == sc->num_tx_desc) 2198 curr_txd = 0; 2199 2200 KKASSERT(sc->num_tx_desc_avail > 0); 2201 sc->num_tx_desc_avail--; 2202 2203 sc->next_avail_tx_desc = curr_txd; 2204 return 1; 2205 } 2206 2207 static int 2208 emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0) 2209 { 2210 struct mbuf *m = *m0; 2211 struct ether_header *eh; 2212 int len; 2213 2214 sc->tx_csum_try_pullup++; 2215 2216 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE; 2217 2218 if (__predict_false(!M_WRITABLE(m))) { 2219 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2220 sc->tx_csum_drop1++; 2221 m_freem(m); 2222 *m0 = NULL; 2223 return ENOBUFS; 2224 } 2225 eh = mtod(m, struct ether_header *); 2226 2227 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2228 len += EVL_ENCAPLEN; 2229 2230 if (m->m_len < len) { 2231 sc->tx_csum_drop2++; 2232 m_freem(m); 2233 *m0 = NULL; 2234 return ENOBUFS; 2235 } 2236 return 0; 2237 } 2238 2239 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2240 sc->tx_csum_pullup1++; 2241 m = m_pullup(m, ETHER_HDR_LEN); 2242 if (m == NULL) { 2243 sc->tx_csum_pullup1_failed++; 2244 *m0 = NULL; 2245 return ENOBUFS; 2246 } 2247 *m0 = m; 2248 } 2249 eh = mtod(m, struct ether_header *); 2250 2251 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2252 len += EVL_ENCAPLEN; 2253 2254 if (m->m_len < len) { 2255 sc->tx_csum_pullup2++; 2256 m = m_pullup(m, len); 2257 if (m == NULL) { 2258 sc->tx_csum_pullup2_failed++; 2259 *m0 = NULL; 2260 return ENOBUFS; 2261 } 2262 *m0 = m; 2263 } 2264 return 0; 2265 } 2266 2267 static void 2268 emx_txeof(struct emx_softc *sc) 2269 { 2270 struct ifnet *ifp = &sc->arpcom.ac_if; 2271 struct emx_txbuf *tx_buffer; 2272 int first, num_avail; 2273 2274 if (sc->tx_dd_head == sc->tx_dd_tail) 2275 return; 2276 2277 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2278 return; 2279 2280 num_avail = sc->num_tx_desc_avail; 2281 first = sc->next_tx_to_clean; 2282 2283 while (sc->tx_dd_head != sc->tx_dd_tail) { 2284 int dd_idx = sc->tx_dd[sc->tx_dd_head]; 2285 struct e1000_tx_desc *tx_desc; 2286 2287 tx_desc = &sc->tx_desc_base[dd_idx]; 2288 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2289 EMX_INC_TXDD_IDX(sc->tx_dd_head); 2290 2291 if (++dd_idx == sc->num_tx_desc) 2292 dd_idx = 0; 2293 2294 while (first != dd_idx) { 2295 logif(pkt_txclean); 2296 2297 num_avail++; 2298 2299 tx_buffer = &sc->tx_buf[first]; 2300 if (tx_buffer->m_head) { 2301 ifp->if_opackets++; 2302 bus_dmamap_unload(sc->txtag, 2303 tx_buffer->map); 2304 m_freem(tx_buffer->m_head); 2305 tx_buffer->m_head = NULL; 2306 } 2307 2308 if (++first == sc->num_tx_desc) 2309 first = 0; 2310 } 2311 } else { 2312 break; 2313 } 2314 } 2315 sc->next_tx_to_clean = first; 2316 sc->num_tx_desc_avail = num_avail; 2317 2318 if (sc->tx_dd_head == sc->tx_dd_tail) { 2319 sc->tx_dd_head = 0; 2320 sc->tx_dd_tail = 0; 2321 } 2322 2323 if (!EMX_IS_OACTIVE(sc)) { 2324 ifp->if_flags &= ~IFF_OACTIVE; 2325 2326 /* All clean, turn off the timer */ 2327 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2328 ifp->if_timer = 0; 2329 } 2330 } 2331 2332 static void 2333 emx_tx_collect(struct emx_softc *sc) 2334 { 2335 struct ifnet *ifp = &sc->arpcom.ac_if; 2336 struct emx_txbuf *tx_buffer; 2337 int tdh, first, num_avail, dd_idx = -1; 2338 2339 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2340 return; 2341 2342 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0)); 2343 if (tdh == sc->next_tx_to_clean) 2344 return; 2345 2346 if (sc->tx_dd_head != sc->tx_dd_tail) 2347 dd_idx = sc->tx_dd[sc->tx_dd_head]; 2348 2349 num_avail = sc->num_tx_desc_avail; 2350 first = sc->next_tx_to_clean; 2351 2352 while (first != tdh) { 2353 logif(pkt_txclean); 2354 2355 num_avail++; 2356 2357 tx_buffer = &sc->tx_buf[first]; 2358 if (tx_buffer->m_head) { 2359 ifp->if_opackets++; 2360 bus_dmamap_unload(sc->txtag, 2361 tx_buffer->map); 2362 m_freem(tx_buffer->m_head); 2363 tx_buffer->m_head = NULL; 2364 } 2365 2366 if (first == dd_idx) { 2367 EMX_INC_TXDD_IDX(sc->tx_dd_head); 2368 if (sc->tx_dd_head == sc->tx_dd_tail) { 2369 sc->tx_dd_head = 0; 2370 sc->tx_dd_tail = 0; 2371 dd_idx = -1; 2372 } else { 2373 dd_idx = sc->tx_dd[sc->tx_dd_head]; 2374 } 2375 } 2376 2377 if (++first == sc->num_tx_desc) 2378 first = 0; 2379 } 2380 sc->next_tx_to_clean = first; 2381 sc->num_tx_desc_avail = num_avail; 2382 2383 if (!EMX_IS_OACTIVE(sc)) { 2384 ifp->if_flags &= ~IFF_OACTIVE; 2385 2386 /* All clean, turn off the timer */ 2387 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2388 ifp->if_timer = 0; 2389 } 2390 } 2391 2392 /* 2393 * When Link is lost sometimes there is work still in the TX ring 2394 * which will result in a watchdog, rather than allow that do an 2395 * attempted cleanup and then reinit here. Note that this has been 2396 * seens mostly with fiber adapters. 2397 */ 2398 static void 2399 emx_tx_purge(struct emx_softc *sc) 2400 { 2401 struct ifnet *ifp = &sc->arpcom.ac_if; 2402 2403 if (!sc->link_active && ifp->if_timer) { 2404 emx_tx_collect(sc); 2405 if (ifp->if_timer) { 2406 if_printf(ifp, "Link lost, TX pending, reinit\n"); 2407 ifp->if_timer = 0; 2408 emx_init(sc); 2409 } 2410 } 2411 } 2412 2413 static int 2414 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init) 2415 { 2416 struct mbuf *m; 2417 bus_dma_segment_t seg; 2418 bus_dmamap_t map; 2419 struct emx_rxbuf *rx_buffer; 2420 int error, nseg; 2421 2422 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 2423 if (m == NULL) { 2424 rdata->mbuf_cluster_failed++; 2425 if (init) { 2426 if_printf(&sc->arpcom.ac_if, 2427 "Unable to allocate RX mbuf\n"); 2428 } 2429 return (ENOBUFS); 2430 } 2431 m->m_len = m->m_pkthdr.len = MCLBYTES; 2432 2433 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN) 2434 m_adj(m, ETHER_ALIGN); 2435 2436 error = bus_dmamap_load_mbuf_segment(rdata->rxtag, 2437 rdata->rx_sparemap, m, 2438 &seg, 1, &nseg, BUS_DMA_NOWAIT); 2439 if (error) { 2440 m_freem(m); 2441 if (init) { 2442 if_printf(&sc->arpcom.ac_if, 2443 "Unable to load RX mbuf\n"); 2444 } 2445 return (error); 2446 } 2447 2448 rx_buffer = &rdata->rx_buf[i]; 2449 if (rx_buffer->m_head != NULL) 2450 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2451 2452 map = rx_buffer->map; 2453 rx_buffer->map = rdata->rx_sparemap; 2454 rdata->rx_sparemap = map; 2455 2456 rx_buffer->m_head = m; 2457 rx_buffer->paddr = seg.ds_addr; 2458 2459 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer); 2460 return (0); 2461 } 2462 2463 static int 2464 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2465 { 2466 device_t dev = sc->dev; 2467 struct emx_rxbuf *rx_buffer; 2468 int i, error, rsize; 2469 2470 /* 2471 * Validate number of receive descriptors. It must not exceed 2472 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2473 */ 2474 if ((emx_rxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 || 2475 emx_rxd > EMX_MAX_RXD || emx_rxd < EMX_MIN_RXD) { 2476 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 2477 EMX_DEFAULT_RXD, emx_rxd); 2478 rdata->num_rx_desc = EMX_DEFAULT_RXD; 2479 } else { 2480 rdata->num_rx_desc = emx_rxd; 2481 } 2482 2483 /* 2484 * Allocate Receive Descriptor ring 2485 */ 2486 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t), 2487 EMX_DBA_ALIGN); 2488 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag, 2489 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK, 2490 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap, 2491 &rdata->rx_desc_paddr); 2492 if (rdata->rx_desc == NULL) { 2493 device_printf(dev, "Unable to allocate rx_desc memory\n"); 2494 return ENOMEM; 2495 } 2496 2497 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc, 2498 M_DEVBUF, M_WAITOK | M_ZERO); 2499 2500 /* 2501 * Create DMA tag for rx buffers 2502 */ 2503 error = bus_dma_tag_create(sc->parent_dtag, /* parent */ 2504 1, 0, /* alignment, bounds */ 2505 BUS_SPACE_MAXADDR, /* lowaddr */ 2506 BUS_SPACE_MAXADDR, /* highaddr */ 2507 NULL, NULL, /* filter, filterarg */ 2508 MCLBYTES, /* maxsize */ 2509 1, /* nsegments */ 2510 MCLBYTES, /* maxsegsize */ 2511 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 2512 &rdata->rxtag); 2513 if (error) { 2514 device_printf(dev, "Unable to allocate RX DMA tag\n"); 2515 kfree(rdata->rx_buf, M_DEVBUF); 2516 rdata->rx_buf = NULL; 2517 return error; 2518 } 2519 2520 /* 2521 * Create spare DMA map for rx buffers 2522 */ 2523 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2524 &rdata->rx_sparemap); 2525 if (error) { 2526 device_printf(dev, "Unable to create spare RX DMA map\n"); 2527 bus_dma_tag_destroy(rdata->rxtag); 2528 kfree(rdata->rx_buf, M_DEVBUF); 2529 rdata->rx_buf = NULL; 2530 return error; 2531 } 2532 2533 /* 2534 * Create DMA maps for rx buffers 2535 */ 2536 for (i = 0; i < rdata->num_rx_desc; i++) { 2537 rx_buffer = &rdata->rx_buf[i]; 2538 2539 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2540 &rx_buffer->map); 2541 if (error) { 2542 device_printf(dev, "Unable to create RX DMA map\n"); 2543 emx_destroy_rx_ring(sc, rdata, i); 2544 return error; 2545 } 2546 } 2547 return (0); 2548 } 2549 2550 static void 2551 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2552 { 2553 int i; 2554 2555 for (i = 0; i < rdata->num_rx_desc; i++) { 2556 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i]; 2557 2558 if (rx_buffer->m_head != NULL) { 2559 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2560 m_freem(rx_buffer->m_head); 2561 rx_buffer->m_head = NULL; 2562 } 2563 } 2564 2565 if (rdata->fmp != NULL) 2566 m_freem(rdata->fmp); 2567 rdata->fmp = NULL; 2568 rdata->lmp = NULL; 2569 } 2570 2571 static int 2572 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2573 { 2574 int i, error; 2575 2576 /* Reset descriptor ring */ 2577 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc); 2578 2579 /* Allocate new ones. */ 2580 for (i = 0; i < rdata->num_rx_desc; i++) { 2581 error = emx_newbuf(sc, rdata, i, 1); 2582 if (error) 2583 return (error); 2584 } 2585 2586 /* Setup our descriptor pointers */ 2587 rdata->next_rx_desc_to_check = 0; 2588 2589 return (0); 2590 } 2591 2592 static void 2593 emx_init_rx_unit(struct emx_softc *sc) 2594 { 2595 struct ifnet *ifp = &sc->arpcom.ac_if; 2596 uint64_t bus_addr; 2597 uint32_t rctl, rxcsum, rfctl; 2598 int i; 2599 2600 /* 2601 * Make sure receives are disabled while setting 2602 * up the descriptor ring 2603 */ 2604 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2605 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2606 2607 /* 2608 * Set the interrupt throttling rate. Value is calculated 2609 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 2610 */ 2611 if (sc->int_throttle_ceil) { 2612 E1000_WRITE_REG(&sc->hw, E1000_ITR, 2613 1000000000 / 256 / sc->int_throttle_ceil); 2614 } else { 2615 E1000_WRITE_REG(&sc->hw, E1000_ITR, 0); 2616 } 2617 2618 /* Use extended RX descriptor */ 2619 rfctl = E1000_RFCTL_EXTEN; 2620 2621 /* Disable accelerated ackknowledge */ 2622 if (sc->hw.mac.type == e1000_82574) 2623 rfctl |= E1000_RFCTL_ACK_DIS; 2624 2625 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl); 2626 2627 /* Setup the Base and Length of the Rx Descriptor Ring */ 2628 for (i = 0; i < sc->rx_ring_inuse; ++i) { 2629 struct emx_rxdata *rdata = &sc->rx_data[i]; 2630 2631 bus_addr = rdata->rx_desc_paddr; 2632 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i), 2633 rdata->num_rx_desc * sizeof(emx_rxdesc_t)); 2634 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i), 2635 (uint32_t)(bus_addr >> 32)); 2636 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i), 2637 (uint32_t)bus_addr); 2638 } 2639 2640 /* Setup the Receive Control Register */ 2641 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2642 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2643 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC | 2644 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2645 2646 /* Make sure VLAN Filters are off */ 2647 rctl &= ~E1000_RCTL_VFE; 2648 2649 /* Don't store bad paket */ 2650 rctl &= ~E1000_RCTL_SBP; 2651 2652 /* MCLBYTES */ 2653 rctl |= E1000_RCTL_SZ_2048; 2654 2655 if (ifp->if_mtu > ETHERMTU) 2656 rctl |= E1000_RCTL_LPE; 2657 else 2658 rctl &= ~E1000_RCTL_LPE; 2659 2660 /* 2661 * Receive Checksum Offload for TCP and UDP 2662 * 2663 * Checksum offloading is also enabled if multiple receive 2664 * queue is to be supported, since we need it to figure out 2665 * packet type. 2666 */ 2667 if (ifp->if_capenable & (IFCAP_RSS | IFCAP_RXCSUM)) { 2668 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM); 2669 2670 /* 2671 * NOTE: 2672 * PCSD must be enabled to enable multiple 2673 * receive queues. 2674 */ 2675 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL | 2676 E1000_RXCSUM_PCSD; 2677 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum); 2678 } 2679 2680 /* 2681 * Configure multiple receive queue (RSS) 2682 */ 2683 if (ifp->if_capenable & IFCAP_RSS) { 2684 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE]; 2685 uint32_t reta; 2686 2687 KASSERT(sc->rx_ring_inuse == EMX_NRX_RING, 2688 ("invalid number of RX ring (%d)", 2689 sc->rx_ring_inuse)); 2690 2691 /* 2692 * NOTE: 2693 * When we reach here, RSS has already been disabled 2694 * in emx_stop(), so we could safely configure RSS key 2695 * and redirect table. 2696 */ 2697 2698 /* 2699 * Configure RSS key 2700 */ 2701 toeplitz_get_key(key, sizeof(key)); 2702 for (i = 0; i < EMX_NRSSRK; ++i) { 2703 uint32_t rssrk; 2704 2705 rssrk = EMX_RSSRK_VAL(key, i); 2706 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk); 2707 2708 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk); 2709 } 2710 2711 /* 2712 * Configure RSS redirect table in following fashion: 2713 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2714 */ 2715 reta = 0; 2716 for (i = 0; i < EMX_RETA_SIZE; ++i) { 2717 uint32_t q; 2718 2719 q = (i % sc->rx_ring_inuse) << EMX_RETA_RINGIDX_SHIFT; 2720 reta |= q << (8 * i); 2721 } 2722 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta); 2723 2724 for (i = 0; i < EMX_NRETA; ++i) 2725 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta); 2726 2727 /* 2728 * Enable multiple receive queues. 2729 * Enable IPv4 RSS standard hash functions. 2730 * Disable RSS interrupt. 2731 */ 2732 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 2733 E1000_MRQC_ENABLE_RSS_2Q | 2734 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2735 E1000_MRQC_RSS_FIELD_IPV4); 2736 } 2737 2738 /* 2739 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2740 * long latencies are observed, like Lenovo X60. This 2741 * change eliminates the problem, but since having positive 2742 * values in RDTR is a known source of problems on other 2743 * platforms another solution is being sought. 2744 */ 2745 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) { 2746 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573); 2747 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573); 2748 } 2749 2750 /* 2751 * Setup the HW Rx Head and Tail Descriptor Pointers 2752 */ 2753 for (i = 0; i < sc->rx_ring_inuse; ++i) { 2754 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0); 2755 E1000_WRITE_REG(&sc->hw, E1000_RDT(i), 2756 sc->rx_data[i].num_rx_desc - 1); 2757 } 2758 2759 /* Enable Receives */ 2760 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 2761 } 2762 2763 static void 2764 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc) 2765 { 2766 struct emx_rxbuf *rx_buffer; 2767 int i; 2768 2769 /* Free Receive Descriptor ring */ 2770 if (rdata->rx_desc) { 2771 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap); 2772 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc, 2773 rdata->rx_desc_dmap); 2774 bus_dma_tag_destroy(rdata->rx_desc_dtag); 2775 2776 rdata->rx_desc = NULL; 2777 } 2778 2779 if (rdata->rx_buf == NULL) 2780 return; 2781 2782 for (i = 0; i < ndesc; i++) { 2783 rx_buffer = &rdata->rx_buf[i]; 2784 2785 KKASSERT(rx_buffer->m_head == NULL); 2786 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map); 2787 } 2788 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap); 2789 bus_dma_tag_destroy(rdata->rxtag); 2790 2791 kfree(rdata->rx_buf, M_DEVBUF); 2792 rdata->rx_buf = NULL; 2793 } 2794 2795 static void 2796 emx_rxeof(struct emx_softc *sc, int ring_idx, int count) 2797 { 2798 struct emx_rxdata *rdata = &sc->rx_data[ring_idx]; 2799 struct ifnet *ifp = &sc->arpcom.ac_if; 2800 uint32_t staterr; 2801 emx_rxdesc_t *current_desc; 2802 struct mbuf *mp; 2803 int i; 2804 struct mbuf_chain chain[MAXCPU]; 2805 2806 i = rdata->next_rx_desc_to_check; 2807 current_desc = &rdata->rx_desc[i]; 2808 staterr = le32toh(current_desc->rxd_staterr); 2809 2810 if (!(staterr & E1000_RXD_STAT_DD)) 2811 return; 2812 2813 ether_input_chain_init(chain); 2814 2815 while ((staterr & E1000_RXD_STAT_DD) && count != 0) { 2816 struct pktinfo *pi = NULL, pi0; 2817 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i]; 2818 struct mbuf *m = NULL; 2819 int eop, len; 2820 2821 logif(pkt_receive); 2822 2823 mp = rx_buf->m_head; 2824 2825 /* 2826 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 2827 * needs to access the last received byte in the mbuf. 2828 */ 2829 bus_dmamap_sync(rdata->rxtag, rx_buf->map, 2830 BUS_DMASYNC_POSTREAD); 2831 2832 len = le16toh(current_desc->rxd_length); 2833 if (staterr & E1000_RXD_STAT_EOP) { 2834 count--; 2835 eop = 1; 2836 } else { 2837 eop = 0; 2838 } 2839 2840 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) { 2841 uint16_t vlan = 0; 2842 uint32_t mrq, rss_hash; 2843 2844 /* 2845 * Save several necessary information, 2846 * before emx_newbuf() destroy it. 2847 */ 2848 if ((staterr & E1000_RXD_STAT_VP) && eop) 2849 vlan = le16toh(current_desc->rxd_vlan); 2850 2851 mrq = le32toh(current_desc->rxd_mrq); 2852 rss_hash = le32toh(current_desc->rxd_rss); 2853 2854 EMX_RSS_DPRINTF(sc, 10, 2855 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n", 2856 ring_idx, mrq, rss_hash); 2857 2858 if (emx_newbuf(sc, rdata, i, 0) != 0) { 2859 ifp->if_iqdrops++; 2860 goto discard; 2861 } 2862 2863 /* Assign correct length to the current fragment */ 2864 mp->m_len = len; 2865 2866 if (rdata->fmp == NULL) { 2867 mp->m_pkthdr.len = len; 2868 rdata->fmp = mp; /* Store the first mbuf */ 2869 rdata->lmp = mp; 2870 } else { 2871 /* 2872 * Chain mbuf's together 2873 */ 2874 rdata->lmp->m_next = mp; 2875 rdata->lmp = rdata->lmp->m_next; 2876 rdata->fmp->m_pkthdr.len += len; 2877 } 2878 2879 if (eop) { 2880 rdata->fmp->m_pkthdr.rcvif = ifp; 2881 ifp->if_ipackets++; 2882 2883 if (ifp->if_capenable & IFCAP_RXCSUM) 2884 emx_rxcsum(staterr, rdata->fmp); 2885 2886 if (staterr & E1000_RXD_STAT_VP) { 2887 rdata->fmp->m_pkthdr.ether_vlantag = 2888 vlan; 2889 rdata->fmp->m_flags |= M_VLANTAG; 2890 } 2891 m = rdata->fmp; 2892 rdata->fmp = NULL; 2893 rdata->lmp = NULL; 2894 2895 if (ifp->if_capenable & IFCAP_RSS) { 2896 pi = emx_rssinfo(m, &pi0, mrq, 2897 rss_hash, staterr); 2898 } 2899 #ifdef EMX_RSS_DEBUG 2900 rdata->rx_pkts++; 2901 #endif 2902 } 2903 } else { 2904 ifp->if_ierrors++; 2905 discard: 2906 emx_setup_rxdesc(current_desc, rx_buf); 2907 if (rdata->fmp != NULL) { 2908 m_freem(rdata->fmp); 2909 rdata->fmp = NULL; 2910 rdata->lmp = NULL; 2911 } 2912 m = NULL; 2913 } 2914 2915 if (m != NULL) 2916 ether_input_chain(ifp, m, pi, chain); 2917 2918 /* Advance our pointers to the next descriptor. */ 2919 if (++i == rdata->num_rx_desc) 2920 i = 0; 2921 2922 current_desc = &rdata->rx_desc[i]; 2923 staterr = le32toh(current_desc->rxd_staterr); 2924 } 2925 rdata->next_rx_desc_to_check = i; 2926 2927 ether_input_dispatch(chain); 2928 2929 /* Advance the E1000's Receive Queue "Tail Pointer". */ 2930 if (--i < 0) 2931 i = rdata->num_rx_desc - 1; 2932 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i); 2933 } 2934 2935 static void 2936 emx_enable_intr(struct emx_softc *sc) 2937 { 2938 lwkt_serialize_handler_enable(&sc->main_serialize); 2939 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK); 2940 } 2941 2942 static void 2943 emx_disable_intr(struct emx_softc *sc) 2944 { 2945 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 2946 lwkt_serialize_handler_disable(&sc->main_serialize); 2947 } 2948 2949 /* 2950 * Bit of a misnomer, what this really means is 2951 * to enable OS management of the system... aka 2952 * to disable special hardware management features 2953 */ 2954 static void 2955 emx_get_mgmt(struct emx_softc *sc) 2956 { 2957 /* A shared code workaround */ 2958 if (sc->has_manage) { 2959 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 2960 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 2961 2962 /* disable hardware interception of ARP */ 2963 manc &= ~(E1000_MANC_ARP_EN); 2964 2965 /* enable receiving management packets to the host */ 2966 manc |= E1000_MANC_EN_MNG2HOST; 2967 #define E1000_MNG2HOST_PORT_623 (1 << 5) 2968 #define E1000_MNG2HOST_PORT_664 (1 << 6) 2969 manc2h |= E1000_MNG2HOST_PORT_623; 2970 manc2h |= E1000_MNG2HOST_PORT_664; 2971 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 2972 2973 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 2974 } 2975 } 2976 2977 /* 2978 * Give control back to hardware management 2979 * controller if there is one. 2980 */ 2981 static void 2982 emx_rel_mgmt(struct emx_softc *sc) 2983 { 2984 if (sc->has_manage) { 2985 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 2986 2987 /* re-enable hardware interception of ARP */ 2988 manc |= E1000_MANC_ARP_EN; 2989 manc &= ~E1000_MANC_EN_MNG2HOST; 2990 2991 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 2992 } 2993 } 2994 2995 /* 2996 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 2997 * For ASF and Pass Through versions of f/w this means that 2998 * the driver is loaded. For AMT version (only with 82573) 2999 * of the f/w this means that the network i/f is open. 3000 */ 3001 static void 3002 emx_get_hw_control(struct emx_softc *sc) 3003 { 3004 uint32_t ctrl_ext, swsm; 3005 3006 /* Let firmware know the driver has taken over */ 3007 switch (sc->hw.mac.type) { 3008 case e1000_82573: 3009 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3010 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3011 swsm | E1000_SWSM_DRV_LOAD); 3012 break; 3013 3014 case e1000_82571: 3015 case e1000_82572: 3016 case e1000_80003es2lan: 3017 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3018 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3019 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3020 break; 3021 3022 default: 3023 break; 3024 } 3025 } 3026 3027 /* 3028 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3029 * For ASF and Pass Through versions of f/w this means that the 3030 * driver is no longer loaded. For AMT version (only with 82573) 3031 * of the f/w this means that the network i/f is closed. 3032 */ 3033 static void 3034 emx_rel_hw_control(struct emx_softc *sc) 3035 { 3036 uint32_t ctrl_ext, swsm; 3037 3038 /* Let firmware taken over control of h/w */ 3039 switch (sc->hw.mac.type) { 3040 case e1000_82573: 3041 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3042 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3043 swsm & ~E1000_SWSM_DRV_LOAD); 3044 break; 3045 3046 case e1000_82571: 3047 case e1000_82572: 3048 case e1000_80003es2lan: 3049 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3050 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3051 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3052 break; 3053 3054 default: 3055 break; 3056 } 3057 } 3058 3059 static int 3060 emx_is_valid_eaddr(const uint8_t *addr) 3061 { 3062 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3063 3064 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3065 return (FALSE); 3066 3067 return (TRUE); 3068 } 3069 3070 /* 3071 * Enable PCI Wake On Lan capability 3072 */ 3073 void 3074 emx_enable_wol(device_t dev) 3075 { 3076 uint16_t cap, status; 3077 uint8_t id; 3078 3079 /* First find the capabilities pointer*/ 3080 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3081 3082 /* Read the PM Capabilities */ 3083 id = pci_read_config(dev, cap, 1); 3084 if (id != PCIY_PMG) /* Something wrong */ 3085 return; 3086 3087 /* 3088 * OK, we have the power capabilities, 3089 * so now get the status register 3090 */ 3091 cap += PCIR_POWER_STATUS; 3092 status = pci_read_config(dev, cap, 2); 3093 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3094 pci_write_config(dev, cap, status, 2); 3095 } 3096 3097 static void 3098 emx_update_stats(struct emx_softc *sc) 3099 { 3100 struct ifnet *ifp = &sc->arpcom.ac_if; 3101 3102 if (sc->hw.phy.media_type == e1000_media_type_copper || 3103 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3104 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 3105 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 3106 } 3107 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 3108 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 3109 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 3110 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 3111 3112 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 3113 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 3114 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 3115 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 3116 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 3117 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 3118 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 3119 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 3120 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 3121 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 3122 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 3123 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 3124 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 3125 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 3126 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 3127 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 3128 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 3129 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 3130 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 3131 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 3132 3133 /* For the 64-bit byte counters the low dword must be read first. */ 3134 /* Both registers clear on the read of the high dword */ 3135 3136 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH); 3137 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH); 3138 3139 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 3140 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 3141 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 3142 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 3143 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 3144 3145 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 3146 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 3147 3148 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 3149 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 3150 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 3151 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 3152 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 3153 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 3154 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 3155 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 3156 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 3157 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 3158 3159 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 3160 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC); 3161 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS); 3162 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR); 3163 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC); 3164 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC); 3165 3166 ifp->if_collisions = sc->stats.colc; 3167 3168 /* Rx Errors */ 3169 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3170 sc->stats.crcerrs + sc->stats.algnerrc + 3171 sc->stats.ruc + sc->stats.roc + 3172 sc->stats.mpc + sc->stats.cexterr; 3173 3174 /* Tx Errors */ 3175 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3176 sc->watchdog_events; 3177 } 3178 3179 static void 3180 emx_print_debug_info(struct emx_softc *sc) 3181 { 3182 device_t dev = sc->dev; 3183 uint8_t *hw_addr = sc->hw.hw_addr; 3184 3185 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3186 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3187 E1000_READ_REG(&sc->hw, E1000_CTRL), 3188 E1000_READ_REG(&sc->hw, E1000_RCTL)); 3189 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3190 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3191 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) ); 3192 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3193 sc->hw.fc.high_water, sc->hw.fc.low_water); 3194 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3195 E1000_READ_REG(&sc->hw, E1000_TIDV), 3196 E1000_READ_REG(&sc->hw, E1000_TADV)); 3197 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3198 E1000_READ_REG(&sc->hw, E1000_RDTR), 3199 E1000_READ_REG(&sc->hw, E1000_RADV)); 3200 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3201 E1000_READ_REG(&sc->hw, E1000_TDH(0)), 3202 E1000_READ_REG(&sc->hw, E1000_TDT(0))); 3203 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3204 E1000_READ_REG(&sc->hw, E1000_RDH(0)), 3205 E1000_READ_REG(&sc->hw, E1000_RDT(0))); 3206 device_printf(dev, "Num Tx descriptors avail = %d\n", 3207 sc->num_tx_desc_avail); 3208 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3209 sc->no_tx_desc_avail1); 3210 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3211 sc->no_tx_desc_avail2); 3212 device_printf(dev, "Std mbuf failed = %ld\n", 3213 sc->mbuf_alloc_failed); 3214 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3215 sc->rx_data[0].mbuf_cluster_failed); 3216 device_printf(dev, "Driver dropped packets = %ld\n", 3217 sc->dropped_pkts); 3218 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3219 sc->no_tx_dma_setup); 3220 3221 device_printf(dev, "TXCSUM try pullup = %lu\n", 3222 sc->tx_csum_try_pullup); 3223 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n", 3224 sc->tx_csum_pullup1); 3225 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n", 3226 sc->tx_csum_pullup1_failed); 3227 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n", 3228 sc->tx_csum_pullup2); 3229 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n", 3230 sc->tx_csum_pullup2_failed); 3231 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n", 3232 sc->tx_csum_drop1); 3233 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n", 3234 sc->tx_csum_drop2); 3235 } 3236 3237 static void 3238 emx_print_hw_stats(struct emx_softc *sc) 3239 { 3240 device_t dev = sc->dev; 3241 3242 device_printf(dev, "Excessive collisions = %lld\n", 3243 (long long)sc->stats.ecol); 3244 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3245 device_printf(dev, "Symbol errors = %lld\n", 3246 (long long)sc->stats.symerrs); 3247 #endif 3248 device_printf(dev, "Sequence errors = %lld\n", 3249 (long long)sc->stats.sec); 3250 device_printf(dev, "Defer count = %lld\n", 3251 (long long)sc->stats.dc); 3252 device_printf(dev, "Missed Packets = %lld\n", 3253 (long long)sc->stats.mpc); 3254 device_printf(dev, "Receive No Buffers = %lld\n", 3255 (long long)sc->stats.rnbc); 3256 /* RLEC is inaccurate on some hardware, calculate our own. */ 3257 device_printf(dev, "Receive Length Errors = %lld\n", 3258 ((long long)sc->stats.roc + (long long)sc->stats.ruc)); 3259 device_printf(dev, "Receive errors = %lld\n", 3260 (long long)sc->stats.rxerrc); 3261 device_printf(dev, "Crc errors = %lld\n", 3262 (long long)sc->stats.crcerrs); 3263 device_printf(dev, "Alignment errors = %lld\n", 3264 (long long)sc->stats.algnerrc); 3265 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3266 (long long)sc->stats.cexterr); 3267 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3268 device_printf(dev, "watchdog timeouts = %ld\n", 3269 sc->watchdog_events); 3270 device_printf(dev, "XON Rcvd = %lld\n", 3271 (long long)sc->stats.xonrxc); 3272 device_printf(dev, "XON Xmtd = %lld\n", 3273 (long long)sc->stats.xontxc); 3274 device_printf(dev, "XOFF Rcvd = %lld\n", 3275 (long long)sc->stats.xoffrxc); 3276 device_printf(dev, "XOFF Xmtd = %lld\n", 3277 (long long)sc->stats.xofftxc); 3278 device_printf(dev, "Good Packets Rcvd = %lld\n", 3279 (long long)sc->stats.gprc); 3280 device_printf(dev, "Good Packets Xmtd = %lld\n", 3281 (long long)sc->stats.gptc); 3282 } 3283 3284 static void 3285 emx_print_nvm_info(struct emx_softc *sc) 3286 { 3287 uint16_t eeprom_data; 3288 int i, j, row = 0; 3289 3290 /* Its a bit crude, but it gets the job done */ 3291 kprintf("\nInterface EEPROM Dump:\n"); 3292 kprintf("Offset\n0x0000 "); 3293 for (i = 0, j = 0; i < 32; i++, j++) { 3294 if (j == 8) { /* Make the offset block */ 3295 j = 0; ++row; 3296 kprintf("\n0x00%x0 ",row); 3297 } 3298 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data); 3299 kprintf("%04x ", eeprom_data); 3300 } 3301 kprintf("\n"); 3302 } 3303 3304 static int 3305 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3306 { 3307 struct emx_softc *sc; 3308 struct ifnet *ifp; 3309 int error, result; 3310 3311 result = -1; 3312 error = sysctl_handle_int(oidp, &result, 0, req); 3313 if (error || !req->newptr) 3314 return (error); 3315 3316 sc = (struct emx_softc *)arg1; 3317 ifp = &sc->arpcom.ac_if; 3318 3319 ifnet_serialize_all(ifp); 3320 3321 if (result == 1) 3322 emx_print_debug_info(sc); 3323 3324 /* 3325 * This value will cause a hex dump of the 3326 * first 32 16-bit words of the EEPROM to 3327 * the screen. 3328 */ 3329 if (result == 2) 3330 emx_print_nvm_info(sc); 3331 3332 ifnet_deserialize_all(ifp); 3333 3334 return (error); 3335 } 3336 3337 static int 3338 emx_sysctl_stats(SYSCTL_HANDLER_ARGS) 3339 { 3340 int error, result; 3341 3342 result = -1; 3343 error = sysctl_handle_int(oidp, &result, 0, req); 3344 if (error || !req->newptr) 3345 return (error); 3346 3347 if (result == 1) { 3348 struct emx_softc *sc = (struct emx_softc *)arg1; 3349 struct ifnet *ifp = &sc->arpcom.ac_if; 3350 3351 ifnet_serialize_all(ifp); 3352 emx_print_hw_stats(sc); 3353 ifnet_deserialize_all(ifp); 3354 } 3355 return (error); 3356 } 3357 3358 static void 3359 emx_add_sysctl(struct emx_softc *sc) 3360 { 3361 #ifdef EMX_RSS_DEBUG 3362 char rx_pkt[32]; 3363 int i; 3364 #endif 3365 3366 sysctl_ctx_init(&sc->sysctl_ctx); 3367 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 3368 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 3369 device_get_nameunit(sc->dev), 3370 CTLFLAG_RD, 0, ""); 3371 if (sc->sysctl_tree == NULL) { 3372 device_printf(sc->dev, "can't add sysctl node\n"); 3373 return; 3374 } 3375 3376 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3377 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3378 emx_sysctl_debug_info, "I", "Debug Information"); 3379 3380 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3381 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3382 emx_sysctl_stats, "I", "Statistics"); 3383 3384 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3385 OID_AUTO, "rxd", CTLFLAG_RD, 3386 &sc->rx_data[0].num_rx_desc, 0, NULL); 3387 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3388 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL); 3389 3390 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3391 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, 3392 sc, 0, emx_sysctl_int_throttle, "I", 3393 "interrupt throttling rate"); 3394 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3395 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW, 3396 sc, 0, emx_sysctl_int_tx_nsegs, "I", 3397 "# segments per TX interrupt"); 3398 3399 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3400 OID_AUTO, "rx_ring_inuse", CTLFLAG_RD, 3401 &sc->rx_ring_inuse, 0, "RX ring in use"); 3402 3403 #ifdef EMX_RSS_DEBUG 3404 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3405 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 3406 0, "RSS debug level"); 3407 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3408 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i); 3409 SYSCTL_ADD_UINT(&sc->sysctl_ctx, 3410 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, 3411 rx_pkt, CTLFLAG_RW, 3412 &sc->rx_data[i].rx_pkts, 0, "RXed packets"); 3413 } 3414 #endif 3415 } 3416 3417 static int 3418 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 3419 { 3420 struct emx_softc *sc = (void *)arg1; 3421 struct ifnet *ifp = &sc->arpcom.ac_if; 3422 int error, throttle; 3423 3424 throttle = sc->int_throttle_ceil; 3425 error = sysctl_handle_int(oidp, &throttle, 0, req); 3426 if (error || req->newptr == NULL) 3427 return error; 3428 if (throttle < 0 || throttle > 1000000000 / 256) 3429 return EINVAL; 3430 3431 if (throttle) { 3432 /* 3433 * Set the interrupt throttling rate in 256ns increments, 3434 * recalculate sysctl value assignment to get exact frequency. 3435 */ 3436 throttle = 1000000000 / 256 / throttle; 3437 3438 /* Upper 16bits of ITR is reserved and should be zero */ 3439 if (throttle & 0xffff0000) 3440 return EINVAL; 3441 } 3442 3443 ifnet_serialize_all(ifp); 3444 3445 if (throttle) 3446 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 3447 else 3448 sc->int_throttle_ceil = 0; 3449 3450 if (ifp->if_flags & IFF_RUNNING) 3451 E1000_WRITE_REG(&sc->hw, E1000_ITR, throttle); 3452 3453 ifnet_deserialize_all(ifp); 3454 3455 if (bootverbose) { 3456 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 3457 sc->int_throttle_ceil); 3458 } 3459 return 0; 3460 } 3461 3462 static int 3463 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 3464 { 3465 struct emx_softc *sc = (void *)arg1; 3466 struct ifnet *ifp = &sc->arpcom.ac_if; 3467 int error, segs; 3468 3469 segs = sc->tx_int_nsegs; 3470 error = sysctl_handle_int(oidp, &segs, 0, req); 3471 if (error || req->newptr == NULL) 3472 return error; 3473 if (segs <= 0) 3474 return EINVAL; 3475 3476 ifnet_serialize_all(ifp); 3477 3478 /* 3479 * Don't allow int_tx_nsegs to become: 3480 * o Less the oact_tx_desc 3481 * o Too large that no TX desc will cause TX interrupt to 3482 * be generated (OACTIVE will never recover) 3483 * o Too small that will cause tx_dd[] overflow 3484 */ 3485 if (segs < sc->oact_tx_desc || 3486 segs >= sc->num_tx_desc - sc->oact_tx_desc || 3487 segs < sc->num_tx_desc / EMX_TXDD_SAFE) { 3488 error = EINVAL; 3489 } else { 3490 error = 0; 3491 sc->tx_int_nsegs = segs; 3492 } 3493 3494 ifnet_deserialize_all(ifp); 3495 3496 return error; 3497 } 3498 3499 static int 3500 emx_dma_alloc(struct emx_softc *sc) 3501 { 3502 int error, i; 3503 3504 /* 3505 * Create top level busdma tag 3506 */ 3507 error = bus_dma_tag_create(NULL, 1, 0, 3508 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3509 NULL, NULL, 3510 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3511 0, &sc->parent_dtag); 3512 if (error) { 3513 device_printf(sc->dev, "could not create top level DMA tag\n"); 3514 return error; 3515 } 3516 3517 /* 3518 * Allocate transmit descriptors ring and buffers 3519 */ 3520 error = emx_create_tx_ring(sc); 3521 if (error) { 3522 device_printf(sc->dev, "Could not setup transmit structures\n"); 3523 return error; 3524 } 3525 3526 /* 3527 * Allocate receive descriptors ring and buffers 3528 */ 3529 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3530 error = emx_create_rx_ring(sc, &sc->rx_data[i]); 3531 if (error) { 3532 device_printf(sc->dev, 3533 "Could not setup receive structures\n"); 3534 return error; 3535 } 3536 } 3537 return 0; 3538 } 3539 3540 static void 3541 emx_dma_free(struct emx_softc *sc) 3542 { 3543 int i; 3544 3545 emx_destroy_tx_ring(sc, sc->num_tx_desc); 3546 3547 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3548 emx_destroy_rx_ring(sc, &sc->rx_data[i], 3549 sc->rx_data[i].num_rx_desc); 3550 } 3551 3552 /* Free top level busdma tag */ 3553 if (sc->parent_dtag != NULL) 3554 bus_dma_tag_destroy(sc->parent_dtag); 3555 } 3556 3557 static void 3558 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 3559 { 3560 struct emx_softc *sc = ifp->if_softc; 3561 3562 switch (slz) { 3563 case IFNET_SERIALIZE_ALL: 3564 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 0); 3565 break; 3566 3567 case IFNET_SERIALIZE_MAIN: 3568 lwkt_serialize_enter(&sc->main_serialize); 3569 break; 3570 3571 case IFNET_SERIALIZE_TX: 3572 lwkt_serialize_enter(&sc->tx_serialize); 3573 break; 3574 3575 case IFNET_SERIALIZE_RX(0): 3576 lwkt_serialize_enter(&sc->rx_data[0].rx_serialize); 3577 break; 3578 3579 case IFNET_SERIALIZE_RX(1): 3580 lwkt_serialize_enter(&sc->rx_data[1].rx_serialize); 3581 break; 3582 3583 default: 3584 panic("%s unsupported serialize type\n", ifp->if_xname); 3585 } 3586 } 3587 3588 static void 3589 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3590 { 3591 struct emx_softc *sc = ifp->if_softc; 3592 3593 switch (slz) { 3594 case IFNET_SERIALIZE_ALL: 3595 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 0); 3596 break; 3597 3598 case IFNET_SERIALIZE_MAIN: 3599 lwkt_serialize_exit(&sc->main_serialize); 3600 break; 3601 3602 case IFNET_SERIALIZE_TX: 3603 lwkt_serialize_exit(&sc->tx_serialize); 3604 break; 3605 3606 case IFNET_SERIALIZE_RX(0): 3607 lwkt_serialize_exit(&sc->rx_data[0].rx_serialize); 3608 break; 3609 3610 case IFNET_SERIALIZE_RX(1): 3611 lwkt_serialize_exit(&sc->rx_data[1].rx_serialize); 3612 break; 3613 3614 default: 3615 panic("%s unsupported serialize type\n", ifp->if_xname); 3616 } 3617 } 3618 3619 static int 3620 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3621 { 3622 struct emx_softc *sc = ifp->if_softc; 3623 3624 switch (slz) { 3625 case IFNET_SERIALIZE_ALL: 3626 return lwkt_serialize_array_try(sc->serializes, 3627 EMX_NSERIALIZE, 0); 3628 3629 case IFNET_SERIALIZE_MAIN: 3630 return lwkt_serialize_try(&sc->main_serialize); 3631 3632 case IFNET_SERIALIZE_TX: 3633 return lwkt_serialize_try(&sc->tx_serialize); 3634 3635 case IFNET_SERIALIZE_RX(0): 3636 return lwkt_serialize_try(&sc->rx_data[0].rx_serialize); 3637 3638 case IFNET_SERIALIZE_RX(1): 3639 return lwkt_serialize_try(&sc->rx_data[1].rx_serialize); 3640 3641 default: 3642 panic("%s unsupported serialize type\n", ifp->if_xname); 3643 } 3644 } 3645 3646 static void 3647 emx_serialize_skipmain(struct emx_softc *sc) 3648 { 3649 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1); 3650 } 3651 3652 static void 3653 emx_deserialize_skipmain(struct emx_softc *sc) 3654 { 3655 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1); 3656 } 3657 3658 #ifdef INVARIANTS 3659 3660 static void 3661 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 3662 boolean_t serialized) 3663 { 3664 struct emx_softc *sc = ifp->if_softc; 3665 int i; 3666 3667 switch (slz) { 3668 case IFNET_SERIALIZE_ALL: 3669 if (serialized) { 3670 for (i = 0; i < EMX_NSERIALIZE; ++i) 3671 ASSERT_SERIALIZED(sc->serializes[i]); 3672 } else { 3673 for (i = 0; i < EMX_NSERIALIZE; ++i) 3674 ASSERT_NOT_SERIALIZED(sc->serializes[i]); 3675 } 3676 break; 3677 3678 case IFNET_SERIALIZE_MAIN: 3679 if (serialized) 3680 ASSERT_SERIALIZED(&sc->main_serialize); 3681 else 3682 ASSERT_NOT_SERIALIZED(&sc->main_serialize); 3683 break; 3684 3685 case IFNET_SERIALIZE_TX: 3686 if (serialized) 3687 ASSERT_SERIALIZED(&sc->tx_serialize); 3688 else 3689 ASSERT_NOT_SERIALIZED(&sc->tx_serialize); 3690 break; 3691 3692 case IFNET_SERIALIZE_RX(0): 3693 if (serialized) 3694 ASSERT_SERIALIZED(&sc->rx_data[0].rx_serialize); 3695 else 3696 ASSERT_NOT_SERIALIZED(&sc->rx_data[0].rx_serialize); 3697 break; 3698 3699 case IFNET_SERIALIZE_RX(1): 3700 if (serialized) 3701 ASSERT_SERIALIZED(&sc->rx_data[1].rx_serialize); 3702 else 3703 ASSERT_NOT_SERIALIZED(&sc->rx_data[1].rx_serialize); 3704 break; 3705 3706 default: 3707 panic("%s unsupported serialize type\n", ifp->if_xname); 3708 } 3709 } 3710 3711 #endif /* INVARIANTS */ 3712 3713 #ifdef IFPOLL_ENABLE 3714 3715 static void 3716 emx_qpoll_status(struct ifnet *ifp, int pollhz __unused) 3717 { 3718 struct emx_softc *sc = ifp->if_softc; 3719 uint32_t reg_icr; 3720 3721 ASSERT_SERIALIZED(&sc->main_serialize); 3722 3723 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 3724 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 3725 emx_serialize_skipmain(sc); 3726 3727 callout_stop(&sc->timer); 3728 sc->hw.mac.get_link_status = 1; 3729 emx_update_link_status(sc); 3730 callout_reset(&sc->timer, hz, emx_timer, sc); 3731 3732 emx_deserialize_skipmain(sc); 3733 } 3734 } 3735 3736 static void 3737 emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused) 3738 { 3739 struct emx_softc *sc = ifp->if_softc; 3740 3741 ASSERT_SERIALIZED(&sc->tx_serialize); 3742 3743 emx_txeof(sc); 3744 if (!ifq_is_empty(&ifp->if_snd)) 3745 if_devstart(ifp); 3746 } 3747 3748 static void 3749 emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle) 3750 { 3751 struct emx_softc *sc = ifp->if_softc; 3752 struct emx_rxdata *rdata = arg; 3753 3754 ASSERT_SERIALIZED(&rdata->rx_serialize); 3755 3756 emx_rxeof(sc, rdata - sc->rx_data, cycle); 3757 } 3758 3759 static void 3760 emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info) 3761 { 3762 struct emx_softc *sc = ifp->if_softc; 3763 3764 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3765 3766 if (info) { 3767 int i; 3768 3769 info->ifpi_status.status_func = emx_qpoll_status; 3770 info->ifpi_status.serializer = &sc->main_serialize; 3771 3772 info->ifpi_tx[0].poll_func = emx_qpoll_tx; 3773 info->ifpi_tx[0].arg = NULL; 3774 info->ifpi_tx[0].serializer = &sc->tx_serialize; 3775 3776 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3777 info->ifpi_rx[i].poll_func = emx_qpoll_rx; 3778 info->ifpi_rx[i].arg = &sc->rx_data[i]; 3779 info->ifpi_rx[i].serializer = 3780 &sc->rx_data[i].rx_serialize; 3781 } 3782 3783 if (ifp->if_flags & IFF_RUNNING) 3784 emx_disable_intr(sc); 3785 } else if (ifp->if_flags & IFF_RUNNING) { 3786 emx_enable_intr(sc); 3787 } 3788 } 3789 3790 #endif /* IFPOLL_ENABLE */ 3791