1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include "opt_ifpoll.h" 68 #include "opt_emx.h" 69 70 #include <sys/param.h> 71 #include <sys/bus.h> 72 #include <sys/endian.h> 73 #include <sys/interrupt.h> 74 #include <sys/kernel.h> 75 #include <sys/ktr.h> 76 #include <sys/malloc.h> 77 #include <sys/mbuf.h> 78 #include <sys/proc.h> 79 #include <sys/rman.h> 80 #include <sys/serialize.h> 81 #include <sys/serialize2.h> 82 #include <sys/socket.h> 83 #include <sys/sockio.h> 84 #include <sys/sysctl.h> 85 #include <sys/systm.h> 86 87 #include <net/bpf.h> 88 #include <net/ethernet.h> 89 #include <net/if.h> 90 #include <net/if_arp.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 #include <net/ifq_var.h> 94 #include <net/if_ringmap.h> 95 #include <net/toeplitz.h> 96 #include <net/toeplitz2.h> 97 #include <net/vlan/if_vlan_var.h> 98 #include <net/vlan/if_vlan_ether.h> 99 #include <net/if_poll.h> 100 101 #include <netinet/in_systm.h> 102 #include <netinet/in.h> 103 #include <netinet/ip.h> 104 #include <netinet/tcp.h> 105 #include <netinet/udp.h> 106 107 #include <bus/pci/pcivar.h> 108 #include <bus/pci/pcireg.h> 109 110 #include <dev/netif/ig_hal/e1000_api.h> 111 #include <dev/netif/ig_hal/e1000_82571.h> 112 #include <dev/netif/ig_hal/e1000_dragonfly.h> 113 #include <dev/netif/emx/if_emx.h> 114 115 #define DEBUG_HW 0 116 117 #ifdef EMX_RSS_DEBUG 118 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \ 119 do { \ 120 if (sc->rss_debug >= lvl) \ 121 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \ 122 } while (0) 123 #else /* !EMX_RSS_DEBUG */ 124 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 125 #endif /* EMX_RSS_DEBUG */ 126 127 #define EMX_NAME "Intel(R) PRO/1000 " 128 129 #define EMX_DEVICE(id) \ 130 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id } 131 #define EMX_DEVICE_NULL { 0, 0, NULL } 132 133 static const struct emx_device { 134 uint16_t vid; 135 uint16_t did; 136 const char *desc; 137 } emx_devices[] = { 138 EMX_DEVICE(82571EB_COPPER), 139 EMX_DEVICE(82571EB_FIBER), 140 EMX_DEVICE(82571EB_SERDES), 141 EMX_DEVICE(82571EB_SERDES_DUAL), 142 EMX_DEVICE(82571EB_SERDES_QUAD), 143 EMX_DEVICE(82571EB_QUAD_COPPER), 144 EMX_DEVICE(82571EB_QUAD_COPPER_BP), 145 EMX_DEVICE(82571EB_QUAD_COPPER_LP), 146 EMX_DEVICE(82571EB_QUAD_FIBER), 147 EMX_DEVICE(82571PT_QUAD_COPPER), 148 149 EMX_DEVICE(82572EI_COPPER), 150 EMX_DEVICE(82572EI_FIBER), 151 EMX_DEVICE(82572EI_SERDES), 152 EMX_DEVICE(82572EI), 153 154 EMX_DEVICE(82573E), 155 EMX_DEVICE(82573E_IAMT), 156 EMX_DEVICE(82573L), 157 158 EMX_DEVICE(80003ES2LAN_COPPER_SPT), 159 EMX_DEVICE(80003ES2LAN_SERDES_SPT), 160 EMX_DEVICE(80003ES2LAN_COPPER_DPT), 161 EMX_DEVICE(80003ES2LAN_SERDES_DPT), 162 163 EMX_DEVICE(82574L), 164 EMX_DEVICE(82574LA), 165 166 EMX_DEVICE(PCH_LPT_I217_LM), 167 EMX_DEVICE(PCH_LPT_I217_V), 168 EMX_DEVICE(PCH_LPTLP_I218_LM), 169 EMX_DEVICE(PCH_LPTLP_I218_V), 170 EMX_DEVICE(PCH_I218_LM2), 171 EMX_DEVICE(PCH_I218_V2), 172 EMX_DEVICE(PCH_I218_LM3), 173 EMX_DEVICE(PCH_I218_V3), 174 EMX_DEVICE(PCH_SPT_I219_LM), 175 EMX_DEVICE(PCH_SPT_I219_V), 176 EMX_DEVICE(PCH_SPT_I219_LM2), 177 EMX_DEVICE(PCH_SPT_I219_V2), 178 EMX_DEVICE(PCH_SPT_I219_LM3), 179 EMX_DEVICE(PCH_SPT_I219_LM4), 180 EMX_DEVICE(PCH_SPT_I219_V4), 181 EMX_DEVICE(PCH_SPT_I219_LM5), 182 EMX_DEVICE(PCH_SPT_I219_V5), 183 184 /* required last entry */ 185 EMX_DEVICE_NULL 186 }; 187 188 static int emx_probe(device_t); 189 static int emx_attach(device_t); 190 static int emx_detach(device_t); 191 static int emx_shutdown(device_t); 192 static int emx_suspend(device_t); 193 static int emx_resume(device_t); 194 195 static void emx_init(void *); 196 static void emx_stop(struct emx_softc *); 197 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 198 static void emx_start(struct ifnet *, struct ifaltq_subque *); 199 #ifdef IFPOLL_ENABLE 200 static void emx_npoll(struct ifnet *, struct ifpoll_info *); 201 static void emx_npoll_status(struct ifnet *); 202 static void emx_npoll_tx(struct ifnet *, void *, int); 203 static void emx_npoll_rx(struct ifnet *, void *, int); 204 #endif 205 static void emx_watchdog(struct ifaltq_subque *); 206 static void emx_media_status(struct ifnet *, struct ifmediareq *); 207 static int emx_media_change(struct ifnet *); 208 static void emx_timer(void *); 209 static void emx_serialize(struct ifnet *, enum ifnet_serialize); 210 static void emx_deserialize(struct ifnet *, enum ifnet_serialize); 211 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize); 212 #ifdef INVARIANTS 213 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize, 214 boolean_t); 215 #endif 216 217 static void emx_intr(void *); 218 static void emx_intr_mask(void *); 219 static void emx_intr_body(struct emx_softc *, boolean_t); 220 static void emx_rxeof(struct emx_rxdata *, int); 221 static void emx_txeof(struct emx_txdata *); 222 static void emx_tx_collect(struct emx_txdata *); 223 static void emx_tx_purge(struct emx_softc *); 224 static void emx_enable_intr(struct emx_softc *); 225 static void emx_disable_intr(struct emx_softc *); 226 227 static int emx_dma_alloc(struct emx_softc *); 228 static void emx_dma_free(struct emx_softc *); 229 static void emx_init_tx_ring(struct emx_txdata *); 230 static int emx_init_rx_ring(struct emx_rxdata *); 231 static void emx_free_tx_ring(struct emx_txdata *); 232 static void emx_free_rx_ring(struct emx_rxdata *); 233 static int emx_create_tx_ring(struct emx_txdata *); 234 static int emx_create_rx_ring(struct emx_rxdata *); 235 static void emx_destroy_tx_ring(struct emx_txdata *, int); 236 static void emx_destroy_rx_ring(struct emx_rxdata *, int); 237 static int emx_newbuf(struct emx_rxdata *, int, int); 238 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *); 239 static int emx_txcsum(struct emx_txdata *, struct mbuf *, 240 uint32_t *, uint32_t *); 241 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **); 242 static int emx_tso_setup(struct emx_txdata *, struct mbuf *, 243 uint32_t *, uint32_t *); 244 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t); 245 246 static int emx_is_valid_eaddr(const uint8_t *); 247 static int emx_reset(struct emx_softc *); 248 static void emx_setup_ifp(struct emx_softc *); 249 static void emx_init_tx_unit(struct emx_softc *); 250 static void emx_init_rx_unit(struct emx_softc *); 251 static void emx_update_stats(struct emx_softc *); 252 static void emx_set_promisc(struct emx_softc *); 253 static void emx_disable_promisc(struct emx_softc *); 254 static void emx_set_multi(struct emx_softc *); 255 static void emx_update_link_status(struct emx_softc *); 256 static void emx_smartspeed(struct emx_softc *); 257 static void emx_set_itr(struct emx_softc *, uint32_t); 258 static void emx_disable_aspm(struct emx_softc *); 259 260 static void emx_print_debug_info(struct emx_softc *); 261 static void emx_print_nvm_info(struct emx_softc *); 262 static void emx_print_hw_stats(struct emx_softc *); 263 264 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS); 265 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 266 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 267 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS); 268 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS); 269 static void emx_add_sysctl(struct emx_softc *); 270 271 static void emx_serialize_skipmain(struct emx_softc *); 272 static void emx_deserialize_skipmain(struct emx_softc *); 273 274 /* Management and WOL Support */ 275 static void emx_get_mgmt(struct emx_softc *); 276 static void emx_rel_mgmt(struct emx_softc *); 277 static void emx_get_hw_control(struct emx_softc *); 278 static void emx_rel_hw_control(struct emx_softc *); 279 static void emx_enable_wol(device_t); 280 281 static device_method_t emx_methods[] = { 282 /* Device interface */ 283 DEVMETHOD(device_probe, emx_probe), 284 DEVMETHOD(device_attach, emx_attach), 285 DEVMETHOD(device_detach, emx_detach), 286 DEVMETHOD(device_shutdown, emx_shutdown), 287 DEVMETHOD(device_suspend, emx_suspend), 288 DEVMETHOD(device_resume, emx_resume), 289 DEVMETHOD_END 290 }; 291 292 static driver_t emx_driver = { 293 "emx", 294 emx_methods, 295 sizeof(struct emx_softc), 296 }; 297 298 static devclass_t emx_devclass; 299 300 DECLARE_DUMMY_MODULE(if_emx); 301 MODULE_DEPEND(emx, ig_hal, 1, 1, 1); 302 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL); 303 304 /* 305 * Tunables 306 */ 307 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR; 308 static int emx_rxd = EMX_DEFAULT_RXD; 309 static int emx_txd = EMX_DEFAULT_TXD; 310 static int emx_smart_pwr_down = 0; 311 static int emx_rxr = 0; 312 static int emx_txr = 1; 313 314 /* Controls whether promiscuous also shows bad packets */ 315 static int emx_debug_sbp = 0; 316 317 static int emx_82573_workaround = 1; 318 static int emx_msi_enable = 1; 319 320 static char emx_flowctrl[IFM_ETH_FC_STRLEN] = IFM_ETH_FC_NONE; 321 322 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil); 323 TUNABLE_INT("hw.emx.rxd", &emx_rxd); 324 TUNABLE_INT("hw.emx.rxr", &emx_rxr); 325 TUNABLE_INT("hw.emx.txd", &emx_txd); 326 TUNABLE_INT("hw.emx.txr", &emx_txr); 327 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down); 328 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp); 329 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround); 330 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable); 331 TUNABLE_STR("hw.emx.flow_ctrl", emx_flowctrl, sizeof(emx_flowctrl)); 332 333 /* Global used in WOL setup with multiport cards */ 334 static int emx_global_quad_port_a = 0; 335 336 /* Set this to one to display debug statistics */ 337 static int emx_display_debug_stats = 0; 338 339 #if !defined(KTR_IF_EMX) 340 #define KTR_IF_EMX KTR_ALL 341 #endif 342 KTR_INFO_MASTER(if_emx); 343 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin"); 344 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end"); 345 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet"); 346 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet"); 347 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean"); 348 #define logif(name) KTR_LOG(if_emx_ ## name) 349 350 static __inline void 351 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf) 352 { 353 rxd->rxd_bufaddr = htole64(rxbuf->paddr); 354 /* DD bit must be cleared */ 355 rxd->rxd_staterr = 0; 356 } 357 358 static __inline void 359 emx_rxcsum(uint32_t staterr, struct mbuf *mp) 360 { 361 /* Ignore Checksum bit is set */ 362 if (staterr & E1000_RXD_STAT_IXSM) 363 return; 364 365 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) == 366 E1000_RXD_STAT_IPCS) 367 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 368 369 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 370 E1000_RXD_STAT_TCPCS) { 371 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 372 CSUM_PSEUDO_HDR | 373 CSUM_FRAG_NOT_CHECKED; 374 mp->m_pkthdr.csum_data = htons(0xffff); 375 } 376 } 377 378 static __inline struct pktinfo * 379 emx_rssinfo(struct mbuf *m, struct pktinfo *pi, 380 uint32_t mrq, uint32_t hash, uint32_t staterr) 381 { 382 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) { 383 case EMX_RXDMRQ_IPV4_TCP: 384 pi->pi_netisr = NETISR_IP; 385 pi->pi_flags = 0; 386 pi->pi_l3proto = IPPROTO_TCP; 387 break; 388 389 case EMX_RXDMRQ_IPV6_TCP: 390 pi->pi_netisr = NETISR_IPV6; 391 pi->pi_flags = 0; 392 pi->pi_l3proto = IPPROTO_TCP; 393 break; 394 395 case EMX_RXDMRQ_IPV4: 396 if (staterr & E1000_RXD_STAT_IXSM) 397 return NULL; 398 399 if ((staterr & 400 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 401 E1000_RXD_STAT_TCPCS) { 402 pi->pi_netisr = NETISR_IP; 403 pi->pi_flags = 0; 404 pi->pi_l3proto = IPPROTO_UDP; 405 break; 406 } 407 /* FALL THROUGH */ 408 default: 409 return NULL; 410 } 411 412 m_sethash(m, toeplitz_hash(hash)); 413 return pi; 414 } 415 416 static int 417 emx_probe(device_t dev) 418 { 419 const struct emx_device *d; 420 uint16_t vid, did; 421 422 vid = pci_get_vendor(dev); 423 did = pci_get_device(dev); 424 425 for (d = emx_devices; d->desc != NULL; ++d) { 426 if (vid == d->vid && did == d->did) { 427 device_set_desc(dev, d->desc); 428 device_set_async_attach(dev, TRUE); 429 return 0; 430 } 431 } 432 return ENXIO; 433 } 434 435 static int 436 emx_attach(device_t dev) 437 { 438 struct emx_softc *sc = device_get_softc(dev); 439 int error = 0, i, throttle, msi_enable; 440 int tx_ring_max, ring_cnt; 441 u_int intr_flags; 442 uint16_t eeprom_data, device_id, apme_mask; 443 driver_intr_t *intr_func; 444 char flowctrl[IFM_ETH_FC_STRLEN]; 445 446 /* 447 * Setup RX rings 448 */ 449 for (i = 0; i < EMX_NRX_RING; ++i) { 450 sc->rx_data[i].sc = sc; 451 sc->rx_data[i].idx = i; 452 } 453 454 /* 455 * Setup TX ring 456 */ 457 for (i = 0; i < EMX_NTX_RING; ++i) { 458 sc->tx_data[i].sc = sc; 459 sc->tx_data[i].idx = i; 460 } 461 462 /* 463 * Initialize serializers 464 */ 465 lwkt_serialize_init(&sc->main_serialize); 466 for (i = 0; i < EMX_NTX_RING; ++i) 467 lwkt_serialize_init(&sc->tx_data[i].tx_serialize); 468 for (i = 0; i < EMX_NRX_RING; ++i) 469 lwkt_serialize_init(&sc->rx_data[i].rx_serialize); 470 471 /* 472 * Initialize serializer array 473 */ 474 i = 0; 475 476 KKASSERT(i < EMX_NSERIALIZE); 477 sc->serializes[i++] = &sc->main_serialize; 478 479 KKASSERT(i < EMX_NSERIALIZE); 480 sc->serializes[i++] = &sc->tx_data[0].tx_serialize; 481 KKASSERT(i < EMX_NSERIALIZE); 482 sc->serializes[i++] = &sc->tx_data[1].tx_serialize; 483 484 KKASSERT(i < EMX_NSERIALIZE); 485 sc->serializes[i++] = &sc->rx_data[0].rx_serialize; 486 KKASSERT(i < EMX_NSERIALIZE); 487 sc->serializes[i++] = &sc->rx_data[1].rx_serialize; 488 489 KKASSERT(i == EMX_NSERIALIZE); 490 491 ifmedia_init(&sc->media, IFM_IMASK | IFM_ETH_FCMASK, 492 emx_media_change, emx_media_status); 493 callout_init_mp(&sc->timer); 494 495 sc->dev = sc->osdep.dev = dev; 496 497 /* 498 * Determine hardware and mac type 499 */ 500 sc->hw.vendor_id = pci_get_vendor(dev); 501 sc->hw.device_id = pci_get_device(dev); 502 sc->hw.revision_id = pci_get_revid(dev); 503 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev); 504 sc->hw.subsystem_device_id = pci_get_subdevice(dev); 505 506 if (e1000_set_mac_type(&sc->hw)) 507 return ENXIO; 508 509 /* Enable bus mastering */ 510 pci_enable_busmaster(dev); 511 512 /* 513 * Allocate IO memory 514 */ 515 sc->memory_rid = EMX_BAR_MEM; 516 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 517 &sc->memory_rid, RF_ACTIVE); 518 if (sc->memory == NULL) { 519 device_printf(dev, "Unable to allocate bus resource: memory\n"); 520 error = ENXIO; 521 goto fail; 522 } 523 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 524 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 525 526 /* XXX This is quite goofy, it is not actually used */ 527 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 528 529 /* 530 * Don't enable MSI-X on 82574, see: 531 * 82574 specification update errata #15 532 * 533 * Don't enable MSI on 82571/82572, see: 534 * 82571/82572 specification update errata #63 535 */ 536 msi_enable = emx_msi_enable; 537 if (msi_enable && 538 (sc->hw.mac.type == e1000_82571 || 539 sc->hw.mac.type == e1000_82572)) 540 msi_enable = 0; 541 again: 542 /* 543 * Allocate interrupt 544 */ 545 sc->intr_type = pci_alloc_1intr(dev, msi_enable, 546 &sc->intr_rid, &intr_flags); 547 548 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) { 549 int unshared; 550 551 unshared = device_getenv_int(dev, "irq.unshared", 0); 552 if (!unshared) { 553 sc->flags |= EMX_FLAG_SHARED_INTR; 554 if (bootverbose) 555 device_printf(dev, "IRQ shared\n"); 556 } else { 557 intr_flags &= ~RF_SHAREABLE; 558 if (bootverbose) 559 device_printf(dev, "IRQ unshared\n"); 560 } 561 } 562 563 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, 564 intr_flags); 565 if (sc->intr_res == NULL) { 566 device_printf(dev, "Unable to allocate bus resource: %s\n", 567 sc->intr_type == PCI_INTR_TYPE_MSI ? "MSI" : "legacy intr"); 568 if (!msi_enable) { 569 /* Retry with MSI. */ 570 msi_enable = 1; 571 sc->flags &= ~EMX_FLAG_SHARED_INTR; 572 goto again; 573 } 574 error = ENXIO; 575 goto fail; 576 } 577 578 /* Save PCI command register for Shared Code */ 579 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 580 sc->hw.back = &sc->osdep; 581 582 /* 583 * For I217/I218, we need to map the flash memory and this 584 * must happen after the MAC is identified. 585 */ 586 if (sc->hw.mac.type == e1000_pch_lpt) { 587 sc->flash_rid = EMX_BAR_FLASH; 588 589 sc->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 590 &sc->flash_rid, RF_ACTIVE); 591 if (sc->flash == NULL) { 592 device_printf(dev, "Mapping of Flash failed\n"); 593 error = ENXIO; 594 goto fail; 595 } 596 sc->osdep.flash_bus_space_tag = rman_get_bustag(sc->flash); 597 sc->osdep.flash_bus_space_handle = 598 rman_get_bushandle(sc->flash); 599 600 /* 601 * This is used in the shared code 602 * XXX this goof is actually not used. 603 */ 604 sc->hw.flash_address = (uint8_t *)sc->flash; 605 } 606 607 /* Do Shared Code initialization */ 608 if (e1000_setup_init_funcs(&sc->hw, TRUE)) { 609 device_printf(dev, "Setup of Shared code failed\n"); 610 error = ENXIO; 611 goto fail; 612 } 613 e1000_get_bus_info(&sc->hw); 614 615 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 616 sc->hw.phy.autoneg_wait_to_complete = FALSE; 617 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 618 619 /* 620 * Interrupt throttle rate 621 */ 622 throttle = device_getenv_int(dev, "int_throttle_ceil", 623 emx_int_throttle_ceil); 624 if (throttle == 0) { 625 sc->int_throttle_ceil = 0; 626 } else { 627 if (throttle < 0) 628 throttle = EMX_DEFAULT_ITR; 629 630 /* Recalculate the tunable value to get the exact frequency. */ 631 throttle = 1000000000 / 256 / throttle; 632 633 /* Upper 16bits of ITR is reserved and should be zero */ 634 if (throttle & 0xffff0000) 635 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR; 636 637 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 638 } 639 640 e1000_init_script_state_82541(&sc->hw, TRUE); 641 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE); 642 643 /* Copper options */ 644 if (sc->hw.phy.media_type == e1000_media_type_copper) { 645 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES; 646 sc->hw.phy.disable_polarity_correction = FALSE; 647 sc->hw.phy.ms_type = EMX_MASTER_SLAVE; 648 } 649 650 /* Set the frame limits assuming standard ethernet sized frames. */ 651 sc->hw.mac.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 652 653 /* This controls when hardware reports transmit completion status. */ 654 sc->hw.mac.report_tx_early = 1; 655 656 /* 657 * Calculate # of RX/TX rings 658 */ 659 ring_cnt = device_getenv_int(dev, "rxr", emx_rxr); 660 sc->rx_rmap = if_ringmap_alloc(dev, ring_cnt, EMX_NRX_RING); 661 662 tx_ring_max = 1; 663 if (sc->hw.mac.type == e1000_82571 || 664 sc->hw.mac.type == e1000_82572 || 665 sc->hw.mac.type == e1000_80003es2lan || 666 sc->hw.mac.type == e1000_pch_lpt || 667 sc->hw.mac.type == e1000_pch_spt || 668 sc->hw.mac.type == e1000_82574) 669 tx_ring_max = EMX_NTX_RING; 670 ring_cnt = device_getenv_int(dev, "txr", emx_txr); 671 sc->tx_rmap = if_ringmap_alloc(dev, ring_cnt, tx_ring_max); 672 673 if_ringmap_match(dev, sc->rx_rmap, sc->tx_rmap); 674 sc->rx_ring_cnt = if_ringmap_count(sc->rx_rmap); 675 sc->tx_ring_cnt = if_ringmap_count(sc->tx_rmap); 676 677 /* Allocate RX/TX rings' busdma(9) stuffs */ 678 error = emx_dma_alloc(sc); 679 if (error) 680 goto fail; 681 682 /* Allocate multicast array memory. */ 683 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX, 684 M_DEVBUF, M_WAITOK); 685 686 /* Indicate SOL/IDER usage */ 687 if (e1000_check_reset_block(&sc->hw)) { 688 device_printf(dev, 689 "PHY reset is blocked due to SOL/IDER session.\n"); 690 } 691 692 /* Disable EEE on I217/I218 */ 693 sc->hw.dev_spec.ich8lan.eee_disable = 1; 694 695 /* 696 * Start from a known state, this is important in reading the 697 * nvm and mac from that. 698 */ 699 e1000_reset_hw(&sc->hw); 700 701 /* Make sure we have a good EEPROM before we read from it */ 702 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 703 /* 704 * Some PCI-E parts fail the first check due to 705 * the link being in sleep state, call it again, 706 * if it fails a second time its a real issue. 707 */ 708 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 709 device_printf(dev, 710 "The EEPROM Checksum Is Not Valid\n"); 711 error = EIO; 712 goto fail; 713 } 714 } 715 716 /* Copy the permanent MAC address out of the EEPROM */ 717 if (e1000_read_mac_addr(&sc->hw) < 0) { 718 device_printf(dev, "EEPROM read error while reading MAC" 719 " address\n"); 720 error = EIO; 721 goto fail; 722 } 723 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) { 724 device_printf(dev, "Invalid MAC address\n"); 725 error = EIO; 726 goto fail; 727 } 728 729 /* Disable ULP support */ 730 e1000_disable_ulp_lpt_lp(&sc->hw, TRUE); 731 732 /* Determine if we have to control management hardware */ 733 if (e1000_enable_mng_pass_thru(&sc->hw)) 734 sc->flags |= EMX_FLAG_HAS_MGMT; 735 736 /* 737 * Setup Wake-on-Lan 738 */ 739 apme_mask = EMX_EEPROM_APME; 740 eeprom_data = 0; 741 switch (sc->hw.mac.type) { 742 case e1000_82573: 743 sc->flags |= EMX_FLAG_HAS_AMT; 744 /* FALL THROUGH */ 745 746 case e1000_82571: 747 case e1000_82572: 748 case e1000_80003es2lan: 749 if (sc->hw.bus.func == 1) { 750 e1000_read_nvm(&sc->hw, 751 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 752 } else { 753 e1000_read_nvm(&sc->hw, 754 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 755 } 756 break; 757 758 default: 759 e1000_read_nvm(&sc->hw, 760 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 761 break; 762 } 763 if (eeprom_data & apme_mask) 764 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 765 766 /* 767 * We have the eeprom settings, now apply the special cases 768 * where the eeprom may be wrong or the board won't support 769 * wake on lan on a particular port 770 */ 771 device_id = pci_get_device(dev); 772 switch (device_id) { 773 case E1000_DEV_ID_82571EB_FIBER: 774 /* 775 * Wake events only supported on port A for dual fiber 776 * regardless of eeprom setting 777 */ 778 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 779 E1000_STATUS_FUNC_1) 780 sc->wol = 0; 781 break; 782 783 case E1000_DEV_ID_82571EB_QUAD_COPPER: 784 case E1000_DEV_ID_82571EB_QUAD_FIBER: 785 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 786 /* if quad port sc, disable WoL on all but port A */ 787 if (emx_global_quad_port_a != 0) 788 sc->wol = 0; 789 /* Reset for multiple quad port adapters */ 790 if (++emx_global_quad_port_a == 4) 791 emx_global_quad_port_a = 0; 792 break; 793 } 794 795 /* XXX disable wol */ 796 sc->wol = 0; 797 798 /* Initialized #of TX rings to use. */ 799 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE); 800 801 /* Setup flow control. */ 802 device_getenv_string(dev, "flow_ctrl", flowctrl, sizeof(flowctrl), 803 emx_flowctrl); 804 sc->ifm_flowctrl = ifmedia_str2ethfc(flowctrl); 805 806 /* Setup OS specific network interface */ 807 emx_setup_ifp(sc); 808 809 /* Add sysctl tree, must after em_setup_ifp() */ 810 emx_add_sysctl(sc); 811 812 /* Reset the hardware */ 813 error = emx_reset(sc); 814 if (error) { 815 /* 816 * Some 82573 parts fail the first reset, call it again, 817 * if it fails a second time its a real issue. 818 */ 819 error = emx_reset(sc); 820 if (error) { 821 device_printf(dev, "Unable to reset the hardware\n"); 822 ether_ifdetach(&sc->arpcom.ac_if); 823 goto fail; 824 } 825 } 826 827 /* Initialize statistics */ 828 emx_update_stats(sc); 829 830 sc->hw.mac.get_link_status = 1; 831 emx_update_link_status(sc); 832 833 /* Non-AMT based hardware can now take control from firmware */ 834 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) == 835 EMX_FLAG_HAS_MGMT) 836 emx_get_hw_control(sc); 837 838 /* 839 * Missing Interrupt Following ICR read: 840 * 841 * 82571/82572 specification update errata #76 842 * 82573 specification update errata #31 843 * 82574 specification update errata #12 844 */ 845 intr_func = emx_intr; 846 if ((sc->flags & EMX_FLAG_SHARED_INTR) && 847 (sc->hw.mac.type == e1000_82571 || 848 sc->hw.mac.type == e1000_82572 || 849 sc->hw.mac.type == e1000_82573 || 850 sc->hw.mac.type == e1000_82574)) 851 intr_func = emx_intr_mask; 852 853 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc, 854 &sc->intr_tag, &sc->main_serialize); 855 if (error) { 856 device_printf(dev, "Failed to register interrupt handler"); 857 ether_ifdetach(&sc->arpcom.ac_if); 858 goto fail; 859 } 860 return (0); 861 fail: 862 emx_detach(dev); 863 return (error); 864 } 865 866 static int 867 emx_detach(device_t dev) 868 { 869 struct emx_softc *sc = device_get_softc(dev); 870 871 if (device_is_attached(dev)) { 872 struct ifnet *ifp = &sc->arpcom.ac_if; 873 874 ifnet_serialize_all(ifp); 875 876 emx_stop(sc); 877 878 e1000_phy_hw_reset(&sc->hw); 879 880 emx_rel_mgmt(sc); 881 emx_rel_hw_control(sc); 882 883 if (sc->wol) { 884 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 885 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 886 emx_enable_wol(dev); 887 } 888 889 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag); 890 891 ifnet_deserialize_all(ifp); 892 893 ether_ifdetach(ifp); 894 } else if (sc->memory != NULL) { 895 emx_rel_hw_control(sc); 896 } 897 898 ifmedia_removeall(&sc->media); 899 bus_generic_detach(dev); 900 901 if (sc->intr_res != NULL) { 902 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, 903 sc->intr_res); 904 } 905 906 if (sc->intr_type == PCI_INTR_TYPE_MSI) 907 pci_release_msi(dev); 908 909 if (sc->memory != NULL) { 910 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid, 911 sc->memory); 912 } 913 914 if (sc->flash != NULL) { 915 bus_release_resource(dev, SYS_RES_MEMORY, sc->flash_rid, 916 sc->flash); 917 } 918 919 emx_dma_free(sc); 920 921 if (sc->mta != NULL) 922 kfree(sc->mta, M_DEVBUF); 923 924 if (sc->rx_rmap != NULL) 925 if_ringmap_free(sc->rx_rmap); 926 if (sc->tx_rmap != NULL) 927 if_ringmap_free(sc->tx_rmap); 928 929 return (0); 930 } 931 932 static int 933 emx_shutdown(device_t dev) 934 { 935 return emx_suspend(dev); 936 } 937 938 static int 939 emx_suspend(device_t dev) 940 { 941 struct emx_softc *sc = device_get_softc(dev); 942 struct ifnet *ifp = &sc->arpcom.ac_if; 943 944 ifnet_serialize_all(ifp); 945 946 emx_stop(sc); 947 948 emx_rel_mgmt(sc); 949 emx_rel_hw_control(sc); 950 951 if (sc->wol) { 952 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 953 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 954 emx_enable_wol(dev); 955 } 956 957 ifnet_deserialize_all(ifp); 958 959 return bus_generic_suspend(dev); 960 } 961 962 static int 963 emx_resume(device_t dev) 964 { 965 struct emx_softc *sc = device_get_softc(dev); 966 struct ifnet *ifp = &sc->arpcom.ac_if; 967 int i; 968 969 ifnet_serialize_all(ifp); 970 971 emx_init(sc); 972 emx_get_mgmt(sc); 973 for (i = 0; i < sc->tx_ring_inuse; ++i) 974 ifsq_devstart_sched(sc->tx_data[i].ifsq); 975 976 ifnet_deserialize_all(ifp); 977 978 return bus_generic_resume(dev); 979 } 980 981 static void 982 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 983 { 984 struct emx_softc *sc = ifp->if_softc; 985 struct emx_txdata *tdata = ifsq_get_priv(ifsq); 986 struct mbuf *m_head; 987 int idx = -1, nsegs = 0; 988 989 KKASSERT(tdata->ifsq == ifsq); 990 ASSERT_SERIALIZED(&tdata->tx_serialize); 991 992 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq)) 993 return; 994 995 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) { 996 ifsq_purge(ifsq); 997 return; 998 } 999 1000 while (!ifsq_is_empty(ifsq)) { 1001 /* Now do we at least have a minimal? */ 1002 if (EMX_IS_OACTIVE(tdata)) { 1003 emx_tx_collect(tdata); 1004 if (EMX_IS_OACTIVE(tdata)) { 1005 ifsq_set_oactive(ifsq); 1006 break; 1007 } 1008 } 1009 1010 logif(pkt_txqueue); 1011 m_head = ifsq_dequeue(ifsq); 1012 if (m_head == NULL) 1013 break; 1014 1015 if (emx_encap(tdata, &m_head, &nsegs, &idx)) { 1016 IFNET_STAT_INC(ifp, oerrors, 1); 1017 emx_tx_collect(tdata); 1018 continue; 1019 } 1020 1021 /* 1022 * TX interrupt are aggressively aggregated, so increasing 1023 * opackets at TX interrupt time will make the opackets 1024 * statistics vastly inaccurate; we do the opackets increment 1025 * now. 1026 */ 1027 IFNET_STAT_INC(ifp, opackets, 1); 1028 1029 if (nsegs >= tdata->tx_wreg_nsegs) { 1030 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx); 1031 nsegs = 0; 1032 idx = -1; 1033 } 1034 1035 /* Send a copy of the frame to the BPF listener */ 1036 ETHER_BPF_MTAP(ifp, m_head); 1037 1038 /* Set timeout in case hardware has problems transmitting. */ 1039 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT; 1040 } 1041 if (idx >= 0) 1042 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx); 1043 } 1044 1045 static int 1046 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1047 { 1048 struct emx_softc *sc = ifp->if_softc; 1049 struct ifreq *ifr = (struct ifreq *)data; 1050 uint16_t eeprom_data = 0; 1051 int max_frame_size, mask, reinit; 1052 int error = 0; 1053 1054 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1055 1056 switch (command) { 1057 case SIOCSIFMTU: 1058 switch (sc->hw.mac.type) { 1059 case e1000_82573: 1060 /* 1061 * 82573 only supports jumbo frames 1062 * if ASPM is disabled. 1063 */ 1064 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1, 1065 &eeprom_data); 1066 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1067 max_frame_size = ETHER_MAX_LEN; 1068 break; 1069 } 1070 /* FALL THROUGH */ 1071 1072 /* Limit Jumbo Frame size */ 1073 case e1000_82571: 1074 case e1000_82572: 1075 case e1000_82574: 1076 case e1000_pch_lpt: 1077 case e1000_pch_spt: 1078 case e1000_80003es2lan: 1079 max_frame_size = 9234; 1080 break; 1081 1082 default: 1083 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1084 break; 1085 } 1086 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1087 ETHER_CRC_LEN) { 1088 error = EINVAL; 1089 break; 1090 } 1091 1092 ifp->if_mtu = ifr->ifr_mtu; 1093 sc->hw.mac.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + 1094 ETHER_CRC_LEN; 1095 1096 if (ifp->if_flags & IFF_RUNNING) 1097 emx_init(sc); 1098 break; 1099 1100 case SIOCSIFFLAGS: 1101 if (ifp->if_flags & IFF_UP) { 1102 if ((ifp->if_flags & IFF_RUNNING)) { 1103 if ((ifp->if_flags ^ sc->if_flags) & 1104 (IFF_PROMISC | IFF_ALLMULTI)) { 1105 emx_disable_promisc(sc); 1106 emx_set_promisc(sc); 1107 } 1108 } else { 1109 emx_init(sc); 1110 } 1111 } else if (ifp->if_flags & IFF_RUNNING) { 1112 emx_stop(sc); 1113 } 1114 sc->if_flags = ifp->if_flags; 1115 break; 1116 1117 case SIOCADDMULTI: 1118 case SIOCDELMULTI: 1119 if (ifp->if_flags & IFF_RUNNING) { 1120 emx_disable_intr(sc); 1121 emx_set_multi(sc); 1122 #ifdef IFPOLL_ENABLE 1123 if (!(ifp->if_flags & IFF_NPOLLING)) 1124 #endif 1125 emx_enable_intr(sc); 1126 } 1127 break; 1128 1129 case SIOCSIFMEDIA: 1130 /* Check SOL/IDER usage */ 1131 if (e1000_check_reset_block(&sc->hw)) { 1132 device_printf(sc->dev, "Media change is" 1133 " blocked due to SOL/IDER session.\n"); 1134 break; 1135 } 1136 /* FALL THROUGH */ 1137 1138 case SIOCGIFMEDIA: 1139 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 1140 break; 1141 1142 case SIOCSIFCAP: 1143 reinit = 0; 1144 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1145 if (mask & IFCAP_RXCSUM) { 1146 ifp->if_capenable ^= IFCAP_RXCSUM; 1147 reinit = 1; 1148 } 1149 if (mask & IFCAP_VLAN_HWTAGGING) { 1150 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1151 reinit = 1; 1152 } 1153 if (mask & IFCAP_TXCSUM) { 1154 ifp->if_capenable ^= IFCAP_TXCSUM; 1155 if (ifp->if_capenable & IFCAP_TXCSUM) 1156 ifp->if_hwassist |= EMX_CSUM_FEATURES; 1157 else 1158 ifp->if_hwassist &= ~EMX_CSUM_FEATURES; 1159 } 1160 if (mask & IFCAP_TSO) { 1161 ifp->if_capenable ^= IFCAP_TSO; 1162 if (ifp->if_capenable & IFCAP_TSO) 1163 ifp->if_hwassist |= CSUM_TSO; 1164 else 1165 ifp->if_hwassist &= ~CSUM_TSO; 1166 } 1167 if (mask & IFCAP_RSS) 1168 ifp->if_capenable ^= IFCAP_RSS; 1169 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1170 emx_init(sc); 1171 break; 1172 1173 default: 1174 error = ether_ioctl(ifp, command, data); 1175 break; 1176 } 1177 return (error); 1178 } 1179 1180 static void 1181 emx_watchdog(struct ifaltq_subque *ifsq) 1182 { 1183 struct emx_txdata *tdata = ifsq_get_priv(ifsq); 1184 struct ifnet *ifp = ifsq_get_ifp(ifsq); 1185 struct emx_softc *sc = ifp->if_softc; 1186 int i; 1187 1188 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1189 1190 /* 1191 * The timer is set to 5 every time start queues a packet. 1192 * Then txeof keeps resetting it as long as it cleans at 1193 * least one descriptor. 1194 * Finally, anytime all descriptors are clean the timer is 1195 * set to 0. 1196 */ 1197 1198 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) == 1199 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) { 1200 /* 1201 * If we reach here, all TX jobs are completed and 1202 * the TX engine should have been idled for some time. 1203 * We don't need to call ifsq_devstart_sched() here. 1204 */ 1205 ifsq_clr_oactive(ifsq); 1206 tdata->tx_watchdog.wd_timer = 0; 1207 return; 1208 } 1209 1210 /* 1211 * If we are in this routine because of pause frames, then 1212 * don't reset the hardware. 1213 */ 1214 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) { 1215 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT; 1216 return; 1217 } 1218 1219 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx); 1220 1221 IFNET_STAT_INC(ifp, oerrors, 1); 1222 1223 emx_init(sc); 1224 for (i = 0; i < sc->tx_ring_inuse; ++i) 1225 ifsq_devstart_sched(sc->tx_data[i].ifsq); 1226 } 1227 1228 static void 1229 emx_init(void *xsc) 1230 { 1231 struct emx_softc *sc = xsc; 1232 struct ifnet *ifp = &sc->arpcom.ac_if; 1233 device_t dev = sc->dev; 1234 boolean_t polling; 1235 int i; 1236 1237 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1238 1239 emx_stop(sc); 1240 1241 /* Get the latest mac address, User can use a LAA */ 1242 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1243 1244 /* Put the address into the Receive Address Array */ 1245 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1246 1247 /* 1248 * With the 82571 sc, RAR[0] may be overwritten 1249 * when the other port is reset, we make a duplicate 1250 * in RAR[14] for that eventuality, this assures 1251 * the interface continues to function. 1252 */ 1253 if (sc->hw.mac.type == e1000_82571) { 1254 e1000_set_laa_state_82571(&sc->hw, TRUE); 1255 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1256 E1000_RAR_ENTRIES - 1); 1257 } 1258 1259 /* Initialize the hardware */ 1260 if (emx_reset(sc)) { 1261 device_printf(dev, "Unable to reset the hardware\n"); 1262 /* XXX emx_stop()? */ 1263 return; 1264 } 1265 emx_update_link_status(sc); 1266 1267 /* Setup VLAN support, basic and offload if available */ 1268 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1269 1270 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1271 uint32_t ctrl; 1272 1273 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 1274 ctrl |= E1000_CTRL_VME; 1275 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 1276 } 1277 1278 /* Configure for OS presence */ 1279 emx_get_mgmt(sc); 1280 1281 polling = FALSE; 1282 #ifdef IFPOLL_ENABLE 1283 if (ifp->if_flags & IFF_NPOLLING) 1284 polling = TRUE; 1285 #endif 1286 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling); 1287 ifq_set_subq_divisor(&ifp->if_snd, sc->tx_ring_inuse); 1288 1289 /* Prepare transmit descriptors and buffers */ 1290 for (i = 0; i < sc->tx_ring_inuse; ++i) 1291 emx_init_tx_ring(&sc->tx_data[i]); 1292 emx_init_tx_unit(sc); 1293 1294 /* Setup Multicast table */ 1295 emx_set_multi(sc); 1296 1297 /* Prepare receive descriptors and buffers */ 1298 for (i = 0; i < sc->rx_ring_cnt; ++i) { 1299 if (emx_init_rx_ring(&sc->rx_data[i])) { 1300 device_printf(dev, 1301 "Could not setup receive structures\n"); 1302 emx_stop(sc); 1303 return; 1304 } 1305 } 1306 emx_init_rx_unit(sc); 1307 1308 /* Don't lose promiscuous settings */ 1309 emx_set_promisc(sc); 1310 1311 ifp->if_flags |= IFF_RUNNING; 1312 for (i = 0; i < sc->tx_ring_inuse; ++i) { 1313 ifsq_clr_oactive(sc->tx_data[i].ifsq); 1314 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog); 1315 } 1316 1317 callout_reset(&sc->timer, hz, emx_timer, sc); 1318 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1319 1320 /* MSI/X configuration for 82574 */ 1321 if (sc->hw.mac.type == e1000_82574) { 1322 int tmp; 1323 1324 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1325 tmp |= E1000_CTRL_EXT_PBA_CLR; 1326 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1327 /* 1328 * XXX MSIX 1329 * Set the IVAR - interrupt vector routing. 1330 * Each nibble represents a vector, high bit 1331 * is enable, other 3 bits are the MSIX table 1332 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1333 * Link (other) to 2, hence the magic number. 1334 */ 1335 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908); 1336 } 1337 1338 /* 1339 * Only enable interrupts if we are not polling, make sure 1340 * they are off otherwise. 1341 */ 1342 if (polling) 1343 emx_disable_intr(sc); 1344 else 1345 emx_enable_intr(sc); 1346 1347 /* AMT based hardware can now take control from firmware */ 1348 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) == 1349 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) 1350 emx_get_hw_control(sc); 1351 } 1352 1353 static void 1354 emx_intr(void *xsc) 1355 { 1356 emx_intr_body(xsc, TRUE); 1357 } 1358 1359 static void 1360 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted) 1361 { 1362 struct ifnet *ifp = &sc->arpcom.ac_if; 1363 uint32_t reg_icr; 1364 1365 logif(intr_beg); 1366 ASSERT_SERIALIZED(&sc->main_serialize); 1367 1368 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1369 1370 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) { 1371 logif(intr_end); 1372 return; 1373 } 1374 1375 /* 1376 * XXX: some laptops trigger several spurious interrupts 1377 * on emx(4) when in the resume cycle. The ICR register 1378 * reports all-ones value in this case. Processing such 1379 * interrupts would lead to a freeze. I don't know why. 1380 */ 1381 if (reg_icr == 0xffffffff) { 1382 logif(intr_end); 1383 return; 1384 } 1385 1386 if (ifp->if_flags & IFF_RUNNING) { 1387 if (reg_icr & 1388 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) { 1389 int i; 1390 1391 for (i = 0; i < sc->rx_ring_cnt; ++i) { 1392 lwkt_serialize_enter( 1393 &sc->rx_data[i].rx_serialize); 1394 emx_rxeof(&sc->rx_data[i], -1); 1395 lwkt_serialize_exit( 1396 &sc->rx_data[i].rx_serialize); 1397 } 1398 } 1399 if (reg_icr & E1000_ICR_TXDW) { 1400 struct emx_txdata *tdata = &sc->tx_data[0]; 1401 1402 lwkt_serialize_enter(&tdata->tx_serialize); 1403 emx_txeof(tdata); 1404 if (!ifsq_is_empty(tdata->ifsq)) 1405 ifsq_devstart(tdata->ifsq); 1406 lwkt_serialize_exit(&tdata->tx_serialize); 1407 } 1408 } 1409 1410 /* Link status change */ 1411 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1412 emx_serialize_skipmain(sc); 1413 1414 callout_stop(&sc->timer); 1415 sc->hw.mac.get_link_status = 1; 1416 emx_update_link_status(sc); 1417 1418 /* Deal with TX cruft when link lost */ 1419 emx_tx_purge(sc); 1420 1421 callout_reset(&sc->timer, hz, emx_timer, sc); 1422 1423 emx_deserialize_skipmain(sc); 1424 } 1425 1426 if (reg_icr & E1000_ICR_RXO) 1427 sc->rx_overruns++; 1428 1429 logif(intr_end); 1430 } 1431 1432 static void 1433 emx_intr_mask(void *xsc) 1434 { 1435 struct emx_softc *sc = xsc; 1436 1437 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 1438 /* 1439 * NOTE: 1440 * ICR.INT_ASSERTED bit will never be set if IMS is 0, 1441 * so don't check it. 1442 */ 1443 emx_intr_body(sc, FALSE); 1444 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK); 1445 } 1446 1447 static void 1448 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1449 { 1450 struct emx_softc *sc = ifp->if_softc; 1451 1452 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1453 1454 emx_update_link_status(sc); 1455 1456 ifmr->ifm_status = IFM_AVALID; 1457 ifmr->ifm_active = IFM_ETHER; 1458 1459 if (!sc->link_active) { 1460 if (sc->hw.mac.autoneg) 1461 ifmr->ifm_active |= IFM_NONE; 1462 else 1463 ifmr->ifm_active |= sc->media.ifm_media; 1464 return; 1465 } 1466 1467 ifmr->ifm_status |= IFM_ACTIVE; 1468 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE) 1469 ifmr->ifm_active |= sc->ifm_flowctrl; 1470 1471 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1472 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1473 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1474 } else { 1475 switch (sc->link_speed) { 1476 case 10: 1477 ifmr->ifm_active |= IFM_10_T; 1478 break; 1479 case 100: 1480 ifmr->ifm_active |= IFM_100_TX; 1481 break; 1482 1483 case 1000: 1484 ifmr->ifm_active |= IFM_1000_T; 1485 break; 1486 } 1487 if (sc->link_duplex == FULL_DUPLEX) 1488 ifmr->ifm_active |= IFM_FDX; 1489 else 1490 ifmr->ifm_active |= IFM_HDX; 1491 } 1492 if (ifmr->ifm_active & IFM_FDX) 1493 ifmr->ifm_active |= e1000_fc2ifmedia(sc->hw.fc.current_mode); 1494 } 1495 1496 static int 1497 emx_media_change(struct ifnet *ifp) 1498 { 1499 struct emx_softc *sc = ifp->if_softc; 1500 struct ifmedia *ifm = &sc->media; 1501 1502 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1503 1504 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1505 return (EINVAL); 1506 1507 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1508 case IFM_AUTO: 1509 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1510 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 1511 break; 1512 1513 case IFM_1000_SX: 1514 case IFM_1000_T: 1515 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1516 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1517 break; 1518 1519 case IFM_100_TX: 1520 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) { 1521 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1522 } else { 1523 if (IFM_OPTIONS(ifm->ifm_media) & 1524 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 1525 if (bootverbose) { 1526 if_printf(ifp, "Flow control is not " 1527 "allowed for half-duplex\n"); 1528 } 1529 return EINVAL; 1530 } 1531 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1532 } 1533 sc->hw.mac.autoneg = FALSE; 1534 sc->hw.phy.autoneg_advertised = 0; 1535 break; 1536 1537 case IFM_10_T: 1538 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) { 1539 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1540 } else { 1541 if (IFM_OPTIONS(ifm->ifm_media) & 1542 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 1543 if (bootverbose) { 1544 if_printf(ifp, "Flow control is not " 1545 "allowed for half-duplex\n"); 1546 } 1547 return EINVAL; 1548 } 1549 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1550 } 1551 sc->hw.mac.autoneg = FALSE; 1552 sc->hw.phy.autoneg_advertised = 0; 1553 break; 1554 1555 default: 1556 if (bootverbose) { 1557 if_printf(ifp, "Unsupported media type %d\n", 1558 IFM_SUBTYPE(ifm->ifm_media)); 1559 } 1560 return EINVAL; 1561 } 1562 sc->ifm_flowctrl = ifm->ifm_media & IFM_ETH_FCMASK; 1563 1564 if (ifp->if_flags & IFF_RUNNING) 1565 emx_init(sc); 1566 1567 return (0); 1568 } 1569 1570 static int 1571 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp, 1572 int *segs_used, int *idx) 1573 { 1574 bus_dma_segment_t segs[EMX_MAX_SCATTER]; 1575 bus_dmamap_t map; 1576 struct emx_txbuf *tx_buffer, *tx_buffer_mapped; 1577 struct e1000_tx_desc *ctxd = NULL; 1578 struct mbuf *m_head = *m_headp; 1579 uint32_t txd_upper, txd_lower, cmd = 0; 1580 int maxsegs, nsegs, i, j, first, last = 0, error; 1581 1582 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1583 error = emx_tso_pullup(tdata, m_headp); 1584 if (error) 1585 return error; 1586 m_head = *m_headp; 1587 } 1588 1589 txd_upper = txd_lower = 0; 1590 1591 /* 1592 * Capture the first descriptor index, this descriptor 1593 * will have the index of the EOP which is the only one 1594 * that now gets a DONE bit writeback. 1595 */ 1596 first = tdata->next_avail_tx_desc; 1597 tx_buffer = &tdata->tx_buf[first]; 1598 tx_buffer_mapped = tx_buffer; 1599 map = tx_buffer->map; 1600 1601 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED; 1602 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc")); 1603 if (maxsegs > EMX_MAX_SCATTER) 1604 maxsegs = EMX_MAX_SCATTER; 1605 1606 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp, 1607 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1608 if (error) { 1609 m_freem(*m_headp); 1610 *m_headp = NULL; 1611 return error; 1612 } 1613 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE); 1614 1615 m_head = *m_headp; 1616 tdata->tx_nsegs += nsegs; 1617 *segs_used += nsegs; 1618 1619 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1620 /* TSO will consume one TX desc */ 1621 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower); 1622 tdata->tx_nsegs += i; 1623 *segs_used += i; 1624 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) { 1625 /* TX csum offloading will consume one TX desc */ 1626 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower); 1627 tdata->tx_nsegs += i; 1628 *segs_used += i; 1629 } 1630 1631 /* Handle VLAN tag */ 1632 if (m_head->m_flags & M_VLANTAG) { 1633 /* Set the vlan id. */ 1634 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16); 1635 /* Tell hardware to add tag */ 1636 txd_lower |= htole32(E1000_TXD_CMD_VLE); 1637 } 1638 1639 i = tdata->next_avail_tx_desc; 1640 1641 /* Set up our transmit descriptors */ 1642 for (j = 0; j < nsegs; j++) { 1643 tx_buffer = &tdata->tx_buf[i]; 1644 ctxd = &tdata->tx_desc_base[i]; 1645 1646 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1647 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1648 txd_lower | segs[j].ds_len); 1649 ctxd->upper.data = htole32(txd_upper); 1650 1651 last = i; 1652 if (++i == tdata->num_tx_desc) 1653 i = 0; 1654 } 1655 1656 tdata->next_avail_tx_desc = i; 1657 1658 KKASSERT(tdata->num_tx_desc_avail > nsegs); 1659 tdata->num_tx_desc_avail -= nsegs; 1660 1661 tx_buffer->m_head = m_head; 1662 tx_buffer_mapped->map = tx_buffer->map; 1663 tx_buffer->map = map; 1664 1665 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) { 1666 tdata->tx_nsegs = 0; 1667 1668 /* 1669 * Report Status (RS) is turned on 1670 * every tx_intr_nsegs descriptors. 1671 */ 1672 cmd = E1000_TXD_CMD_RS; 1673 1674 /* 1675 * Keep track of the descriptor, which will 1676 * be written back by hardware. 1677 */ 1678 tdata->tx_dd[tdata->tx_dd_tail] = last; 1679 EMX_INC_TXDD_IDX(tdata->tx_dd_tail); 1680 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head); 1681 } 1682 1683 /* 1684 * Last Descriptor of Packet needs End Of Packet (EOP) 1685 */ 1686 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1687 1688 /* 1689 * Defer TDT updating, until enough descriptors are setup 1690 */ 1691 *idx = i; 1692 1693 #ifdef EMX_TSS_DEBUG 1694 tdata->tx_pkts++; 1695 #endif 1696 1697 return (0); 1698 } 1699 1700 static void 1701 emx_set_promisc(struct emx_softc *sc) 1702 { 1703 struct ifnet *ifp = &sc->arpcom.ac_if; 1704 uint32_t reg_rctl; 1705 1706 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1707 1708 if (ifp->if_flags & IFF_PROMISC) { 1709 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1710 /* Turn this on if you want to see bad packets */ 1711 if (emx_debug_sbp) 1712 reg_rctl |= E1000_RCTL_SBP; 1713 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1714 } else if (ifp->if_flags & IFF_ALLMULTI) { 1715 reg_rctl |= E1000_RCTL_MPE; 1716 reg_rctl &= ~E1000_RCTL_UPE; 1717 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1718 } 1719 } 1720 1721 static void 1722 emx_disable_promisc(struct emx_softc *sc) 1723 { 1724 uint32_t reg_rctl; 1725 1726 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1727 1728 reg_rctl &= ~E1000_RCTL_UPE; 1729 reg_rctl &= ~E1000_RCTL_MPE; 1730 reg_rctl &= ~E1000_RCTL_SBP; 1731 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1732 } 1733 1734 static void 1735 emx_set_multi(struct emx_softc *sc) 1736 { 1737 struct ifnet *ifp = &sc->arpcom.ac_if; 1738 struct ifmultiaddr *ifma; 1739 uint32_t reg_rctl = 0; 1740 uint8_t *mta; 1741 int mcnt = 0; 1742 1743 mta = sc->mta; 1744 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX); 1745 1746 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1747 if (ifma->ifma_addr->sa_family != AF_LINK) 1748 continue; 1749 1750 if (mcnt == EMX_MCAST_ADDR_MAX) 1751 break; 1752 1753 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1754 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1755 mcnt++; 1756 } 1757 1758 if (mcnt >= EMX_MCAST_ADDR_MAX) { 1759 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1760 reg_rctl |= E1000_RCTL_MPE; 1761 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1762 } else { 1763 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1764 } 1765 } 1766 1767 /* 1768 * This routine checks for link status and updates statistics. 1769 */ 1770 static void 1771 emx_timer(void *xsc) 1772 { 1773 struct emx_softc *sc = xsc; 1774 struct ifnet *ifp = &sc->arpcom.ac_if; 1775 1776 lwkt_serialize_enter(&sc->main_serialize); 1777 1778 emx_update_link_status(sc); 1779 emx_update_stats(sc); 1780 1781 /* Reset LAA into RAR[0] on 82571 */ 1782 if (e1000_get_laa_state_82571(&sc->hw) == TRUE) 1783 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1784 1785 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1786 emx_print_hw_stats(sc); 1787 1788 emx_smartspeed(sc); 1789 1790 callout_reset(&sc->timer, hz, emx_timer, sc); 1791 1792 lwkt_serialize_exit(&sc->main_serialize); 1793 } 1794 1795 static void 1796 emx_update_link_status(struct emx_softc *sc) 1797 { 1798 struct e1000_hw *hw = &sc->hw; 1799 struct ifnet *ifp = &sc->arpcom.ac_if; 1800 device_t dev = sc->dev; 1801 uint32_t link_check = 0; 1802 1803 /* Get the cached link value or read phy for real */ 1804 switch (hw->phy.media_type) { 1805 case e1000_media_type_copper: 1806 if (hw->mac.get_link_status) { 1807 /* Do the work to read phy */ 1808 e1000_check_for_link(hw); 1809 link_check = !hw->mac.get_link_status; 1810 if (link_check) /* ESB2 fix */ 1811 e1000_cfg_on_link_up(hw); 1812 } else { 1813 link_check = TRUE; 1814 } 1815 break; 1816 1817 case e1000_media_type_fiber: 1818 e1000_check_for_link(hw); 1819 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 1820 break; 1821 1822 case e1000_media_type_internal_serdes: 1823 e1000_check_for_link(hw); 1824 link_check = sc->hw.mac.serdes_has_link; 1825 break; 1826 1827 case e1000_media_type_unknown: 1828 default: 1829 break; 1830 } 1831 1832 /* Now check for a transition */ 1833 if (link_check && sc->link_active == 0) { 1834 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1835 &sc->link_duplex); 1836 1837 /* 1838 * Check if we should enable/disable SPEED_MODE bit on 1839 * 82571EB/82572EI 1840 */ 1841 if (sc->link_speed != SPEED_1000 && 1842 (hw->mac.type == e1000_82571 || 1843 hw->mac.type == e1000_82572)) { 1844 int tarc0; 1845 1846 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1847 tarc0 &= ~EMX_TARC_SPEED_MODE; 1848 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1849 } 1850 if (bootverbose) { 1851 char flowctrl[IFM_ETH_FC_STRLEN]; 1852 1853 e1000_fc2str(hw->fc.current_mode, flowctrl, 1854 sizeof(flowctrl)); 1855 device_printf(dev, "Link is up %d Mbps %s, " 1856 "Flow control: %s\n", 1857 sc->link_speed, 1858 (sc->link_duplex == FULL_DUPLEX) ? 1859 "Full Duplex" : "Half Duplex", 1860 flowctrl); 1861 } 1862 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE) 1863 e1000_force_flowctrl(hw, sc->ifm_flowctrl); 1864 sc->link_active = 1; 1865 sc->smartspeed = 0; 1866 ifp->if_baudrate = sc->link_speed * 1000000; 1867 ifp->if_link_state = LINK_STATE_UP; 1868 if_link_state_change(ifp); 1869 } else if (!link_check && sc->link_active == 1) { 1870 ifp->if_baudrate = sc->link_speed = 0; 1871 sc->link_duplex = 0; 1872 if (bootverbose) 1873 device_printf(dev, "Link is Down\n"); 1874 sc->link_active = 0; 1875 ifp->if_link_state = LINK_STATE_DOWN; 1876 if_link_state_change(ifp); 1877 } 1878 } 1879 1880 static void 1881 emx_stop(struct emx_softc *sc) 1882 { 1883 struct ifnet *ifp = &sc->arpcom.ac_if; 1884 int i; 1885 1886 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1887 1888 emx_disable_intr(sc); 1889 1890 callout_stop(&sc->timer); 1891 1892 ifp->if_flags &= ~IFF_RUNNING; 1893 for (i = 0; i < sc->tx_ring_cnt; ++i) { 1894 struct emx_txdata *tdata = &sc->tx_data[i]; 1895 1896 ifsq_clr_oactive(tdata->ifsq); 1897 ifsq_watchdog_stop(&tdata->tx_watchdog); 1898 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED; 1899 } 1900 1901 /* 1902 * Disable multiple receive queues. 1903 * 1904 * NOTE: 1905 * We should disable multiple receive queues before 1906 * resetting the hardware. 1907 */ 1908 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0); 1909 1910 e1000_reset_hw(&sc->hw); 1911 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1912 1913 for (i = 0; i < sc->tx_ring_cnt; ++i) 1914 emx_free_tx_ring(&sc->tx_data[i]); 1915 for (i = 0; i < sc->rx_ring_cnt; ++i) 1916 emx_free_rx_ring(&sc->rx_data[i]); 1917 } 1918 1919 static int 1920 emx_reset(struct emx_softc *sc) 1921 { 1922 device_t dev = sc->dev; 1923 uint16_t rx_buffer_size; 1924 uint32_t pba; 1925 1926 /* Set up smart power down as default off on newer adapters. */ 1927 if (!emx_smart_pwr_down && 1928 (sc->hw.mac.type == e1000_82571 || 1929 sc->hw.mac.type == e1000_82572)) { 1930 uint16_t phy_tmp = 0; 1931 1932 /* Speed up time to link by disabling smart power down. */ 1933 e1000_read_phy_reg(&sc->hw, 1934 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1935 phy_tmp &= ~IGP02E1000_PM_SPD; 1936 e1000_write_phy_reg(&sc->hw, 1937 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1938 } 1939 1940 /* 1941 * Packet Buffer Allocation (PBA) 1942 * Writing PBA sets the receive portion of the buffer 1943 * the remainder is used for the transmit buffer. 1944 */ 1945 switch (sc->hw.mac.type) { 1946 /* Total Packet Buffer on these is 48K */ 1947 case e1000_82571: 1948 case e1000_82572: 1949 case e1000_80003es2lan: 1950 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1951 break; 1952 1953 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1954 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1955 break; 1956 1957 case e1000_82574: 1958 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1959 break; 1960 1961 case e1000_pch_lpt: 1962 case e1000_pch_spt: 1963 pba = E1000_PBA_26K; 1964 break; 1965 1966 default: 1967 /* Devices before 82547 had a Packet Buffer of 64K. */ 1968 if (sc->hw.mac.max_frame_size > 8192) 1969 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1970 else 1971 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1972 } 1973 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba); 1974 1975 /* 1976 * These parameters control the automatic generation (Tx) and 1977 * response (Rx) to Ethernet PAUSE frames. 1978 * - High water mark should allow for at least two frames to be 1979 * received after sending an XOFF. 1980 * - Low water mark works best when it is very near the high water mark. 1981 * This allows the receiver to restart by sending XON when it has 1982 * drained a bit. Here we use an arbitary value of 1500 which will 1983 * restart after one full frame is pulled from the buffer. There 1984 * could be several smaller frames in the buffer and if so they will 1985 * not trigger the XON until their total number reduces the buffer 1986 * by 1500. 1987 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1988 */ 1989 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10; 1990 1991 sc->hw.fc.high_water = rx_buffer_size - 1992 roundup2(sc->hw.mac.max_frame_size, 1024); 1993 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500; 1994 1995 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME; 1996 sc->hw.fc.send_xon = TRUE; 1997 sc->hw.fc.requested_mode = e1000_ifmedia2fc(sc->ifm_flowctrl); 1998 1999 /* 2000 * Device specific overrides/settings 2001 */ 2002 if (sc->hw.mac.type == e1000_pch_lpt || 2003 sc->hw.mac.type == e1000_pch_spt) { 2004 sc->hw.fc.high_water = 0x5C20; 2005 sc->hw.fc.low_water = 0x5048; 2006 sc->hw.fc.pause_time = 0x0650; 2007 sc->hw.fc.refresh_time = 0x0400; 2008 /* Jumbos need adjusted PBA */ 2009 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) 2010 E1000_WRITE_REG(&sc->hw, E1000_PBA, 12); 2011 else 2012 E1000_WRITE_REG(&sc->hw, E1000_PBA, 26); 2013 } else if (sc->hw.mac.type == e1000_80003es2lan) { 2014 sc->hw.fc.pause_time = 0xFFFF; 2015 } 2016 2017 /* Issue a global reset */ 2018 e1000_reset_hw(&sc->hw); 2019 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 2020 emx_disable_aspm(sc); 2021 2022 if (e1000_init_hw(&sc->hw) < 0) { 2023 device_printf(dev, "Hardware Initialization Failed\n"); 2024 return (EIO); 2025 } 2026 2027 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 2028 e1000_get_phy_info(&sc->hw); 2029 e1000_check_for_link(&sc->hw); 2030 2031 return (0); 2032 } 2033 2034 static void 2035 emx_setup_ifp(struct emx_softc *sc) 2036 { 2037 struct ifnet *ifp = &sc->arpcom.ac_if; 2038 int i; 2039 2040 if_initname(ifp, device_get_name(sc->dev), 2041 device_get_unit(sc->dev)); 2042 ifp->if_softc = sc; 2043 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2044 ifp->if_init = emx_init; 2045 ifp->if_ioctl = emx_ioctl; 2046 ifp->if_start = emx_start; 2047 #ifdef IFPOLL_ENABLE 2048 ifp->if_npoll = emx_npoll; 2049 #endif 2050 ifp->if_serialize = emx_serialize; 2051 ifp->if_deserialize = emx_deserialize; 2052 ifp->if_tryserialize = emx_tryserialize; 2053 #ifdef INVARIANTS 2054 ifp->if_serialize_assert = emx_serialize_assert; 2055 #endif 2056 2057 ifp->if_nmbclusters = sc->rx_ring_cnt * sc->rx_data[0].num_rx_desc; 2058 2059 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1); 2060 ifq_set_ready(&ifp->if_snd); 2061 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt); 2062 2063 ifp->if_mapsubq = ifq_mapsubq_modulo; 2064 ifq_set_subq_divisor(&ifp->if_snd, 1); 2065 2066 ether_ifattach(ifp, sc->hw.mac.addr, NULL); 2067 2068 ifp->if_capabilities = IFCAP_HWCSUM | 2069 IFCAP_VLAN_HWTAGGING | 2070 IFCAP_VLAN_MTU | 2071 IFCAP_TSO; 2072 if (sc->rx_ring_cnt > 1) 2073 ifp->if_capabilities |= IFCAP_RSS; 2074 ifp->if_capenable = ifp->if_capabilities; 2075 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO; 2076 2077 /* 2078 * Tell the upper layer(s) we support long frames. 2079 */ 2080 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2081 2082 for (i = 0; i < sc->tx_ring_cnt; ++i) { 2083 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i); 2084 struct emx_txdata *tdata = &sc->tx_data[i]; 2085 2086 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res)); 2087 ifsq_set_priv(ifsq, tdata); 2088 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize); 2089 tdata->ifsq = ifsq; 2090 2091 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog); 2092 } 2093 2094 /* 2095 * Specify the media types supported by this sc and register 2096 * callbacks to update media and link information 2097 */ 2098 if (sc->hw.phy.media_type == e1000_media_type_fiber || 2099 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 2100 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2101 0, NULL); 2102 } else { 2103 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2104 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2105 0, NULL); 2106 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2107 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2108 0, NULL); 2109 if (sc->hw.phy.type != e1000_phy_ife) { 2110 ifmedia_add(&sc->media, 2111 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2112 } 2113 } 2114 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2115 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO | sc->ifm_flowctrl); 2116 } 2117 2118 /* 2119 * Workaround for SmartSpeed on 82541 and 82547 controllers 2120 */ 2121 static void 2122 emx_smartspeed(struct emx_softc *sc) 2123 { 2124 uint16_t phy_tmp; 2125 2126 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp || 2127 sc->hw.mac.autoneg == 0 || 2128 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2129 return; 2130 2131 if (sc->smartspeed == 0) { 2132 /* 2133 * If Master/Slave config fault is asserted twice, 2134 * we assume back-to-back 2135 */ 2136 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2137 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2138 return; 2139 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2140 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2141 e1000_read_phy_reg(&sc->hw, 2142 PHY_1000T_CTRL, &phy_tmp); 2143 if (phy_tmp & CR_1000T_MS_ENABLE) { 2144 phy_tmp &= ~CR_1000T_MS_ENABLE; 2145 e1000_write_phy_reg(&sc->hw, 2146 PHY_1000T_CTRL, phy_tmp); 2147 sc->smartspeed++; 2148 if (sc->hw.mac.autoneg && 2149 !e1000_phy_setup_autoneg(&sc->hw) && 2150 !e1000_read_phy_reg(&sc->hw, 2151 PHY_CONTROL, &phy_tmp)) { 2152 phy_tmp |= MII_CR_AUTO_NEG_EN | 2153 MII_CR_RESTART_AUTO_NEG; 2154 e1000_write_phy_reg(&sc->hw, 2155 PHY_CONTROL, phy_tmp); 2156 } 2157 } 2158 } 2159 return; 2160 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) { 2161 /* If still no link, perhaps using 2/3 pair cable */ 2162 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2163 phy_tmp |= CR_1000T_MS_ENABLE; 2164 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2165 if (sc->hw.mac.autoneg && 2166 !e1000_phy_setup_autoneg(&sc->hw) && 2167 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2168 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2169 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2170 } 2171 } 2172 2173 /* Restart process after EMX_SMARTSPEED_MAX iterations */ 2174 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX) 2175 sc->smartspeed = 0; 2176 } 2177 2178 static int 2179 emx_create_tx_ring(struct emx_txdata *tdata) 2180 { 2181 device_t dev = tdata->sc->dev; 2182 struct emx_txbuf *tx_buffer; 2183 int error, i, tsize, ntxd; 2184 2185 /* 2186 * Validate number of transmit descriptors. It must not exceed 2187 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2188 */ 2189 ntxd = device_getenv_int(dev, "txd", emx_txd); 2190 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 || 2191 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) { 2192 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 2193 EMX_DEFAULT_TXD, ntxd); 2194 tdata->num_tx_desc = EMX_DEFAULT_TXD; 2195 } else { 2196 tdata->num_tx_desc = ntxd; 2197 } 2198 2199 /* 2200 * Allocate Transmit Descriptor ring 2201 */ 2202 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc), 2203 EMX_DBA_ALIGN); 2204 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag, 2205 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK, 2206 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap, 2207 &tdata->tx_desc_paddr); 2208 if (tdata->tx_desc_base == NULL) { 2209 device_printf(dev, "Unable to allocate tx_desc memory\n"); 2210 return ENOMEM; 2211 } 2212 2213 tsize = __VM_CACHELINE_ALIGN( 2214 sizeof(struct emx_txbuf) * tdata->num_tx_desc); 2215 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO); 2216 2217 /* 2218 * Create DMA tags for tx buffers 2219 */ 2220 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */ 2221 1, 0, /* alignment, bounds */ 2222 BUS_SPACE_MAXADDR, /* lowaddr */ 2223 BUS_SPACE_MAXADDR, /* highaddr */ 2224 NULL, NULL, /* filter, filterarg */ 2225 EMX_TSO_SIZE, /* maxsize */ 2226 EMX_MAX_SCATTER, /* nsegments */ 2227 EMX_MAX_SEGSIZE, /* maxsegsize */ 2228 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2229 BUS_DMA_ONEBPAGE, /* flags */ 2230 &tdata->txtag); 2231 if (error) { 2232 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2233 kfree(tdata->tx_buf, M_DEVBUF); 2234 tdata->tx_buf = NULL; 2235 return error; 2236 } 2237 2238 /* 2239 * Create DMA maps for tx buffers 2240 */ 2241 for (i = 0; i < tdata->num_tx_desc; i++) { 2242 tx_buffer = &tdata->tx_buf[i]; 2243 2244 error = bus_dmamap_create(tdata->txtag, 2245 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2246 &tx_buffer->map); 2247 if (error) { 2248 device_printf(dev, "Unable to create TX DMA map\n"); 2249 emx_destroy_tx_ring(tdata, i); 2250 return error; 2251 } 2252 } 2253 2254 /* 2255 * Setup TX parameters 2256 */ 2257 tdata->spare_tx_desc = EMX_TX_SPARE; 2258 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG; 2259 2260 /* 2261 * Keep following relationship between spare_tx_desc, oact_tx_desc 2262 * and tx_intr_nsegs: 2263 * (spare_tx_desc + EMX_TX_RESERVED) <= 2264 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs 2265 */ 2266 tdata->oact_tx_desc = tdata->num_tx_desc / 8; 2267 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX) 2268 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX; 2269 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED) 2270 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED; 2271 2272 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16; 2273 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc) 2274 tdata->tx_intr_nsegs = tdata->oact_tx_desc; 2275 2276 /* 2277 * Pullup extra 4bytes into the first data segment for TSO, see: 2278 * 82571/82572 specification update errata #7 2279 * 2280 * Same applies to I217 (and maybe I218 and I219). 2281 * 2282 * NOTE: 2283 * 4bytes instead of 2bytes, which are mentioned in the errata, 2284 * are pulled; mainly to keep rest of the data properly aligned. 2285 */ 2286 if (tdata->sc->hw.mac.type == e1000_82571 || 2287 tdata->sc->hw.mac.type == e1000_82572 || 2288 tdata->sc->hw.mac.type == e1000_pch_lpt || 2289 tdata->sc->hw.mac.type == e1000_pch_spt) 2290 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX; 2291 2292 return (0); 2293 } 2294 2295 static void 2296 emx_init_tx_ring(struct emx_txdata *tdata) 2297 { 2298 /* Clear the old ring contents */ 2299 bzero(tdata->tx_desc_base, 2300 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc); 2301 2302 /* Reset state */ 2303 tdata->next_avail_tx_desc = 0; 2304 tdata->next_tx_to_clean = 0; 2305 tdata->num_tx_desc_avail = tdata->num_tx_desc; 2306 2307 tdata->tx_flags |= EMX_TXFLAG_ENABLED; 2308 if (tdata->sc->tx_ring_inuse > 1) { 2309 tdata->tx_flags |= EMX_TXFLAG_FORCECTX; 2310 if (bootverbose) { 2311 if_printf(&tdata->sc->arpcom.ac_if, 2312 "TX %d force ctx setup\n", tdata->idx); 2313 } 2314 } 2315 } 2316 2317 static void 2318 emx_init_tx_unit(struct emx_softc *sc) 2319 { 2320 uint32_t tctl, tarc, tipg = 0, txdctl; 2321 int i; 2322 2323 for (i = 0; i < sc->tx_ring_inuse; ++i) { 2324 struct emx_txdata *tdata = &sc->tx_data[i]; 2325 uint64_t bus_addr; 2326 2327 /* Setup the Base and Length of the Tx Descriptor Ring */ 2328 bus_addr = tdata->tx_desc_paddr; 2329 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i), 2330 tdata->num_tx_desc * sizeof(struct e1000_tx_desc)); 2331 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i), 2332 (uint32_t)(bus_addr >> 32)); 2333 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i), 2334 (uint32_t)bus_addr); 2335 /* Setup the HW Tx Head and Tail descriptor pointers */ 2336 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0); 2337 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0); 2338 } 2339 2340 /* Set the default values for the Tx Inter Packet Gap timer */ 2341 switch (sc->hw.mac.type) { 2342 case e1000_80003es2lan: 2343 tipg = DEFAULT_82543_TIPG_IPGR1; 2344 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2345 E1000_TIPG_IPGR2_SHIFT; 2346 break; 2347 2348 default: 2349 if (sc->hw.phy.media_type == e1000_media_type_fiber || 2350 sc->hw.phy.media_type == e1000_media_type_internal_serdes) 2351 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2352 else 2353 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2354 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2355 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2356 break; 2357 } 2358 2359 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg); 2360 2361 /* NOTE: 0 is not allowed for TIDV */ 2362 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1); 2363 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0); 2364 2365 /* 2366 * Errata workaround (obtained from Linux). This is necessary 2367 * to make multiple TX queues work on 82574. 2368 * XXX can't find it in any published errata though. 2369 */ 2370 txdctl = E1000_READ_REG(&sc->hw, E1000_TXDCTL(0)); 2371 E1000_WRITE_REG(&sc->hw, E1000_TXDCTL(1), txdctl); 2372 2373 if (sc->hw.mac.type == e1000_82571 || 2374 sc->hw.mac.type == e1000_82572) { 2375 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2376 tarc |= EMX_TARC_SPEED_MODE; 2377 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2378 } else if (sc->hw.mac.type == e1000_80003es2lan) { 2379 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2380 tarc |= 1; 2381 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2382 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2383 tarc |= 1; 2384 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2385 } 2386 2387 /* Program the Transmit Control Register */ 2388 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL); 2389 tctl &= ~E1000_TCTL_CT; 2390 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2391 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2392 tctl |= E1000_TCTL_MULR; 2393 2394 /* This write will effectively turn on the transmit unit. */ 2395 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl); 2396 2397 if (sc->hw.mac.type == e1000_82571 || 2398 sc->hw.mac.type == e1000_82572 || 2399 sc->hw.mac.type == e1000_80003es2lan) { 2400 /* Bit 28 of TARC1 must be cleared when MULR is enabled */ 2401 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2402 tarc &= ~(1 << 28); 2403 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2404 } 2405 2406 if (sc->tx_ring_inuse > 1) { 2407 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2408 tarc &= ~EMX_TARC_COUNT_MASK; 2409 tarc |= 1; 2410 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2411 2412 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2413 tarc &= ~EMX_TARC_COUNT_MASK; 2414 tarc |= 1; 2415 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2416 } 2417 } 2418 2419 static void 2420 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc) 2421 { 2422 struct emx_txbuf *tx_buffer; 2423 int i; 2424 2425 /* Free Transmit Descriptor ring */ 2426 if (tdata->tx_desc_base) { 2427 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap); 2428 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base, 2429 tdata->tx_desc_dmap); 2430 bus_dma_tag_destroy(tdata->tx_desc_dtag); 2431 2432 tdata->tx_desc_base = NULL; 2433 } 2434 2435 if (tdata->tx_buf == NULL) 2436 return; 2437 2438 for (i = 0; i < ndesc; i++) { 2439 tx_buffer = &tdata->tx_buf[i]; 2440 2441 KKASSERT(tx_buffer->m_head == NULL); 2442 bus_dmamap_destroy(tdata->txtag, tx_buffer->map); 2443 } 2444 bus_dma_tag_destroy(tdata->txtag); 2445 2446 kfree(tdata->tx_buf, M_DEVBUF); 2447 tdata->tx_buf = NULL; 2448 } 2449 2450 /* 2451 * The offload context needs to be set when we transfer the first 2452 * packet of a particular protocol (TCP/UDP). This routine has been 2453 * enhanced to deal with inserted VLAN headers. 2454 * 2455 * If the new packet's ether header length, ip header length and 2456 * csum offloading type are same as the previous packet, we should 2457 * avoid allocating a new csum context descriptor; mainly to take 2458 * advantage of the pipeline effect of the TX data read request. 2459 * 2460 * This function returns number of TX descrptors allocated for 2461 * csum context. 2462 */ 2463 static int 2464 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp, 2465 uint32_t *txd_upper, uint32_t *txd_lower) 2466 { 2467 struct e1000_context_desc *TXD; 2468 int curr_txd, ehdrlen, csum_flags; 2469 uint32_t cmd, hdr_len, ip_hlen; 2470 2471 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES; 2472 ip_hlen = mp->m_pkthdr.csum_iphlen; 2473 ehdrlen = mp->m_pkthdr.csum_lhlen; 2474 2475 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 && 2476 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen && 2477 tdata->csum_flags == csum_flags) { 2478 /* 2479 * Same csum offload context as the previous packets; 2480 * just return. 2481 */ 2482 *txd_upper = tdata->csum_txd_upper; 2483 *txd_lower = tdata->csum_txd_lower; 2484 return 0; 2485 } 2486 2487 /* 2488 * Setup a new csum offload context. 2489 */ 2490 2491 curr_txd = tdata->next_avail_tx_desc; 2492 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd]; 2493 2494 cmd = 0; 2495 2496 /* Setup of IP header checksum. */ 2497 if (csum_flags & CSUM_IP) { 2498 /* 2499 * Start offset for header checksum calculation. 2500 * End offset for header checksum calculation. 2501 * Offset of place to put the checksum. 2502 */ 2503 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2504 TXD->lower_setup.ip_fields.ipcse = 2505 htole16(ehdrlen + ip_hlen - 1); 2506 TXD->lower_setup.ip_fields.ipcso = 2507 ehdrlen + offsetof(struct ip, ip_sum); 2508 cmd |= E1000_TXD_CMD_IP; 2509 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2510 } 2511 hdr_len = ehdrlen + ip_hlen; 2512 2513 if (csum_flags & CSUM_TCP) { 2514 /* 2515 * Start offset for payload checksum calculation. 2516 * End offset for payload checksum calculation. 2517 * Offset of place to put the checksum. 2518 */ 2519 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2520 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2521 TXD->upper_setup.tcp_fields.tucso = 2522 hdr_len + offsetof(struct tcphdr, th_sum); 2523 cmd |= E1000_TXD_CMD_TCP; 2524 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2525 } else if (csum_flags & CSUM_UDP) { 2526 /* 2527 * Start offset for header checksum calculation. 2528 * End offset for header checksum calculation. 2529 * Offset of place to put the checksum. 2530 */ 2531 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2532 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2533 TXD->upper_setup.tcp_fields.tucso = 2534 hdr_len + offsetof(struct udphdr, uh_sum); 2535 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2536 } 2537 2538 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2539 E1000_TXD_DTYP_D; /* Data descr */ 2540 2541 /* Save the information for this csum offloading context */ 2542 tdata->csum_lhlen = ehdrlen; 2543 tdata->csum_iphlen = ip_hlen; 2544 tdata->csum_flags = csum_flags; 2545 tdata->csum_txd_upper = *txd_upper; 2546 tdata->csum_txd_lower = *txd_lower; 2547 2548 TXD->tcp_seg_setup.data = htole32(0); 2549 TXD->cmd_and_length = 2550 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2551 2552 if (++curr_txd == tdata->num_tx_desc) 2553 curr_txd = 0; 2554 2555 KKASSERT(tdata->num_tx_desc_avail > 0); 2556 tdata->num_tx_desc_avail--; 2557 2558 tdata->next_avail_tx_desc = curr_txd; 2559 return 1; 2560 } 2561 2562 static void 2563 emx_txeof(struct emx_txdata *tdata) 2564 { 2565 struct emx_txbuf *tx_buffer; 2566 int first, num_avail; 2567 2568 if (tdata->tx_dd_head == tdata->tx_dd_tail) 2569 return; 2570 2571 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2572 return; 2573 2574 num_avail = tdata->num_tx_desc_avail; 2575 first = tdata->next_tx_to_clean; 2576 2577 while (tdata->tx_dd_head != tdata->tx_dd_tail) { 2578 int dd_idx = tdata->tx_dd[tdata->tx_dd_head]; 2579 struct e1000_tx_desc *tx_desc; 2580 2581 tx_desc = &tdata->tx_desc_base[dd_idx]; 2582 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2583 EMX_INC_TXDD_IDX(tdata->tx_dd_head); 2584 2585 if (++dd_idx == tdata->num_tx_desc) 2586 dd_idx = 0; 2587 2588 while (first != dd_idx) { 2589 logif(pkt_txclean); 2590 2591 num_avail++; 2592 2593 tx_buffer = &tdata->tx_buf[first]; 2594 if (tx_buffer->m_head) { 2595 bus_dmamap_unload(tdata->txtag, 2596 tx_buffer->map); 2597 m_freem(tx_buffer->m_head); 2598 tx_buffer->m_head = NULL; 2599 } 2600 2601 if (++first == tdata->num_tx_desc) 2602 first = 0; 2603 } 2604 } else { 2605 break; 2606 } 2607 } 2608 tdata->next_tx_to_clean = first; 2609 tdata->num_tx_desc_avail = num_avail; 2610 2611 if (tdata->tx_dd_head == tdata->tx_dd_tail) { 2612 tdata->tx_dd_head = 0; 2613 tdata->tx_dd_tail = 0; 2614 } 2615 2616 if (!EMX_IS_OACTIVE(tdata)) { 2617 ifsq_clr_oactive(tdata->ifsq); 2618 2619 /* All clean, turn off the timer */ 2620 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2621 tdata->tx_watchdog.wd_timer = 0; 2622 } 2623 } 2624 2625 static void 2626 emx_tx_collect(struct emx_txdata *tdata) 2627 { 2628 struct emx_txbuf *tx_buffer; 2629 int tdh, first, num_avail, dd_idx = -1; 2630 2631 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2632 return; 2633 2634 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx)); 2635 if (tdh == tdata->next_tx_to_clean) 2636 return; 2637 2638 if (tdata->tx_dd_head != tdata->tx_dd_tail) 2639 dd_idx = tdata->tx_dd[tdata->tx_dd_head]; 2640 2641 num_avail = tdata->num_tx_desc_avail; 2642 first = tdata->next_tx_to_clean; 2643 2644 while (first != tdh) { 2645 logif(pkt_txclean); 2646 2647 num_avail++; 2648 2649 tx_buffer = &tdata->tx_buf[first]; 2650 if (tx_buffer->m_head) { 2651 bus_dmamap_unload(tdata->txtag, 2652 tx_buffer->map); 2653 m_freem(tx_buffer->m_head); 2654 tx_buffer->m_head = NULL; 2655 } 2656 2657 if (first == dd_idx) { 2658 EMX_INC_TXDD_IDX(tdata->tx_dd_head); 2659 if (tdata->tx_dd_head == tdata->tx_dd_tail) { 2660 tdata->tx_dd_head = 0; 2661 tdata->tx_dd_tail = 0; 2662 dd_idx = -1; 2663 } else { 2664 dd_idx = tdata->tx_dd[tdata->tx_dd_head]; 2665 } 2666 } 2667 2668 if (++first == tdata->num_tx_desc) 2669 first = 0; 2670 } 2671 tdata->next_tx_to_clean = first; 2672 tdata->num_tx_desc_avail = num_avail; 2673 2674 if (!EMX_IS_OACTIVE(tdata)) { 2675 ifsq_clr_oactive(tdata->ifsq); 2676 2677 /* All clean, turn off the timer */ 2678 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2679 tdata->tx_watchdog.wd_timer = 0; 2680 } 2681 } 2682 2683 /* 2684 * When Link is lost sometimes there is work still in the TX ring 2685 * which will result in a watchdog, rather than allow that do an 2686 * attempted cleanup and then reinit here. Note that this has been 2687 * seens mostly with fiber adapters. 2688 */ 2689 static void 2690 emx_tx_purge(struct emx_softc *sc) 2691 { 2692 int i; 2693 2694 if (sc->link_active) 2695 return; 2696 2697 for (i = 0; i < sc->tx_ring_inuse; ++i) { 2698 struct emx_txdata *tdata = &sc->tx_data[i]; 2699 2700 if (tdata->tx_watchdog.wd_timer) { 2701 emx_tx_collect(tdata); 2702 if (tdata->tx_watchdog.wd_timer) { 2703 if_printf(&sc->arpcom.ac_if, 2704 "Link lost, TX pending, reinit\n"); 2705 emx_init(sc); 2706 return; 2707 } 2708 } 2709 } 2710 } 2711 2712 static int 2713 emx_newbuf(struct emx_rxdata *rdata, int i, int init) 2714 { 2715 struct mbuf *m; 2716 bus_dma_segment_t seg; 2717 bus_dmamap_t map; 2718 struct emx_rxbuf *rx_buffer; 2719 int error, nseg; 2720 2721 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 2722 if (m == NULL) { 2723 if (init) { 2724 if_printf(&rdata->sc->arpcom.ac_if, 2725 "Unable to allocate RX mbuf\n"); 2726 } 2727 return (ENOBUFS); 2728 } 2729 m->m_len = m->m_pkthdr.len = MCLBYTES; 2730 2731 if (rdata->sc->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN) 2732 m_adj(m, ETHER_ALIGN); 2733 2734 error = bus_dmamap_load_mbuf_segment(rdata->rxtag, 2735 rdata->rx_sparemap, m, 2736 &seg, 1, &nseg, BUS_DMA_NOWAIT); 2737 if (error) { 2738 m_freem(m); 2739 if (init) { 2740 if_printf(&rdata->sc->arpcom.ac_if, 2741 "Unable to load RX mbuf\n"); 2742 } 2743 return (error); 2744 } 2745 2746 rx_buffer = &rdata->rx_buf[i]; 2747 if (rx_buffer->m_head != NULL) 2748 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2749 2750 map = rx_buffer->map; 2751 rx_buffer->map = rdata->rx_sparemap; 2752 rdata->rx_sparemap = map; 2753 2754 rx_buffer->m_head = m; 2755 rx_buffer->paddr = seg.ds_addr; 2756 2757 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer); 2758 return (0); 2759 } 2760 2761 static int 2762 emx_create_rx_ring(struct emx_rxdata *rdata) 2763 { 2764 device_t dev = rdata->sc->dev; 2765 struct emx_rxbuf *rx_buffer; 2766 int i, error, rsize, nrxd; 2767 2768 /* 2769 * Validate number of receive descriptors. It must not exceed 2770 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2771 */ 2772 nrxd = device_getenv_int(dev, "rxd", emx_rxd); 2773 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 || 2774 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) { 2775 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 2776 EMX_DEFAULT_RXD, nrxd); 2777 rdata->num_rx_desc = EMX_DEFAULT_RXD; 2778 } else { 2779 rdata->num_rx_desc = nrxd; 2780 } 2781 2782 /* 2783 * Allocate Receive Descriptor ring 2784 */ 2785 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t), 2786 EMX_DBA_ALIGN); 2787 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag, 2788 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK, 2789 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap, 2790 &rdata->rx_desc_paddr); 2791 if (rdata->rx_desc == NULL) { 2792 device_printf(dev, "Unable to allocate rx_desc memory\n"); 2793 return ENOMEM; 2794 } 2795 2796 rsize = __VM_CACHELINE_ALIGN( 2797 sizeof(struct emx_rxbuf) * rdata->num_rx_desc); 2798 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO); 2799 2800 /* 2801 * Create DMA tag for rx buffers 2802 */ 2803 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */ 2804 1, 0, /* alignment, bounds */ 2805 BUS_SPACE_MAXADDR, /* lowaddr */ 2806 BUS_SPACE_MAXADDR, /* highaddr */ 2807 NULL, NULL, /* filter, filterarg */ 2808 MCLBYTES, /* maxsize */ 2809 1, /* nsegments */ 2810 MCLBYTES, /* maxsegsize */ 2811 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 2812 &rdata->rxtag); 2813 if (error) { 2814 device_printf(dev, "Unable to allocate RX DMA tag\n"); 2815 kfree(rdata->rx_buf, M_DEVBUF); 2816 rdata->rx_buf = NULL; 2817 return error; 2818 } 2819 2820 /* 2821 * Create spare DMA map for rx buffers 2822 */ 2823 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2824 &rdata->rx_sparemap); 2825 if (error) { 2826 device_printf(dev, "Unable to create spare RX DMA map\n"); 2827 bus_dma_tag_destroy(rdata->rxtag); 2828 kfree(rdata->rx_buf, M_DEVBUF); 2829 rdata->rx_buf = NULL; 2830 return error; 2831 } 2832 2833 /* 2834 * Create DMA maps for rx buffers 2835 */ 2836 for (i = 0; i < rdata->num_rx_desc; i++) { 2837 rx_buffer = &rdata->rx_buf[i]; 2838 2839 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2840 &rx_buffer->map); 2841 if (error) { 2842 device_printf(dev, "Unable to create RX DMA map\n"); 2843 emx_destroy_rx_ring(rdata, i); 2844 return error; 2845 } 2846 } 2847 return (0); 2848 } 2849 2850 static void 2851 emx_free_rx_ring(struct emx_rxdata *rdata) 2852 { 2853 int i; 2854 2855 for (i = 0; i < rdata->num_rx_desc; i++) { 2856 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i]; 2857 2858 if (rx_buffer->m_head != NULL) { 2859 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2860 m_freem(rx_buffer->m_head); 2861 rx_buffer->m_head = NULL; 2862 } 2863 } 2864 2865 if (rdata->fmp != NULL) 2866 m_freem(rdata->fmp); 2867 rdata->fmp = NULL; 2868 rdata->lmp = NULL; 2869 } 2870 2871 static void 2872 emx_free_tx_ring(struct emx_txdata *tdata) 2873 { 2874 int i; 2875 2876 for (i = 0; i < tdata->num_tx_desc; i++) { 2877 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i]; 2878 2879 if (tx_buffer->m_head != NULL) { 2880 bus_dmamap_unload(tdata->txtag, tx_buffer->map); 2881 m_freem(tx_buffer->m_head); 2882 tx_buffer->m_head = NULL; 2883 } 2884 } 2885 2886 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX; 2887 2888 tdata->csum_flags = 0; 2889 tdata->csum_lhlen = 0; 2890 tdata->csum_iphlen = 0; 2891 tdata->csum_thlen = 0; 2892 tdata->csum_mss = 0; 2893 tdata->csum_pktlen = 0; 2894 2895 tdata->tx_dd_head = 0; 2896 tdata->tx_dd_tail = 0; 2897 tdata->tx_nsegs = 0; 2898 } 2899 2900 static int 2901 emx_init_rx_ring(struct emx_rxdata *rdata) 2902 { 2903 int i, error; 2904 2905 /* Reset descriptor ring */ 2906 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc); 2907 2908 /* Allocate new ones. */ 2909 for (i = 0; i < rdata->num_rx_desc; i++) { 2910 error = emx_newbuf(rdata, i, 1); 2911 if (error) 2912 return (error); 2913 } 2914 2915 /* Setup our descriptor pointers */ 2916 rdata->next_rx_desc_to_check = 0; 2917 2918 return (0); 2919 } 2920 2921 static void 2922 emx_init_rx_unit(struct emx_softc *sc) 2923 { 2924 struct ifnet *ifp = &sc->arpcom.ac_if; 2925 uint64_t bus_addr; 2926 uint32_t rctl, itr, rfctl; 2927 int i; 2928 2929 /* 2930 * Make sure receives are disabled while setting 2931 * up the descriptor ring 2932 */ 2933 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2934 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2935 2936 /* 2937 * Set the interrupt throttling rate. Value is calculated 2938 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 2939 */ 2940 if (sc->int_throttle_ceil) 2941 itr = 1000000000 / 256 / sc->int_throttle_ceil; 2942 else 2943 itr = 0; 2944 emx_set_itr(sc, itr); 2945 2946 /* Use extended RX descriptor */ 2947 rfctl = E1000_RFCTL_EXTEN; 2948 2949 /* Disable accelerated ackknowledge */ 2950 if (sc->hw.mac.type == e1000_82574) 2951 rfctl |= E1000_RFCTL_ACK_DIS; 2952 2953 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl); 2954 2955 /* 2956 * Receive Checksum Offload for TCP and UDP 2957 * 2958 * Checksum offloading is also enabled if multiple receive 2959 * queue is to be supported, since we need it to figure out 2960 * packet type. 2961 */ 2962 if ((ifp->if_capenable & IFCAP_RXCSUM) || 2963 sc->rx_ring_cnt > 1) { 2964 uint32_t rxcsum; 2965 2966 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM); 2967 2968 /* 2969 * NOTE: 2970 * PCSD must be enabled to enable multiple 2971 * receive queues. 2972 */ 2973 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL | 2974 E1000_RXCSUM_PCSD; 2975 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum); 2976 } 2977 2978 /* 2979 * Configure multiple receive queue (RSS) 2980 */ 2981 if (sc->rx_ring_cnt > 1) { 2982 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE]; 2983 int r, j; 2984 2985 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING, 2986 ("invalid number of RX ring (%d)", sc->rx_ring_cnt)); 2987 2988 /* 2989 * NOTE: 2990 * When we reach here, RSS has already been disabled 2991 * in emx_stop(), so we could safely configure RSS key 2992 * and redirect table. 2993 */ 2994 2995 /* 2996 * Configure RSS key 2997 */ 2998 toeplitz_get_key(key, sizeof(key)); 2999 for (i = 0; i < EMX_NRSSRK; ++i) { 3000 uint32_t rssrk; 3001 3002 rssrk = EMX_RSSRK_VAL(key, i); 3003 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk); 3004 3005 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk); 3006 } 3007 3008 /* 3009 * Configure RSS redirect table. 3010 */ 3011 if_ringmap_rdrtable(sc->rx_rmap, sc->rdr_table, 3012 EMX_RDRTABLE_SIZE); 3013 3014 r = 0; 3015 for (j = 0; j < EMX_NRETA; ++j) { 3016 uint32_t reta = 0; 3017 3018 for (i = 0; i < EMX_RETA_SIZE; ++i) { 3019 uint32_t q; 3020 3021 q = sc->rdr_table[r] << EMX_RETA_RINGIDX_SHIFT; 3022 reta |= q << (8 * i); 3023 ++r; 3024 } 3025 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta); 3026 E1000_WRITE_REG(&sc->hw, E1000_RETA(j), reta); 3027 } 3028 3029 /* 3030 * Enable multiple receive queues. 3031 * Enable IPv4 RSS standard hash functions. 3032 * Disable RSS interrupt. 3033 */ 3034 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 3035 E1000_MRQC_ENABLE_RSS_2Q | 3036 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3037 E1000_MRQC_RSS_FIELD_IPV4); 3038 } 3039 3040 /* 3041 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3042 * long latencies are observed, like Lenovo X60. This 3043 * change eliminates the problem, but since having positive 3044 * values in RDTR is a known source of problems on other 3045 * platforms another solution is being sought. 3046 */ 3047 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) { 3048 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573); 3049 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573); 3050 } 3051 3052 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3053 struct emx_rxdata *rdata = &sc->rx_data[i]; 3054 3055 /* 3056 * Setup the Base and Length of the Rx Descriptor Ring 3057 */ 3058 bus_addr = rdata->rx_desc_paddr; 3059 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i), 3060 rdata->num_rx_desc * sizeof(emx_rxdesc_t)); 3061 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i), 3062 (uint32_t)(bus_addr >> 32)); 3063 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i), 3064 (uint32_t)bus_addr); 3065 3066 /* 3067 * Setup the HW Rx Head and Tail Descriptor Pointers 3068 */ 3069 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0); 3070 E1000_WRITE_REG(&sc->hw, E1000_RDT(i), 3071 sc->rx_data[i].num_rx_desc - 1); 3072 } 3073 3074 if (sc->hw.mac.type >= e1000_pch2lan) { 3075 if (ifp->if_mtu > ETHERMTU) 3076 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, TRUE); 3077 else 3078 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, FALSE); 3079 } 3080 3081 /* Setup the Receive Control Register */ 3082 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3083 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3084 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC | 3085 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3086 3087 /* Make sure VLAN Filters are off */ 3088 rctl &= ~E1000_RCTL_VFE; 3089 3090 /* Don't store bad paket */ 3091 rctl &= ~E1000_RCTL_SBP; 3092 3093 /* MCLBYTES */ 3094 rctl |= E1000_RCTL_SZ_2048; 3095 3096 if (ifp->if_mtu > ETHERMTU) 3097 rctl |= E1000_RCTL_LPE; 3098 else 3099 rctl &= ~E1000_RCTL_LPE; 3100 3101 /* Enable Receives */ 3102 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 3103 } 3104 3105 static void 3106 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc) 3107 { 3108 struct emx_rxbuf *rx_buffer; 3109 int i; 3110 3111 /* Free Receive Descriptor ring */ 3112 if (rdata->rx_desc) { 3113 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap); 3114 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc, 3115 rdata->rx_desc_dmap); 3116 bus_dma_tag_destroy(rdata->rx_desc_dtag); 3117 3118 rdata->rx_desc = NULL; 3119 } 3120 3121 if (rdata->rx_buf == NULL) 3122 return; 3123 3124 for (i = 0; i < ndesc; i++) { 3125 rx_buffer = &rdata->rx_buf[i]; 3126 3127 KKASSERT(rx_buffer->m_head == NULL); 3128 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map); 3129 } 3130 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap); 3131 bus_dma_tag_destroy(rdata->rxtag); 3132 3133 kfree(rdata->rx_buf, M_DEVBUF); 3134 rdata->rx_buf = NULL; 3135 } 3136 3137 static void 3138 emx_rxeof(struct emx_rxdata *rdata, int count) 3139 { 3140 struct ifnet *ifp = &rdata->sc->arpcom.ac_if; 3141 uint32_t staterr; 3142 emx_rxdesc_t *current_desc; 3143 struct mbuf *mp; 3144 int i, cpuid = mycpuid; 3145 3146 i = rdata->next_rx_desc_to_check; 3147 current_desc = &rdata->rx_desc[i]; 3148 staterr = le32toh(current_desc->rxd_staterr); 3149 3150 if (!(staterr & E1000_RXD_STAT_DD)) 3151 return; 3152 3153 while ((staterr & E1000_RXD_STAT_DD) && count != 0) { 3154 struct pktinfo *pi = NULL, pi0; 3155 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i]; 3156 struct mbuf *m = NULL; 3157 int eop, len; 3158 3159 logif(pkt_receive); 3160 3161 mp = rx_buf->m_head; 3162 3163 /* 3164 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3165 * needs to access the last received byte in the mbuf. 3166 */ 3167 bus_dmamap_sync(rdata->rxtag, rx_buf->map, 3168 BUS_DMASYNC_POSTREAD); 3169 3170 len = le16toh(current_desc->rxd_length); 3171 if (staterr & E1000_RXD_STAT_EOP) { 3172 count--; 3173 eop = 1; 3174 } else { 3175 eop = 0; 3176 } 3177 3178 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) { 3179 uint16_t vlan = 0; 3180 uint32_t mrq, rss_hash; 3181 3182 /* 3183 * Save several necessary information, 3184 * before emx_newbuf() destroy it. 3185 */ 3186 if ((staterr & E1000_RXD_STAT_VP) && eop) 3187 vlan = le16toh(current_desc->rxd_vlan); 3188 3189 mrq = le32toh(current_desc->rxd_mrq); 3190 rss_hash = le32toh(current_desc->rxd_rss); 3191 3192 EMX_RSS_DPRINTF(rdata->sc, 10, 3193 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n", 3194 rdata->idx, mrq, rss_hash); 3195 3196 if (emx_newbuf(rdata, i, 0) != 0) { 3197 IFNET_STAT_INC(ifp, iqdrops, 1); 3198 goto discard; 3199 } 3200 3201 /* Assign correct length to the current fragment */ 3202 mp->m_len = len; 3203 3204 if (rdata->fmp == NULL) { 3205 mp->m_pkthdr.len = len; 3206 rdata->fmp = mp; /* Store the first mbuf */ 3207 rdata->lmp = mp; 3208 } else { 3209 /* 3210 * Chain mbuf's together 3211 */ 3212 rdata->lmp->m_next = mp; 3213 rdata->lmp = rdata->lmp->m_next; 3214 rdata->fmp->m_pkthdr.len += len; 3215 } 3216 3217 if (eop) { 3218 rdata->fmp->m_pkthdr.rcvif = ifp; 3219 IFNET_STAT_INC(ifp, ipackets, 1); 3220 3221 if (ifp->if_capenable & IFCAP_RXCSUM) 3222 emx_rxcsum(staterr, rdata->fmp); 3223 3224 if (staterr & E1000_RXD_STAT_VP) { 3225 rdata->fmp->m_pkthdr.ether_vlantag = 3226 vlan; 3227 rdata->fmp->m_flags |= M_VLANTAG; 3228 } 3229 m = rdata->fmp; 3230 rdata->fmp = NULL; 3231 rdata->lmp = NULL; 3232 3233 if (ifp->if_capenable & IFCAP_RSS) { 3234 pi = emx_rssinfo(m, &pi0, mrq, 3235 rss_hash, staterr); 3236 } 3237 #ifdef EMX_RSS_DEBUG 3238 rdata->rx_pkts++; 3239 #endif 3240 } 3241 } else { 3242 IFNET_STAT_INC(ifp, ierrors, 1); 3243 discard: 3244 emx_setup_rxdesc(current_desc, rx_buf); 3245 if (rdata->fmp != NULL) { 3246 m_freem(rdata->fmp); 3247 rdata->fmp = NULL; 3248 rdata->lmp = NULL; 3249 } 3250 m = NULL; 3251 } 3252 3253 if (m != NULL) 3254 ifp->if_input(ifp, m, pi, cpuid); 3255 3256 /* Advance our pointers to the next descriptor. */ 3257 if (++i == rdata->num_rx_desc) 3258 i = 0; 3259 3260 current_desc = &rdata->rx_desc[i]; 3261 staterr = le32toh(current_desc->rxd_staterr); 3262 } 3263 rdata->next_rx_desc_to_check = i; 3264 3265 /* Advance the E1000's Receive Queue "Tail Pointer". */ 3266 if (--i < 0) 3267 i = rdata->num_rx_desc - 1; 3268 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i); 3269 } 3270 3271 static void 3272 emx_enable_intr(struct emx_softc *sc) 3273 { 3274 uint32_t ims_mask = IMS_ENABLE_MASK; 3275 3276 lwkt_serialize_handler_enable(&sc->main_serialize); 3277 3278 #if 0 3279 if (sc->hw.mac.type == e1000_82574) { 3280 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK); 3281 ims_mask |= EM_MSIX_MASK; 3282 } 3283 #endif 3284 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask); 3285 } 3286 3287 static void 3288 emx_disable_intr(struct emx_softc *sc) 3289 { 3290 if (sc->hw.mac.type == e1000_82574) 3291 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0); 3292 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 3293 3294 lwkt_serialize_handler_disable(&sc->main_serialize); 3295 } 3296 3297 /* 3298 * Bit of a misnomer, what this really means is 3299 * to enable OS management of the system... aka 3300 * to disable special hardware management features 3301 */ 3302 static void 3303 emx_get_mgmt(struct emx_softc *sc) 3304 { 3305 /* A shared code workaround */ 3306 if (sc->flags & EMX_FLAG_HAS_MGMT) { 3307 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3308 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3309 3310 /* disable hardware interception of ARP */ 3311 manc &= ~(E1000_MANC_ARP_EN); 3312 3313 /* enable receiving management packets to the host */ 3314 manc |= E1000_MANC_EN_MNG2HOST; 3315 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3316 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3317 manc2h |= E1000_MNG2HOST_PORT_623; 3318 manc2h |= E1000_MNG2HOST_PORT_664; 3319 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3320 3321 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3322 } 3323 } 3324 3325 /* 3326 * Give control back to hardware management 3327 * controller if there is one. 3328 */ 3329 static void 3330 emx_rel_mgmt(struct emx_softc *sc) 3331 { 3332 if (sc->flags & EMX_FLAG_HAS_MGMT) { 3333 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3334 3335 /* re-enable hardware interception of ARP */ 3336 manc |= E1000_MANC_ARP_EN; 3337 manc &= ~E1000_MANC_EN_MNG2HOST; 3338 3339 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3340 } 3341 } 3342 3343 /* 3344 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3345 * For ASF and Pass Through versions of f/w this means that 3346 * the driver is loaded. For AMT version (only with 82573) 3347 * of the f/w this means that the network i/f is open. 3348 */ 3349 static void 3350 emx_get_hw_control(struct emx_softc *sc) 3351 { 3352 /* Let firmware know the driver has taken over */ 3353 if (sc->hw.mac.type == e1000_82573) { 3354 uint32_t swsm; 3355 3356 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3357 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3358 swsm | E1000_SWSM_DRV_LOAD); 3359 } else { 3360 uint32_t ctrl_ext; 3361 3362 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3363 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3364 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3365 } 3366 sc->flags |= EMX_FLAG_HW_CTRL; 3367 } 3368 3369 /* 3370 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3371 * For ASF and Pass Through versions of f/w this means that the 3372 * driver is no longer loaded. For AMT version (only with 82573) 3373 * of the f/w this means that the network i/f is closed. 3374 */ 3375 static void 3376 emx_rel_hw_control(struct emx_softc *sc) 3377 { 3378 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0) 3379 return; 3380 sc->flags &= ~EMX_FLAG_HW_CTRL; 3381 3382 /* Let firmware taken over control of h/w */ 3383 if (sc->hw.mac.type == e1000_82573) { 3384 uint32_t swsm; 3385 3386 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3387 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3388 swsm & ~E1000_SWSM_DRV_LOAD); 3389 } else { 3390 uint32_t ctrl_ext; 3391 3392 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3393 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3394 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3395 } 3396 } 3397 3398 static int 3399 emx_is_valid_eaddr(const uint8_t *addr) 3400 { 3401 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3402 3403 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3404 return (FALSE); 3405 3406 return (TRUE); 3407 } 3408 3409 /* 3410 * Enable PCI Wake On Lan capability 3411 */ 3412 static void 3413 emx_enable_wol(device_t dev) 3414 { 3415 uint16_t cap, status; 3416 uint8_t id; 3417 3418 /* First find the capabilities pointer*/ 3419 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3420 3421 /* Read the PM Capabilities */ 3422 id = pci_read_config(dev, cap, 1); 3423 if (id != PCIY_PMG) /* Something wrong */ 3424 return; 3425 3426 /* 3427 * OK, we have the power capabilities, 3428 * so now get the status register 3429 */ 3430 cap += PCIR_POWER_STATUS; 3431 status = pci_read_config(dev, cap, 2); 3432 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3433 pci_write_config(dev, cap, status, 2); 3434 } 3435 3436 static void 3437 emx_update_stats(struct emx_softc *sc) 3438 { 3439 struct ifnet *ifp = &sc->arpcom.ac_if; 3440 3441 if (sc->hw.phy.media_type == e1000_media_type_copper || 3442 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3443 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 3444 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 3445 } 3446 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 3447 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 3448 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 3449 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 3450 3451 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 3452 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 3453 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 3454 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 3455 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 3456 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 3457 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 3458 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 3459 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 3460 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 3461 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 3462 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 3463 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 3464 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 3465 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 3466 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 3467 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 3468 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 3469 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 3470 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 3471 3472 /* For the 64-bit byte counters the low dword must be read first. */ 3473 /* Both registers clear on the read of the high dword */ 3474 3475 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH); 3476 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH); 3477 3478 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 3479 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 3480 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 3481 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 3482 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 3483 3484 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 3485 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 3486 3487 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 3488 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 3489 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 3490 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 3491 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 3492 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 3493 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 3494 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 3495 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 3496 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 3497 3498 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 3499 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC); 3500 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS); 3501 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR); 3502 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC); 3503 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC); 3504 3505 IFNET_STAT_SET(ifp, collisions, sc->stats.colc); 3506 3507 /* Rx Errors */ 3508 IFNET_STAT_SET(ifp, ierrors, 3509 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc + 3510 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr); 3511 3512 /* Tx Errors */ 3513 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol); 3514 } 3515 3516 static void 3517 emx_print_debug_info(struct emx_softc *sc) 3518 { 3519 device_t dev = sc->dev; 3520 uint8_t *hw_addr = sc->hw.hw_addr; 3521 int i; 3522 3523 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3524 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3525 E1000_READ_REG(&sc->hw, E1000_CTRL), 3526 E1000_READ_REG(&sc->hw, E1000_RCTL)); 3527 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3528 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3529 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) ); 3530 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3531 sc->hw.fc.high_water, sc->hw.fc.low_water); 3532 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3533 E1000_READ_REG(&sc->hw, E1000_TIDV), 3534 E1000_READ_REG(&sc->hw, E1000_TADV)); 3535 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3536 E1000_READ_REG(&sc->hw, E1000_RDTR), 3537 E1000_READ_REG(&sc->hw, E1000_RADV)); 3538 3539 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3540 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i, 3541 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 3542 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 3543 } 3544 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3545 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i, 3546 E1000_READ_REG(&sc->hw, E1000_RDH(i)), 3547 E1000_READ_REG(&sc->hw, E1000_RDT(i))); 3548 } 3549 3550 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3551 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i, 3552 sc->tx_data[i].num_tx_desc_avail); 3553 device_printf(dev, "TX %d TSO segments = %lu\n", i, 3554 sc->tx_data[i].tso_segments); 3555 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i, 3556 sc->tx_data[i].tso_ctx_reused); 3557 } 3558 } 3559 3560 static void 3561 emx_print_hw_stats(struct emx_softc *sc) 3562 { 3563 device_t dev = sc->dev; 3564 3565 device_printf(dev, "Excessive collisions = %lld\n", 3566 (long long)sc->stats.ecol); 3567 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3568 device_printf(dev, "Symbol errors = %lld\n", 3569 (long long)sc->stats.symerrs); 3570 #endif 3571 device_printf(dev, "Sequence errors = %lld\n", 3572 (long long)sc->stats.sec); 3573 device_printf(dev, "Defer count = %lld\n", 3574 (long long)sc->stats.dc); 3575 device_printf(dev, "Missed Packets = %lld\n", 3576 (long long)sc->stats.mpc); 3577 device_printf(dev, "Receive No Buffers = %lld\n", 3578 (long long)sc->stats.rnbc); 3579 /* RLEC is inaccurate on some hardware, calculate our own. */ 3580 device_printf(dev, "Receive Length Errors = %lld\n", 3581 ((long long)sc->stats.roc + (long long)sc->stats.ruc)); 3582 device_printf(dev, "Receive errors = %lld\n", 3583 (long long)sc->stats.rxerrc); 3584 device_printf(dev, "Crc errors = %lld\n", 3585 (long long)sc->stats.crcerrs); 3586 device_printf(dev, "Alignment errors = %lld\n", 3587 (long long)sc->stats.algnerrc); 3588 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3589 (long long)sc->stats.cexterr); 3590 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3591 device_printf(dev, "XON Rcvd = %lld\n", 3592 (long long)sc->stats.xonrxc); 3593 device_printf(dev, "XON Xmtd = %lld\n", 3594 (long long)sc->stats.xontxc); 3595 device_printf(dev, "XOFF Rcvd = %lld\n", 3596 (long long)sc->stats.xoffrxc); 3597 device_printf(dev, "XOFF Xmtd = %lld\n", 3598 (long long)sc->stats.xofftxc); 3599 device_printf(dev, "Good Packets Rcvd = %lld\n", 3600 (long long)sc->stats.gprc); 3601 device_printf(dev, "Good Packets Xmtd = %lld\n", 3602 (long long)sc->stats.gptc); 3603 } 3604 3605 static void 3606 emx_print_nvm_info(struct emx_softc *sc) 3607 { 3608 uint16_t eeprom_data; 3609 int i, j, row = 0; 3610 3611 /* Its a bit crude, but it gets the job done */ 3612 kprintf("\nInterface EEPROM Dump:\n"); 3613 kprintf("Offset\n0x0000 "); 3614 for (i = 0, j = 0; i < 32; i++, j++) { 3615 if (j == 8) { /* Make the offset block */ 3616 j = 0; ++row; 3617 kprintf("\n0x00%x0 ",row); 3618 } 3619 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data); 3620 kprintf("%04x ", eeprom_data); 3621 } 3622 kprintf("\n"); 3623 } 3624 3625 static int 3626 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3627 { 3628 struct emx_softc *sc; 3629 struct ifnet *ifp; 3630 int error, result; 3631 3632 result = -1; 3633 error = sysctl_handle_int(oidp, &result, 0, req); 3634 if (error || !req->newptr) 3635 return (error); 3636 3637 sc = (struct emx_softc *)arg1; 3638 ifp = &sc->arpcom.ac_if; 3639 3640 ifnet_serialize_all(ifp); 3641 3642 if (result == 1) 3643 emx_print_debug_info(sc); 3644 3645 /* 3646 * This value will cause a hex dump of the 3647 * first 32 16-bit words of the EEPROM to 3648 * the screen. 3649 */ 3650 if (result == 2) 3651 emx_print_nvm_info(sc); 3652 3653 ifnet_deserialize_all(ifp); 3654 3655 return (error); 3656 } 3657 3658 static int 3659 emx_sysctl_stats(SYSCTL_HANDLER_ARGS) 3660 { 3661 int error, result; 3662 3663 result = -1; 3664 error = sysctl_handle_int(oidp, &result, 0, req); 3665 if (error || !req->newptr) 3666 return (error); 3667 3668 if (result == 1) { 3669 struct emx_softc *sc = (struct emx_softc *)arg1; 3670 struct ifnet *ifp = &sc->arpcom.ac_if; 3671 3672 ifnet_serialize_all(ifp); 3673 emx_print_hw_stats(sc); 3674 ifnet_deserialize_all(ifp); 3675 } 3676 return (error); 3677 } 3678 3679 static void 3680 emx_add_sysctl(struct emx_softc *sc) 3681 { 3682 struct sysctl_ctx_list *ctx; 3683 struct sysctl_oid *tree; 3684 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG) 3685 char pkt_desc[32]; 3686 int i; 3687 #endif 3688 3689 ctx = device_get_sysctl_ctx(sc->dev); 3690 tree = device_get_sysctl_tree(sc->dev); 3691 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 3692 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3693 emx_sysctl_debug_info, "I", "Debug Information"); 3694 3695 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 3696 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3697 emx_sysctl_stats, "I", "Statistics"); 3698 3699 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 3700 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0, 3701 "# of RX descs"); 3702 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 3703 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0, 3704 "# of TX descs"); 3705 3706 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 3707 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3708 emx_sysctl_int_throttle, "I", "interrupt throttling rate"); 3709 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 3710 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3711 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt"); 3712 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 3713 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3714 emx_sysctl_tx_wreg_nsegs, "I", 3715 "# segments sent before write to hardware register"); 3716 3717 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 3718 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0, 3719 "# of RX rings"); 3720 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 3721 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0, 3722 "# of TX rings"); 3723 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 3724 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0, 3725 "# of TX rings used"); 3726 3727 #ifdef IFPOLL_ENABLE 3728 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 3729 OID_AUTO, "tx_poll_cpumap", CTLTYPE_OPAQUE | CTLFLAG_RD, 3730 sc->tx_rmap, 0, if_ringmap_cpumap_sysctl, "I", 3731 "TX polling CPU map"); 3732 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 3733 OID_AUTO, "rx_poll_cpumap", CTLTYPE_OPAQUE | CTLFLAG_RD, 3734 sc->rx_rmap, 0, if_ringmap_cpumap_sysctl, "I", 3735 "RX polling CPU map"); 3736 #endif 3737 3738 #ifdef EMX_RSS_DEBUG 3739 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 3740 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 3741 0, "RSS debug level"); 3742 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3743 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i); 3744 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 3745 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts, 3746 "RXed packets"); 3747 } 3748 #endif 3749 #ifdef EMX_TSS_DEBUG 3750 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3751 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i); 3752 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 3753 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts, 3754 "TXed packets"); 3755 } 3756 #endif 3757 } 3758 3759 static int 3760 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 3761 { 3762 struct emx_softc *sc = (void *)arg1; 3763 struct ifnet *ifp = &sc->arpcom.ac_if; 3764 int error, throttle; 3765 3766 throttle = sc->int_throttle_ceil; 3767 error = sysctl_handle_int(oidp, &throttle, 0, req); 3768 if (error || req->newptr == NULL) 3769 return error; 3770 if (throttle < 0 || throttle > 1000000000 / 256) 3771 return EINVAL; 3772 3773 if (throttle) { 3774 /* 3775 * Set the interrupt throttling rate in 256ns increments, 3776 * recalculate sysctl value assignment to get exact frequency. 3777 */ 3778 throttle = 1000000000 / 256 / throttle; 3779 3780 /* Upper 16bits of ITR is reserved and should be zero */ 3781 if (throttle & 0xffff0000) 3782 return EINVAL; 3783 } 3784 3785 ifnet_serialize_all(ifp); 3786 3787 if (throttle) 3788 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 3789 else 3790 sc->int_throttle_ceil = 0; 3791 3792 if (ifp->if_flags & IFF_RUNNING) 3793 emx_set_itr(sc, throttle); 3794 3795 ifnet_deserialize_all(ifp); 3796 3797 if (bootverbose) { 3798 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 3799 sc->int_throttle_ceil); 3800 } 3801 return 0; 3802 } 3803 3804 static int 3805 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS) 3806 { 3807 struct emx_softc *sc = (void *)arg1; 3808 struct ifnet *ifp = &sc->arpcom.ac_if; 3809 struct emx_txdata *tdata = &sc->tx_data[0]; 3810 int error, segs; 3811 3812 segs = tdata->tx_intr_nsegs; 3813 error = sysctl_handle_int(oidp, &segs, 0, req); 3814 if (error || req->newptr == NULL) 3815 return error; 3816 if (segs <= 0) 3817 return EINVAL; 3818 3819 ifnet_serialize_all(ifp); 3820 3821 /* 3822 * Don't allow tx_intr_nsegs to become: 3823 * o Less the oact_tx_desc 3824 * o Too large that no TX desc will cause TX interrupt to 3825 * be generated (OACTIVE will never recover) 3826 * o Too small that will cause tx_dd[] overflow 3827 */ 3828 if (segs < tdata->oact_tx_desc || 3829 segs >= tdata->num_tx_desc - tdata->oact_tx_desc || 3830 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) { 3831 error = EINVAL; 3832 } else { 3833 int i; 3834 3835 error = 0; 3836 for (i = 0; i < sc->tx_ring_cnt; ++i) 3837 sc->tx_data[i].tx_intr_nsegs = segs; 3838 } 3839 3840 ifnet_deserialize_all(ifp); 3841 3842 return error; 3843 } 3844 3845 static int 3846 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS) 3847 { 3848 struct emx_softc *sc = (void *)arg1; 3849 struct ifnet *ifp = &sc->arpcom.ac_if; 3850 int error, nsegs, i; 3851 3852 nsegs = sc->tx_data[0].tx_wreg_nsegs; 3853 error = sysctl_handle_int(oidp, &nsegs, 0, req); 3854 if (error || req->newptr == NULL) 3855 return error; 3856 3857 ifnet_serialize_all(ifp); 3858 for (i = 0; i < sc->tx_ring_cnt; ++i) 3859 sc->tx_data[i].tx_wreg_nsegs =nsegs; 3860 ifnet_deserialize_all(ifp); 3861 3862 return 0; 3863 } 3864 3865 static int 3866 emx_dma_alloc(struct emx_softc *sc) 3867 { 3868 int error, i; 3869 3870 /* 3871 * Create top level busdma tag 3872 */ 3873 error = bus_dma_tag_create(NULL, 1, 0, 3874 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3875 NULL, NULL, 3876 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3877 0, &sc->parent_dtag); 3878 if (error) { 3879 device_printf(sc->dev, "could not create top level DMA tag\n"); 3880 return error; 3881 } 3882 3883 /* 3884 * Allocate transmit descriptors ring and buffers 3885 */ 3886 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3887 error = emx_create_tx_ring(&sc->tx_data[i]); 3888 if (error) { 3889 device_printf(sc->dev, 3890 "Could not setup transmit structures\n"); 3891 return error; 3892 } 3893 } 3894 3895 /* 3896 * Allocate receive descriptors ring and buffers 3897 */ 3898 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3899 error = emx_create_rx_ring(&sc->rx_data[i]); 3900 if (error) { 3901 device_printf(sc->dev, 3902 "Could not setup receive structures\n"); 3903 return error; 3904 } 3905 } 3906 return 0; 3907 } 3908 3909 static void 3910 emx_dma_free(struct emx_softc *sc) 3911 { 3912 int i; 3913 3914 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3915 emx_destroy_tx_ring(&sc->tx_data[i], 3916 sc->tx_data[i].num_tx_desc); 3917 } 3918 3919 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3920 emx_destroy_rx_ring(&sc->rx_data[i], 3921 sc->rx_data[i].num_rx_desc); 3922 } 3923 3924 /* Free top level busdma tag */ 3925 if (sc->parent_dtag != NULL) 3926 bus_dma_tag_destroy(sc->parent_dtag); 3927 } 3928 3929 static void 3930 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 3931 { 3932 struct emx_softc *sc = ifp->if_softc; 3933 3934 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz); 3935 } 3936 3937 static void 3938 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3939 { 3940 struct emx_softc *sc = ifp->if_softc; 3941 3942 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz); 3943 } 3944 3945 static int 3946 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3947 { 3948 struct emx_softc *sc = ifp->if_softc; 3949 3950 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz); 3951 } 3952 3953 static void 3954 emx_serialize_skipmain(struct emx_softc *sc) 3955 { 3956 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1); 3957 } 3958 3959 static void 3960 emx_deserialize_skipmain(struct emx_softc *sc) 3961 { 3962 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1); 3963 } 3964 3965 #ifdef INVARIANTS 3966 3967 static void 3968 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 3969 boolean_t serialized) 3970 { 3971 struct emx_softc *sc = ifp->if_softc; 3972 3973 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE, 3974 slz, serialized); 3975 } 3976 3977 #endif /* INVARIANTS */ 3978 3979 #ifdef IFPOLL_ENABLE 3980 3981 static void 3982 emx_npoll_status(struct ifnet *ifp) 3983 { 3984 struct emx_softc *sc = ifp->if_softc; 3985 uint32_t reg_icr; 3986 3987 ASSERT_SERIALIZED(&sc->main_serialize); 3988 3989 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 3990 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 3991 callout_stop(&sc->timer); 3992 sc->hw.mac.get_link_status = 1; 3993 emx_update_link_status(sc); 3994 callout_reset(&sc->timer, hz, emx_timer, sc); 3995 } 3996 } 3997 3998 static void 3999 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused) 4000 { 4001 struct emx_txdata *tdata = arg; 4002 4003 ASSERT_SERIALIZED(&tdata->tx_serialize); 4004 4005 emx_txeof(tdata); 4006 if (!ifsq_is_empty(tdata->ifsq)) 4007 ifsq_devstart(tdata->ifsq); 4008 } 4009 4010 static void 4011 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle) 4012 { 4013 struct emx_rxdata *rdata = arg; 4014 4015 ASSERT_SERIALIZED(&rdata->rx_serialize); 4016 4017 emx_rxeof(rdata, cycle); 4018 } 4019 4020 static void 4021 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info) 4022 { 4023 struct emx_softc *sc = ifp->if_softc; 4024 int i, txr_cnt; 4025 4026 ASSERT_IFNET_SERIALIZED_ALL(ifp); 4027 4028 if (info) { 4029 int cpu; 4030 4031 info->ifpi_status.status_func = emx_npoll_status; 4032 info->ifpi_status.serializer = &sc->main_serialize; 4033 4034 txr_cnt = emx_get_txring_inuse(sc, TRUE); 4035 for (i = 0; i < txr_cnt; ++i) { 4036 struct emx_txdata *tdata = &sc->tx_data[i]; 4037 4038 cpu = if_ringmap_cpumap(sc->tx_rmap, i); 4039 KKASSERT(cpu < netisr_ncpus); 4040 info->ifpi_tx[cpu].poll_func = emx_npoll_tx; 4041 info->ifpi_tx[cpu].arg = tdata; 4042 info->ifpi_tx[cpu].serializer = &tdata->tx_serialize; 4043 ifsq_set_cpuid(tdata->ifsq, cpu); 4044 } 4045 4046 for (i = 0; i < sc->rx_ring_cnt; ++i) { 4047 struct emx_rxdata *rdata = &sc->rx_data[i]; 4048 4049 cpu = if_ringmap_cpumap(sc->rx_rmap, i); 4050 KKASSERT(cpu < netisr_ncpus); 4051 info->ifpi_rx[cpu].poll_func = emx_npoll_rx; 4052 info->ifpi_rx[cpu].arg = rdata; 4053 info->ifpi_rx[cpu].serializer = &rdata->rx_serialize; 4054 } 4055 } else { 4056 for (i = 0; i < sc->tx_ring_cnt; ++i) { 4057 struct emx_txdata *tdata = &sc->tx_data[i]; 4058 4059 ifsq_set_cpuid(tdata->ifsq, 4060 rman_get_cpuid(sc->intr_res)); 4061 } 4062 } 4063 if (ifp->if_flags & IFF_RUNNING) 4064 emx_init(sc); 4065 } 4066 4067 #endif /* IFPOLL_ENABLE */ 4068 4069 static void 4070 emx_set_itr(struct emx_softc *sc, uint32_t itr) 4071 { 4072 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr); 4073 if (sc->hw.mac.type == e1000_82574) { 4074 int i; 4075 4076 /* 4077 * When using MSIX interrupts we need to 4078 * throttle using the EITR register 4079 */ 4080 for (i = 0; i < 4; ++i) 4081 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr); 4082 } 4083 } 4084 4085 /* 4086 * Disable the L0s, 82574L Errata #20 4087 */ 4088 static void 4089 emx_disable_aspm(struct emx_softc *sc) 4090 { 4091 uint16_t link_cap, link_ctrl, disable; 4092 uint8_t pcie_ptr, reg; 4093 device_t dev = sc->dev; 4094 4095 switch (sc->hw.mac.type) { 4096 case e1000_82571: 4097 case e1000_82572: 4098 case e1000_82573: 4099 /* 4100 * 82573 specification update 4101 * errata #8 disable L0s 4102 * errata #41 disable L1 4103 * 4104 * 82571/82572 specification update 4105 # errata #13 disable L1 4106 * errata #68 disable L0s 4107 */ 4108 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 4109 break; 4110 4111 case e1000_82574: 4112 /* 4113 * 82574 specification update errata #20 4114 * 4115 * There is no need to disable L1 4116 */ 4117 disable = PCIEM_LNKCTL_ASPM_L0S; 4118 break; 4119 4120 default: 4121 return; 4122 } 4123 4124 pcie_ptr = pci_get_pciecap_ptr(dev); 4125 if (pcie_ptr == 0) 4126 return; 4127 4128 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 4129 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 4130 return; 4131 4132 if (bootverbose) 4133 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable); 4134 4135 reg = pcie_ptr + PCIER_LINKCTRL; 4136 link_ctrl = pci_read_config(dev, reg, 2); 4137 link_ctrl &= ~disable; 4138 pci_write_config(dev, reg, link_ctrl, 2); 4139 } 4140 4141 static int 4142 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp) 4143 { 4144 int iphlen, hoff, thoff, ex = 0; 4145 struct mbuf *m; 4146 struct ip *ip; 4147 4148 m = *mp; 4149 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 4150 4151 iphlen = m->m_pkthdr.csum_iphlen; 4152 thoff = m->m_pkthdr.csum_thlen; 4153 hoff = m->m_pkthdr.csum_lhlen; 4154 4155 KASSERT(iphlen > 0, ("invalid ip hlen")); 4156 KASSERT(thoff > 0, ("invalid tcp hlen")); 4157 KASSERT(hoff > 0, ("invalid ether hlen")); 4158 4159 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX) 4160 ex = 4; 4161 4162 if (m->m_len < hoff + iphlen + thoff + ex) { 4163 m = m_pullup(m, hoff + iphlen + thoff + ex); 4164 if (m == NULL) { 4165 *mp = NULL; 4166 return ENOBUFS; 4167 } 4168 *mp = m; 4169 } 4170 ip = mtodoff(m, struct ip *, hoff); 4171 ip->ip_len = 0; 4172 4173 return 0; 4174 } 4175 4176 static int 4177 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp, 4178 uint32_t *txd_upper, uint32_t *txd_lower) 4179 { 4180 struct e1000_context_desc *TXD; 4181 int hoff, iphlen, thoff, hlen; 4182 int mss, pktlen, curr_txd; 4183 4184 #ifdef EMX_TSO_DEBUG 4185 tdata->tso_segments++; 4186 #endif 4187 4188 iphlen = mp->m_pkthdr.csum_iphlen; 4189 thoff = mp->m_pkthdr.csum_thlen; 4190 hoff = mp->m_pkthdr.csum_lhlen; 4191 mss = mp->m_pkthdr.tso_segsz; 4192 pktlen = mp->m_pkthdr.len; 4193 4194 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 && 4195 tdata->csum_flags == CSUM_TSO && 4196 tdata->csum_iphlen == iphlen && 4197 tdata->csum_lhlen == hoff && 4198 tdata->csum_thlen == thoff && 4199 tdata->csum_mss == mss && 4200 tdata->csum_pktlen == pktlen) { 4201 *txd_upper = tdata->csum_txd_upper; 4202 *txd_lower = tdata->csum_txd_lower; 4203 #ifdef EMX_TSO_DEBUG 4204 tdata->tso_ctx_reused++; 4205 #endif 4206 return 0; 4207 } 4208 hlen = hoff + iphlen + thoff; 4209 4210 /* 4211 * Setup a new TSO context. 4212 */ 4213 4214 curr_txd = tdata->next_avail_tx_desc; 4215 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd]; 4216 4217 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 4218 E1000_TXD_DTYP_D | /* Data descr type */ 4219 E1000_TXD_CMD_TSE; /* Do TSE on this packet */ 4220 4221 /* IP and/or TCP header checksum calculation and insertion. */ 4222 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 4223 4224 /* 4225 * Start offset for header checksum calculation. 4226 * End offset for header checksum calculation. 4227 * Offset of place put the checksum. 4228 */ 4229 TXD->lower_setup.ip_fields.ipcss = hoff; 4230 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1); 4231 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum); 4232 4233 /* 4234 * Start offset for payload checksum calculation. 4235 * End offset for payload checksum calculation. 4236 * Offset of place to put the checksum. 4237 */ 4238 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen; 4239 TXD->upper_setup.tcp_fields.tucse = 0; 4240 TXD->upper_setup.tcp_fields.tucso = 4241 hoff + iphlen + offsetof(struct tcphdr, th_sum); 4242 4243 /* 4244 * Payload size per packet w/o any headers. 4245 * Length of all headers up to payload. 4246 */ 4247 TXD->tcp_seg_setup.fields.mss = htole16(mss); 4248 TXD->tcp_seg_setup.fields.hdr_len = hlen; 4249 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS | 4250 E1000_TXD_CMD_DEXT | /* Extended descr */ 4251 E1000_TXD_CMD_TSE | /* TSE context */ 4252 E1000_TXD_CMD_IP | /* Do IP csum */ 4253 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 4254 (pktlen - hlen)); /* Total len */ 4255 4256 /* Save the information for this TSO context */ 4257 tdata->csum_flags = CSUM_TSO; 4258 tdata->csum_lhlen = hoff; 4259 tdata->csum_iphlen = iphlen; 4260 tdata->csum_thlen = thoff; 4261 tdata->csum_mss = mss; 4262 tdata->csum_pktlen = pktlen; 4263 tdata->csum_txd_upper = *txd_upper; 4264 tdata->csum_txd_lower = *txd_lower; 4265 4266 if (++curr_txd == tdata->num_tx_desc) 4267 curr_txd = 0; 4268 4269 KKASSERT(tdata->num_tx_desc_avail > 0); 4270 tdata->num_tx_desc_avail--; 4271 4272 tdata->next_avail_tx_desc = curr_txd; 4273 return 1; 4274 } 4275 4276 static int 4277 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling) 4278 { 4279 if (polling) 4280 return sc->tx_ring_cnt; 4281 else 4282 return 1; 4283 } 4284