1 /* 2 * Copyright (c) 2001-2008, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_EMX_H_ 33 #define _IF_EMX_H_ 34 35 /* Tunables */ 36 37 /* 38 * EMX_TXD: Maximum number of Transmit Descriptors 39 * Valid Range: 256-4096 for others 40 * Default Value: 512 41 * This value is the number of transmit descriptors allocated by the driver. 42 * Increasing this value allows the driver to queue more transmits. Each 43 * descriptor is 16 bytes. 44 * Since TDLEN should be multiple of 128bytes, the number of transmit 45 * desscriptors should meet the following condition. 46 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 47 */ 48 #define EMX_MIN_TXD 256 49 #define EMX_MAX_TXD 4096 50 #define EMX_DEFAULT_TXD 512 51 52 /* 53 * EMX_RXD - Maximum number of receive Descriptors 54 * Valid Range: 256-4096 for others 55 * Default Value: 512 56 * This value is the number of receive descriptors allocated by the driver. 57 * Increasing this value allows the driver to buffer more incoming packets. 58 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 59 * descriptor. The maximum MTU size is 16110. 60 * Since TDLEN should be multiple of 128bytes, the number of transmit 61 * desscriptors should meet the following condition. 62 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 63 */ 64 #define EMX_MIN_RXD 256 65 #define EMX_MAX_RXD 4096 66 #define EMX_DEFAULT_RXD 512 67 68 /* 69 * Receive Interrupt Delay Timer (Packet Timer) 70 * 71 * NOTE: 72 * RDTR and RADV are deprecated; use ITR instead. They are only used to 73 * workaround hardware bug on certain 82573 based NICs. 74 */ 75 #define EMX_RDTR_82573 32 76 77 /* 78 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 79 * 80 * NOTE: 81 * RDTR and RADV are deprecated; use ITR instead. They are only used to 82 * workaround hardware bug on certain 82573 based NICs. 83 */ 84 #define EMX_RADV_82573 64 85 86 /* 87 * This parameter controls the duration of transmit watchdog timer. 88 */ 89 #define EMX_TX_TIMEOUT 5 90 91 /* One for TX csum offloading desc, the other 2 are reserved */ 92 #define EMX_TX_RESERVED 3 93 94 /* Large enough for 64K TSO segment */ 95 #define EMX_TX_SPARE 33 96 97 #define EMX_TX_OACTIVE_MAX 64 98 99 /* Interrupt throttle rate */ 100 #define EMX_DEFAULT_ITR 6000 101 102 /* Number of segments sent before writing to TX related registers */ 103 #define EMX_DEFAULT_TXWREG 8 104 105 /* 106 * This parameter controls whether or not autonegotation is enabled. 107 * 0 - Disable autonegotiation 108 * 1 - Enable autonegotiation 109 */ 110 #define EMX_DO_AUTO_NEG 1 111 112 /* Tunables -- End */ 113 114 #define EMX_AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \ 115 ADVERTISE_10_FULL | \ 116 ADVERTISE_100_HALF | \ 117 ADVERTISE_100_FULL | \ 118 ADVERTISE_1000_FULL) 119 120 #define EMX_AUTO_ALL_MODES 0 121 122 /* PHY master/slave setting */ 123 #define EMX_MASTER_SLAVE e1000_ms_hw_default 124 125 /* 126 * Micellaneous constants 127 */ 128 #define EMX_VENDOR_ID 0x8086 129 130 #define EMX_BAR_MEM PCIR_BAR(0) 131 132 #define EMX_JUMBO_PBA 0x00000028 133 #define EMX_DEFAULT_PBA 0x00000030 134 #define EMX_SMARTSPEED_DOWNSHIFT 3 135 #define EMX_SMARTSPEED_MAX 15 136 #define EMX_MAX_INTR 10 137 138 #define EMX_MCAST_ADDR_MAX 128 139 #define EMX_FC_PAUSE_TIME 1000 140 #define EMX_EEPROM_APME 0x400; 141 142 /* 143 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 144 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 145 * also optimize cache line size effect. H/W supports up to cache line size 128. 146 */ 147 #define EMX_DBA_ALIGN 128 148 149 /* 150 * Speed mode bit in TARC0. 151 * 82571EB/82572EI only, used to improve small packet transmit performance. 152 */ 153 #define EMX_TARC_SPEED_MODE (1 << 21) 154 155 /* 156 * Multiple TX queues arbitration count mask in TARC0/TARC1. 157 */ 158 #define EMX_TARC_COUNT_MASK 0x7f 159 160 #define EMX_MAX_SCATTER 64 161 #define EMX_TSO_SIZE (IP_MAXPACKET + \ 162 sizeof(struct ether_vlan_header)) 163 #define EMX_MAX_SEGSIZE PAGE_SIZE 164 #define EMX_MSIX_MASK 0x01F00000 /* For 82574 use */ 165 166 #define EMX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 167 168 /* 169 * 82574 has a nonstandard address for EIAC 170 * and since its only used in MSIX, and in 171 * the em driver only 82574 uses MSIX we can 172 * solve it just using this define. 173 */ 174 #define EMX_EIAC 0x000DC 175 176 #define EMX_NRSSRK 10 177 #define EMX_RSSRK_SIZE 4 178 #define EMX_RSSRK_VAL(key, i) (key[(i) * EMX_RSSRK_SIZE] | \ 179 key[(i) * EMX_RSSRK_SIZE + 1] << 8 | \ 180 key[(i) * EMX_RSSRK_SIZE + 2] << 16 | \ 181 key[(i) * EMX_RSSRK_SIZE + 3] << 24) 182 183 #define EMX_NRETA 32 184 #define EMX_RETA_SIZE 4 185 #define EMX_RETA_RINGIDX_SHIFT 7 186 187 #define EMX_NRX_RING 2 188 #define EMX_NTX_RING 2 189 #define EMX_NSERIALIZE 5 190 191 typedef union e1000_rx_desc_extended emx_rxdesc_t; 192 193 #define rxd_bufaddr read.buffer_addr /* 64bits */ 194 #define rxd_length wb.upper.length /* 16bits */ 195 #define rxd_vlan wb.upper.vlan /* 16bits */ 196 #define rxd_staterr wb.upper.status_error /* 32bits */ 197 #define rxd_mrq wb.lower.mrq /* 32bits */ 198 #define rxd_rss wb.lower.hi_dword.rss /* 32bits */ 199 200 #define EMX_RXDMRQ_RSSTYPE_MASK 0xf 201 #define EMX_RXDMRQ_NO_HASH 0 202 #define EMX_RXDMRQ_IPV4_TCP 1 203 #define EMX_RXDMRQ_IPV4 2 204 #define EMX_RXDMRQ_IPV6_TCP 3 205 #define EMX_RXDMRQ_IPV6 5 206 207 struct emx_softc; 208 209 struct emx_rxdata { 210 struct lwkt_serialize rx_serialize; 211 struct emx_softc *sc; 212 int idx; 213 214 /* 215 * Receive definitions 216 * 217 * we have an array of num_rx_desc rx_desc (handled by the 218 * controller), and paired with an array of rx_buffers 219 * (at rx_buffer_area). 220 * The next pair to check on receive is at offset next_rx_desc_to_check 221 */ 222 emx_rxdesc_t *rx_desc; 223 uint32_t next_rx_desc_to_check; 224 int num_rx_desc; 225 struct emx_rxbuf *rx_buf; 226 bus_dma_tag_t rxtag; 227 bus_dmamap_t rx_sparemap; 228 229 /* 230 * First/last mbuf pointers, for 231 * collecting multisegment RX packets. 232 */ 233 struct mbuf *fmp; 234 struct mbuf *lmp; 235 236 /* RX statistics */ 237 unsigned long rx_pkts; 238 239 bus_dma_tag_t rx_desc_dtag; 240 bus_dmamap_t rx_desc_dmap; 241 bus_addr_t rx_desc_paddr; 242 } __cachealign; 243 244 struct emx_txdata { 245 struct lwkt_serialize tx_serialize; 246 struct emx_softc *sc; 247 struct ifaltq_subque *ifsq; 248 int idx; 249 uint32_t tx_flags; 250 #define EMX_TXFLAG_TSO_PULLEX 0x1 251 #define EMX_TXFLAG_ENABLED 0x2 252 #define EMX_TXFLAG_FORCECTX 0x4 253 254 /* 255 * Transmit definitions 256 * 257 * We have an array of num_tx_desc descriptors (handled 258 * by the controller) paired with an array of tx_buffers 259 * (at tx_buffer_area). 260 * The index of the next available descriptor is next_avail_tx_desc. 261 * The number of remaining tx_desc is num_tx_desc_avail. 262 */ 263 struct e1000_tx_desc *tx_desc_base; 264 struct emx_txbuf *tx_buf; 265 uint32_t next_avail_tx_desc; 266 uint32_t next_tx_to_clean; 267 int num_tx_desc_avail; 268 int num_tx_desc; 269 bus_dma_tag_t txtag; /* dma tag for tx */ 270 int spare_tx_desc; 271 int oact_tx_desc; 272 273 /* Saved csum offloading context information */ 274 int csum_flags; 275 int csum_lhlen; 276 int csum_iphlen; 277 278 int csum_thlen; /* TSO */ 279 int csum_mss; /* TSO */ 280 int csum_pktlen; /* TSO */ 281 282 uint32_t csum_txd_upper; 283 uint32_t csum_txd_lower; 284 285 int tx_wreg_nsegs; 286 287 /* 288 * Variables used to reduce TX interrupt rate and 289 * number of device's TX ring write requests. 290 * 291 * tx_nsegs: 292 * Number of TX descriptors setup so far. 293 * 294 * tx_int_nsegs: 295 * Once tx_nsegs > tx_int_nsegs, RS bit will be set 296 * in the last TX descriptor of the packet, and 297 * tx_nsegs will be reset to 0. So TX interrupt and 298 * TX ring write request should be generated roughly 299 * every tx_int_nsegs TX descriptors. 300 * 301 * tx_dd[]: 302 * Index of the TX descriptors which have RS bit set, 303 * i.e. DD bit will be set on this TX descriptor after 304 * the data of the TX descriptor are transfered to 305 * hardware's internal packet buffer. Only the TX 306 * descriptors listed in tx_dd[] will be checked upon 307 * TX interrupt. This array is used as circular ring. 308 * 309 * tx_dd_tail, tx_dd_head: 310 * Tail and head index of valid elements in tx_dd[]. 311 * tx_dd_tail == tx_dd_head means there is no valid 312 * elements in tx_dd[]. tx_dd_tail points to the position 313 * which is one beyond the last valid element in tx_dd[]. 314 * tx_dd_head points to the first valid element in 315 * tx_dd[]. 316 */ 317 int tx_intr_nsegs; 318 int tx_nsegs; 319 int tx_dd_tail; 320 int tx_dd_head; 321 #define EMX_TXDD_MAX 64 322 #define EMX_TXDD_SAFE 48 /* 48 <= val < EMX_TXDD_MAX */ 323 int tx_dd[EMX_TXDD_MAX]; 324 325 struct ifsubq_watchdog tx_watchdog; 326 327 /* TX statistics */ 328 unsigned long tx_pkts; 329 unsigned long tso_segments; 330 unsigned long tso_ctx_reused; 331 332 bus_dma_tag_t tx_desc_dtag; 333 bus_dmamap_t tx_desc_dmap; 334 bus_addr_t tx_desc_paddr; 335 } __cachealign; 336 337 struct emx_softc { 338 struct arpcom arpcom; 339 struct e1000_hw hw; 340 int flags; 341 #define EMX_FLAG_SHARED_INTR 0x0001 342 #define EMX_FLAG_HAS_MGMT 0x0004 343 #define EMX_FLAG_HAS_AMT 0x0008 344 #define EMX_FLAG_HW_CTRL 0x0010 345 346 /* DragonFly operating-system-specific structures. */ 347 struct e1000_osdep osdep; 348 device_t dev; 349 350 bus_dma_tag_t parent_dtag; 351 352 struct resource *memory; 353 int memory_rid; 354 355 struct resource *intr_res; 356 void *intr_tag; 357 int intr_rid; 358 int intr_type; 359 360 struct ifmedia media; 361 struct callout timer; 362 int if_flags; 363 int max_frame_size; 364 int min_frame_size; 365 366 /* WOL register value */ 367 int wol; 368 369 /* Multicast array memory */ 370 uint8_t *mta; 371 372 /* Info about the board itself */ 373 uint8_t link_active; 374 uint16_t link_speed; 375 uint16_t link_duplex; 376 uint32_t smartspeed; 377 int int_throttle_ceil; 378 379 int rx_npoll_off; 380 int tx_npoll_off; 381 382 struct lwkt_serialize main_serialize; 383 struct lwkt_serialize *serializes[EMX_NSERIALIZE]; 384 385 int tx_ring_cnt; 386 int tx_ring_inuse; 387 struct emx_txdata tx_data[EMX_NTX_RING]; 388 389 int rss_debug; 390 int rx_ring_cnt; 391 struct emx_rxdata rx_data[EMX_NRX_RING]; 392 393 /* Misc stats maintained by the driver */ 394 unsigned long rx_overruns; 395 396 /* sysctl tree glue */ 397 struct sysctl_ctx_list sysctl_ctx; 398 struct sysctl_oid *sysctl_tree; 399 400 struct e1000_hw_stats stats; 401 }; 402 403 struct emx_txbuf { 404 struct mbuf *m_head; 405 bus_dmamap_t map; 406 }; 407 408 struct emx_rxbuf { 409 struct mbuf *m_head; 410 bus_dmamap_t map; 411 bus_addr_t paddr; 412 }; 413 414 #define EMX_IS_OACTIVE(tdata) \ 415 ((tdata)->num_tx_desc_avail <= (tdata)->oact_tx_desc) 416 417 #define EMX_INC_TXDD_IDX(idx) \ 418 do { \ 419 if (++(idx) == EMX_TXDD_MAX) \ 420 (idx) = 0; \ 421 } while (0) 422 423 #endif /* !_IF_EMX_H_ */ 424