1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.42 2005/12/31 14:07:59 sephe Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include "opt_polling.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 #include <sys/thread2.h> 46 47 #include <net/if.h> 48 #include <net/ifq_var.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #ifdef NS 53 #include <netns/ns.h> 54 #include <netns/ns_if.h> 55 #endif 56 57 #include <net/bpf.h> 58 #include <sys/sockio.h> 59 #include <sys/bus.h> 60 #include <machine/bus.h> 61 #include <sys/rman.h> 62 #include <machine/resource.h> 63 64 #include <net/ethernet.h> 65 #include <net/if_arp.h> 66 67 #include <vm/vm.h> /* for vtophys */ 68 #include <vm/pmap.h> /* for vtophys */ 69 70 #include <net/if_types.h> 71 #include <net/vlan/if_vlan_var.h> 72 73 #include <bus/pci/pcivar.h> 74 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76 #include "../mii_layer/mii.h" 77 #include "../mii_layer/miivar.h" 78 79 #include "if_fxpreg.h" 80 #include "if_fxpvar.h" 81 #include "rcvbundl.h" 82 83 #include "miibus_if.h" 84 85 /* 86 * NOTE! On the Alpha, we have an alignment constraint. The 87 * card DMAs the packet immediately following the RFA. However, 88 * the first thing in the packet is a 14-byte Ethernet header. 89 * This means that the packet is misaligned. To compensate, 90 * we actually offset the RFA 2 bytes into the cluster. This 91 * alignes the packet after the Ethernet header at a 32-bit 92 * boundary. HOWEVER! This means that the RFA is misaligned! 93 */ 94 #define RFA_ALIGNMENT_FUDGE 2 95 96 /* 97 * Set initial transmit threshold at 64 (512 bytes). This is 98 * increased by 64 (512 bytes) at a time, to maximum of 192 99 * (1536 bytes), if an underrun occurs. 100 */ 101 static int tx_threshold = 64; 102 103 /* 104 * The configuration byte map has several undefined fields which 105 * must be one or must be zero. Set up a template for these bits 106 * only, (assuming a 82557 chip) leaving the actual configuration 107 * to fxp_init. 108 * 109 * See struct fxp_cb_config for the bit definitions. 110 */ 111 static u_char fxp_cb_config_template[] = { 112 0x0, 0x0, /* cb_status */ 113 0x0, 0x0, /* cb_command */ 114 0x0, 0x0, 0x0, 0x0, /* link_addr */ 115 0x0, /* 0 */ 116 0x0, /* 1 */ 117 0x0, /* 2 */ 118 0x0, /* 3 */ 119 0x0, /* 4 */ 120 0x0, /* 5 */ 121 0x32, /* 6 */ 122 0x0, /* 7 */ 123 0x0, /* 8 */ 124 0x0, /* 9 */ 125 0x6, /* 10 */ 126 0x0, /* 11 */ 127 0x0, /* 12 */ 128 0x0, /* 13 */ 129 0xf2, /* 14 */ 130 0x48, /* 15 */ 131 0x0, /* 16 */ 132 0x40, /* 17 */ 133 0xf0, /* 18 */ 134 0x0, /* 19 */ 135 0x3f, /* 20 */ 136 0x5 /* 21 */ 137 }; 138 139 struct fxp_ident { 140 u_int16_t devid; 141 int16_t revid; /* -1 matches anything */ 142 char *name; 143 }; 144 145 /* 146 * Claim various Intel PCI device identifiers for this driver. The 147 * sub-vendor and sub-device field are extensively used to identify 148 * particular variants, but we don't currently differentiate between 149 * them. 150 */ 151 static struct fxp_ident fxp_ident_table[] = { 152 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 153 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 154 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 155 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 156 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 157 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 158 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 162 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 163 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 165 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 167 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 169 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 170 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 171 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, 172 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 173 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 174 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 175 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 176 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 179 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 180 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 181 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 184 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 185 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 188 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 189 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 190 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 191 { 0, -1, NULL }, 192 }; 193 194 static int fxp_probe(device_t dev); 195 static int fxp_attach(device_t dev); 196 static int fxp_detach(device_t dev); 197 static int fxp_shutdown(device_t dev); 198 static int fxp_suspend(device_t dev); 199 static int fxp_resume(device_t dev); 200 201 static void fxp_intr(void *xsc); 202 static void fxp_intr_body(struct fxp_softc *sc, 203 u_int8_t statack, int count); 204 205 static void fxp_init(void *xsc); 206 static void fxp_tick(void *xsc); 207 static void fxp_powerstate_d0(device_t dev); 208 static void fxp_start(struct ifnet *ifp); 209 static void fxp_stop(struct fxp_softc *sc); 210 static void fxp_release(device_t dev); 211 static int fxp_ioctl(struct ifnet *ifp, u_long command, 212 caddr_t data, struct ucred *); 213 static void fxp_watchdog(struct ifnet *ifp); 214 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 215 static int fxp_mc_addrs(struct fxp_softc *sc); 216 static void fxp_mc_setup(struct fxp_softc *sc); 217 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 218 int autosize); 219 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 220 u_int16_t data); 221 static void fxp_autosize_eeprom(struct fxp_softc *sc); 222 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 223 int offset, int words); 224 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 225 int offset, int words); 226 static int fxp_ifmedia_upd(struct ifnet *ifp); 227 static void fxp_ifmedia_sts(struct ifnet *ifp, 228 struct ifmediareq *ifmr); 229 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 230 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 231 struct ifmediareq *ifmr); 232 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 233 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 234 int value); 235 static void fxp_load_ucode(struct fxp_softc *sc); 236 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 237 int low, int high); 238 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 239 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 240 #ifdef DEVICE_POLLING 241 static poll_handler_t fxp_poll; 242 #endif 243 244 static void fxp_lwcopy(volatile u_int32_t *src, 245 volatile u_int32_t *dst); 246 static void fxp_scb_wait(struct fxp_softc *sc); 247 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 248 static void fxp_dma_wait(volatile u_int16_t *status, 249 struct fxp_softc *sc); 250 251 static device_method_t fxp_methods[] = { 252 /* Device interface */ 253 DEVMETHOD(device_probe, fxp_probe), 254 DEVMETHOD(device_attach, fxp_attach), 255 DEVMETHOD(device_detach, fxp_detach), 256 DEVMETHOD(device_shutdown, fxp_shutdown), 257 DEVMETHOD(device_suspend, fxp_suspend), 258 DEVMETHOD(device_resume, fxp_resume), 259 260 /* MII interface */ 261 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 262 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 263 264 { 0, 0 } 265 }; 266 267 static driver_t fxp_driver = { 268 "fxp", 269 fxp_methods, 270 sizeof(struct fxp_softc), 271 }; 272 273 static devclass_t fxp_devclass; 274 275 DECLARE_DUMMY_MODULE(if_fxp); 276 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 277 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 278 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 279 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 280 281 static int fxp_rnr; 282 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 283 284 /* 285 * Copy a 16-bit aligned 32-bit quantity. 286 */ 287 static void 288 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 289 { 290 #ifdef __i386__ 291 *dst = *src; 292 #else 293 volatile u_int16_t *a = (volatile u_int16_t *)src; 294 volatile u_int16_t *b = (volatile u_int16_t *)dst; 295 296 b[0] = a[0]; 297 b[1] = a[1]; 298 #endif 299 } 300 301 /* 302 * Wait for the previous command to be accepted (but not necessarily 303 * completed). 304 */ 305 static void 306 fxp_scb_wait(struct fxp_softc *sc) 307 { 308 int i = 10000; 309 310 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 311 DELAY(2); 312 if (i == 0) { 313 if_printf(&sc->arpcom.ac_if, 314 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 315 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 316 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 317 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 318 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 319 } 320 } 321 322 static void 323 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 324 { 325 326 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 327 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 328 fxp_scb_wait(sc); 329 } 330 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 331 } 332 333 static void 334 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 335 { 336 int i = 10000; 337 338 while (!(*status & FXP_CB_STATUS_C) && --i) 339 DELAY(2); 340 if (i == 0) 341 if_printf(&sc->arpcom.ac_if, "DMA timeout\n"); 342 } 343 344 /* 345 * Return identification string if this is device is ours. 346 */ 347 static int 348 fxp_probe(device_t dev) 349 { 350 u_int16_t devid; 351 u_int8_t revid; 352 struct fxp_ident *ident; 353 354 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 355 devid = pci_get_device(dev); 356 revid = pci_get_revid(dev); 357 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 358 if (ident->devid == devid && 359 (ident->revid == revid || ident->revid == -1)) { 360 device_set_desc(dev, ident->name); 361 return (0); 362 } 363 } 364 } 365 return (ENXIO); 366 } 367 368 static void 369 fxp_powerstate_d0(device_t dev) 370 { 371 u_int32_t iobase, membase, irq; 372 373 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 374 /* Save important PCI config data. */ 375 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 376 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 377 irq = pci_read_config(dev, PCIR_INTLINE, 4); 378 379 /* Reset the power state. */ 380 device_printf(dev, "chip is in D%d power mode " 381 "-- setting to D0\n", pci_get_powerstate(dev)); 382 383 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 384 385 /* Restore PCI config data. */ 386 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 387 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 388 pci_write_config(dev, PCIR_INTLINE, irq, 4); 389 } 390 } 391 392 static int 393 fxp_attach(device_t dev) 394 { 395 int error = 0; 396 struct fxp_softc *sc = device_get_softc(dev); 397 struct ifnet *ifp; 398 u_int32_t val; 399 u_int16_t data; 400 int i, rid, m1, m2, prefer_iomap; 401 402 callout_init(&sc->fxp_stat_timer); 403 sysctl_ctx_init(&sc->sysctl_ctx); 404 405 /* 406 * Enable bus mastering. Enable memory space too, in case 407 * BIOS/Prom forgot about it. 408 */ 409 pci_enable_busmaster(dev); 410 pci_enable_io(dev, SYS_RES_MEMORY); 411 val = pci_read_config(dev, PCIR_COMMAND, 2); 412 413 fxp_powerstate_d0(dev); 414 415 /* 416 * Figure out which we should try first - memory mapping or i/o mapping? 417 * We default to memory mapping. Then we accept an override from the 418 * command line. Then we check to see which one is enabled. 419 */ 420 m1 = PCIM_CMD_MEMEN; 421 m2 = PCIM_CMD_PORTEN; 422 prefer_iomap = 0; 423 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 424 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 425 m1 = PCIM_CMD_PORTEN; 426 m2 = PCIM_CMD_MEMEN; 427 } 428 429 if (val & m1) { 430 sc->rtp = 431 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 432 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 433 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 434 RF_ACTIVE); 435 } 436 if (sc->mem == NULL && (val & m2)) { 437 sc->rtp = 438 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 439 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 440 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 441 RF_ACTIVE); 442 } 443 444 if (!sc->mem) { 445 device_printf(dev, "could not map device registers\n"); 446 error = ENXIO; 447 goto fail; 448 } 449 if (bootverbose) { 450 device_printf(dev, "using %s space register mapping\n", 451 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 452 } 453 454 sc->sc_st = rman_get_bustag(sc->mem); 455 sc->sc_sh = rman_get_bushandle(sc->mem); 456 457 /* 458 * Allocate our interrupt. 459 */ 460 rid = 0; 461 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 462 RF_SHAREABLE | RF_ACTIVE); 463 if (sc->irq == NULL) { 464 device_printf(dev, "could not map interrupt\n"); 465 error = ENXIO; 466 goto fail; 467 } 468 469 /* 470 * Reset to a stable state. 471 */ 472 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 473 DELAY(10); 474 475 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 476 M_DEVBUF, M_WAITOK | M_ZERO); 477 478 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 479 M_WAITOK | M_ZERO); 480 481 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 482 483 /* 484 * Pre-allocate our receive buffers. 485 */ 486 for (i = 0; i < FXP_NRFABUFS; i++) { 487 if (fxp_add_rfabuf(sc, NULL) != 0) { 488 goto failmem; 489 } 490 } 491 492 /* 493 * Find out how large of an SEEPROM we have. 494 */ 495 fxp_autosize_eeprom(sc); 496 497 /* 498 * Determine whether we must use the 503 serial interface. 499 */ 500 fxp_read_eeprom(sc, &data, 6, 1); 501 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 502 (data & FXP_PHY_SERIAL_ONLY)) 503 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 504 505 /* 506 * Create the sysctl tree 507 */ 508 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 509 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 510 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 511 if (sc->sysctl_tree == NULL) 512 goto fail; 513 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 514 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 515 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 516 "FXP driver receive interrupt microcode bundling delay"); 517 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 518 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 519 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 520 "FXP driver receive interrupt microcode bundle size limit"); 521 522 /* 523 * Pull in device tunables. 524 */ 525 sc->tunable_int_delay = TUNABLE_INT_DELAY; 526 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 527 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 528 "int_delay", &sc->tunable_int_delay); 529 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 530 "bundle_max", &sc->tunable_bundle_max); 531 532 /* 533 * Find out the chip revision; lump all 82557 revs together. 534 */ 535 fxp_read_eeprom(sc, &data, 5, 1); 536 if ((data >> 8) == 1) 537 sc->revision = FXP_REV_82557; 538 else 539 sc->revision = pci_get_revid(dev); 540 541 /* 542 * Enable workarounds for certain chip revision deficiencies. 543 * 544 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 545 * some systems based a normal 82559 design, have a defect where 546 * the chip can cause a PCI protocol violation if it receives 547 * a CU_RESUME command when it is entering the IDLE state. The 548 * workaround is to disable Dynamic Standby Mode, so the chip never 549 * deasserts CLKRUN#, and always remains in an active state. 550 * 551 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 552 */ 553 i = pci_get_device(dev); 554 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 555 sc->revision >= FXP_REV_82559_A0) { 556 fxp_read_eeprom(sc, &data, 10, 1); 557 if (data & 0x02) { /* STB enable */ 558 u_int16_t cksum; 559 int i; 560 561 device_printf(dev, 562 "Disabling dynamic standby mode in EEPROM\n"); 563 data &= ~0x02; 564 fxp_write_eeprom(sc, &data, 10, 1); 565 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 566 cksum = 0; 567 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 568 fxp_read_eeprom(sc, &data, i, 1); 569 cksum += data; 570 } 571 i = (1 << sc->eeprom_size) - 1; 572 cksum = 0xBABA - cksum; 573 fxp_read_eeprom(sc, &data, i, 1); 574 fxp_write_eeprom(sc, &cksum, i, 1); 575 device_printf(dev, 576 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 577 i, data, cksum); 578 #if 1 579 /* 580 * If the user elects to continue, try the software 581 * workaround, as it is better than nothing. 582 */ 583 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 584 #endif 585 } 586 } 587 588 /* 589 * If we are not a 82557 chip, we can enable extended features. 590 */ 591 if (sc->revision != FXP_REV_82557) { 592 /* 593 * If MWI is enabled in the PCI configuration, and there 594 * is a valid cacheline size (8 or 16 dwords), then tell 595 * the board to turn on MWI. 596 */ 597 if (val & PCIM_CMD_MWRICEN && 598 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 599 sc->flags |= FXP_FLAG_MWI_ENABLE; 600 601 /* turn on the extended TxCB feature */ 602 sc->flags |= FXP_FLAG_EXT_TXCB; 603 604 /* enable reception of long frames for VLAN */ 605 sc->flags |= FXP_FLAG_LONG_PKT_EN; 606 } 607 608 /* 609 * Read MAC address. 610 */ 611 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 612 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 613 device_printf(dev, "10Mbps\n"); 614 if (bootverbose) { 615 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 616 pci_get_vendor(dev), pci_get_device(dev), 617 pci_get_subvendor(dev), pci_get_subdevice(dev), 618 pci_get_revid(dev)); 619 fxp_read_eeprom(sc, &data, 10, 1); 620 device_printf(dev, "Dynamic Standby mode is %s\n", 621 data & 0x02 ? "enabled" : "disabled"); 622 } 623 624 /* 625 * If this is only a 10Mbps device, then there is no MII, and 626 * the PHY will use a serial interface instead. 627 * 628 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 629 * doesn't have a programming interface of any sort. The 630 * media is sensed automatically based on how the link partner 631 * is configured. This is, in essence, manual configuration. 632 */ 633 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 634 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 635 fxp_serial_ifmedia_sts); 636 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 637 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 638 } else { 639 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 640 fxp_ifmedia_sts)) { 641 device_printf(dev, "MII without any PHY!\n"); 642 error = ENXIO; 643 goto fail; 644 } 645 } 646 647 ifp = &sc->arpcom.ac_if; 648 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 649 ifp->if_baudrate = 100000000; 650 ifp->if_init = fxp_init; 651 ifp->if_softc = sc; 652 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 653 ifp->if_ioctl = fxp_ioctl; 654 ifp->if_start = fxp_start; 655 #ifdef DEVICE_POLLING 656 ifp->if_poll = fxp_poll; 657 #endif 658 ifp->if_watchdog = fxp_watchdog; 659 660 /* 661 * Attach the interface. 662 */ 663 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 664 665 /* 666 * Tell the upper layer(s) we support long frames. 667 */ 668 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 669 670 /* 671 * Let the system queue as many packets as we have available 672 * TX descriptors. 673 */ 674 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1); 675 ifq_set_ready(&ifp->if_snd); 676 677 error = bus_setup_intr(dev, sc->irq, INTR_NETSAFE, 678 fxp_intr, sc, &sc->ih, 679 ifp->if_serializer); 680 if (error) { 681 ether_ifdetach(ifp); 682 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 683 ifmedia_removeall(&sc->sc_media); 684 device_printf(dev, "could not setup irq\n"); 685 goto fail; 686 } 687 688 return (0); 689 690 failmem: 691 device_printf(dev, "Failed to malloc memory\n"); 692 error = ENOMEM; 693 fail: 694 fxp_release(dev); 695 return (error); 696 } 697 698 /* 699 * release all resources 700 */ 701 static void 702 fxp_release(device_t dev) 703 { 704 struct fxp_softc *sc = device_get_softc(dev); 705 706 if (sc->miibus) 707 device_delete_child(dev, sc->miibus); 708 bus_generic_detach(dev); 709 710 if (sc->cbl_base) 711 free(sc->cbl_base, M_DEVBUF); 712 if (sc->fxp_stats) 713 free(sc->fxp_stats, M_DEVBUF); 714 if (sc->mcsp) 715 free(sc->mcsp, M_DEVBUF); 716 if (sc->rfa_headm) 717 m_freem(sc->rfa_headm); 718 719 if (sc->irq) 720 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 721 if (sc->mem) 722 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); 723 724 sysctl_ctx_free(&sc->sysctl_ctx); 725 } 726 727 /* 728 * Detach interface. 729 */ 730 static int 731 fxp_detach(device_t dev) 732 { 733 struct fxp_softc *sc = device_get_softc(dev); 734 735 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 736 737 /* 738 * Stop DMA and drop transmit queue. 739 */ 740 fxp_stop(sc); 741 742 /* 743 * Disable interrupts. 744 * 745 * NOTE: This should be done after fxp_stop(), because software 746 * resetting in fxp_stop() may leave interrupts turned on. 747 */ 748 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 749 750 /* 751 * Free all media structures. 752 */ 753 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 754 ifmedia_removeall(&sc->sc_media); 755 756 if (sc->ih) 757 bus_teardown_intr(dev, sc->irq, sc->ih); 758 759 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 760 761 /* 762 * Close down routes etc. 763 */ 764 ether_ifdetach(&sc->arpcom.ac_if); 765 766 /* Release our allocated resources. */ 767 fxp_release(dev); 768 769 return (0); 770 } 771 772 /* 773 * Device shutdown routine. Called at system shutdown after sync. The 774 * main purpose of this routine is to shut off receiver DMA so that 775 * kernel memory doesn't get clobbered during warmboot. 776 */ 777 static int 778 fxp_shutdown(device_t dev) 779 { 780 /* 781 * Make sure that DMA is disabled prior to reboot. Not doing 782 * do could allow DMA to corrupt kernel memory during the 783 * reboot before the driver initializes. 784 */ 785 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 786 return (0); 787 } 788 789 /* 790 * Device suspend routine. Stop the interface and save some PCI 791 * settings in case the BIOS doesn't restore them properly on 792 * resume. 793 */ 794 static int 795 fxp_suspend(device_t dev) 796 { 797 struct fxp_softc *sc = device_get_softc(dev); 798 int i; 799 800 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 801 802 fxp_stop(sc); 803 804 for (i = 0; i < 5; i++) 805 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 806 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 807 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 808 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 809 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 810 811 sc->suspended = 1; 812 813 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 814 return (0); 815 } 816 817 /* 818 * Device resume routine. Restore some PCI settings in case the BIOS 819 * doesn't, re-enable busmastering, and restart the interface if 820 * appropriate. 821 */ 822 static int 823 fxp_resume(device_t dev) 824 { 825 struct fxp_softc *sc = device_get_softc(dev); 826 struct ifnet *ifp = &sc->arpcom.ac_if; 827 int i; 828 829 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 830 831 fxp_powerstate_d0(dev); 832 833 /* better way to do this? */ 834 for (i = 0; i < 5; i++) 835 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 836 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 837 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 838 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 839 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 840 841 /* reenable busmastering and memory space */ 842 pci_enable_busmaster(dev); 843 pci_enable_io(dev, SYS_RES_MEMORY); 844 845 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 846 DELAY(10); 847 848 /* reinitialize interface if necessary */ 849 if (ifp->if_flags & IFF_UP) 850 fxp_init(sc); 851 852 sc->suspended = 0; 853 854 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 855 return (0); 856 } 857 858 static void 859 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 860 { 861 u_int16_t reg; 862 int x; 863 864 /* 865 * Shift in data. 866 */ 867 for (x = 1 << (length - 1); x; x >>= 1) { 868 if (data & x) 869 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 870 else 871 reg = FXP_EEPROM_EECS; 872 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 873 DELAY(1); 874 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 875 DELAY(1); 876 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 877 DELAY(1); 878 } 879 } 880 881 /* 882 * Read from the serial EEPROM. Basically, you manually shift in 883 * the read opcode (one bit at a time) and then shift in the address, 884 * and then you shift out the data (all of this one bit at a time). 885 * The word size is 16 bits, so you have to provide the address for 886 * every 16 bits of data. 887 */ 888 static u_int16_t 889 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 890 { 891 u_int16_t reg, data; 892 int x; 893 894 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 895 /* 896 * Shift in read opcode. 897 */ 898 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 899 /* 900 * Shift in address. 901 */ 902 data = 0; 903 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 904 if (offset & x) 905 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 906 else 907 reg = FXP_EEPROM_EECS; 908 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 909 DELAY(1); 910 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 911 DELAY(1); 912 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 913 DELAY(1); 914 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 915 data++; 916 if (autosize && reg == 0) { 917 sc->eeprom_size = data; 918 break; 919 } 920 } 921 /* 922 * Shift out data. 923 */ 924 data = 0; 925 reg = FXP_EEPROM_EECS; 926 for (x = 1 << 15; x; x >>= 1) { 927 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 928 DELAY(1); 929 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 930 data |= x; 931 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 932 DELAY(1); 933 } 934 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 935 DELAY(1); 936 937 return (data); 938 } 939 940 static void 941 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 942 { 943 int i; 944 945 /* 946 * Erase/write enable. 947 */ 948 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 949 fxp_eeprom_shiftin(sc, 0x4, 3); 950 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 951 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 952 DELAY(1); 953 /* 954 * Shift in write opcode, address, data. 955 */ 956 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 957 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 958 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 959 fxp_eeprom_shiftin(sc, data, 16); 960 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 961 DELAY(1); 962 /* 963 * Wait for EEPROM to finish up. 964 */ 965 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 966 DELAY(1); 967 for (i = 0; i < 1000; i++) { 968 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 969 break; 970 DELAY(50); 971 } 972 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 973 DELAY(1); 974 /* 975 * Erase/write disable. 976 */ 977 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 978 fxp_eeprom_shiftin(sc, 0x4, 3); 979 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 980 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 981 DELAY(1); 982 } 983 984 /* 985 * From NetBSD: 986 * 987 * Figure out EEPROM size. 988 * 989 * 559's can have either 64-word or 256-word EEPROMs, the 558 990 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 991 * talks about the existance of 16 to 256 word EEPROMs. 992 * 993 * The only known sizes are 64 and 256, where the 256 version is used 994 * by CardBus cards to store CIS information. 995 * 996 * The address is shifted in msb-to-lsb, and after the last 997 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 998 * after which follows the actual data. We try to detect this zero, by 999 * probing the data-out bit in the EEPROM control register just after 1000 * having shifted in a bit. If the bit is zero, we assume we've 1001 * shifted enough address bits. The data-out should be tri-state, 1002 * before this, which should translate to a logical one. 1003 */ 1004 static void 1005 fxp_autosize_eeprom(struct fxp_softc *sc) 1006 { 1007 1008 /* guess maximum size of 256 words */ 1009 sc->eeprom_size = 8; 1010 1011 /* autosize */ 1012 (void) fxp_eeprom_getword(sc, 0, 1); 1013 } 1014 1015 static void 1016 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1017 { 1018 int i; 1019 1020 for (i = 0; i < words; i++) 1021 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1022 } 1023 1024 static void 1025 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1026 { 1027 int i; 1028 1029 for (i = 0; i < words; i++) 1030 fxp_eeprom_putword(sc, offset + i, data[i]); 1031 } 1032 1033 /* 1034 * Start packet transmission on the interface. 1035 */ 1036 static void 1037 fxp_start(struct ifnet *ifp) 1038 { 1039 struct fxp_softc *sc = ifp->if_softc; 1040 struct fxp_cb_tx *txp; 1041 1042 /* 1043 * See if we need to suspend xmit until the multicast filter 1044 * has been reprogrammed (which can only be done at the head 1045 * of the command chain). 1046 */ 1047 if (sc->need_mcsetup) { 1048 return; 1049 } 1050 1051 txp = NULL; 1052 1053 /* 1054 * We're finished if there is nothing more to add to the list or if 1055 * we're all filled up with buffers to transmit. 1056 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1057 * a NOP command when needed. 1058 */ 1059 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) { 1060 struct mbuf *m, *mb_head; 1061 int segment, ntries = 0; 1062 1063 /* 1064 * Grab a packet to transmit. The packet is dequeued, 1065 * once we are sure that we have enough free descriptors. 1066 */ 1067 mb_head = ifq_poll(&ifp->if_snd); 1068 if (mb_head == NULL) 1069 break; 1070 1071 /* 1072 * Get pointer to next available tx desc. 1073 */ 1074 txp = sc->cbl_last->next; 1075 1076 /* 1077 * Go through each of the mbufs in the chain and initialize 1078 * the transmit buffer descriptors with the physical address 1079 * and size of the mbuf. 1080 */ 1081 tbdinit: 1082 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1083 if (m->m_len != 0) { 1084 if (segment == FXP_NTXSEG) 1085 break; 1086 txp->tbd[segment].tb_addr = 1087 vtophys(mtod(m, vm_offset_t)); 1088 txp->tbd[segment].tb_size = m->m_len; 1089 segment++; 1090 } 1091 } 1092 if (m != NULL) { 1093 struct mbuf *mn; 1094 1095 /* 1096 * We ran out of segments. We have to recopy this 1097 * mbuf chain first. Bail out if we can't get the 1098 * new buffers. 1099 */ 1100 if (ntries > 0) 1101 break; 1102 mn = m_dup(mb_head, MB_DONTWAIT); 1103 if (mn == NULL) 1104 break; 1105 /* We can transmit the packet, dequeue it. */ 1106 ifq_dequeue(&ifp->if_snd, mb_head); 1107 m_freem(mb_head); 1108 mb_head = mn; 1109 ntries = 1; 1110 goto tbdinit; 1111 } else { 1112 /* Nothing to worry about, just dequeue. */ 1113 ifq_dequeue(&ifp->if_snd, mb_head); 1114 } 1115 1116 txp->tbd_number = segment; 1117 txp->mb_head = mb_head; 1118 txp->cb_status = 0; 1119 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1120 txp->cb_command = 1121 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1122 FXP_CB_COMMAND_S; 1123 } else { 1124 txp->cb_command = 1125 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1126 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1127 /* 1128 * Set a 5 second timer just in case we don't hear 1129 * from the card again. 1130 */ 1131 ifp->if_timer = 5; 1132 } 1133 txp->tx_threshold = tx_threshold; 1134 1135 /* 1136 * Advance the end of list forward. 1137 */ 1138 1139 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1140 sc->cbl_last = txp; 1141 1142 /* 1143 * Advance the beginning of the list forward if there are 1144 * no other packets queued (when nothing is queued, cbl_first 1145 * sits on the last TxCB that was sent out). 1146 */ 1147 if (sc->tx_queued == 0) 1148 sc->cbl_first = txp; 1149 1150 sc->tx_queued++; 1151 1152 BPF_MTAP(ifp, mb_head); 1153 } 1154 1155 /* 1156 * We're finished. If we added to the list, issue a RESUME to get DMA 1157 * going again if suspended. 1158 */ 1159 if (txp != NULL) { 1160 fxp_scb_wait(sc); 1161 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1162 } 1163 } 1164 1165 #ifdef DEVICE_POLLING 1166 1167 static void 1168 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1169 { 1170 struct fxp_softc *sc = ifp->if_softc; 1171 u_int8_t statack; 1172 1173 switch(cmd) { 1174 case POLL_REGISTER: 1175 /* disable interrupts */ 1176 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1177 break; 1178 case POLL_DEREGISTER: 1179 /* enable interrupts */ 1180 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1181 break; 1182 default: 1183 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1184 FXP_SCB_STATACK_FR; 1185 if (cmd == POLL_AND_CHECK_STATUS) { 1186 u_int8_t tmp; 1187 1188 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1189 if (tmp == 0xff || tmp == 0) 1190 return; /* nothing to do */ 1191 tmp &= ~statack; 1192 /* ack what we can */ 1193 if (tmp != 0) 1194 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1195 statack |= tmp; 1196 } 1197 fxp_intr_body(sc, statack, count); 1198 break; 1199 } 1200 } 1201 1202 #endif /* DEVICE_POLLING */ 1203 1204 /* 1205 * Process interface interrupts. 1206 */ 1207 static void 1208 fxp_intr(void *xsc) 1209 { 1210 struct fxp_softc *sc = xsc; 1211 u_int8_t statack; 1212 1213 if (sc->suspended) { 1214 return; 1215 } 1216 1217 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1218 /* 1219 * It should not be possible to have all bits set; the 1220 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1221 * all bits are set, this may indicate that the card has 1222 * been physically ejected, so ignore it. 1223 */ 1224 if (statack == 0xff) 1225 return; 1226 1227 /* 1228 * First ACK all the interrupts in this pass. 1229 */ 1230 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1231 fxp_intr_body(sc, statack, -1); 1232 } 1233 } 1234 1235 static void 1236 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1237 { 1238 struct ifnet *ifp = &sc->arpcom.ac_if; 1239 struct mbuf *m; 1240 struct fxp_rfa *rfa; 1241 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1242 1243 if (rnr) 1244 fxp_rnr++; 1245 #ifdef DEVICE_POLLING 1246 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1247 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1248 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1249 rnr = 1; 1250 } 1251 #endif 1252 1253 /* 1254 * Free any finished transmit mbuf chains. 1255 * 1256 * Handle the CNA event likt a CXTNO event. It used to 1257 * be that this event (control unit not ready) was not 1258 * encountered, but it is now with the SMPng modifications. 1259 * The exact sequence of events that occur when the interface 1260 * is brought up are different now, and if this event 1261 * goes unhandled, the configuration/rxfilter setup sequence 1262 * can stall for several seconds. The result is that no 1263 * packets go out onto the wire for about 5 to 10 seconds 1264 * after the interface is ifconfig'ed for the first time. 1265 */ 1266 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1267 struct fxp_cb_tx *txp; 1268 1269 for (txp = sc->cbl_first; sc->tx_queued && 1270 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1271 txp = txp->next) { 1272 if ((m = txp->mb_head) != NULL) { 1273 txp->mb_head = NULL; 1274 sc->tx_queued--; 1275 m_freem(m); 1276 } else { 1277 sc->tx_queued--; 1278 } 1279 } 1280 sc->cbl_first = txp; 1281 ifp->if_timer = 0; 1282 if (sc->tx_queued == 0) { 1283 if (sc->need_mcsetup) 1284 fxp_mc_setup(sc); 1285 } 1286 /* 1287 * Try to start more packets transmitting. 1288 */ 1289 if (!ifq_is_empty(&ifp->if_snd)) 1290 (*ifp->if_start)(ifp); 1291 } 1292 1293 /* 1294 * Just return if nothing happened on the receive side. 1295 */ 1296 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1297 return; 1298 1299 /* 1300 * Process receiver interrupts. If a no-resource (RNR) 1301 * condition exists, get whatever packets we can and 1302 * re-start the receiver. 1303 * 1304 * When using polling, we do not process the list to completion, 1305 * so when we get an RNR interrupt we must defer the restart 1306 * until we hit the last buffer with the C bit set. 1307 * If we run out of cycles and rfa_headm has the C bit set, 1308 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1309 * that the info will be used in the subsequent polling cycle. 1310 */ 1311 for (;;) { 1312 m = sc->rfa_headm; 1313 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1314 RFA_ALIGNMENT_FUDGE); 1315 1316 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1317 if (count >= 0 && count-- == 0) { 1318 if (rnr) { 1319 /* Defer RNR processing until the next time. */ 1320 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1321 rnr = 0; 1322 } 1323 break; 1324 } 1325 #endif /* DEVICE_POLLING */ 1326 1327 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1328 break; 1329 1330 /* 1331 * Remove first packet from the chain. 1332 */ 1333 sc->rfa_headm = m->m_next; 1334 m->m_next = NULL; 1335 1336 /* 1337 * Add a new buffer to the receive chain. 1338 * If this fails, the old buffer is recycled 1339 * instead. 1340 */ 1341 if (fxp_add_rfabuf(sc, m) == 0) { 1342 int total_len; 1343 1344 /* 1345 * Fetch packet length (the top 2 bits of 1346 * actual_size are flags set by the controller 1347 * upon completion), and drop the packet in case 1348 * of bogus length or CRC errors. 1349 */ 1350 total_len = rfa->actual_size & 0x3fff; 1351 if (total_len < sizeof(struct ether_header) || 1352 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1353 sizeof(struct fxp_rfa) || 1354 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1355 m_freem(m); 1356 continue; 1357 } 1358 m->m_pkthdr.len = m->m_len = total_len; 1359 ifp->if_input(ifp, m); 1360 } 1361 } 1362 if (rnr) { 1363 fxp_scb_wait(sc); 1364 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1365 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1366 RFA_ALIGNMENT_FUDGE); 1367 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1368 } 1369 } 1370 1371 /* 1372 * Update packet in/out/collision statistics. The i82557 doesn't 1373 * allow you to access these counters without doing a fairly 1374 * expensive DMA to get _all_ of the statistics it maintains, so 1375 * we do this operation here only once per second. The statistics 1376 * counters in the kernel are updated from the previous dump-stats 1377 * DMA and then a new dump-stats DMA is started. The on-chip 1378 * counters are zeroed when the DMA completes. If we can't start 1379 * the DMA immediately, we don't wait - we just prepare to read 1380 * them again next time. 1381 */ 1382 static void 1383 fxp_tick(void *xsc) 1384 { 1385 struct fxp_softc *sc = xsc; 1386 struct ifnet *ifp = &sc->arpcom.ac_if; 1387 struct fxp_stats *sp = sc->fxp_stats; 1388 struct fxp_cb_tx *txp; 1389 struct mbuf *m; 1390 1391 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1392 1393 ifp->if_opackets += sp->tx_good; 1394 ifp->if_collisions += sp->tx_total_collisions; 1395 if (sp->rx_good) { 1396 ifp->if_ipackets += sp->rx_good; 1397 sc->rx_idle_secs = 0; 1398 } else { 1399 /* 1400 * Receiver's been idle for another second. 1401 */ 1402 sc->rx_idle_secs++; 1403 } 1404 ifp->if_ierrors += 1405 sp->rx_crc_errors + 1406 sp->rx_alignment_errors + 1407 sp->rx_rnr_errors + 1408 sp->rx_overrun_errors; 1409 /* 1410 * If any transmit underruns occured, bump up the transmit 1411 * threshold by another 512 bytes (64 * 8). 1412 */ 1413 if (sp->tx_underruns) { 1414 ifp->if_oerrors += sp->tx_underruns; 1415 if (tx_threshold < 192) 1416 tx_threshold += 64; 1417 } 1418 1419 /* 1420 * Release any xmit buffers that have completed DMA. This isn't 1421 * strictly necessary to do here, but it's advantagous for mbufs 1422 * with external storage to be released in a timely manner rather 1423 * than being defered for a potentially long time. This limits 1424 * the delay to a maximum of one second. 1425 */ 1426 for (txp = sc->cbl_first; sc->tx_queued && 1427 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1428 txp = txp->next) { 1429 if ((m = txp->mb_head) != NULL) { 1430 txp->mb_head = NULL; 1431 sc->tx_queued--; 1432 m_freem(m); 1433 } else { 1434 sc->tx_queued--; 1435 } 1436 } 1437 sc->cbl_first = txp; 1438 /* 1439 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1440 * then assume the receiver has locked up and attempt to clear 1441 * the condition by reprogramming the multicast filter. This is 1442 * a work-around for a bug in the 82557 where the receiver locks 1443 * up if it gets certain types of garbage in the syncronization 1444 * bits prior to the packet header. This bug is supposed to only 1445 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1446 * mode as well (perhaps due to a 10/100 speed transition). 1447 */ 1448 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1449 sc->rx_idle_secs = 0; 1450 fxp_mc_setup(sc); 1451 } 1452 /* 1453 * If there is no pending command, start another stats 1454 * dump. Otherwise punt for now. 1455 */ 1456 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1457 /* 1458 * Start another stats dump. 1459 */ 1460 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1461 } else { 1462 /* 1463 * A previous command is still waiting to be accepted. 1464 * Just zero our copy of the stats and wait for the 1465 * next timer event to update them. 1466 */ 1467 sp->tx_good = 0; 1468 sp->tx_underruns = 0; 1469 sp->tx_total_collisions = 0; 1470 1471 sp->rx_good = 0; 1472 sp->rx_crc_errors = 0; 1473 sp->rx_alignment_errors = 0; 1474 sp->rx_rnr_errors = 0; 1475 sp->rx_overrun_errors = 0; 1476 } 1477 if (sc->miibus != NULL) 1478 mii_tick(device_get_softc(sc->miibus)); 1479 /* 1480 * Schedule another timeout one second from now. 1481 */ 1482 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1483 1484 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1485 } 1486 1487 /* 1488 * Stop the interface. Cancels the statistics updater and resets 1489 * the interface. 1490 */ 1491 static void 1492 fxp_stop(struct fxp_softc *sc) 1493 { 1494 struct ifnet *ifp = &sc->arpcom.ac_if; 1495 struct fxp_cb_tx *txp; 1496 int i; 1497 1498 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1499 ifp->if_timer = 0; 1500 1501 /* 1502 * Cancel stats updater. 1503 */ 1504 callout_stop(&sc->fxp_stat_timer); 1505 1506 /* 1507 * Issue software reset, which also unloads the microcode. 1508 */ 1509 sc->flags &= ~FXP_FLAG_UCODE; 1510 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1511 DELAY(50); 1512 1513 /* 1514 * Release any xmit buffers. 1515 */ 1516 txp = sc->cbl_base; 1517 if (txp != NULL) { 1518 for (i = 0; i < FXP_NTXCB; i++) { 1519 if (txp[i].mb_head != NULL) { 1520 m_freem(txp[i].mb_head); 1521 txp[i].mb_head = NULL; 1522 } 1523 } 1524 } 1525 sc->tx_queued = 0; 1526 1527 /* 1528 * Free all the receive buffers then reallocate/reinitialize 1529 */ 1530 if (sc->rfa_headm != NULL) 1531 m_freem(sc->rfa_headm); 1532 sc->rfa_headm = NULL; 1533 sc->rfa_tailm = NULL; 1534 for (i = 0; i < FXP_NRFABUFS; i++) { 1535 if (fxp_add_rfabuf(sc, NULL) != 0) { 1536 /* 1537 * This "can't happen" - we're at splimp() 1538 * and we just freed all the buffers we need 1539 * above. 1540 */ 1541 panic("fxp_stop: no buffers!"); 1542 } 1543 } 1544 } 1545 1546 /* 1547 * Watchdog/transmission transmit timeout handler. Called when a 1548 * transmission is started on the interface, but no interrupt is 1549 * received before the timeout. This usually indicates that the 1550 * card has wedged for some reason. 1551 */ 1552 static void 1553 fxp_watchdog(struct ifnet *ifp) 1554 { 1555 if_printf(ifp, "device timeout\n"); 1556 ifp->if_oerrors++; 1557 fxp_init(ifp->if_softc); 1558 } 1559 1560 static void 1561 fxp_init(void *xsc) 1562 { 1563 struct fxp_softc *sc = xsc; 1564 struct ifnet *ifp = &sc->arpcom.ac_if; 1565 struct fxp_cb_config *cbp; 1566 struct fxp_cb_ias *cb_ias; 1567 struct fxp_cb_tx *txp; 1568 struct fxp_cb_mcs *mcsp; 1569 int i, prm; 1570 1571 /* 1572 * Cancel any pending I/O 1573 */ 1574 fxp_stop(sc); 1575 1576 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1577 1578 /* 1579 * Initialize base of CBL and RFA memory. Loading with zero 1580 * sets it up for regular linear addressing. 1581 */ 1582 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1583 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1584 1585 fxp_scb_wait(sc); 1586 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1587 1588 /* 1589 * Initialize base of dump-stats buffer. 1590 */ 1591 fxp_scb_wait(sc); 1592 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1593 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1594 1595 /* 1596 * Attempt to load microcode if requested. 1597 */ 1598 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1599 fxp_load_ucode(sc); 1600 1601 /* 1602 * Initialize the multicast address list. 1603 */ 1604 if (fxp_mc_addrs(sc)) { 1605 mcsp = sc->mcsp; 1606 mcsp->cb_status = 0; 1607 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1608 mcsp->link_addr = -1; 1609 /* 1610 * Start the multicast setup command. 1611 */ 1612 fxp_scb_wait(sc); 1613 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1614 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1615 /* ...and wait for it to complete. */ 1616 fxp_dma_wait(&mcsp->cb_status, sc); 1617 } 1618 1619 /* 1620 * We temporarily use memory that contains the TxCB list to 1621 * construct the config CB. The TxCB list memory is rebuilt 1622 * later. 1623 */ 1624 cbp = (struct fxp_cb_config *) sc->cbl_base; 1625 1626 /* 1627 * This bcopy is kind of disgusting, but there are a bunch of must be 1628 * zero and must be one bits in this structure and this is the easiest 1629 * way to initialize them all to proper values. 1630 */ 1631 bcopy(fxp_cb_config_template, 1632 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1633 sizeof(fxp_cb_config_template)); 1634 1635 cbp->cb_status = 0; 1636 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1637 cbp->link_addr = -1; /* (no) next command */ 1638 cbp->byte_count = 22; /* (22) bytes to config */ 1639 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1640 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1641 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1642 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1643 cbp->type_enable = 0; /* actually reserved */ 1644 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1645 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1646 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1647 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1648 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1649 cbp->late_scb = 0; /* (don't) defer SCB update */ 1650 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1651 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1652 cbp->ci_int = 1; /* interrupt on CU idle */ 1653 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1654 cbp->ext_stats_dis = 1; /* disable extended counters */ 1655 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1656 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1657 cbp->disc_short_rx = !prm; /* discard short packets */ 1658 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1659 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1660 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1661 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1662 cbp->csma_dis = 0; /* (don't) disable link */ 1663 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1664 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1665 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1666 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1667 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1668 cbp->nsai = 1; /* (don't) disable source addr insert */ 1669 cbp->preamble_length = 2; /* (7 byte) preamble */ 1670 cbp->loopback = 0; /* (don't) loopback */ 1671 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1672 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1673 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1674 cbp->promiscuous = prm; /* promiscuous mode */ 1675 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1676 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1677 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1678 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1679 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1680 1681 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1682 cbp->padding = 1; /* (do) pad short tx packets */ 1683 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1684 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1685 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1686 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1687 /* must set wake_en in PMCSR also */ 1688 cbp->force_fdx = 0; /* (don't) force full duplex */ 1689 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1690 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1691 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1692 1693 if (sc->revision == FXP_REV_82557) { 1694 /* 1695 * The 82557 has no hardware flow control, the values 1696 * below are the defaults for the chip. 1697 */ 1698 cbp->fc_delay_lsb = 0; 1699 cbp->fc_delay_msb = 0x40; 1700 cbp->pri_fc_thresh = 3; 1701 cbp->tx_fc_dis = 0; 1702 cbp->rx_fc_restop = 0; 1703 cbp->rx_fc_restart = 0; 1704 cbp->fc_filter = 0; 1705 cbp->pri_fc_loc = 1; 1706 } else { 1707 cbp->fc_delay_lsb = 0x1f; 1708 cbp->fc_delay_msb = 0x01; 1709 cbp->pri_fc_thresh = 3; 1710 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1711 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1712 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1713 cbp->fc_filter = !prm; /* drop FC frames to host */ 1714 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1715 } 1716 1717 /* 1718 * Start the config command/DMA. 1719 */ 1720 fxp_scb_wait(sc); 1721 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1722 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1723 /* ...and wait for it to complete. */ 1724 fxp_dma_wait(&cbp->cb_status, sc); 1725 1726 /* 1727 * Now initialize the station address. Temporarily use the TxCB 1728 * memory area like we did above for the config CB. 1729 */ 1730 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1731 cb_ias->cb_status = 0; 1732 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1733 cb_ias->link_addr = -1; 1734 bcopy(sc->arpcom.ac_enaddr, 1735 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1736 sizeof(sc->arpcom.ac_enaddr)); 1737 1738 /* 1739 * Start the IAS (Individual Address Setup) command/DMA. 1740 */ 1741 fxp_scb_wait(sc); 1742 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1743 /* ...and wait for it to complete. */ 1744 fxp_dma_wait(&cb_ias->cb_status, sc); 1745 1746 /* 1747 * Initialize transmit control block (TxCB) list. 1748 */ 1749 1750 txp = sc->cbl_base; 1751 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1752 for (i = 0; i < FXP_NTXCB; i++) { 1753 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1754 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1755 txp[i].link_addr = 1756 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1757 if (sc->flags & FXP_FLAG_EXT_TXCB) 1758 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1759 else 1760 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1761 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1762 } 1763 /* 1764 * Set the suspend flag on the first TxCB and start the control 1765 * unit. It will execute the NOP and then suspend. 1766 */ 1767 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1768 sc->cbl_first = sc->cbl_last = txp; 1769 sc->tx_queued = 1; 1770 1771 fxp_scb_wait(sc); 1772 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1773 1774 /* 1775 * Initialize receiver buffer area - RFA. 1776 */ 1777 fxp_scb_wait(sc); 1778 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1779 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1780 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1781 1782 /* 1783 * Set current media. 1784 */ 1785 if (sc->miibus != NULL) 1786 mii_mediachg(device_get_softc(sc->miibus)); 1787 1788 ifp->if_flags |= IFF_RUNNING; 1789 ifp->if_flags &= ~IFF_OACTIVE; 1790 1791 /* 1792 * Enable interrupts. 1793 */ 1794 #ifdef DEVICE_POLLING 1795 /* 1796 * ... but only do that if we are not polling. And because (presumably) 1797 * the default is interrupts on, we need to disable them explicitly! 1798 */ 1799 if ( ifp->if_flags & IFF_POLLING ) 1800 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1801 else 1802 #endif /* DEVICE_POLLING */ 1803 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1804 1805 /* 1806 * Start stats updater. 1807 */ 1808 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1809 } 1810 1811 static int 1812 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1813 { 1814 1815 return (0); 1816 } 1817 1818 static void 1819 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1820 { 1821 1822 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1823 } 1824 1825 /* 1826 * Change media according to request. 1827 */ 1828 static int 1829 fxp_ifmedia_upd(struct ifnet *ifp) 1830 { 1831 struct fxp_softc *sc = ifp->if_softc; 1832 struct mii_data *mii; 1833 1834 mii = device_get_softc(sc->miibus); 1835 mii_mediachg(mii); 1836 return (0); 1837 } 1838 1839 /* 1840 * Notify the world which media we're using. 1841 */ 1842 static void 1843 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1844 { 1845 struct fxp_softc *sc = ifp->if_softc; 1846 struct mii_data *mii; 1847 1848 mii = device_get_softc(sc->miibus); 1849 mii_pollstat(mii); 1850 ifmr->ifm_active = mii->mii_media_active; 1851 ifmr->ifm_status = mii->mii_media_status; 1852 1853 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1854 sc->cu_resume_bug = 1; 1855 else 1856 sc->cu_resume_bug = 0; 1857 } 1858 1859 /* 1860 * Add a buffer to the end of the RFA buffer list. 1861 * Return 0 if successful, 1 for failure. A failure results in 1862 * adding the 'oldm' (if non-NULL) on to the end of the list - 1863 * tossing out its old contents and recycling it. 1864 * The RFA struct is stuck at the beginning of mbuf cluster and the 1865 * data pointer is fixed up to point just past it. 1866 */ 1867 static int 1868 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1869 { 1870 u_int32_t v; 1871 struct mbuf *m; 1872 struct fxp_rfa *rfa, *p_rfa; 1873 1874 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1875 if (m == NULL) { /* try to recycle the old mbuf instead */ 1876 if (oldm == NULL) 1877 return 1; 1878 m = oldm; 1879 m->m_data = m->m_ext.ext_buf; 1880 } 1881 1882 /* 1883 * Move the data pointer up so that the incoming data packet 1884 * will be 32-bit aligned. 1885 */ 1886 m->m_data += RFA_ALIGNMENT_FUDGE; 1887 1888 /* 1889 * Get a pointer to the base of the mbuf cluster and move 1890 * data start past it. 1891 */ 1892 rfa = mtod(m, struct fxp_rfa *); 1893 m->m_data += sizeof(struct fxp_rfa); 1894 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1895 1896 /* 1897 * Initialize the rest of the RFA. Note that since the RFA 1898 * is misaligned, we cannot store values directly. Instead, 1899 * we use an optimized, inline copy. 1900 */ 1901 1902 rfa->rfa_status = 0; 1903 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1904 rfa->actual_size = 0; 1905 1906 v = -1; 1907 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1908 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1909 1910 /* 1911 * If there are other buffers already on the list, attach this 1912 * one to the end by fixing up the tail to point to this one. 1913 */ 1914 if (sc->rfa_headm != NULL) { 1915 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1916 RFA_ALIGNMENT_FUDGE); 1917 sc->rfa_tailm->m_next = m; 1918 v = vtophys(rfa); 1919 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1920 p_rfa->rfa_control = 0; 1921 } else { 1922 sc->rfa_headm = m; 1923 } 1924 sc->rfa_tailm = m; 1925 1926 return (m == oldm); 1927 } 1928 1929 static volatile int 1930 fxp_miibus_readreg(device_t dev, int phy, int reg) 1931 { 1932 struct fxp_softc *sc = device_get_softc(dev); 1933 int count = 10000; 1934 int value; 1935 1936 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1937 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1938 1939 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1940 && count--) 1941 DELAY(10); 1942 1943 if (count <= 0) 1944 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1945 1946 return (value & 0xffff); 1947 } 1948 1949 static void 1950 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1951 { 1952 struct fxp_softc *sc = device_get_softc(dev); 1953 int count = 10000; 1954 1955 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1956 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1957 (value & 0xffff)); 1958 1959 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1960 count--) 1961 DELAY(10); 1962 1963 if (count <= 0) 1964 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1965 } 1966 1967 static int 1968 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1969 { 1970 struct fxp_softc *sc = ifp->if_softc; 1971 struct ifreq *ifr = (struct ifreq *)data; 1972 struct mii_data *mii; 1973 int error = 0; 1974 1975 switch (command) { 1976 1977 case SIOCSIFFLAGS: 1978 if (ifp->if_flags & IFF_ALLMULTI) 1979 sc->flags |= FXP_FLAG_ALL_MCAST; 1980 else 1981 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1982 1983 /* 1984 * If interface is marked up and not running, then start it. 1985 * If it is marked down and running, stop it. 1986 * XXX If it's up then re-initialize it. This is so flags 1987 * such as IFF_PROMISC are handled. 1988 */ 1989 if (ifp->if_flags & IFF_UP) { 1990 fxp_init(sc); 1991 } else { 1992 if (ifp->if_flags & IFF_RUNNING) 1993 fxp_stop(sc); 1994 } 1995 break; 1996 1997 case SIOCADDMULTI: 1998 case SIOCDELMULTI: 1999 if (ifp->if_flags & IFF_ALLMULTI) 2000 sc->flags |= FXP_FLAG_ALL_MCAST; 2001 else 2002 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2003 /* 2004 * Multicast list has changed; set the hardware filter 2005 * accordingly. 2006 */ 2007 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2008 fxp_mc_setup(sc); 2009 /* 2010 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2011 * again rather than else {}. 2012 */ 2013 if (sc->flags & FXP_FLAG_ALL_MCAST) 2014 fxp_init(sc); 2015 error = 0; 2016 break; 2017 2018 case SIOCSIFMEDIA: 2019 case SIOCGIFMEDIA: 2020 if (sc->miibus != NULL) { 2021 mii = device_get_softc(sc->miibus); 2022 error = ifmedia_ioctl(ifp, ifr, 2023 &mii->mii_media, command); 2024 } else { 2025 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2026 } 2027 break; 2028 2029 default: 2030 error = ether_ioctl(ifp, command, data); 2031 break; 2032 } 2033 return (error); 2034 } 2035 2036 /* 2037 * Fill in the multicast address list and return number of entries. 2038 */ 2039 static int 2040 fxp_mc_addrs(struct fxp_softc *sc) 2041 { 2042 struct fxp_cb_mcs *mcsp = sc->mcsp; 2043 struct ifnet *ifp = &sc->arpcom.ac_if; 2044 struct ifmultiaddr *ifma; 2045 int nmcasts; 2046 2047 nmcasts = 0; 2048 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2049 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2050 if (ifma->ifma_addr->sa_family != AF_LINK) 2051 continue; 2052 if (nmcasts >= MAXMCADDR) { 2053 sc->flags |= FXP_FLAG_ALL_MCAST; 2054 nmcasts = 0; 2055 break; 2056 } 2057 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2058 (void *)(uintptr_t)(volatile void *) 2059 &sc->mcsp->mc_addr[nmcasts][0], 6); 2060 nmcasts++; 2061 } 2062 } 2063 mcsp->mc_cnt = nmcasts * 6; 2064 return (nmcasts); 2065 } 2066 2067 /* 2068 * Program the multicast filter. 2069 * 2070 * We have an artificial restriction that the multicast setup command 2071 * must be the first command in the chain, so we take steps to ensure 2072 * this. By requiring this, it allows us to keep up the performance of 2073 * the pre-initialized command ring (esp. link pointers) by not actually 2074 * inserting the mcsetup command in the ring - i.e. its link pointer 2075 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2076 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2077 * lead into the regular TxCB ring when it completes. 2078 * 2079 * This function must be called at splimp. 2080 */ 2081 static void 2082 fxp_mc_setup(struct fxp_softc *sc) 2083 { 2084 struct fxp_cb_mcs *mcsp = sc->mcsp; 2085 struct ifnet *ifp = &sc->arpcom.ac_if; 2086 int count; 2087 2088 /* 2089 * If there are queued commands, we must wait until they are all 2090 * completed. If we are already waiting, then add a NOP command 2091 * with interrupt option so that we're notified when all commands 2092 * have been completed - fxp_start() ensures that no additional 2093 * TX commands will be added when need_mcsetup is true. 2094 */ 2095 if (sc->tx_queued) { 2096 struct fxp_cb_tx *txp; 2097 2098 /* 2099 * need_mcsetup will be true if we are already waiting for the 2100 * NOP command to be completed (see below). In this case, bail. 2101 */ 2102 if (sc->need_mcsetup) 2103 return; 2104 sc->need_mcsetup = 1; 2105 2106 /* 2107 * Add a NOP command with interrupt so that we are notified 2108 * when all TX commands have been processed. 2109 */ 2110 txp = sc->cbl_last->next; 2111 txp->mb_head = NULL; 2112 txp->cb_status = 0; 2113 txp->cb_command = FXP_CB_COMMAND_NOP | 2114 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2115 /* 2116 * Advance the end of list forward. 2117 */ 2118 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2119 sc->cbl_last = txp; 2120 sc->tx_queued++; 2121 /* 2122 * Issue a resume in case the CU has just suspended. 2123 */ 2124 fxp_scb_wait(sc); 2125 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2126 /* 2127 * Set a 5 second timer just in case we don't hear from the 2128 * card again. 2129 */ 2130 ifp->if_timer = 5; 2131 2132 return; 2133 } 2134 sc->need_mcsetup = 0; 2135 2136 /* 2137 * Initialize multicast setup descriptor. 2138 */ 2139 mcsp->next = sc->cbl_base; 2140 mcsp->mb_head = NULL; 2141 mcsp->cb_status = 0; 2142 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2143 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2144 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2145 (void) fxp_mc_addrs(sc); 2146 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2147 sc->tx_queued = 1; 2148 2149 /* 2150 * Wait until command unit is not active. This should never 2151 * be the case when nothing is queued, but make sure anyway. 2152 */ 2153 count = 100; 2154 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2155 FXP_SCB_CUS_ACTIVE && --count) 2156 DELAY(10); 2157 if (count == 0) { 2158 if_printf(&sc->arpcom.ac_if, "command queue timeout\n"); 2159 return; 2160 } 2161 2162 /* 2163 * Start the multicast setup command. 2164 */ 2165 fxp_scb_wait(sc); 2166 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2167 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2168 2169 ifp->if_timer = 2; 2170 return; 2171 } 2172 2173 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2174 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2175 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2176 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2177 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2178 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2179 2180 #define UCODE(x) x, sizeof(x) 2181 2182 struct ucode { 2183 u_int32_t revision; 2184 u_int32_t *ucode; 2185 int length; 2186 u_short int_delay_offset; 2187 u_short bundle_max_offset; 2188 } ucode_table[] = { 2189 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2190 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2191 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2192 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2193 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2194 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2195 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2196 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2197 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2198 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2199 { 0, NULL, 0, 0, 0 } 2200 }; 2201 2202 static void 2203 fxp_load_ucode(struct fxp_softc *sc) 2204 { 2205 struct ucode *uc; 2206 struct fxp_cb_ucode *cbp; 2207 2208 for (uc = ucode_table; uc->ucode != NULL; uc++) 2209 if (sc->revision == uc->revision) 2210 break; 2211 if (uc->ucode == NULL) 2212 return; 2213 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2214 cbp->cb_status = 0; 2215 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2216 cbp->link_addr = -1; /* (no) next command */ 2217 memcpy(cbp->ucode, uc->ucode, uc->length); 2218 if (uc->int_delay_offset) 2219 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2220 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2221 if (uc->bundle_max_offset) 2222 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2223 sc->tunable_bundle_max; 2224 /* 2225 * Download the ucode to the chip. 2226 */ 2227 fxp_scb_wait(sc); 2228 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2229 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2230 /* ...and wait for it to complete. */ 2231 fxp_dma_wait(&cbp->cb_status, sc); 2232 if_printf(&sc->arpcom.ac_if, 2233 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2234 sc->tunable_int_delay, 2235 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2236 sc->flags |= FXP_FLAG_UCODE; 2237 } 2238 2239 static int 2240 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2241 { 2242 int error, value; 2243 2244 value = *(int *)arg1; 2245 error = sysctl_handle_int(oidp, &value, 0, req); 2246 if (error || !req->newptr) 2247 return (error); 2248 if (value < low || value > high) 2249 return (EINVAL); 2250 *(int *)arg1 = value; 2251 return (0); 2252 } 2253 2254 /* 2255 * Interrupt delay is expressed in microseconds, a multiplier is used 2256 * to convert this to the appropriate clock ticks before using. 2257 */ 2258 static int 2259 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2260 { 2261 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2262 } 2263 2264 static int 2265 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2266 { 2267 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2268 } 2269