xref: /dragonfly/sys/dev/netif/fxp/if_fxp.c (revision 89a89091)
1 /*-
2  * Copyright (c) 1995, David Greenman
3  * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice unmodified, this list of conditions, and the following
11  *    disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $
29  */
30 
31 /*
32  * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
33  */
34 
35 #include "opt_polling.h"
36 
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/mbuf.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/interrupt.h>
43 #include <sys/socket.h>
44 #include <sys/sysctl.h>
45 #include <sys/thread2.h>
46 
47 #include <net/if.h>
48 #include <net/ifq_var.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 
52 #include <net/bpf.h>
53 #include <sys/sockio.h>
54 #include <sys/bus.h>
55 #include <sys/rman.h>
56 
57 #include <net/ethernet.h>
58 #include <net/if_arp.h>
59 
60 #include <vm/vm.h>		/* for vtophys */
61 #include <vm/pmap.h>		/* for vtophys */
62 
63 #include <net/if_types.h>
64 #include <net/vlan/if_vlan_var.h>
65 
66 #include <bus/pci/pcivar.h>
67 #include <bus/pci/pcireg.h>		/* for PCIM_CMD_xxx */
68 
69 #include "../mii_layer/mii.h"
70 #include "../mii_layer/miivar.h"
71 
72 #include "if_fxpreg.h"
73 #include "if_fxpvar.h"
74 #include "rcvbundl.h"
75 
76 #include "miibus_if.h"
77 
78 /*
79  * NOTE!  On the Alpha, we have an alignment constraint.  The
80  * card DMAs the packet immediately following the RFA.  However,
81  * the first thing in the packet is a 14-byte Ethernet header.
82  * This means that the packet is misaligned.  To compensate,
83  * we actually offset the RFA 2 bytes into the cluster.  This
84  * alignes the packet after the Ethernet header at a 32-bit
85  * boundary.  HOWEVER!  This means that the RFA is misaligned!
86  */
87 #define	RFA_ALIGNMENT_FUDGE	2
88 
89 /*
90  * Set initial transmit threshold at 64 (512 bytes). This is
91  * increased by 64 (512 bytes) at a time, to maximum of 192
92  * (1536 bytes), if an underrun occurs.
93  */
94 static int tx_threshold = 64;
95 
96 /*
97  * The configuration byte map has several undefined fields which
98  * must be one or must be zero.  Set up a template for these bits
99  * only, (assuming a 82557 chip) leaving the actual configuration
100  * to fxp_init.
101  *
102  * See struct fxp_cb_config for the bit definitions.
103  */
104 static u_char fxp_cb_config_template[] = {
105 	0x0, 0x0,		/* cb_status */
106 	0x0, 0x0,		/* cb_command */
107 	0x0, 0x0, 0x0, 0x0,	/* link_addr */
108 	0x0,	/*  0 */
109 	0x0,	/*  1 */
110 	0x0,	/*  2 */
111 	0x0,	/*  3 */
112 	0x0,	/*  4 */
113 	0x0,	/*  5 */
114 	0x32,	/*  6 */
115 	0x0,	/*  7 */
116 	0x0,	/*  8 */
117 	0x0,	/*  9 */
118 	0x6,	/* 10 */
119 	0x0,	/* 11 */
120 	0x0,	/* 12 */
121 	0x0,	/* 13 */
122 	0xf2,	/* 14 */
123 	0x48,	/* 15 */
124 	0x0,	/* 16 */
125 	0x40,	/* 17 */
126 	0xf0,	/* 18 */
127 	0x0,	/* 19 */
128 	0x3f,	/* 20 */
129 	0x5	/* 21 */
130 };
131 
132 struct fxp_ident {
133 	u_int16_t	devid;
134 	int16_t		revid;		/* -1 matches anything */
135 	char 		*name;
136 };
137 
138 /*
139  * Claim various Intel PCI device identifiers for this driver.  The
140  * sub-vendor and sub-device field are extensively used to identify
141  * particular variants, but we don't currently differentiate between
142  * them.
143  */
144 static struct fxp_ident fxp_ident_table[] = {
145      { 0x1029,	-1,	"Intel 82559 PCI/CardBus Pro/100" },
146      { 0x1030,	-1,	"Intel 82559 Pro/100 Ethernet" },
147      { 0x1031,	-1,	"Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
148      { 0x1032,	-1,	"Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
149      { 0x1033,	-1,	"Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
150      { 0x1034,	-1,	"Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
151      { 0x1035,	-1,	"Intel 82801CAM (ICH3) Pro/100 Ethernet" },
152      { 0x1036,	-1,	"Intel 82801CAM (ICH3) Pro/100 Ethernet" },
153      { 0x1037,	-1,	"Intel 82801CAM (ICH3) Pro/100 Ethernet" },
154      { 0x1038,	-1,	"Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
155      { 0x1039,	-1,	"Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
156      { 0x103A,	-1,	"Intel 82801DB (ICH4) Pro/100 Ethernet" },
157      { 0x103B,	-1,	"Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
158      { 0x103C,	-1,	"Intel 82801DB (ICH4) Pro/100 Ethernet" },
159      { 0x103D,	-1,	"Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
160      { 0x103E,	-1,	"Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
161      { 0x1050,	-1,	"Intel 82801BA (D865) Pro/100 VE Ethernet" },
162      { 0x1051,	-1,	"Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
163      { 0x1059,	-1,	"Intel 82551QM Pro/100 M Mobile Connection" },
164      { 0x1064,	-1,	"Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" },
165      { 0x1065,	-1,	"Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
166      { 0x1068,	-1,	"Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
167      { 0x1069,	-1,	"Intel 82562EM/EX/GX Pro/100 Ethernet" },
168      { 0x1091,	-1,	"Intel 82562GX Pro/100 Ethernet" },
169      { 0x1092,	-1,	"Intel Pro/100 VE Network Connection" },
170      { 0x1093,	-1,	"Intel Pro/100 VM Network Connection" },
171      { 0x1094,	-1,	"Intel Pro/100 946GZ (ICH7) Network Connection" },
172      { 0x1209,	-1,	"Intel 82559ER Embedded 10/100 Ethernet" },
173      { 0x1229,	0x01,	"Intel 82557 Pro/100 Ethernet" },
174      { 0x1229,	0x02,	"Intel 82557 Pro/100 Ethernet" },
175      { 0x1229,	0x03,	"Intel 82557 Pro/100 Ethernet" },
176      { 0x1229,	0x04,	"Intel 82558 Pro/100 Ethernet" },
177      { 0x1229,	0x05,	"Intel 82558 Pro/100 Ethernet" },
178      { 0x1229,	0x06,	"Intel 82559 Pro/100 Ethernet" },
179      { 0x1229,	0x07,	"Intel 82559 Pro/100 Ethernet" },
180      { 0x1229,	0x08,	"Intel 82559 Pro/100 Ethernet" },
181      { 0x1229,	0x09,	"Intel 82559ER Pro/100 Ethernet" },
182      { 0x1229,	0x0c,	"Intel 82550 Pro/100 Ethernet" },
183      { 0x1229,	0x0d,	"Intel 82550 Pro/100 Ethernet" },
184      { 0x1229,	0x0e,	"Intel 82550 Pro/100 Ethernet" },
185      { 0x1229,	0x0f,	"Intel 82551 Pro/100 Ethernet" },
186      { 0x1229,	0x10,	"Intel 82551 Pro/100 Ethernet" },
187      { 0x1229,	-1,	"Intel 82557/8/9 Pro/100 Ethernet" },
188      { 0x2449,	-1,	"Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
189      { 0x27dc,	-1,	"Intel 82801GB (ICH7) 10/100 Ethernet" },
190      { 0,	-1,	NULL },
191 };
192 
193 static int		fxp_probe(device_t dev);
194 static int		fxp_attach(device_t dev);
195 static int		fxp_detach(device_t dev);
196 static int		fxp_shutdown(device_t dev);
197 static int		fxp_suspend(device_t dev);
198 static int		fxp_resume(device_t dev);
199 
200 static void		fxp_intr(void *xsc);
201 static void		fxp_intr_body(struct fxp_softc *sc,
202 				u_int8_t statack, int count);
203 
204 static void 		fxp_init(void *xsc);
205 static void 		fxp_tick(void *xsc);
206 static void		fxp_powerstate_d0(device_t dev);
207 static void 		fxp_start(struct ifnet *ifp);
208 static void		fxp_stop(struct fxp_softc *sc);
209 static void 		fxp_release(device_t dev);
210 static int		fxp_ioctl(struct ifnet *ifp, u_long command,
211 			    caddr_t data, struct ucred *);
212 static void 		fxp_watchdog(struct ifnet *ifp);
213 static int		fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
214 static int		fxp_mc_addrs(struct fxp_softc *sc);
215 static void		fxp_mc_setup(struct fxp_softc *sc);
216 static u_int16_t	fxp_eeprom_getword(struct fxp_softc *sc, int offset,
217 			    int autosize);
218 static void 		fxp_eeprom_putword(struct fxp_softc *sc, int offset,
219 			    u_int16_t data);
220 static void		fxp_autosize_eeprom(struct fxp_softc *sc);
221 static void		fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
222 			    int offset, int words);
223 static void		fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
224 			    int offset, int words);
225 static int		fxp_ifmedia_upd(struct ifnet *ifp);
226 static void		fxp_ifmedia_sts(struct ifnet *ifp,
227 			    struct ifmediareq *ifmr);
228 static int		fxp_serial_ifmedia_upd(struct ifnet *ifp);
229 static void		fxp_serial_ifmedia_sts(struct ifnet *ifp,
230 			    struct ifmediareq *ifmr);
231 static int		fxp_miibus_readreg(device_t dev, int phy, int reg);
232 static void		fxp_miibus_writereg(device_t dev, int phy, int reg,
233 			    int value);
234 static void		fxp_load_ucode(struct fxp_softc *sc);
235 static int		sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
236 static int		sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
237 #ifdef DEVICE_POLLING
238 static poll_handler_t fxp_poll;
239 #endif
240 
241 static void		fxp_lwcopy(volatile u_int32_t *src,
242 			    volatile u_int32_t *dst);
243 static void 		fxp_scb_wait(struct fxp_softc *sc);
244 static void		fxp_scb_cmd(struct fxp_softc *sc, int cmd);
245 static void		fxp_dma_wait(volatile u_int16_t *status,
246 			    struct fxp_softc *sc);
247 
248 static device_method_t fxp_methods[] = {
249 	/* Device interface */
250 	DEVMETHOD(device_probe,		fxp_probe),
251 	DEVMETHOD(device_attach,	fxp_attach),
252 	DEVMETHOD(device_detach,	fxp_detach),
253 	DEVMETHOD(device_shutdown,	fxp_shutdown),
254 	DEVMETHOD(device_suspend,	fxp_suspend),
255 	DEVMETHOD(device_resume,	fxp_resume),
256 
257 	/* MII interface */
258 	DEVMETHOD(miibus_readreg,	fxp_miibus_readreg),
259 	DEVMETHOD(miibus_writereg,	fxp_miibus_writereg),
260 
261 	{ 0, 0 }
262 };
263 
264 static driver_t fxp_driver = {
265 	"fxp",
266 	fxp_methods,
267 	sizeof(struct fxp_softc),
268 };
269 
270 static devclass_t fxp_devclass;
271 
272 DECLARE_DUMMY_MODULE(if_fxp);
273 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1);
274 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, NULL, NULL);
275 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, NULL, NULL);
276 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL);
277 
278 static int fxp_rnr;
279 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
280 
281 /*
282  * Copy a 16-bit aligned 32-bit quantity.
283  */
284 static void
285 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
286 {
287 #ifdef __i386__
288 	*dst = *src;
289 #else
290 	volatile u_int16_t *a = (volatile u_int16_t *)src;
291 	volatile u_int16_t *b = (volatile u_int16_t *)dst;
292 
293 	b[0] = a[0];
294 	b[1] = a[1];
295 #endif
296 }
297 
298 /*
299  * Wait for the previous command to be accepted (but not necessarily
300  * completed).
301  */
302 static void
303 fxp_scb_wait(struct fxp_softc *sc)
304 {
305 	int i = 10000;
306 
307 	while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
308 		DELAY(2);
309 	if (i == 0) {
310 		if_printf(&sc->arpcom.ac_if,
311 		    "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
312 		    CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
313 		    CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
314 		    CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
315 		    CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
316 	}
317 }
318 
319 static void
320 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
321 {
322 
323 	if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
324 		CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
325 		fxp_scb_wait(sc);
326 	}
327 	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
328 }
329 
330 static void
331 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
332 {
333 	int i = 10000;
334 
335 	while (!(*status & FXP_CB_STATUS_C) && --i)
336 		DELAY(2);
337 	if (i == 0)
338 		if_printf(&sc->arpcom.ac_if, "DMA timeout\n");
339 }
340 
341 /*
342  * Return identification string if this is device is ours.
343  */
344 static int
345 fxp_probe(device_t dev)
346 {
347 	u_int16_t devid;
348 	u_int8_t revid;
349 	struct fxp_ident *ident;
350 
351 	if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
352 		devid = pci_get_device(dev);
353 		revid = pci_get_revid(dev);
354 		for (ident = fxp_ident_table; ident->name != NULL; ident++) {
355 			if (ident->devid == devid &&
356 			    (ident->revid == revid || ident->revid == -1)) {
357 				device_set_desc(dev, ident->name);
358 				return (0);
359 			}
360 		}
361 	}
362 	return (ENXIO);
363 }
364 
365 static void
366 fxp_powerstate_d0(device_t dev)
367 {
368 	u_int32_t iobase, membase, irq;
369 
370 	if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
371 		/* Save important PCI config data. */
372 		iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
373 		membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
374 		irq = pci_read_config(dev, PCIR_INTLINE, 4);
375 
376 		/* Reset the power state. */
377 		device_printf(dev, "chip is in D%d power mode "
378 		    "-- setting to D0\n", pci_get_powerstate(dev));
379 
380 		pci_set_powerstate(dev, PCI_POWERSTATE_D0);
381 
382 		/* Restore PCI config data. */
383 		pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
384 		pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
385 		pci_write_config(dev, PCIR_INTLINE, irq, 4);
386 	}
387 }
388 
389 static int
390 fxp_attach(device_t dev)
391 {
392 	int error = 0;
393 	struct fxp_softc *sc = device_get_softc(dev);
394 	struct ifnet *ifp;
395 	u_int32_t val;
396 	u_int16_t data;
397 	int i, rid, m1, m2, prefer_iomap;
398 
399 	callout_init(&sc->fxp_stat_timer);
400 	sysctl_ctx_init(&sc->sysctl_ctx);
401 
402 	/*
403 	 * Enable bus mastering. Enable memory space too, in case
404 	 * BIOS/Prom forgot about it.
405 	 */
406 	pci_enable_busmaster(dev);
407 	pci_enable_io(dev, SYS_RES_MEMORY);
408 	val = pci_read_config(dev, PCIR_COMMAND, 2);
409 
410 	fxp_powerstate_d0(dev);
411 
412 	/*
413 	 * Figure out which we should try first - memory mapping or i/o mapping?
414 	 * We default to memory mapping. Then we accept an override from the
415 	 * command line. Then we check to see which one is enabled.
416 	 */
417 	m1 = PCIM_CMD_MEMEN;
418 	m2 = PCIM_CMD_PORTEN;
419 	prefer_iomap = 0;
420 	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
421 	    "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
422 		m1 = PCIM_CMD_PORTEN;
423 		m2 = PCIM_CMD_MEMEN;
424 	}
425 
426 	if (val & m1) {
427 		sc->rtp =
428 		    (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
429 		sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
430 		sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
431 		    RF_ACTIVE);
432 	}
433 	if (sc->mem == NULL && (val & m2)) {
434 		sc->rtp =
435 		    (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
436 		sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
437 		sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
438             	    RF_ACTIVE);
439 	}
440 
441 	if (!sc->mem) {
442 		device_printf(dev, "could not map device registers\n");
443 		error = ENXIO;
444 		goto fail;
445         }
446 	if (bootverbose) {
447 		device_printf(dev, "using %s space register mapping\n",
448 		   sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
449 	}
450 
451 	sc->sc_st = rman_get_bustag(sc->mem);
452 	sc->sc_sh = rman_get_bushandle(sc->mem);
453 
454 	/*
455 	 * Allocate our interrupt.
456 	 */
457 	rid = 0;
458 	sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
459 	    RF_SHAREABLE | RF_ACTIVE);
460 	if (sc->irq == NULL) {
461 		device_printf(dev, "could not map interrupt\n");
462 		error = ENXIO;
463 		goto fail;
464 	}
465 
466 	/*
467 	 * Reset to a stable state.
468 	 */
469 	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
470 	DELAY(10);
471 
472 	sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
473 	    M_DEVBUF, M_WAITOK | M_ZERO);
474 
475 	sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF,
476 	    M_WAITOK | M_ZERO);
477 
478 	sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK);
479 
480 	/*
481 	 * Pre-allocate our receive buffers.
482 	 */
483 	for (i = 0; i < FXP_NRFABUFS; i++) {
484 		if (fxp_add_rfabuf(sc, NULL) != 0) {
485 			goto failmem;
486 		}
487 	}
488 
489 	/*
490 	 * Find out how large of an SEEPROM we have.
491 	 */
492 	fxp_autosize_eeprom(sc);
493 
494 	/*
495 	 * Determine whether we must use the 503 serial interface.
496 	 */
497 	fxp_read_eeprom(sc, &data, 6, 1);
498 	if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
499 	    (data & FXP_PHY_SERIAL_ONLY))
500 		sc->flags |= FXP_FLAG_SERIAL_MEDIA;
501 
502 	/*
503 	 * Create the sysctl tree
504 	 */
505 	sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
506 	    SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
507 	    device_get_nameunit(dev), CTLFLAG_RD, 0, "");
508 	if (sc->sysctl_tree == NULL)
509 		goto fail;
510 	SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
511 	    OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
512 	    &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
513 	    "FXP driver receive interrupt microcode bundling delay");
514 	SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
515 	    OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
516 	    &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
517 	    "FXP driver receive interrupt microcode bundle size limit");
518 
519 	/*
520 	 * Pull in device tunables.
521 	 */
522 	sc->tunable_int_delay = TUNABLE_INT_DELAY;
523 	sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
524 	resource_int_value(device_get_name(dev), device_get_unit(dev),
525 	    "int_delay", &sc->tunable_int_delay);
526 	resource_int_value(device_get_name(dev), device_get_unit(dev),
527 	    "bundle_max", &sc->tunable_bundle_max);
528 
529 	/*
530 	 * Find out the chip revision; lump all 82557 revs together.
531 	 */
532 	fxp_read_eeprom(sc, &data, 5, 1);
533 	if ((data >> 8) == 1)
534 		sc->revision = FXP_REV_82557;
535 	else
536 		sc->revision = pci_get_revid(dev);
537 
538 	/*
539 	 * Enable workarounds for certain chip revision deficiencies.
540 	 *
541 	 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
542 	 * some systems based a normal 82559 design, have a defect where
543 	 * the chip can cause a PCI protocol violation if it receives
544 	 * a CU_RESUME command when it is entering the IDLE state.  The
545 	 * workaround is to disable Dynamic Standby Mode, so the chip never
546 	 * deasserts CLKRUN#, and always remains in an active state.
547 	 *
548 	 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
549 	 */
550 	i = pci_get_device(dev);
551 	if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
552 	    sc->revision >= FXP_REV_82559_A0) {
553 		fxp_read_eeprom(sc, &data, 10, 1);
554 		if (data & 0x02) {			/* STB enable */
555 			u_int16_t cksum;
556 			int i;
557 
558 			device_printf(dev,
559 			    "Disabling dynamic standby mode in EEPROM\n");
560 			data &= ~0x02;
561 			fxp_write_eeprom(sc, &data, 10, 1);
562 			device_printf(dev, "New EEPROM ID: 0x%x\n", data);
563 			cksum = 0;
564 			for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
565 				fxp_read_eeprom(sc, &data, i, 1);
566 				cksum += data;
567 			}
568 			i = (1 << sc->eeprom_size) - 1;
569 			cksum = 0xBABA - cksum;
570 			fxp_read_eeprom(sc, &data, i, 1);
571 			fxp_write_eeprom(sc, &cksum, i, 1);
572 			device_printf(dev,
573 			    "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
574 			    i, data, cksum);
575 #if 1
576 			/*
577 			 * If the user elects to continue, try the software
578 			 * workaround, as it is better than nothing.
579 			 */
580 			sc->flags |= FXP_FLAG_CU_RESUME_BUG;
581 #endif
582 		}
583 	}
584 
585 	/*
586 	 * If we are not a 82557 chip, we can enable extended features.
587 	 */
588 	if (sc->revision != FXP_REV_82557) {
589 		/*
590 		 * If MWI is enabled in the PCI configuration, and there
591 		 * is a valid cacheline size (8 or 16 dwords), then tell
592 		 * the board to turn on MWI.
593 		 */
594 		if (val & PCIM_CMD_MWRICEN &&
595 		    pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
596 			sc->flags |= FXP_FLAG_MWI_ENABLE;
597 
598 		/* turn on the extended TxCB feature */
599 		sc->flags |= FXP_FLAG_EXT_TXCB;
600 
601 		/* enable reception of long frames for VLAN */
602 		sc->flags |= FXP_FLAG_LONG_PKT_EN;
603 	}
604 
605 	/*
606 	 * Read MAC address.
607 	 */
608 	fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
609 	if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
610 		device_printf(dev, "10Mbps\n");
611 	if (bootverbose) {
612 		device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
613 		    pci_get_vendor(dev), pci_get_device(dev),
614 		    pci_get_subvendor(dev), pci_get_subdevice(dev),
615 		    pci_get_revid(dev));
616 		fxp_read_eeprom(sc, &data, 10, 1);
617 		device_printf(dev, "Dynamic Standby mode is %s\n",
618 		    data & 0x02 ? "enabled" : "disabled");
619 	}
620 
621 	/*
622 	 * If this is only a 10Mbps device, then there is no MII, and
623 	 * the PHY will use a serial interface instead.
624 	 *
625 	 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
626 	 * doesn't have a programming interface of any sort.  The
627 	 * media is sensed automatically based on how the link partner
628 	 * is configured.  This is, in essence, manual configuration.
629 	 */
630 	if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
631 		ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
632 		    fxp_serial_ifmedia_sts);
633 		ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
634 		ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
635 	} else {
636 		if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
637 		    fxp_ifmedia_sts)) {
638 	                device_printf(dev, "MII without any PHY!\n");
639 			error = ENXIO;
640 			goto fail;
641 		}
642 	}
643 
644 	ifp = &sc->arpcom.ac_if;
645 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
646 	ifp->if_baudrate = 100000000;
647 	ifp->if_init = fxp_init;
648 	ifp->if_softc = sc;
649 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
650 	ifp->if_ioctl = fxp_ioctl;
651 	ifp->if_start = fxp_start;
652 #ifdef DEVICE_POLLING
653 	ifp->if_poll = fxp_poll;
654 #endif
655 	ifp->if_watchdog = fxp_watchdog;
656 
657 	/*
658 	 * Attach the interface.
659 	 */
660 	ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
661 
662 	/*
663 	 * Tell the upper layer(s) we support long frames.
664 	 */
665 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
666 
667 	/*
668 	 * Let the system queue as many packets as we have available
669 	 * TX descriptors.
670 	 */
671 	ifq_set_maxlen(&ifp->if_snd, FXP_USABLE_TXCB);
672 	ifq_set_ready(&ifp->if_snd);
673 
674 	error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
675 			       fxp_intr, sc, &sc->ih,
676 			       ifp->if_serializer);
677 	if (error) {
678 		ether_ifdetach(ifp);
679 		if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
680 			ifmedia_removeall(&sc->sc_media);
681 		device_printf(dev, "could not setup irq\n");
682 		goto fail;
683 	}
684 
685 	ifp->if_cpuid = rman_get_cpuid(sc->irq);
686 	KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
687 
688 	return (0);
689 
690 failmem:
691 	device_printf(dev, "Failed to malloc memory\n");
692 	error = ENOMEM;
693 fail:
694 	fxp_release(dev);
695 	return (error);
696 }
697 
698 /*
699  * release all resources
700  */
701 static void
702 fxp_release(device_t dev)
703 {
704 	struct fxp_softc *sc = device_get_softc(dev);
705 
706 	if (sc->miibus)
707 		device_delete_child(dev, sc->miibus);
708 	bus_generic_detach(dev);
709 
710 	if (sc->cbl_base)
711 		kfree(sc->cbl_base, M_DEVBUF);
712 	if (sc->fxp_stats)
713 		kfree(sc->fxp_stats, M_DEVBUF);
714 	if (sc->mcsp)
715 		kfree(sc->mcsp, M_DEVBUF);
716 	if (sc->rfa_headm)
717 		m_freem(sc->rfa_headm);
718 
719 	if (sc->irq)
720 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
721 	if (sc->mem)
722 		bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem);
723 
724         sysctl_ctx_free(&sc->sysctl_ctx);
725 }
726 
727 /*
728  * Detach interface.
729  */
730 static int
731 fxp_detach(device_t dev)
732 {
733 	struct fxp_softc *sc = device_get_softc(dev);
734 
735 	lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
736 
737 	/*
738 	 * Stop DMA and drop transmit queue.
739 	 */
740 	fxp_stop(sc);
741 
742 	/*
743 	 * Disable interrupts.
744 	 *
745 	 * NOTE: This should be done after fxp_stop(), because software
746 	 * resetting in fxp_stop() may leave interrupts turned on.
747 	 */
748 	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
749 
750 	/*
751 	 * Free all media structures.
752 	 */
753 	if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
754 		ifmedia_removeall(&sc->sc_media);
755 
756 	if (sc->ih)
757 		bus_teardown_intr(dev, sc->irq, sc->ih);
758 
759 	lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
760 
761 	/*
762 	 * Close down routes etc.
763 	 */
764 	ether_ifdetach(&sc->arpcom.ac_if);
765 
766 	/* Release our allocated resources. */
767 	fxp_release(dev);
768 
769 	return (0);
770 }
771 
772 /*
773  * Device shutdown routine. Called at system shutdown after sync. The
774  * main purpose of this routine is to shut off receiver DMA so that
775  * kernel memory doesn't get clobbered during warmboot.
776  */
777 static int
778 fxp_shutdown(device_t dev)
779 {
780 	struct fxp_softc *sc = device_get_softc(dev);
781 	struct ifnet *ifp = &sc->arpcom.ac_if;
782 
783 	lwkt_serialize_enter(ifp->if_serializer);
784 	/*
785 	 * Make sure that DMA is disabled prior to reboot. Not doing
786 	 * do could allow DMA to corrupt kernel memory during the
787 	 * reboot before the driver initializes.
788 	 */
789 	fxp_stop(sc);
790 	lwkt_serialize_exit(ifp->if_serializer);
791 	return (0);
792 }
793 
794 /*
795  * Device suspend routine.  Stop the interface and save some PCI
796  * settings in case the BIOS doesn't restore them properly on
797  * resume.
798  */
799 static int
800 fxp_suspend(device_t dev)
801 {
802 	struct fxp_softc *sc = device_get_softc(dev);
803 	int i;
804 
805 	lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
806 
807 	fxp_stop(sc);
808 
809 	for (i = 0; i < 5; i++)
810 		sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
811 	sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
812 	sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
813 	sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
814 	sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
815 
816 	sc->suspended = 1;
817 
818 	lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
819 	return (0);
820 }
821 
822 /*
823  * Device resume routine.  Restore some PCI settings in case the BIOS
824  * doesn't, re-enable busmastering, and restart the interface if
825  * appropriate.
826  */
827 static int
828 fxp_resume(device_t dev)
829 {
830 	struct fxp_softc *sc = device_get_softc(dev);
831 	struct ifnet *ifp = &sc->arpcom.ac_if;
832 	int i;
833 
834 	lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
835 
836 	fxp_powerstate_d0(dev);
837 
838 	/* better way to do this? */
839 	for (i = 0; i < 5; i++)
840 		pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
841 	pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
842 	pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
843 	pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
844 	pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
845 
846 	/* reenable busmastering and memory space */
847 	pci_enable_busmaster(dev);
848 	pci_enable_io(dev, SYS_RES_MEMORY);
849 
850 	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
851 	DELAY(10);
852 
853 	/* reinitialize interface if necessary */
854 	if (ifp->if_flags & IFF_UP)
855 		fxp_init(sc);
856 
857 	sc->suspended = 0;
858 
859 	lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
860 	return (0);
861 }
862 
863 static void
864 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
865 {
866 	u_int16_t reg;
867 	int x;
868 
869 	/*
870 	 * Shift in data.
871 	 */
872 	for (x = 1 << (length - 1); x; x >>= 1) {
873 		if (data & x)
874 			reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
875 		else
876 			reg = FXP_EEPROM_EECS;
877 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
878 		DELAY(1);
879 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
880 		DELAY(1);
881 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
882 		DELAY(1);
883 	}
884 }
885 
886 /*
887  * Read from the serial EEPROM. Basically, you manually shift in
888  * the read opcode (one bit at a time) and then shift in the address,
889  * and then you shift out the data (all of this one bit at a time).
890  * The word size is 16 bits, so you have to provide the address for
891  * every 16 bits of data.
892  */
893 static u_int16_t
894 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
895 {
896 	u_int16_t reg, data;
897 	int x;
898 
899 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
900 	/*
901 	 * Shift in read opcode.
902 	 */
903 	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
904 	/*
905 	 * Shift in address.
906 	 */
907 	data = 0;
908 	for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
909 		if (offset & x)
910 			reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
911 		else
912 			reg = FXP_EEPROM_EECS;
913 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
914 		DELAY(1);
915 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
916 		DELAY(1);
917 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
918 		DELAY(1);
919 		reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
920 		data++;
921 		if (autosize && reg == 0) {
922 			sc->eeprom_size = data;
923 			break;
924 		}
925 	}
926 	/*
927 	 * Shift out data.
928 	 */
929 	data = 0;
930 	reg = FXP_EEPROM_EECS;
931 	for (x = 1 << 15; x; x >>= 1) {
932 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
933 		DELAY(1);
934 		if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
935 			data |= x;
936 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
937 		DELAY(1);
938 	}
939 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
940 	DELAY(1);
941 
942 	return (data);
943 }
944 
945 static void
946 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
947 {
948 	int i;
949 
950 	/*
951 	 * Erase/write enable.
952 	 */
953 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
954 	fxp_eeprom_shiftin(sc, 0x4, 3);
955 	fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
956 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
957 	DELAY(1);
958 	/*
959 	 * Shift in write opcode, address, data.
960 	 */
961 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
962 	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
963 	fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
964 	fxp_eeprom_shiftin(sc, data, 16);
965 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
966 	DELAY(1);
967 	/*
968 	 * Wait for EEPROM to finish up.
969 	 */
970 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
971 	DELAY(1);
972 	for (i = 0; i < 1000; i++) {
973 		if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
974 			break;
975 		DELAY(50);
976 	}
977 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
978 	DELAY(1);
979 	/*
980 	 * Erase/write disable.
981 	 */
982 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
983 	fxp_eeprom_shiftin(sc, 0x4, 3);
984 	fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
985 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
986 	DELAY(1);
987 }
988 
989 /*
990  * From NetBSD:
991  *
992  * Figure out EEPROM size.
993  *
994  * 559's can have either 64-word or 256-word EEPROMs, the 558
995  * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
996  * talks about the existance of 16 to 256 word EEPROMs.
997  *
998  * The only known sizes are 64 and 256, where the 256 version is used
999  * by CardBus cards to store CIS information.
1000  *
1001  * The address is shifted in msb-to-lsb, and after the last
1002  * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1003  * after which follows the actual data. We try to detect this zero, by
1004  * probing the data-out bit in the EEPROM control register just after
1005  * having shifted in a bit. If the bit is zero, we assume we've
1006  * shifted enough address bits. The data-out should be tri-state,
1007  * before this, which should translate to a logical one.
1008  */
1009 static void
1010 fxp_autosize_eeprom(struct fxp_softc *sc)
1011 {
1012 
1013 	/* guess maximum size of 256 words */
1014 	sc->eeprom_size = 8;
1015 
1016 	/* autosize */
1017 	fxp_eeprom_getword(sc, 0, 1);
1018 }
1019 
1020 static void
1021 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1022 {
1023 	int i;
1024 
1025 	for (i = 0; i < words; i++)
1026 		data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1027 }
1028 
1029 static void
1030 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1031 {
1032 	int i;
1033 
1034 	for (i = 0; i < words; i++)
1035 		fxp_eeprom_putword(sc, offset + i, data[i]);
1036 }
1037 
1038 /*
1039  * Start packet transmission on the interface.
1040  */
1041 static void
1042 fxp_start(struct ifnet *ifp)
1043 {
1044 	struct fxp_softc *sc = ifp->if_softc;
1045 	struct fxp_cb_tx *txp;
1046 
1047 	ASSERT_SERIALIZED(ifp->if_serializer);
1048 
1049 	/*
1050 	 * See if we need to suspend xmit until the multicast filter
1051 	 * has been reprogrammed (which can only be done at the head
1052 	 * of the command chain).
1053 	 */
1054 	if (sc->need_mcsetup) {
1055 		ifq_purge(&ifp->if_snd);
1056 		return;
1057 	}
1058 
1059 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1060 		return;
1061 
1062 	txp = NULL;
1063 
1064 	/*
1065 	 * We're finished if there is nothing more to add to the list or if
1066 	 * we're all filled up with buffers to transmit.
1067 	 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1068 	 *       a NOP command when needed.
1069 	 */
1070 	while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_USABLE_TXCB) {
1071 		struct mbuf *m, *mb_head;
1072 		int segment, ntries = 0;
1073 
1074 		/*
1075 		 * Grab a packet to transmit.
1076 		 */
1077 		mb_head = ifq_dequeue(&ifp->if_snd, NULL);
1078 		if (mb_head == NULL)
1079 			break;
1080 tbdinit:
1081 		/*
1082 		 * Make sure that the packet fits into one TX desc
1083 		 */
1084 		segment = 0;
1085 		for (m = mb_head; m != NULL; m = m->m_next) {
1086 			if (m->m_len != 0) {
1087 				++segment;
1088 				if (segment >= FXP_NTXSEG)
1089 					break;
1090 			}
1091 		}
1092 		if (segment >= FXP_NTXSEG) {
1093 			struct mbuf *mn;
1094 
1095 			if (ntries) {
1096 				/*
1097 				 * Packet is excessively fragmented,
1098 				 * and will never fit into one TX
1099 				 * desc.  Give it up.
1100 				 */
1101 				m_freem(mb_head);
1102 				ifp->if_oerrors++;
1103 				continue;
1104 			}
1105 
1106 			mn = m_dup(mb_head, MB_DONTWAIT);
1107 			if (mn == NULL) {
1108 				m_freem(mb_head);
1109 				ifp->if_oerrors++;
1110 				continue;
1111 			}
1112 
1113 			m_freem(mb_head);
1114 			mb_head = mn;
1115 			ntries = 1;
1116 			goto tbdinit;
1117 		}
1118 
1119 		/*
1120 		 * Get pointer to next available tx desc.
1121 		 */
1122 		txp = sc->cbl_last->next;
1123 
1124 		/*
1125 		 * Go through each of the mbufs in the chain and initialize
1126 		 * the transmit buffer descriptors with the physical address
1127 		 * and size of the mbuf.
1128 		 */
1129 		for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1130 			if (m->m_len != 0) {
1131 				KKASSERT(segment < FXP_NTXSEG);
1132 
1133 				txp->tbd[segment].tb_addr =
1134 				    vtophys(mtod(m, vm_offset_t));
1135 				txp->tbd[segment].tb_size = m->m_len;
1136 				segment++;
1137 			}
1138 		}
1139 		KKASSERT(m == NULL);
1140 
1141 		txp->tbd_number = segment;
1142 		txp->mb_head = mb_head;
1143 		txp->cb_status = 0;
1144 		if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1145 			txp->cb_command =
1146 			    FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1147 			    FXP_CB_COMMAND_S;
1148 		} else {
1149 			txp->cb_command =
1150 			    FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1151 			    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1152 		}
1153 		txp->tx_threshold = tx_threshold;
1154 
1155 		/*
1156 		 * Advance the end of list forward.
1157 		 */
1158 		sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1159 		sc->cbl_last = txp;
1160 
1161 		/*
1162 		 * Advance the beginning of the list forward if there are
1163 		 * no other packets queued (when nothing is queued, cbl_first
1164 		 * sits on the last TxCB that was sent out).
1165 		 */
1166 		if (sc->tx_queued == 0)
1167 			sc->cbl_first = txp;
1168 
1169 		sc->tx_queued++;
1170 		/*
1171 		 * Set a 5 second timer just in case we don't hear
1172 		 * from the card again.
1173 		 */
1174 		ifp->if_timer = 5;
1175 
1176 		BPF_MTAP(ifp, mb_head);
1177 	}
1178 
1179 	if (sc->tx_queued >= FXP_USABLE_TXCB)
1180 		ifp->if_flags |= IFF_OACTIVE;
1181 
1182 	/*
1183 	 * We're finished. If we added to the list, issue a RESUME to get DMA
1184 	 * going again if suspended.
1185 	 */
1186 	if (txp != NULL) {
1187 		fxp_scb_wait(sc);
1188 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1189 	}
1190 }
1191 
1192 #ifdef DEVICE_POLLING
1193 
1194 static void
1195 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1196 {
1197 	struct fxp_softc *sc = ifp->if_softc;
1198 	u_int8_t statack;
1199 
1200 	ASSERT_SERIALIZED(ifp->if_serializer);
1201 
1202 	switch(cmd) {
1203 	case POLL_REGISTER:
1204 		/* disable interrupts */
1205 		CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1206 		break;
1207 	case POLL_DEREGISTER:
1208 		/* enable interrupts */
1209 		CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1210 		break;
1211 	default:
1212 		statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1213 			  FXP_SCB_STATACK_FR;
1214 		if (cmd == POLL_AND_CHECK_STATUS) {
1215 			u_int8_t tmp;
1216 
1217 			tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1218 			if (tmp == 0xff || tmp == 0)
1219 				return; /* nothing to do */
1220 			tmp &= ~statack;
1221 			/* ack what we can */
1222 			if (tmp != 0)
1223 				CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1224 			statack |= tmp;
1225 		}
1226 		fxp_intr_body(sc, statack, count);
1227 		break;
1228 	}
1229 }
1230 
1231 #endif /* DEVICE_POLLING */
1232 
1233 /*
1234  * Process interface interrupts.
1235  */
1236 static void
1237 fxp_intr(void *xsc)
1238 {
1239 	struct fxp_softc *sc = xsc;
1240 	u_int8_t statack;
1241 
1242 	ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
1243 
1244 	if (sc->suspended) {
1245 		return;
1246 	}
1247 
1248 	while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1249 		/*
1250 		 * It should not be possible to have all bits set; the
1251 		 * FXP_SCB_INTR_SWI bit always returns 0 on a read.  If
1252 		 * all bits are set, this may indicate that the card has
1253 		 * been physically ejected, so ignore it.
1254 		 */
1255 		if (statack == 0xff)
1256 			return;
1257 
1258 		/*
1259 		 * First ACK all the interrupts in this pass.
1260 		 */
1261 		CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1262 		fxp_intr_body(sc, statack, -1);
1263 	}
1264 }
1265 
1266 static void
1267 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1268 {
1269 	struct ifnet *ifp = &sc->arpcom.ac_if;
1270 	struct mbuf *m;
1271 	struct fxp_rfa *rfa;
1272 	int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1273 
1274 	if (rnr)
1275 		fxp_rnr++;
1276 #ifdef DEVICE_POLLING
1277 	/* Pick up a deferred RNR condition if `count' ran out last time. */
1278 	if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1279 		sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1280 		rnr = 1;
1281 	}
1282 #endif
1283 
1284 	/*
1285 	 * Free any finished transmit mbuf chains.
1286 	 *
1287 	 * Handle the CNA event likt a CXTNO event. It used to
1288 	 * be that this event (control unit not ready) was not
1289 	 * encountered, but it is now with the SMPng modifications.
1290 	 * The exact sequence of events that occur when the interface
1291 	 * is brought up are different now, and if this event
1292 	 * goes unhandled, the configuration/rxfilter setup sequence
1293 	 * can stall for several seconds. The result is that no
1294 	 * packets go out onto the wire for about 5 to 10 seconds
1295 	 * after the interface is ifconfig'ed for the first time.
1296 	 */
1297 	if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1298 		struct fxp_cb_tx *txp;
1299 
1300 		for (txp = sc->cbl_first; sc->tx_queued &&
1301 		    (txp->cb_status & FXP_CB_STATUS_C) != 0;
1302 		    txp = txp->next) {
1303 			if ((m = txp->mb_head) != NULL) {
1304 				txp->mb_head = NULL;
1305 				sc->tx_queued--;
1306 				m_freem(m);
1307 			} else {
1308 				sc->tx_queued--;
1309 			}
1310 		}
1311 		sc->cbl_first = txp;
1312 
1313 		if (sc->tx_queued < FXP_USABLE_TXCB)
1314 			ifp->if_flags &= ~IFF_OACTIVE;
1315 
1316 		if (sc->tx_queued == 0) {
1317 			ifp->if_timer = 0;
1318 			if (sc->need_mcsetup)
1319 				fxp_mc_setup(sc);
1320 		}
1321 
1322 		/*
1323 		 * Try to start more packets transmitting.
1324 		 */
1325 		if (!ifq_is_empty(&ifp->if_snd))
1326 			if_devstart(ifp);
1327 	}
1328 
1329 	/*
1330 	 * Just return if nothing happened on the receive side.
1331 	 */
1332 	if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1333 		return;
1334 
1335 	/*
1336 	 * Process receiver interrupts. If a no-resource (RNR)
1337 	 * condition exists, get whatever packets we can and
1338 	 * re-start the receiver.
1339 	 *
1340 	 * When using polling, we do not process the list to completion,
1341 	 * so when we get an RNR interrupt we must defer the restart
1342 	 * until we hit the last buffer with the C bit set.
1343 	 * If we run out of cycles and rfa_headm has the C bit set,
1344 	 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1345 	 * that the info will be used in the subsequent polling cycle.
1346 	 */
1347 	for (;;) {
1348 		m = sc->rfa_headm;
1349 		rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1350 					 RFA_ALIGNMENT_FUDGE);
1351 
1352 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1353 		if (count >= 0 && count-- == 0) {
1354 			if (rnr) {
1355 				/* Defer RNR processing until the next time. */
1356 				sc->flags |= FXP_FLAG_DEFERRED_RNR;
1357 				rnr = 0;
1358 			}
1359 			break;
1360 		}
1361 #endif /* DEVICE_POLLING */
1362 
1363 		if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0)
1364 			break;
1365 
1366 		/*
1367 		 * Remove first packet from the chain.
1368 		 */
1369 		sc->rfa_headm = m->m_next;
1370 		if (sc->rfa_headm == NULL)
1371 			sc->rfa_tailm = NULL;
1372 		m->m_next = NULL;
1373 
1374 		/*
1375 		 * Add a new buffer to the receive chain.
1376 		 * If this fails, the old buffer is recycled
1377 		 * instead.
1378 		 */
1379 		if (fxp_add_rfabuf(sc, m) == 0) {
1380 			int total_len;
1381 
1382 			/*
1383 			 * Fetch packet length (the top 2 bits of
1384 			 * actual_size are flags set by the controller
1385 			 * upon completion), and drop the packet in case
1386 			 * of bogus length or CRC errors.
1387 			 */
1388 			total_len = rfa->actual_size & 0x3fff;
1389 			if (total_len < sizeof(struct ether_header) ||
1390 			    total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1391 					sizeof(struct fxp_rfa) ||
1392 			    (rfa->rfa_status & FXP_RFA_STATUS_CRC)) {
1393 				m_freem(m);
1394 				continue;
1395 			}
1396 			m->m_pkthdr.len = m->m_len = total_len;
1397 			ifp->if_input(ifp, m);
1398 		}
1399 	}
1400 
1401 	if (rnr) {
1402 		fxp_scb_wait(sc);
1403 		CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1404 		    vtophys(sc->rfa_headm->m_ext.ext_buf) +
1405 		    RFA_ALIGNMENT_FUDGE);
1406 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1407 	}
1408 }
1409 
1410 /*
1411  * Update packet in/out/collision statistics. The i82557 doesn't
1412  * allow you to access these counters without doing a fairly
1413  * expensive DMA to get _all_ of the statistics it maintains, so
1414  * we do this operation here only once per second. The statistics
1415  * counters in the kernel are updated from the previous dump-stats
1416  * DMA and then a new dump-stats DMA is started. The on-chip
1417  * counters are zeroed when the DMA completes. If we can't start
1418  * the DMA immediately, we don't wait - we just prepare to read
1419  * them again next time.
1420  */
1421 static void
1422 fxp_tick(void *xsc)
1423 {
1424 	struct fxp_softc *sc = xsc;
1425 	struct ifnet *ifp = &sc->arpcom.ac_if;
1426 	struct fxp_stats *sp = sc->fxp_stats;
1427 	struct fxp_cb_tx *txp;
1428 	struct mbuf *m;
1429 
1430 	lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1431 
1432 	ifp->if_opackets += sp->tx_good;
1433 	ifp->if_collisions += sp->tx_total_collisions;
1434 	if (sp->rx_good) {
1435 		ifp->if_ipackets += sp->rx_good;
1436 		sc->rx_idle_secs = 0;
1437 	} else {
1438 		/*
1439 		 * Receiver's been idle for another second.
1440 		 */
1441 		sc->rx_idle_secs++;
1442 	}
1443 	ifp->if_ierrors +=
1444 	    sp->rx_crc_errors +
1445 	    sp->rx_alignment_errors +
1446 	    sp->rx_rnr_errors +
1447 	    sp->rx_overrun_errors;
1448 	/*
1449 	 * If any transmit underruns occured, bump up the transmit
1450 	 * threshold by another 512 bytes (64 * 8).
1451 	 */
1452 	if (sp->tx_underruns) {
1453 		ifp->if_oerrors += sp->tx_underruns;
1454 		if (tx_threshold < 192)
1455 			tx_threshold += 64;
1456 	}
1457 
1458 	/*
1459 	 * Release any xmit buffers that have completed DMA. This isn't
1460 	 * strictly necessary to do here, but it's advantagous for mbufs
1461 	 * with external storage to be released in a timely manner rather
1462 	 * than being defered for a potentially long time. This limits
1463 	 * the delay to a maximum of one second.
1464 	 */
1465 	for (txp = sc->cbl_first; sc->tx_queued &&
1466 	    (txp->cb_status & FXP_CB_STATUS_C) != 0;
1467 	    txp = txp->next) {
1468 		if ((m = txp->mb_head) != NULL) {
1469 			txp->mb_head = NULL;
1470 			sc->tx_queued--;
1471 			m_freem(m);
1472 		} else {
1473 			sc->tx_queued--;
1474 		}
1475 	}
1476 	sc->cbl_first = txp;
1477 
1478 	if (sc->tx_queued < FXP_USABLE_TXCB)
1479 		ifp->if_flags &= ~IFF_OACTIVE;
1480 	if (sc->tx_queued == 0)
1481 		ifp->if_timer = 0;
1482 
1483  	/*
1484 	 * Try to start more packets transmitting.
1485 	 */
1486 	if (!ifq_is_empty(&ifp->if_snd))
1487 		if_devstart(ifp);
1488 
1489 	/*
1490 	 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1491 	 * then assume the receiver has locked up and attempt to clear
1492 	 * the condition by reprogramming the multicast filter. This is
1493 	 * a work-around for a bug in the 82557 where the receiver locks
1494 	 * up if it gets certain types of garbage in the syncronization
1495 	 * bits prior to the packet header. This bug is supposed to only
1496 	 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1497 	 * mode as well (perhaps due to a 10/100 speed transition).
1498 	 */
1499 	if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1500 		sc->rx_idle_secs = 0;
1501 		fxp_mc_setup(sc);
1502 	}
1503 	/*
1504 	 * If there is no pending command, start another stats
1505 	 * dump. Otherwise punt for now.
1506 	 */
1507 	if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1508 		/*
1509 		 * Start another stats dump.
1510 		 */
1511 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1512 	} else {
1513 		/*
1514 		 * A previous command is still waiting to be accepted.
1515 		 * Just zero our copy of the stats and wait for the
1516 		 * next timer event to update them.
1517 		 */
1518 		sp->tx_good = 0;
1519 		sp->tx_underruns = 0;
1520 		sp->tx_total_collisions = 0;
1521 
1522 		sp->rx_good = 0;
1523 		sp->rx_crc_errors = 0;
1524 		sp->rx_alignment_errors = 0;
1525 		sp->rx_rnr_errors = 0;
1526 		sp->rx_overrun_errors = 0;
1527 	}
1528 	if (sc->miibus != NULL)
1529 		mii_tick(device_get_softc(sc->miibus));
1530 	/*
1531 	 * Schedule another timeout one second from now.
1532 	 */
1533 	callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1534 
1535 	lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1536 }
1537 
1538 /*
1539  * Stop the interface. Cancels the statistics updater and resets
1540  * the interface.
1541  */
1542 static void
1543 fxp_stop(struct fxp_softc *sc)
1544 {
1545 	struct ifnet *ifp = &sc->arpcom.ac_if;
1546 	struct fxp_cb_tx *txp;
1547 	int i;
1548 
1549 	ASSERT_SERIALIZED(ifp->if_serializer);
1550 
1551 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1552 	ifp->if_timer = 0;
1553 
1554 	/*
1555 	 * Cancel stats updater.
1556 	 */
1557 	callout_stop(&sc->fxp_stat_timer);
1558 
1559 	/*
1560 	 * Issue software reset, which also unloads the microcode.
1561 	 */
1562 	sc->flags &= ~FXP_FLAG_UCODE;
1563 	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1564 	DELAY(50);
1565 
1566 	/*
1567 	 * Release any xmit buffers.
1568 	 */
1569 	txp = sc->cbl_base;
1570 	if (txp != NULL) {
1571 		for (i = 0; i < FXP_NTXCB; i++) {
1572 			if (txp[i].mb_head != NULL) {
1573 				m_freem(txp[i].mb_head);
1574 				txp[i].mb_head = NULL;
1575 			}
1576 		}
1577 	}
1578 	sc->tx_queued = 0;
1579 
1580 	/*
1581 	 * Free all the receive buffers then reallocate/reinitialize
1582 	 */
1583 	if (sc->rfa_headm != NULL)
1584 		m_freem(sc->rfa_headm);
1585 	sc->rfa_headm = NULL;
1586 	sc->rfa_tailm = NULL;
1587 	for (i = 0; i < FXP_NRFABUFS; i++) {
1588 		if (fxp_add_rfabuf(sc, NULL) != 0) {
1589 			/*
1590 			 * This "can't happen" - we're at splimp()
1591 			 * and we just freed all the buffers we need
1592 			 * above.
1593 			 */
1594 			panic("fxp_stop: no buffers!");
1595 		}
1596 	}
1597 }
1598 
1599 /*
1600  * Watchdog/transmission transmit timeout handler. Called when a
1601  * transmission is started on the interface, but no interrupt is
1602  * received before the timeout. This usually indicates that the
1603  * card has wedged for some reason.
1604  */
1605 static void
1606 fxp_watchdog(struct ifnet *ifp)
1607 {
1608 	ASSERT_SERIALIZED(ifp->if_serializer);
1609 
1610 	if_printf(ifp, "device timeout\n");
1611 	ifp->if_oerrors++;
1612 	fxp_init(ifp->if_softc);
1613 }
1614 
1615 static void
1616 fxp_init(void *xsc)
1617 {
1618 	struct fxp_softc *sc = xsc;
1619 	struct ifnet *ifp = &sc->arpcom.ac_if;
1620 	struct fxp_cb_config *cbp;
1621 	struct fxp_cb_ias *cb_ias;
1622 	struct fxp_cb_tx *txp;
1623 	struct fxp_cb_mcs *mcsp;
1624 	int i, prm;
1625 
1626 	ASSERT_SERIALIZED(ifp->if_serializer);
1627 
1628 	/*
1629 	 * Cancel any pending I/O
1630 	 */
1631 	fxp_stop(sc);
1632 
1633 	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1634 
1635 	/*
1636 	 * Initialize base of CBL and RFA memory. Loading with zero
1637 	 * sets it up for regular linear addressing.
1638 	 */
1639 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1640 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1641 
1642 	fxp_scb_wait(sc);
1643 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1644 
1645 	/*
1646 	 * Initialize base of dump-stats buffer.
1647 	 */
1648 	fxp_scb_wait(sc);
1649 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1650 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1651 
1652 	/*
1653 	 * Attempt to load microcode if requested.
1654 	 */
1655 	if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1656 		fxp_load_ucode(sc);
1657 
1658 	/*
1659 	 * Initialize the multicast address list.
1660 	 */
1661 	if (fxp_mc_addrs(sc)) {
1662 		mcsp = sc->mcsp;
1663 		mcsp->cb_status = 0;
1664 		mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1665 		mcsp->link_addr = -1;
1666 		/*
1667 	 	 * Start the multicast setup command.
1668 		 */
1669 		fxp_scb_wait(sc);
1670 		CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1671 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1672 		/* ...and wait for it to complete. */
1673 		fxp_dma_wait(&mcsp->cb_status, sc);
1674 	}
1675 
1676 	/*
1677 	 * We temporarily use memory that contains the TxCB list to
1678 	 * construct the config CB. The TxCB list memory is rebuilt
1679 	 * later.
1680 	 */
1681 	cbp = (struct fxp_cb_config *) sc->cbl_base;
1682 
1683 	/*
1684 	 * This bcopy is kind of disgusting, but there are a bunch of must be
1685 	 * zero and must be one bits in this structure and this is the easiest
1686 	 * way to initialize them all to proper values.
1687 	 */
1688 	bcopy(fxp_cb_config_template,
1689 		(void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1690 		sizeof(fxp_cb_config_template));
1691 
1692 	cbp->cb_status =	0;
1693 	cbp->cb_command =	FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1694 	cbp->link_addr =	-1;	/* (no) next command */
1695 	cbp->byte_count =	22;	/* (22) bytes to config */
1696 	cbp->rx_fifo_limit =	8;	/* rx fifo threshold (32 bytes) */
1697 	cbp->tx_fifo_limit =	0;	/* tx fifo threshold (0 bytes) */
1698 	cbp->adaptive_ifs =	0;	/* (no) adaptive interframe spacing */
1699 	cbp->mwi_enable =	sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1700 	cbp->type_enable =	0;	/* actually reserved */
1701 	cbp->read_align_en =	sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1702 	cbp->end_wr_on_cl =	sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1703 	cbp->rx_dma_bytecount =	0;	/* (no) rx DMA max */
1704 	cbp->tx_dma_bytecount =	0;	/* (no) tx DMA max */
1705 	cbp->dma_mbce =		0;	/* (disable) dma max counters */
1706 	cbp->late_scb =		0;	/* (don't) defer SCB update */
1707 	cbp->direct_dma_dis =	1;	/* disable direct rcv dma mode */
1708 	cbp->tno_int_or_tco_en =0;	/* (disable) tx not okay interrupt */
1709 	cbp->ci_int =		1;	/* interrupt on CU idle */
1710 	cbp->ext_txcb_dis = 	sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1711 	cbp->ext_stats_dis = 	1;	/* disable extended counters */
1712 	cbp->keep_overrun_rx = 	0;	/* don't pass overrun frames to host */
1713 	cbp->save_bf =		sc->revision == FXP_REV_82557 ? 1 : prm;
1714 	cbp->disc_short_rx =	!prm;	/* discard short packets */
1715 	cbp->underrun_retry =	1;	/* retry mode (once) on DMA underrun */
1716 	cbp->two_frames =	0;	/* do not limit FIFO to 2 frames */
1717 	cbp->dyn_tbd =		0;	/* (no) dynamic TBD mode */
1718 	cbp->mediatype =	sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1719 	cbp->csma_dis =		0;	/* (don't) disable link */
1720 	cbp->tcp_udp_cksum =	0;	/* (don't) enable checksum */
1721 	cbp->vlan_tco =		0;	/* (don't) enable vlan wakeup */
1722 	cbp->link_wake_en =	0;	/* (don't) assert PME# on link change */
1723 	cbp->arp_wake_en =	0;	/* (don't) assert PME# on arp */
1724 	cbp->mc_wake_en =	0;	/* (don't) enable PME# on mcmatch */
1725 	cbp->nsai =		1;	/* (don't) disable source addr insert */
1726 	cbp->preamble_length =	2;	/* (7 byte) preamble */
1727 	cbp->loopback =		0;	/* (don't) loopback */
1728 	cbp->linear_priority =	0;	/* (normal CSMA/CD operation) */
1729 	cbp->linear_pri_mode =	0;	/* (wait after xmit only) */
1730 	cbp->interfrm_spacing =	6;	/* (96 bits of) interframe spacing */
1731 	cbp->promiscuous =	prm;	/* promiscuous mode */
1732 	cbp->bcast_disable =	0;	/* (don't) disable broadcasts */
1733 	cbp->wait_after_win =	0;	/* (don't) enable modified backoff alg*/
1734 	cbp->ignore_ul =	0;	/* consider U/L bit in IA matching */
1735 	cbp->crc16_en =		0;	/* (don't) enable crc-16 algorithm */
1736 	cbp->crscdt =		sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1737 
1738 	cbp->stripping =	!prm;	/* truncate rx packet to byte count */
1739 	cbp->padding =		1;	/* (do) pad short tx packets */
1740 	cbp->rcv_crc_xfer =	0;	/* (don't) xfer CRC to host */
1741 	cbp->long_rx_en =	sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1742 	cbp->ia_wake_en =	0;	/* (don't) wake up on address match */
1743 	cbp->magic_pkt_dis =	0;	/* (don't) disable magic packet */
1744 					/* must set wake_en in PMCSR also */
1745 	cbp->force_fdx =	0;	/* (don't) force full duplex */
1746 	cbp->fdx_pin_en =	1;	/* (enable) FDX# pin */
1747 	cbp->multi_ia =		0;	/* (don't) accept multiple IAs */
1748 	cbp->mc_all =		sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1749 
1750 	if (sc->revision == FXP_REV_82557) {
1751 		/*
1752 		 * The 82557 has no hardware flow control, the values
1753 		 * below are the defaults for the chip.
1754 		 */
1755 		cbp->fc_delay_lsb =	0;
1756 		cbp->fc_delay_msb =	0x40;
1757 		cbp->pri_fc_thresh =	3;
1758 		cbp->tx_fc_dis =	0;
1759 		cbp->rx_fc_restop =	0;
1760 		cbp->rx_fc_restart =	0;
1761 		cbp->fc_filter =	0;
1762 		cbp->pri_fc_loc =	1;
1763 	} else {
1764 		cbp->fc_delay_lsb =	0x1f;
1765 		cbp->fc_delay_msb =	0x01;
1766 		cbp->pri_fc_thresh =	3;
1767 		cbp->tx_fc_dis =	0;	/* enable transmit FC */
1768 		cbp->rx_fc_restop =	1;	/* enable FC restop frames */
1769 		cbp->rx_fc_restart =	1;	/* enable FC restart frames */
1770 		cbp->fc_filter =	!prm;	/* drop FC frames to host */
1771 		cbp->pri_fc_loc =	1;	/* FC pri location (byte31) */
1772 	}
1773 
1774 	/*
1775 	 * Start the config command/DMA.
1776 	 */
1777 	fxp_scb_wait(sc);
1778 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1779 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1780 	/* ...and wait for it to complete. */
1781 	fxp_dma_wait(&cbp->cb_status, sc);
1782 
1783 	/*
1784 	 * Now initialize the station address. Temporarily use the TxCB
1785 	 * memory area like we did above for the config CB.
1786 	 */
1787 	cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1788 	cb_ias->cb_status = 0;
1789 	cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1790 	cb_ias->link_addr = -1;
1791 	bcopy(sc->arpcom.ac_enaddr,
1792 	    (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1793 	    sizeof(sc->arpcom.ac_enaddr));
1794 
1795 	/*
1796 	 * Start the IAS (Individual Address Setup) command/DMA.
1797 	 */
1798 	fxp_scb_wait(sc);
1799 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1800 	/* ...and wait for it to complete. */
1801 	fxp_dma_wait(&cb_ias->cb_status, sc);
1802 
1803 	/*
1804 	 * Initialize transmit control block (TxCB) list.
1805 	 */
1806 
1807 	txp = sc->cbl_base;
1808 	bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1809 	for (i = 0; i < FXP_NTXCB; i++) {
1810 		txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1811 		txp[i].cb_command = FXP_CB_COMMAND_NOP;
1812 		txp[i].link_addr =
1813 		    vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1814 		if (sc->flags & FXP_FLAG_EXT_TXCB)
1815 			txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1816 		else
1817 			txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1818 		txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1819 	}
1820 	/*
1821 	 * Set the suspend flag on the first TxCB and start the control
1822 	 * unit. It will execute the NOP and then suspend.
1823 	 */
1824 	txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1825 	sc->cbl_first = sc->cbl_last = txp;
1826 	sc->tx_queued = 1;
1827 
1828 	fxp_scb_wait(sc);
1829 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1830 
1831 	/*
1832 	 * Initialize receiver buffer area - RFA.
1833 	 */
1834 	fxp_scb_wait(sc);
1835 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1836 	    vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1837 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1838 
1839 	/*
1840 	 * Set current media.
1841 	 */
1842 	if (sc->miibus != NULL)
1843 		mii_mediachg(device_get_softc(sc->miibus));
1844 
1845 	ifp->if_flags |= IFF_RUNNING;
1846 	ifp->if_flags &= ~IFF_OACTIVE;
1847 
1848 	/*
1849 	 * Enable interrupts.
1850 	 */
1851 #ifdef DEVICE_POLLING
1852 	/*
1853 	 * ... but only do that if we are not polling. And because (presumably)
1854 	 * the default is interrupts on, we need to disable them explicitly!
1855 	 */
1856 	if ( ifp->if_flags & IFF_POLLING )
1857 		CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1858 	else
1859 #endif /* DEVICE_POLLING */
1860 	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1861 
1862 	/*
1863 	 * Start stats updater.
1864 	 */
1865 	callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1866 }
1867 
1868 static int
1869 fxp_serial_ifmedia_upd(struct ifnet *ifp)
1870 {
1871 	ASSERT_SERIALIZED(ifp->if_serializer);
1872 	return (0);
1873 }
1874 
1875 static void
1876 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1877 {
1878 	ASSERT_SERIALIZED(ifp->if_serializer);
1879 	ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1880 }
1881 
1882 /*
1883  * Change media according to request.
1884  */
1885 static int
1886 fxp_ifmedia_upd(struct ifnet *ifp)
1887 {
1888 	struct fxp_softc *sc = ifp->if_softc;
1889 	struct mii_data *mii;
1890 
1891 	ASSERT_SERIALIZED(ifp->if_serializer);
1892 
1893 	mii = device_get_softc(sc->miibus);
1894 	mii_mediachg(mii);
1895 	return (0);
1896 }
1897 
1898 /*
1899  * Notify the world which media we're using.
1900  */
1901 static void
1902 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1903 {
1904 	struct fxp_softc *sc = ifp->if_softc;
1905 	struct mii_data *mii;
1906 
1907 	ASSERT_SERIALIZED(ifp->if_serializer);
1908 
1909 	mii = device_get_softc(sc->miibus);
1910 	mii_pollstat(mii);
1911 	ifmr->ifm_active = mii->mii_media_active;
1912 	ifmr->ifm_status = mii->mii_media_status;
1913 
1914 	if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1915 		sc->cu_resume_bug = 1;
1916 	else
1917 		sc->cu_resume_bug = 0;
1918 }
1919 
1920 /*
1921  * Add a buffer to the end of the RFA buffer list.
1922  * Return 0 if successful, 1 for failure. A failure results in
1923  * adding the 'oldm' (if non-NULL) on to the end of the list -
1924  * tossing out its old contents and recycling it.
1925  * The RFA struct is stuck at the beginning of mbuf cluster and the
1926  * data pointer is fixed up to point just past it.
1927  */
1928 static int
1929 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1930 {
1931 	u_int32_t v;
1932 	struct mbuf *m;
1933 	struct fxp_rfa *rfa, *p_rfa;
1934 
1935 	m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1936 	if (m == NULL) { /* try to recycle the old mbuf instead */
1937 		if (oldm == NULL)
1938 			return 1;
1939 		m = oldm;
1940 		m->m_data = m->m_ext.ext_buf;
1941 	}
1942 
1943 	/*
1944 	 * Move the data pointer up so that the incoming data packet
1945 	 * will be 32-bit aligned.
1946 	 */
1947 	m->m_data += RFA_ALIGNMENT_FUDGE;
1948 
1949 	/*
1950 	 * Get a pointer to the base of the mbuf cluster and move
1951 	 * data start past it.
1952 	 */
1953 	rfa = mtod(m, struct fxp_rfa *);
1954 	m->m_data += sizeof(struct fxp_rfa);
1955 	rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) -
1956 				RFA_ALIGNMENT_FUDGE);
1957 
1958 	/*
1959 	 * Initialize the rest of the RFA.  Note that since the RFA
1960 	 * is misaligned, we cannot store values directly.  Instead,
1961 	 * we use an optimized, inline copy.
1962 	 */
1963 
1964 	rfa->rfa_status = 0;
1965 	rfa->rfa_control = FXP_RFA_CONTROL_EL;
1966 	rfa->actual_size = 0;
1967 
1968 	v = -1;
1969 	fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1970 	fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1971 
1972 	/*
1973 	 * If there are other buffers already on the list, attach this
1974 	 * one to the end by fixing up the tail to point to this one.
1975 	 */
1976 	if (sc->rfa_headm != NULL) {
1977 		p_rfa = (struct fxp_rfa *)(sc->rfa_tailm->m_ext.ext_buf +
1978 					   RFA_ALIGNMENT_FUDGE);
1979 		sc->rfa_tailm->m_next = m;
1980 		v = vtophys(rfa);
1981 		fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1982 		p_rfa->rfa_control = 0;
1983 	} else {
1984 		sc->rfa_headm = m;
1985 	}
1986 	sc->rfa_tailm = m;
1987 
1988 	return (m == oldm);
1989 }
1990 
1991 static int
1992 fxp_miibus_readreg(device_t dev, int phy, int reg)
1993 {
1994 	struct fxp_softc *sc = device_get_softc(dev);
1995 	int count = 10000;
1996 	int value;
1997 
1998 	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1999 	    (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2000 
2001 	while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2002 	    && count--)
2003 		DELAY(10);
2004 
2005 	if (count <= 0)
2006 		device_printf(dev, "fxp_miibus_readreg: timed out\n");
2007 
2008 	return (value & 0xffff);
2009 }
2010 
2011 static void
2012 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2013 {
2014 	struct fxp_softc *sc = device_get_softc(dev);
2015 	int count = 10000;
2016 
2017 	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2018 	    (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2019 	    (value & 0xffff));
2020 
2021 	while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2022 	    count--)
2023 		DELAY(10);
2024 
2025 	if (count <= 0)
2026 		device_printf(dev, "fxp_miibus_writereg: timed out\n");
2027 }
2028 
2029 static int
2030 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2031 {
2032 	struct fxp_softc *sc = ifp->if_softc;
2033 	struct ifreq *ifr = (struct ifreq *)data;
2034 	struct mii_data *mii;
2035 	int error = 0;
2036 
2037 	ASSERT_SERIALIZED(ifp->if_serializer);
2038 
2039 	switch (command) {
2040 
2041 	case SIOCSIFFLAGS:
2042 		if (ifp->if_flags & IFF_ALLMULTI)
2043 			sc->flags |= FXP_FLAG_ALL_MCAST;
2044 		else
2045 			sc->flags &= ~FXP_FLAG_ALL_MCAST;
2046 
2047 		/*
2048 		 * If interface is marked up and not running, then start it.
2049 		 * If it is marked down and running, stop it.
2050 		 * XXX If it's up then re-initialize it. This is so flags
2051 		 * such as IFF_PROMISC are handled.
2052 		 */
2053 		if (ifp->if_flags & IFF_UP) {
2054 			fxp_init(sc);
2055 		} else {
2056 			if (ifp->if_flags & IFF_RUNNING)
2057 				fxp_stop(sc);
2058 		}
2059 		break;
2060 
2061 	case SIOCADDMULTI:
2062 	case SIOCDELMULTI:
2063 		if (ifp->if_flags & IFF_ALLMULTI)
2064 			sc->flags |= FXP_FLAG_ALL_MCAST;
2065 		else
2066 			sc->flags &= ~FXP_FLAG_ALL_MCAST;
2067 		/*
2068 		 * Multicast list has changed; set the hardware filter
2069 		 * accordingly.
2070 		 */
2071 		if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2072 			fxp_mc_setup(sc);
2073 		/*
2074 		 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2075 		 * again rather than else {}.
2076 		 */
2077 		if (sc->flags & FXP_FLAG_ALL_MCAST)
2078 			fxp_init(sc);
2079 		error = 0;
2080 		break;
2081 
2082 	case SIOCSIFMEDIA:
2083 	case SIOCGIFMEDIA:
2084 		if (sc->miibus != NULL) {
2085 			mii = device_get_softc(sc->miibus);
2086                         error = ifmedia_ioctl(ifp, ifr,
2087                             &mii->mii_media, command);
2088 		} else {
2089                         error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2090 		}
2091 		break;
2092 
2093 	default:
2094 		error = ether_ioctl(ifp, command, data);
2095 		break;
2096 	}
2097 	return (error);
2098 }
2099 
2100 /*
2101  * Fill in the multicast address list and return number of entries.
2102  */
2103 static int
2104 fxp_mc_addrs(struct fxp_softc *sc)
2105 {
2106 	struct fxp_cb_mcs *mcsp = sc->mcsp;
2107 	struct ifnet *ifp = &sc->arpcom.ac_if;
2108 	struct ifmultiaddr *ifma;
2109 	int nmcasts;
2110 
2111 	nmcasts = 0;
2112 	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2113 		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2114 			if (ifma->ifma_addr->sa_family != AF_LINK)
2115 				continue;
2116 			if (nmcasts >= MAXMCADDR) {
2117 				sc->flags |= FXP_FLAG_ALL_MCAST;
2118 				nmcasts = 0;
2119 				break;
2120 			}
2121 			bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2122 			    (void *)(uintptr_t)(volatile void *)
2123 				&sc->mcsp->mc_addr[nmcasts][0], 6);
2124 			nmcasts++;
2125 		}
2126 	}
2127 	mcsp->mc_cnt = nmcasts * 6;
2128 	return (nmcasts);
2129 }
2130 
2131 /*
2132  * Program the multicast filter.
2133  *
2134  * We have an artificial restriction that the multicast setup command
2135  * must be the first command in the chain, so we take steps to ensure
2136  * this. By requiring this, it allows us to keep up the performance of
2137  * the pre-initialized command ring (esp. link pointers) by not actually
2138  * inserting the mcsetup command in the ring - i.e. its link pointer
2139  * points to the TxCB ring, but the mcsetup descriptor itself is not part
2140  * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2141  * lead into the regular TxCB ring when it completes.
2142  *
2143  * This function must be called at splimp.
2144  */
2145 static void
2146 fxp_mc_setup(struct fxp_softc *sc)
2147 {
2148 	struct fxp_cb_mcs *mcsp = sc->mcsp;
2149 	struct ifnet *ifp = &sc->arpcom.ac_if;
2150 	int count;
2151 
2152 	/*
2153 	 * If there are queued commands, we must wait until they are all
2154 	 * completed. If we are already waiting, then add a NOP command
2155 	 * with interrupt option so that we're notified when all commands
2156 	 * have been completed - fxp_start() ensures that no additional
2157 	 * TX commands will be added when need_mcsetup is true.
2158 	 */
2159 	if (sc->tx_queued) {
2160 		struct fxp_cb_tx *txp;
2161 
2162 		/*
2163 		 * need_mcsetup will be true if we are already waiting for the
2164 		 * NOP command to be completed (see below). In this case, bail.
2165 		 */
2166 		if (sc->need_mcsetup)
2167 			return;
2168 		sc->need_mcsetup = 1;
2169 
2170 		/*
2171 		 * Add a NOP command with interrupt so that we are notified
2172 		 * when all TX commands have been processed.
2173 		 */
2174 		txp = sc->cbl_last->next;
2175 		txp->mb_head = NULL;
2176 		txp->cb_status = 0;
2177 		txp->cb_command = FXP_CB_COMMAND_NOP |
2178 		    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2179 		/*
2180 		 * Advance the end of list forward.
2181 		 */
2182 		sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2183 		sc->cbl_last = txp;
2184 		sc->tx_queued++;
2185 		/*
2186 		 * Issue a resume in case the CU has just suspended.
2187 		 */
2188 		fxp_scb_wait(sc);
2189 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2190 		/*
2191 		 * Set a 5 second timer just in case we don't hear from the
2192 		 * card again.
2193 		 */
2194 		ifp->if_timer = 5;
2195 
2196 		return;
2197 	}
2198 	sc->need_mcsetup = 0;
2199 
2200 	/*
2201 	 * Initialize multicast setup descriptor.
2202 	 */
2203 	mcsp->next = sc->cbl_base;
2204 	mcsp->mb_head = NULL;
2205 	mcsp->cb_status = 0;
2206 	mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2207 	    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2208 	mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2209 	fxp_mc_addrs(sc);
2210 	sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2211 	sc->tx_queued = 1;
2212 
2213 	/*
2214 	 * Wait until command unit is not active. This should never
2215 	 * be the case when nothing is queued, but make sure anyway.
2216 	 */
2217 	count = 100;
2218 	while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2219 	    FXP_SCB_CUS_ACTIVE && --count)
2220 		DELAY(10);
2221 	if (count == 0) {
2222 		if_printf(&sc->arpcom.ac_if, "command queue timeout\n");
2223 		return;
2224 	}
2225 
2226 	/*
2227 	 * Start the multicast setup command.
2228 	 */
2229 	fxp_scb_wait(sc);
2230 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2231 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2232 
2233 	ifp->if_timer = 2;
2234 	return;
2235 }
2236 
2237 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2238 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2239 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2240 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2241 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2242 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2243 
2244 #define UCODE(x)	x, sizeof(x)
2245 
2246 struct ucode {
2247 	u_int32_t	revision;
2248 	u_int32_t	*ucode;
2249 	int		length;
2250 	u_short		int_delay_offset;
2251 	u_short		bundle_max_offset;
2252 } ucode_table[] = {
2253 	{ FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2254 	{ FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2255 	{ FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2256 	    D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2257 	{ FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2258 	    D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2259 	{ FXP_REV_82550, UCODE(fxp_ucode_d102),
2260 	    D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2261 	{ FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2262 	    D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2263 	{ 0, NULL, 0, 0, 0 }
2264 };
2265 
2266 static void
2267 fxp_load_ucode(struct fxp_softc *sc)
2268 {
2269 	struct ucode *uc;
2270 	struct fxp_cb_ucode *cbp;
2271 
2272 	for (uc = ucode_table; uc->ucode != NULL; uc++)
2273 		if (sc->revision == uc->revision)
2274 			break;
2275 	if (uc->ucode == NULL)
2276 		return;
2277 	cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2278 	cbp->cb_status = 0;
2279 	cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2280 	cbp->link_addr = -1;    	/* (no) next command */
2281 	memcpy(cbp->ucode, uc->ucode, uc->length);
2282 	if (uc->int_delay_offset)
2283 		*(u_short *)&cbp->ucode[uc->int_delay_offset] =
2284 		    sc->tunable_int_delay + sc->tunable_int_delay / 2;
2285 	if (uc->bundle_max_offset)
2286 		*(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2287 		    sc->tunable_bundle_max;
2288 	/*
2289 	 * Download the ucode to the chip.
2290 	 */
2291 	fxp_scb_wait(sc);
2292 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2293 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2294 	/* ...and wait for it to complete. */
2295 	fxp_dma_wait(&cbp->cb_status, sc);
2296 	if_printf(&sc->arpcom.ac_if,
2297 	    "Microcode loaded, int_delay: %d usec  bundle_max: %d\n",
2298 	    sc->tunable_int_delay,
2299 	    uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2300 	sc->flags |= FXP_FLAG_UCODE;
2301 }
2302 
2303 /*
2304  * Interrupt delay is expressed in microseconds, a multiplier is used
2305  * to convert this to the appropriate clock ticks before using.
2306  */
2307 static int
2308 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2309 {
2310 	return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2311 }
2312 
2313 static int
2314 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2315 {
2316 	return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
2317 }
2318