1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.55 2008/06/27 10:55:23 sephe Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include "opt_polling.h" 37 #include "opt_ethernet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/interrupt.h> 45 #include <sys/socket.h> 46 #include <sys/sysctl.h> 47 #include <sys/thread2.h> 48 49 #include <net/if.h> 50 #include <net/ifq_var.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 54 #ifdef NS 55 #include <netns/ns.h> 56 #include <netns/ns_if.h> 57 #endif 58 59 #include <net/bpf.h> 60 #include <sys/sockio.h> 61 #include <sys/bus.h> 62 #include <sys/rman.h> 63 64 #include <net/ethernet.h> 65 #include <net/if_arp.h> 66 67 #include <vm/vm.h> /* for vtophys */ 68 #include <vm/pmap.h> /* for vtophys */ 69 70 #include <net/if_types.h> 71 #include <net/vlan/if_vlan_var.h> 72 73 #include <bus/pci/pcivar.h> 74 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76 #include "../mii_layer/mii.h" 77 #include "../mii_layer/miivar.h" 78 79 #include "if_fxpreg.h" 80 #include "if_fxpvar.h" 81 #include "rcvbundl.h" 82 83 #include "miibus_if.h" 84 85 /* 86 * NOTE! On the Alpha, we have an alignment constraint. The 87 * card DMAs the packet immediately following the RFA. However, 88 * the first thing in the packet is a 14-byte Ethernet header. 89 * This means that the packet is misaligned. To compensate, 90 * we actually offset the RFA 2 bytes into the cluster. This 91 * alignes the packet after the Ethernet header at a 32-bit 92 * boundary. HOWEVER! This means that the RFA is misaligned! 93 */ 94 #define RFA_ALIGNMENT_FUDGE 2 95 96 /* 97 * Set initial transmit threshold at 64 (512 bytes). This is 98 * increased by 64 (512 bytes) at a time, to maximum of 192 99 * (1536 bytes), if an underrun occurs. 100 */ 101 static int tx_threshold = 64; 102 103 /* 104 * The configuration byte map has several undefined fields which 105 * must be one or must be zero. Set up a template for these bits 106 * only, (assuming a 82557 chip) leaving the actual configuration 107 * to fxp_init. 108 * 109 * See struct fxp_cb_config for the bit definitions. 110 */ 111 static u_char fxp_cb_config_template[] = { 112 0x0, 0x0, /* cb_status */ 113 0x0, 0x0, /* cb_command */ 114 0x0, 0x0, 0x0, 0x0, /* link_addr */ 115 0x0, /* 0 */ 116 0x0, /* 1 */ 117 0x0, /* 2 */ 118 0x0, /* 3 */ 119 0x0, /* 4 */ 120 0x0, /* 5 */ 121 0x32, /* 6 */ 122 0x0, /* 7 */ 123 0x0, /* 8 */ 124 0x0, /* 9 */ 125 0x6, /* 10 */ 126 0x0, /* 11 */ 127 0x0, /* 12 */ 128 0x0, /* 13 */ 129 0xf2, /* 14 */ 130 0x48, /* 15 */ 131 0x0, /* 16 */ 132 0x40, /* 17 */ 133 0xf0, /* 18 */ 134 0x0, /* 19 */ 135 0x3f, /* 20 */ 136 0x5 /* 21 */ 137 }; 138 139 struct fxp_ident { 140 u_int16_t devid; 141 int16_t revid; /* -1 matches anything */ 142 char *name; 143 }; 144 145 /* 146 * Claim various Intel PCI device identifiers for this driver. The 147 * sub-vendor and sub-device field are extensively used to identify 148 * particular variants, but we don't currently differentiate between 149 * them. 150 */ 151 static struct fxp_ident fxp_ident_table[] = { 152 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 153 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 154 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 155 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 156 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 157 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 158 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 162 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 163 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 165 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 167 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 169 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 170 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 171 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, 172 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 173 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 174 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 175 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" }, 176 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 177 { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, 178 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 179 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 180 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 181 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 182 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 183 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 184 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 185 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 186 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 187 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 188 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 189 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 190 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 191 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 192 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 193 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 194 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 195 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 196 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 197 { 0, -1, NULL }, 198 }; 199 200 static int fxp_probe(device_t dev); 201 static int fxp_attach(device_t dev); 202 static int fxp_detach(device_t dev); 203 static int fxp_shutdown(device_t dev); 204 static int fxp_suspend(device_t dev); 205 static int fxp_resume(device_t dev); 206 207 static void fxp_intr(void *xsc); 208 static void fxp_intr_body(struct fxp_softc *sc, 209 u_int8_t statack, int count); 210 211 static void fxp_init(void *xsc); 212 static void fxp_tick(void *xsc); 213 static void fxp_powerstate_d0(device_t dev); 214 static void fxp_start(struct ifnet *ifp); 215 static void fxp_stop(struct fxp_softc *sc); 216 static void fxp_release(device_t dev); 217 static int fxp_ioctl(struct ifnet *ifp, u_long command, 218 caddr_t data, struct ucred *); 219 static void fxp_watchdog(struct ifnet *ifp); 220 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 221 static int fxp_mc_addrs(struct fxp_softc *sc); 222 static void fxp_mc_setup(struct fxp_softc *sc); 223 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 224 int autosize); 225 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 226 u_int16_t data); 227 static void fxp_autosize_eeprom(struct fxp_softc *sc); 228 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 229 int offset, int words); 230 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 231 int offset, int words); 232 static int fxp_ifmedia_upd(struct ifnet *ifp); 233 static void fxp_ifmedia_sts(struct ifnet *ifp, 234 struct ifmediareq *ifmr); 235 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 236 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 237 struct ifmediareq *ifmr); 238 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 239 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 240 int value); 241 static void fxp_load_ucode(struct fxp_softc *sc); 242 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 243 int low, int high); 244 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 245 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 246 #ifdef DEVICE_POLLING 247 static poll_handler_t fxp_poll; 248 #endif 249 250 static void fxp_lwcopy(volatile u_int32_t *src, 251 volatile u_int32_t *dst); 252 static void fxp_scb_wait(struct fxp_softc *sc); 253 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 254 static void fxp_dma_wait(volatile u_int16_t *status, 255 struct fxp_softc *sc); 256 257 static device_method_t fxp_methods[] = { 258 /* Device interface */ 259 DEVMETHOD(device_probe, fxp_probe), 260 DEVMETHOD(device_attach, fxp_attach), 261 DEVMETHOD(device_detach, fxp_detach), 262 DEVMETHOD(device_shutdown, fxp_shutdown), 263 DEVMETHOD(device_suspend, fxp_suspend), 264 DEVMETHOD(device_resume, fxp_resume), 265 266 /* MII interface */ 267 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 268 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 269 270 { 0, 0 } 271 }; 272 273 static driver_t fxp_driver = { 274 "fxp", 275 fxp_methods, 276 sizeof(struct fxp_softc), 277 }; 278 279 static devclass_t fxp_devclass; 280 281 DECLARE_DUMMY_MODULE(if_fxp); 282 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 283 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 284 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 285 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 286 287 static int fxp_rnr; 288 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 289 290 /* 291 * Copy a 16-bit aligned 32-bit quantity. 292 */ 293 static void 294 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 295 { 296 #ifdef __i386__ 297 *dst = *src; 298 #else 299 volatile u_int16_t *a = (volatile u_int16_t *)src; 300 volatile u_int16_t *b = (volatile u_int16_t *)dst; 301 302 b[0] = a[0]; 303 b[1] = a[1]; 304 #endif 305 } 306 307 /* 308 * Wait for the previous command to be accepted (but not necessarily 309 * completed). 310 */ 311 static void 312 fxp_scb_wait(struct fxp_softc *sc) 313 { 314 int i = 10000; 315 316 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 317 DELAY(2); 318 if (i == 0) { 319 if_printf(&sc->arpcom.ac_if, 320 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 321 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 322 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 323 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 324 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 325 } 326 } 327 328 static void 329 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 330 { 331 332 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 333 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 334 fxp_scb_wait(sc); 335 } 336 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 337 } 338 339 static void 340 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 341 { 342 int i = 10000; 343 344 while (!(*status & FXP_CB_STATUS_C) && --i) 345 DELAY(2); 346 if (i == 0) 347 if_printf(&sc->arpcom.ac_if, "DMA timeout\n"); 348 } 349 350 /* 351 * Return identification string if this is device is ours. 352 */ 353 static int 354 fxp_probe(device_t dev) 355 { 356 u_int16_t devid; 357 u_int8_t revid; 358 struct fxp_ident *ident; 359 360 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 361 devid = pci_get_device(dev); 362 revid = pci_get_revid(dev); 363 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 364 if (ident->devid == devid && 365 (ident->revid == revid || ident->revid == -1)) { 366 device_set_desc(dev, ident->name); 367 return (0); 368 } 369 } 370 } 371 return (ENXIO); 372 } 373 374 static void 375 fxp_powerstate_d0(device_t dev) 376 { 377 u_int32_t iobase, membase, irq; 378 379 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 380 /* Save important PCI config data. */ 381 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 382 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 383 irq = pci_read_config(dev, PCIR_INTLINE, 4); 384 385 /* Reset the power state. */ 386 device_printf(dev, "chip is in D%d power mode " 387 "-- setting to D0\n", pci_get_powerstate(dev)); 388 389 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 390 391 /* Restore PCI config data. */ 392 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 393 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 394 pci_write_config(dev, PCIR_INTLINE, irq, 4); 395 } 396 } 397 398 static int 399 fxp_attach(device_t dev) 400 { 401 int error = 0; 402 struct fxp_softc *sc = device_get_softc(dev); 403 struct ifnet *ifp; 404 u_int32_t val; 405 u_int16_t data; 406 int i, rid, m1, m2, prefer_iomap; 407 408 callout_init(&sc->fxp_stat_timer); 409 sysctl_ctx_init(&sc->sysctl_ctx); 410 411 /* 412 * Enable bus mastering. Enable memory space too, in case 413 * BIOS/Prom forgot about it. 414 */ 415 pci_enable_busmaster(dev); 416 pci_enable_io(dev, SYS_RES_MEMORY); 417 val = pci_read_config(dev, PCIR_COMMAND, 2); 418 419 fxp_powerstate_d0(dev); 420 421 /* 422 * Figure out which we should try first - memory mapping or i/o mapping? 423 * We default to memory mapping. Then we accept an override from the 424 * command line. Then we check to see which one is enabled. 425 */ 426 m1 = PCIM_CMD_MEMEN; 427 m2 = PCIM_CMD_PORTEN; 428 prefer_iomap = 0; 429 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 430 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 431 m1 = PCIM_CMD_PORTEN; 432 m2 = PCIM_CMD_MEMEN; 433 } 434 435 if (val & m1) { 436 sc->rtp = 437 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 438 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 439 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 440 RF_ACTIVE); 441 } 442 if (sc->mem == NULL && (val & m2)) { 443 sc->rtp = 444 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 445 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 446 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 447 RF_ACTIVE); 448 } 449 450 if (!sc->mem) { 451 device_printf(dev, "could not map device registers\n"); 452 error = ENXIO; 453 goto fail; 454 } 455 if (bootverbose) { 456 device_printf(dev, "using %s space register mapping\n", 457 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 458 } 459 460 sc->sc_st = rman_get_bustag(sc->mem); 461 sc->sc_sh = rman_get_bushandle(sc->mem); 462 463 /* 464 * Allocate our interrupt. 465 */ 466 rid = 0; 467 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 468 RF_SHAREABLE | RF_ACTIVE); 469 if (sc->irq == NULL) { 470 device_printf(dev, "could not map interrupt\n"); 471 error = ENXIO; 472 goto fail; 473 } 474 475 /* 476 * Reset to a stable state. 477 */ 478 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 479 DELAY(10); 480 481 sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 482 M_DEVBUF, M_WAITOK | M_ZERO); 483 484 sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF, 485 M_WAITOK | M_ZERO); 486 487 sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 488 489 /* 490 * Pre-allocate our receive buffers. 491 */ 492 for (i = 0; i < FXP_NRFABUFS; i++) { 493 if (fxp_add_rfabuf(sc, NULL) != 0) { 494 goto failmem; 495 } 496 } 497 498 /* 499 * Find out how large of an SEEPROM we have. 500 */ 501 fxp_autosize_eeprom(sc); 502 503 /* 504 * Determine whether we must use the 503 serial interface. 505 */ 506 fxp_read_eeprom(sc, &data, 6, 1); 507 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 508 (data & FXP_PHY_SERIAL_ONLY)) 509 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 510 511 /* 512 * Create the sysctl tree 513 */ 514 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 515 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 516 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 517 if (sc->sysctl_tree == NULL) 518 goto fail; 519 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 520 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 521 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 522 "FXP driver receive interrupt microcode bundling delay"); 523 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 524 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 525 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 526 "FXP driver receive interrupt microcode bundle size limit"); 527 528 /* 529 * Pull in device tunables. 530 */ 531 sc->tunable_int_delay = TUNABLE_INT_DELAY; 532 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 533 resource_int_value(device_get_name(dev), device_get_unit(dev), 534 "int_delay", &sc->tunable_int_delay); 535 resource_int_value(device_get_name(dev), device_get_unit(dev), 536 "bundle_max", &sc->tunable_bundle_max); 537 538 /* 539 * Find out the chip revision; lump all 82557 revs together. 540 */ 541 fxp_read_eeprom(sc, &data, 5, 1); 542 if ((data >> 8) == 1) 543 sc->revision = FXP_REV_82557; 544 else 545 sc->revision = pci_get_revid(dev); 546 547 /* 548 * Enable workarounds for certain chip revision deficiencies. 549 * 550 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 551 * some systems based a normal 82559 design, have a defect where 552 * the chip can cause a PCI protocol violation if it receives 553 * a CU_RESUME command when it is entering the IDLE state. The 554 * workaround is to disable Dynamic Standby Mode, so the chip never 555 * deasserts CLKRUN#, and always remains in an active state. 556 * 557 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 558 */ 559 i = pci_get_device(dev); 560 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 561 sc->revision >= FXP_REV_82559_A0) { 562 fxp_read_eeprom(sc, &data, 10, 1); 563 if (data & 0x02) { /* STB enable */ 564 u_int16_t cksum; 565 int i; 566 567 device_printf(dev, 568 "Disabling dynamic standby mode in EEPROM\n"); 569 data &= ~0x02; 570 fxp_write_eeprom(sc, &data, 10, 1); 571 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 572 cksum = 0; 573 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 574 fxp_read_eeprom(sc, &data, i, 1); 575 cksum += data; 576 } 577 i = (1 << sc->eeprom_size) - 1; 578 cksum = 0xBABA - cksum; 579 fxp_read_eeprom(sc, &data, i, 1); 580 fxp_write_eeprom(sc, &cksum, i, 1); 581 device_printf(dev, 582 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 583 i, data, cksum); 584 #if 1 585 /* 586 * If the user elects to continue, try the software 587 * workaround, as it is better than nothing. 588 */ 589 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 590 #endif 591 } 592 } 593 594 /* 595 * If we are not a 82557 chip, we can enable extended features. 596 */ 597 if (sc->revision != FXP_REV_82557) { 598 /* 599 * If MWI is enabled in the PCI configuration, and there 600 * is a valid cacheline size (8 or 16 dwords), then tell 601 * the board to turn on MWI. 602 */ 603 if (val & PCIM_CMD_MWRICEN && 604 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 605 sc->flags |= FXP_FLAG_MWI_ENABLE; 606 607 /* turn on the extended TxCB feature */ 608 sc->flags |= FXP_FLAG_EXT_TXCB; 609 610 /* enable reception of long frames for VLAN */ 611 sc->flags |= FXP_FLAG_LONG_PKT_EN; 612 } 613 614 /* 615 * Read MAC address. 616 */ 617 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 618 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 619 device_printf(dev, "10Mbps\n"); 620 if (bootverbose) { 621 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 622 pci_get_vendor(dev), pci_get_device(dev), 623 pci_get_subvendor(dev), pci_get_subdevice(dev), 624 pci_get_revid(dev)); 625 fxp_read_eeprom(sc, &data, 10, 1); 626 device_printf(dev, "Dynamic Standby mode is %s\n", 627 data & 0x02 ? "enabled" : "disabled"); 628 } 629 630 /* 631 * If this is only a 10Mbps device, then there is no MII, and 632 * the PHY will use a serial interface instead. 633 * 634 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 635 * doesn't have a programming interface of any sort. The 636 * media is sensed automatically based on how the link partner 637 * is configured. This is, in essence, manual configuration. 638 */ 639 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 640 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 641 fxp_serial_ifmedia_sts); 642 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 643 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 644 } else { 645 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 646 fxp_ifmedia_sts)) { 647 device_printf(dev, "MII without any PHY!\n"); 648 error = ENXIO; 649 goto fail; 650 } 651 } 652 653 ifp = &sc->arpcom.ac_if; 654 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 655 ifp->if_baudrate = 100000000; 656 ifp->if_init = fxp_init; 657 ifp->if_softc = sc; 658 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 659 ifp->if_ioctl = fxp_ioctl; 660 ifp->if_start = fxp_start; 661 #ifdef DEVICE_POLLING 662 ifp->if_poll = fxp_poll; 663 #endif 664 ifp->if_watchdog = fxp_watchdog; 665 666 /* 667 * Attach the interface. 668 */ 669 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 670 671 /* 672 * Tell the upper layer(s) we support long frames. 673 */ 674 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 675 676 /* 677 * Let the system queue as many packets as we have available 678 * TX descriptors. 679 */ 680 ifq_set_maxlen(&ifp->if_snd, FXP_USABLE_TXCB); 681 ifq_set_ready(&ifp->if_snd); 682 683 error = bus_setup_intr(dev, sc->irq, INTR_NETSAFE, 684 fxp_intr, sc, &sc->ih, 685 ifp->if_serializer); 686 if (error) { 687 ether_ifdetach(ifp); 688 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 689 ifmedia_removeall(&sc->sc_media); 690 device_printf(dev, "could not setup irq\n"); 691 goto fail; 692 } 693 694 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->irq)); 695 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 696 697 return (0); 698 699 failmem: 700 device_printf(dev, "Failed to malloc memory\n"); 701 error = ENOMEM; 702 fail: 703 fxp_release(dev); 704 return (error); 705 } 706 707 /* 708 * release all resources 709 */ 710 static void 711 fxp_release(device_t dev) 712 { 713 struct fxp_softc *sc = device_get_softc(dev); 714 715 if (sc->miibus) 716 device_delete_child(dev, sc->miibus); 717 bus_generic_detach(dev); 718 719 if (sc->cbl_base) 720 kfree(sc->cbl_base, M_DEVBUF); 721 if (sc->fxp_stats) 722 kfree(sc->fxp_stats, M_DEVBUF); 723 if (sc->mcsp) 724 kfree(sc->mcsp, M_DEVBUF); 725 if (sc->rfa_headm) 726 m_freem(sc->rfa_headm); 727 728 if (sc->irq) 729 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 730 if (sc->mem) 731 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); 732 733 sysctl_ctx_free(&sc->sysctl_ctx); 734 } 735 736 /* 737 * Detach interface. 738 */ 739 static int 740 fxp_detach(device_t dev) 741 { 742 struct fxp_softc *sc = device_get_softc(dev); 743 744 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 745 746 /* 747 * Stop DMA and drop transmit queue. 748 */ 749 fxp_stop(sc); 750 751 /* 752 * Disable interrupts. 753 * 754 * NOTE: This should be done after fxp_stop(), because software 755 * resetting in fxp_stop() may leave interrupts turned on. 756 */ 757 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 758 759 /* 760 * Free all media structures. 761 */ 762 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 763 ifmedia_removeall(&sc->sc_media); 764 765 if (sc->ih) 766 bus_teardown_intr(dev, sc->irq, sc->ih); 767 768 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 769 770 /* 771 * Close down routes etc. 772 */ 773 ether_ifdetach(&sc->arpcom.ac_if); 774 775 /* Release our allocated resources. */ 776 fxp_release(dev); 777 778 return (0); 779 } 780 781 /* 782 * Device shutdown routine. Called at system shutdown after sync. The 783 * main purpose of this routine is to shut off receiver DMA so that 784 * kernel memory doesn't get clobbered during warmboot. 785 */ 786 static int 787 fxp_shutdown(device_t dev) 788 { 789 struct fxp_softc *sc = device_get_softc(dev); 790 struct ifnet *ifp = &sc->arpcom.ac_if; 791 792 lwkt_serialize_enter(ifp->if_serializer); 793 /* 794 * Make sure that DMA is disabled prior to reboot. Not doing 795 * do could allow DMA to corrupt kernel memory during the 796 * reboot before the driver initializes. 797 */ 798 fxp_stop(sc); 799 lwkt_serialize_exit(ifp->if_serializer); 800 return (0); 801 } 802 803 /* 804 * Device suspend routine. Stop the interface and save some PCI 805 * settings in case the BIOS doesn't restore them properly on 806 * resume. 807 */ 808 static int 809 fxp_suspend(device_t dev) 810 { 811 struct fxp_softc *sc = device_get_softc(dev); 812 int i; 813 814 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 815 816 fxp_stop(sc); 817 818 for (i = 0; i < 5; i++) 819 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 820 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 821 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 822 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 823 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 824 825 sc->suspended = 1; 826 827 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 828 return (0); 829 } 830 831 /* 832 * Device resume routine. Restore some PCI settings in case the BIOS 833 * doesn't, re-enable busmastering, and restart the interface if 834 * appropriate. 835 */ 836 static int 837 fxp_resume(device_t dev) 838 { 839 struct fxp_softc *sc = device_get_softc(dev); 840 struct ifnet *ifp = &sc->arpcom.ac_if; 841 int i; 842 843 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 844 845 fxp_powerstate_d0(dev); 846 847 /* better way to do this? */ 848 for (i = 0; i < 5; i++) 849 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 850 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 851 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 852 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 853 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 854 855 /* reenable busmastering and memory space */ 856 pci_enable_busmaster(dev); 857 pci_enable_io(dev, SYS_RES_MEMORY); 858 859 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 860 DELAY(10); 861 862 /* reinitialize interface if necessary */ 863 if (ifp->if_flags & IFF_UP) 864 fxp_init(sc); 865 866 sc->suspended = 0; 867 868 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 869 return (0); 870 } 871 872 static void 873 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 874 { 875 u_int16_t reg; 876 int x; 877 878 /* 879 * Shift in data. 880 */ 881 for (x = 1 << (length - 1); x; x >>= 1) { 882 if (data & x) 883 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 884 else 885 reg = FXP_EEPROM_EECS; 886 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 887 DELAY(1); 888 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 889 DELAY(1); 890 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 891 DELAY(1); 892 } 893 } 894 895 /* 896 * Read from the serial EEPROM. Basically, you manually shift in 897 * the read opcode (one bit at a time) and then shift in the address, 898 * and then you shift out the data (all of this one bit at a time). 899 * The word size is 16 bits, so you have to provide the address for 900 * every 16 bits of data. 901 */ 902 static u_int16_t 903 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 904 { 905 u_int16_t reg, data; 906 int x; 907 908 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 909 /* 910 * Shift in read opcode. 911 */ 912 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 913 /* 914 * Shift in address. 915 */ 916 data = 0; 917 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 918 if (offset & x) 919 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 920 else 921 reg = FXP_EEPROM_EECS; 922 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 923 DELAY(1); 924 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 925 DELAY(1); 926 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 927 DELAY(1); 928 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 929 data++; 930 if (autosize && reg == 0) { 931 sc->eeprom_size = data; 932 break; 933 } 934 } 935 /* 936 * Shift out data. 937 */ 938 data = 0; 939 reg = FXP_EEPROM_EECS; 940 for (x = 1 << 15; x; x >>= 1) { 941 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 942 DELAY(1); 943 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 944 data |= x; 945 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 946 DELAY(1); 947 } 948 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 949 DELAY(1); 950 951 return (data); 952 } 953 954 static void 955 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 956 { 957 int i; 958 959 /* 960 * Erase/write enable. 961 */ 962 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 963 fxp_eeprom_shiftin(sc, 0x4, 3); 964 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 965 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 966 DELAY(1); 967 /* 968 * Shift in write opcode, address, data. 969 */ 970 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 971 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 972 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 973 fxp_eeprom_shiftin(sc, data, 16); 974 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 975 DELAY(1); 976 /* 977 * Wait for EEPROM to finish up. 978 */ 979 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 980 DELAY(1); 981 for (i = 0; i < 1000; i++) { 982 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 983 break; 984 DELAY(50); 985 } 986 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 987 DELAY(1); 988 /* 989 * Erase/write disable. 990 */ 991 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 992 fxp_eeprom_shiftin(sc, 0x4, 3); 993 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 994 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 995 DELAY(1); 996 } 997 998 /* 999 * From NetBSD: 1000 * 1001 * Figure out EEPROM size. 1002 * 1003 * 559's can have either 64-word or 256-word EEPROMs, the 558 1004 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1005 * talks about the existance of 16 to 256 word EEPROMs. 1006 * 1007 * The only known sizes are 64 and 256, where the 256 version is used 1008 * by CardBus cards to store CIS information. 1009 * 1010 * The address is shifted in msb-to-lsb, and after the last 1011 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1012 * after which follows the actual data. We try to detect this zero, by 1013 * probing the data-out bit in the EEPROM control register just after 1014 * having shifted in a bit. If the bit is zero, we assume we've 1015 * shifted enough address bits. The data-out should be tri-state, 1016 * before this, which should translate to a logical one. 1017 */ 1018 static void 1019 fxp_autosize_eeprom(struct fxp_softc *sc) 1020 { 1021 1022 /* guess maximum size of 256 words */ 1023 sc->eeprom_size = 8; 1024 1025 /* autosize */ 1026 fxp_eeprom_getword(sc, 0, 1); 1027 } 1028 1029 static void 1030 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1031 { 1032 int i; 1033 1034 for (i = 0; i < words; i++) 1035 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1036 } 1037 1038 static void 1039 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1040 { 1041 int i; 1042 1043 for (i = 0; i < words; i++) 1044 fxp_eeprom_putword(sc, offset + i, data[i]); 1045 } 1046 1047 /* 1048 * Start packet transmission on the interface. 1049 */ 1050 static void 1051 fxp_start(struct ifnet *ifp) 1052 { 1053 struct fxp_softc *sc = ifp->if_softc; 1054 struct fxp_cb_tx *txp; 1055 1056 /* 1057 * See if we need to suspend xmit until the multicast filter 1058 * has been reprogrammed (which can only be done at the head 1059 * of the command chain). 1060 */ 1061 if (sc->need_mcsetup) { 1062 ifq_purge(&ifp->if_snd); 1063 return; 1064 } 1065 1066 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1067 return; 1068 1069 txp = NULL; 1070 1071 /* 1072 * We're finished if there is nothing more to add to the list or if 1073 * we're all filled up with buffers to transmit. 1074 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1075 * a NOP command when needed. 1076 */ 1077 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_USABLE_TXCB) { 1078 struct mbuf *m, *mb_head; 1079 int segment, ntries = 0; 1080 1081 /* 1082 * Grab a packet to transmit. 1083 */ 1084 mb_head = ifq_dequeue(&ifp->if_snd, NULL); 1085 if (mb_head == NULL) 1086 break; 1087 tbdinit: 1088 /* 1089 * Make sure that the packet fits into one TX desc 1090 */ 1091 segment = 0; 1092 for (m = mb_head; m != NULL; m = m->m_next) { 1093 if (m->m_len != 0) { 1094 ++segment; 1095 if (segment >= FXP_NTXSEG) 1096 break; 1097 } 1098 } 1099 if (segment >= FXP_NTXSEG) { 1100 struct mbuf *mn; 1101 1102 if (ntries) { 1103 /* 1104 * Packet is excessively fragmented, 1105 * and will never fit into one TX 1106 * desc. Give it up. 1107 */ 1108 m_freem(mb_head); 1109 ifp->if_oerrors++; 1110 continue; 1111 } 1112 1113 mn = m_dup(mb_head, MB_DONTWAIT); 1114 if (mn == NULL) { 1115 m_freem(mb_head); 1116 ifp->if_oerrors++; 1117 continue; 1118 } 1119 1120 m_freem(mb_head); 1121 mb_head = mn; 1122 ntries = 1; 1123 goto tbdinit; 1124 } 1125 1126 /* 1127 * Get pointer to next available tx desc. 1128 */ 1129 txp = sc->cbl_last->next; 1130 1131 /* 1132 * Go through each of the mbufs in the chain and initialize 1133 * the transmit buffer descriptors with the physical address 1134 * and size of the mbuf. 1135 */ 1136 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1137 if (m->m_len != 0) { 1138 KKASSERT(segment < FXP_NTXSEG); 1139 1140 txp->tbd[segment].tb_addr = 1141 vtophys(mtod(m, vm_offset_t)); 1142 txp->tbd[segment].tb_size = m->m_len; 1143 segment++; 1144 } 1145 } 1146 KKASSERT(m == NULL); 1147 1148 txp->tbd_number = segment; 1149 txp->mb_head = mb_head; 1150 txp->cb_status = 0; 1151 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1152 txp->cb_command = 1153 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1154 FXP_CB_COMMAND_S; 1155 } else { 1156 txp->cb_command = 1157 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1158 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1159 } 1160 txp->tx_threshold = tx_threshold; 1161 1162 /* 1163 * Advance the end of list forward. 1164 */ 1165 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1166 sc->cbl_last = txp; 1167 1168 /* 1169 * Advance the beginning of the list forward if there are 1170 * no other packets queued (when nothing is queued, cbl_first 1171 * sits on the last TxCB that was sent out). 1172 */ 1173 if (sc->tx_queued == 0) 1174 sc->cbl_first = txp; 1175 1176 sc->tx_queued++; 1177 /* 1178 * Set a 5 second timer just in case we don't hear 1179 * from the card again. 1180 */ 1181 ifp->if_timer = 5; 1182 1183 BPF_MTAP(ifp, mb_head); 1184 } 1185 1186 if (sc->tx_queued >= FXP_USABLE_TXCB) 1187 ifp->if_flags |= IFF_OACTIVE; 1188 1189 /* 1190 * We're finished. If we added to the list, issue a RESUME to get DMA 1191 * going again if suspended. 1192 */ 1193 if (txp != NULL) { 1194 fxp_scb_wait(sc); 1195 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1196 } 1197 } 1198 1199 #ifdef DEVICE_POLLING 1200 1201 static void 1202 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1203 { 1204 struct fxp_softc *sc = ifp->if_softc; 1205 u_int8_t statack; 1206 1207 switch(cmd) { 1208 case POLL_REGISTER: 1209 /* disable interrupts */ 1210 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1211 break; 1212 case POLL_DEREGISTER: 1213 /* enable interrupts */ 1214 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1215 break; 1216 default: 1217 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1218 FXP_SCB_STATACK_FR; 1219 if (cmd == POLL_AND_CHECK_STATUS) { 1220 u_int8_t tmp; 1221 1222 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1223 if (tmp == 0xff || tmp == 0) 1224 return; /* nothing to do */ 1225 tmp &= ~statack; 1226 /* ack what we can */ 1227 if (tmp != 0) 1228 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1229 statack |= tmp; 1230 } 1231 fxp_intr_body(sc, statack, count); 1232 break; 1233 } 1234 } 1235 1236 #endif /* DEVICE_POLLING */ 1237 1238 /* 1239 * Process interface interrupts. 1240 */ 1241 static void 1242 fxp_intr(void *xsc) 1243 { 1244 struct fxp_softc *sc = xsc; 1245 u_int8_t statack; 1246 1247 if (sc->suspended) { 1248 return; 1249 } 1250 1251 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1252 /* 1253 * It should not be possible to have all bits set; the 1254 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1255 * all bits are set, this may indicate that the card has 1256 * been physically ejected, so ignore it. 1257 */ 1258 if (statack == 0xff) 1259 return; 1260 1261 /* 1262 * First ACK all the interrupts in this pass. 1263 */ 1264 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1265 fxp_intr_body(sc, statack, -1); 1266 } 1267 } 1268 1269 static void 1270 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1271 { 1272 struct ifnet *ifp = &sc->arpcom.ac_if; 1273 struct mbuf *m; 1274 struct fxp_rfa *rfa; 1275 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1276 #ifdef ETHER_INPUT_CHAIN 1277 struct mbuf_chain chain[MAXCPU]; 1278 #endif 1279 1280 if (rnr) 1281 fxp_rnr++; 1282 #ifdef DEVICE_POLLING 1283 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1284 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1285 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1286 rnr = 1; 1287 } 1288 #endif 1289 1290 /* 1291 * Free any finished transmit mbuf chains. 1292 * 1293 * Handle the CNA event likt a CXTNO event. It used to 1294 * be that this event (control unit not ready) was not 1295 * encountered, but it is now with the SMPng modifications. 1296 * The exact sequence of events that occur when the interface 1297 * is brought up are different now, and if this event 1298 * goes unhandled, the configuration/rxfilter setup sequence 1299 * can stall for several seconds. The result is that no 1300 * packets go out onto the wire for about 5 to 10 seconds 1301 * after the interface is ifconfig'ed for the first time. 1302 */ 1303 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1304 struct fxp_cb_tx *txp; 1305 1306 for (txp = sc->cbl_first; sc->tx_queued && 1307 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1308 txp = txp->next) { 1309 if ((m = txp->mb_head) != NULL) { 1310 txp->mb_head = NULL; 1311 sc->tx_queued--; 1312 m_freem(m); 1313 } else { 1314 sc->tx_queued--; 1315 } 1316 } 1317 sc->cbl_first = txp; 1318 1319 if (sc->tx_queued < FXP_USABLE_TXCB) 1320 ifp->if_flags &= ~IFF_OACTIVE; 1321 1322 if (sc->tx_queued == 0) { 1323 ifp->if_timer = 0; 1324 if (sc->need_mcsetup) 1325 fxp_mc_setup(sc); 1326 } 1327 1328 /* 1329 * Try to start more packets transmitting. 1330 */ 1331 if (!ifq_is_empty(&ifp->if_snd)) 1332 if_devstart(ifp); 1333 } 1334 1335 /* 1336 * Just return if nothing happened on the receive side. 1337 */ 1338 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1339 return; 1340 1341 #ifdef ETHER_INPUT_CHAIN 1342 ether_input_chain_init(chain); 1343 #endif 1344 1345 /* 1346 * Process receiver interrupts. If a no-resource (RNR) 1347 * condition exists, get whatever packets we can and 1348 * re-start the receiver. 1349 * 1350 * When using polling, we do not process the list to completion, 1351 * so when we get an RNR interrupt we must defer the restart 1352 * until we hit the last buffer with the C bit set. 1353 * If we run out of cycles and rfa_headm has the C bit set, 1354 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1355 * that the info will be used in the subsequent polling cycle. 1356 */ 1357 for (;;) { 1358 m = sc->rfa_headm; 1359 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1360 RFA_ALIGNMENT_FUDGE); 1361 1362 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1363 if (count >= 0 && count-- == 0) { 1364 if (rnr) { 1365 /* Defer RNR processing until the next time. */ 1366 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1367 rnr = 0; 1368 } 1369 break; 1370 } 1371 #endif /* DEVICE_POLLING */ 1372 1373 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1374 break; 1375 1376 /* 1377 * Remove first packet from the chain. 1378 */ 1379 sc->rfa_headm = m->m_next; 1380 m->m_next = NULL; 1381 1382 /* 1383 * Add a new buffer to the receive chain. 1384 * If this fails, the old buffer is recycled 1385 * instead. 1386 */ 1387 if (fxp_add_rfabuf(sc, m) == 0) { 1388 int total_len; 1389 1390 /* 1391 * Fetch packet length (the top 2 bits of 1392 * actual_size are flags set by the controller 1393 * upon completion), and drop the packet in case 1394 * of bogus length or CRC errors. 1395 */ 1396 total_len = rfa->actual_size & 0x3fff; 1397 if (total_len < sizeof(struct ether_header) || 1398 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1399 sizeof(struct fxp_rfa) || 1400 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1401 m_freem(m); 1402 continue; 1403 } 1404 m->m_pkthdr.len = m->m_len = total_len; 1405 #ifdef ETHER_INPUT_CHAIN 1406 #ifdef ETHER_INPUT2 1407 ether_input_chain2(ifp, m, chain); 1408 #else 1409 ether_input_chain(ifp, m, chain); 1410 #endif 1411 #else 1412 ifp->if_input(ifp, m); 1413 #endif 1414 } 1415 } 1416 1417 #ifdef ETHER_INPUT_CHAIN 1418 ether_input_dispatch(chain); 1419 #endif 1420 1421 if (rnr) { 1422 fxp_scb_wait(sc); 1423 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1424 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1425 RFA_ALIGNMENT_FUDGE); 1426 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1427 } 1428 } 1429 1430 /* 1431 * Update packet in/out/collision statistics. The i82557 doesn't 1432 * allow you to access these counters without doing a fairly 1433 * expensive DMA to get _all_ of the statistics it maintains, so 1434 * we do this operation here only once per second. The statistics 1435 * counters in the kernel are updated from the previous dump-stats 1436 * DMA and then a new dump-stats DMA is started. The on-chip 1437 * counters are zeroed when the DMA completes. If we can't start 1438 * the DMA immediately, we don't wait - we just prepare to read 1439 * them again next time. 1440 */ 1441 static void 1442 fxp_tick(void *xsc) 1443 { 1444 struct fxp_softc *sc = xsc; 1445 struct ifnet *ifp = &sc->arpcom.ac_if; 1446 struct fxp_stats *sp = sc->fxp_stats; 1447 struct fxp_cb_tx *txp; 1448 struct mbuf *m; 1449 1450 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1451 1452 ifp->if_opackets += sp->tx_good; 1453 ifp->if_collisions += sp->tx_total_collisions; 1454 if (sp->rx_good) { 1455 ifp->if_ipackets += sp->rx_good; 1456 sc->rx_idle_secs = 0; 1457 } else { 1458 /* 1459 * Receiver's been idle for another second. 1460 */ 1461 sc->rx_idle_secs++; 1462 } 1463 ifp->if_ierrors += 1464 sp->rx_crc_errors + 1465 sp->rx_alignment_errors + 1466 sp->rx_rnr_errors + 1467 sp->rx_overrun_errors; 1468 /* 1469 * If any transmit underruns occured, bump up the transmit 1470 * threshold by another 512 bytes (64 * 8). 1471 */ 1472 if (sp->tx_underruns) { 1473 ifp->if_oerrors += sp->tx_underruns; 1474 if (tx_threshold < 192) 1475 tx_threshold += 64; 1476 } 1477 1478 /* 1479 * Release any xmit buffers that have completed DMA. This isn't 1480 * strictly necessary to do here, but it's advantagous for mbufs 1481 * with external storage to be released in a timely manner rather 1482 * than being defered for a potentially long time. This limits 1483 * the delay to a maximum of one second. 1484 */ 1485 for (txp = sc->cbl_first; sc->tx_queued && 1486 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1487 txp = txp->next) { 1488 if ((m = txp->mb_head) != NULL) { 1489 txp->mb_head = NULL; 1490 sc->tx_queued--; 1491 m_freem(m); 1492 } else { 1493 sc->tx_queued--; 1494 } 1495 } 1496 sc->cbl_first = txp; 1497 1498 if (sc->tx_queued < FXP_USABLE_TXCB) 1499 ifp->if_flags &= ~IFF_OACTIVE; 1500 if (sc->tx_queued == 0) 1501 ifp->if_timer = 0; 1502 1503 /* 1504 * Try to start more packets transmitting. 1505 */ 1506 if (!ifq_is_empty(&ifp->if_snd)) 1507 if_devstart(ifp); 1508 1509 /* 1510 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1511 * then assume the receiver has locked up and attempt to clear 1512 * the condition by reprogramming the multicast filter. This is 1513 * a work-around for a bug in the 82557 where the receiver locks 1514 * up if it gets certain types of garbage in the syncronization 1515 * bits prior to the packet header. This bug is supposed to only 1516 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1517 * mode as well (perhaps due to a 10/100 speed transition). 1518 */ 1519 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1520 sc->rx_idle_secs = 0; 1521 fxp_mc_setup(sc); 1522 } 1523 /* 1524 * If there is no pending command, start another stats 1525 * dump. Otherwise punt for now. 1526 */ 1527 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1528 /* 1529 * Start another stats dump. 1530 */ 1531 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1532 } else { 1533 /* 1534 * A previous command is still waiting to be accepted. 1535 * Just zero our copy of the stats and wait for the 1536 * next timer event to update them. 1537 */ 1538 sp->tx_good = 0; 1539 sp->tx_underruns = 0; 1540 sp->tx_total_collisions = 0; 1541 1542 sp->rx_good = 0; 1543 sp->rx_crc_errors = 0; 1544 sp->rx_alignment_errors = 0; 1545 sp->rx_rnr_errors = 0; 1546 sp->rx_overrun_errors = 0; 1547 } 1548 if (sc->miibus != NULL) 1549 mii_tick(device_get_softc(sc->miibus)); 1550 /* 1551 * Schedule another timeout one second from now. 1552 */ 1553 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1554 1555 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1556 } 1557 1558 /* 1559 * Stop the interface. Cancels the statistics updater and resets 1560 * the interface. 1561 */ 1562 static void 1563 fxp_stop(struct fxp_softc *sc) 1564 { 1565 struct ifnet *ifp = &sc->arpcom.ac_if; 1566 struct fxp_cb_tx *txp; 1567 int i; 1568 1569 ASSERT_SERIALIZED(ifp->if_serializer); 1570 1571 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1572 ifp->if_timer = 0; 1573 1574 /* 1575 * Cancel stats updater. 1576 */ 1577 callout_stop(&sc->fxp_stat_timer); 1578 1579 /* 1580 * Issue software reset, which also unloads the microcode. 1581 */ 1582 sc->flags &= ~FXP_FLAG_UCODE; 1583 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1584 DELAY(50); 1585 1586 /* 1587 * Release any xmit buffers. 1588 */ 1589 txp = sc->cbl_base; 1590 if (txp != NULL) { 1591 for (i = 0; i < FXP_NTXCB; i++) { 1592 if (txp[i].mb_head != NULL) { 1593 m_freem(txp[i].mb_head); 1594 txp[i].mb_head = NULL; 1595 } 1596 } 1597 } 1598 sc->tx_queued = 0; 1599 1600 /* 1601 * Free all the receive buffers then reallocate/reinitialize 1602 */ 1603 if (sc->rfa_headm != NULL) 1604 m_freem(sc->rfa_headm); 1605 sc->rfa_headm = NULL; 1606 sc->rfa_tailm = NULL; 1607 for (i = 0; i < FXP_NRFABUFS; i++) { 1608 if (fxp_add_rfabuf(sc, NULL) != 0) { 1609 /* 1610 * This "can't happen" - we're at splimp() 1611 * and we just freed all the buffers we need 1612 * above. 1613 */ 1614 panic("fxp_stop: no buffers!"); 1615 } 1616 } 1617 } 1618 1619 /* 1620 * Watchdog/transmission transmit timeout handler. Called when a 1621 * transmission is started on the interface, but no interrupt is 1622 * received before the timeout. This usually indicates that the 1623 * card has wedged for some reason. 1624 */ 1625 static void 1626 fxp_watchdog(struct ifnet *ifp) 1627 { 1628 if_printf(ifp, "device timeout\n"); 1629 ifp->if_oerrors++; 1630 fxp_init(ifp->if_softc); 1631 } 1632 1633 static void 1634 fxp_init(void *xsc) 1635 { 1636 struct fxp_softc *sc = xsc; 1637 struct ifnet *ifp = &sc->arpcom.ac_if; 1638 struct fxp_cb_config *cbp; 1639 struct fxp_cb_ias *cb_ias; 1640 struct fxp_cb_tx *txp; 1641 struct fxp_cb_mcs *mcsp; 1642 int i, prm; 1643 1644 /* 1645 * Cancel any pending I/O 1646 */ 1647 fxp_stop(sc); 1648 1649 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1650 1651 /* 1652 * Initialize base of CBL and RFA memory. Loading with zero 1653 * sets it up for regular linear addressing. 1654 */ 1655 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1656 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1657 1658 fxp_scb_wait(sc); 1659 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1660 1661 /* 1662 * Initialize base of dump-stats buffer. 1663 */ 1664 fxp_scb_wait(sc); 1665 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1666 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1667 1668 /* 1669 * Attempt to load microcode if requested. 1670 */ 1671 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1672 fxp_load_ucode(sc); 1673 1674 /* 1675 * Initialize the multicast address list. 1676 */ 1677 if (fxp_mc_addrs(sc)) { 1678 mcsp = sc->mcsp; 1679 mcsp->cb_status = 0; 1680 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1681 mcsp->link_addr = -1; 1682 /* 1683 * Start the multicast setup command. 1684 */ 1685 fxp_scb_wait(sc); 1686 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1687 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1688 /* ...and wait for it to complete. */ 1689 fxp_dma_wait(&mcsp->cb_status, sc); 1690 } 1691 1692 /* 1693 * We temporarily use memory that contains the TxCB list to 1694 * construct the config CB. The TxCB list memory is rebuilt 1695 * later. 1696 */ 1697 cbp = (struct fxp_cb_config *) sc->cbl_base; 1698 1699 /* 1700 * This bcopy is kind of disgusting, but there are a bunch of must be 1701 * zero and must be one bits in this structure and this is the easiest 1702 * way to initialize them all to proper values. 1703 */ 1704 bcopy(fxp_cb_config_template, 1705 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1706 sizeof(fxp_cb_config_template)); 1707 1708 cbp->cb_status = 0; 1709 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1710 cbp->link_addr = -1; /* (no) next command */ 1711 cbp->byte_count = 22; /* (22) bytes to config */ 1712 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1713 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1714 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1715 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1716 cbp->type_enable = 0; /* actually reserved */ 1717 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1718 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1719 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1720 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1721 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1722 cbp->late_scb = 0; /* (don't) defer SCB update */ 1723 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1724 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1725 cbp->ci_int = 1; /* interrupt on CU idle */ 1726 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1727 cbp->ext_stats_dis = 1; /* disable extended counters */ 1728 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1729 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1730 cbp->disc_short_rx = !prm; /* discard short packets */ 1731 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1732 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1733 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1734 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1735 cbp->csma_dis = 0; /* (don't) disable link */ 1736 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1737 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1738 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1739 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1740 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1741 cbp->nsai = 1; /* (don't) disable source addr insert */ 1742 cbp->preamble_length = 2; /* (7 byte) preamble */ 1743 cbp->loopback = 0; /* (don't) loopback */ 1744 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1745 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1746 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1747 cbp->promiscuous = prm; /* promiscuous mode */ 1748 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1749 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1750 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1751 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1752 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1753 1754 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1755 cbp->padding = 1; /* (do) pad short tx packets */ 1756 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1757 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1758 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1759 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1760 /* must set wake_en in PMCSR also */ 1761 cbp->force_fdx = 0; /* (don't) force full duplex */ 1762 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1763 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1764 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1765 1766 if (sc->revision == FXP_REV_82557) { 1767 /* 1768 * The 82557 has no hardware flow control, the values 1769 * below are the defaults for the chip. 1770 */ 1771 cbp->fc_delay_lsb = 0; 1772 cbp->fc_delay_msb = 0x40; 1773 cbp->pri_fc_thresh = 3; 1774 cbp->tx_fc_dis = 0; 1775 cbp->rx_fc_restop = 0; 1776 cbp->rx_fc_restart = 0; 1777 cbp->fc_filter = 0; 1778 cbp->pri_fc_loc = 1; 1779 } else { 1780 cbp->fc_delay_lsb = 0x1f; 1781 cbp->fc_delay_msb = 0x01; 1782 cbp->pri_fc_thresh = 3; 1783 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1784 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1785 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1786 cbp->fc_filter = !prm; /* drop FC frames to host */ 1787 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1788 } 1789 1790 /* 1791 * Start the config command/DMA. 1792 */ 1793 fxp_scb_wait(sc); 1794 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1795 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1796 /* ...and wait for it to complete. */ 1797 fxp_dma_wait(&cbp->cb_status, sc); 1798 1799 /* 1800 * Now initialize the station address. Temporarily use the TxCB 1801 * memory area like we did above for the config CB. 1802 */ 1803 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1804 cb_ias->cb_status = 0; 1805 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1806 cb_ias->link_addr = -1; 1807 bcopy(sc->arpcom.ac_enaddr, 1808 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1809 sizeof(sc->arpcom.ac_enaddr)); 1810 1811 /* 1812 * Start the IAS (Individual Address Setup) command/DMA. 1813 */ 1814 fxp_scb_wait(sc); 1815 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1816 /* ...and wait for it to complete. */ 1817 fxp_dma_wait(&cb_ias->cb_status, sc); 1818 1819 /* 1820 * Initialize transmit control block (TxCB) list. 1821 */ 1822 1823 txp = sc->cbl_base; 1824 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1825 for (i = 0; i < FXP_NTXCB; i++) { 1826 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1827 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1828 txp[i].link_addr = 1829 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1830 if (sc->flags & FXP_FLAG_EXT_TXCB) 1831 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1832 else 1833 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1834 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1835 } 1836 /* 1837 * Set the suspend flag on the first TxCB and start the control 1838 * unit. It will execute the NOP and then suspend. 1839 */ 1840 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1841 sc->cbl_first = sc->cbl_last = txp; 1842 sc->tx_queued = 1; 1843 1844 fxp_scb_wait(sc); 1845 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1846 1847 /* 1848 * Initialize receiver buffer area - RFA. 1849 */ 1850 fxp_scb_wait(sc); 1851 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1852 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1853 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1854 1855 /* 1856 * Set current media. 1857 */ 1858 if (sc->miibus != NULL) 1859 mii_mediachg(device_get_softc(sc->miibus)); 1860 1861 ifp->if_flags |= IFF_RUNNING; 1862 ifp->if_flags &= ~IFF_OACTIVE; 1863 1864 /* 1865 * Enable interrupts. 1866 */ 1867 #ifdef DEVICE_POLLING 1868 /* 1869 * ... but only do that if we are not polling. And because (presumably) 1870 * the default is interrupts on, we need to disable them explicitly! 1871 */ 1872 if ( ifp->if_flags & IFF_POLLING ) 1873 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1874 else 1875 #endif /* DEVICE_POLLING */ 1876 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1877 1878 /* 1879 * Start stats updater. 1880 */ 1881 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1882 } 1883 1884 static int 1885 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1886 { 1887 1888 return (0); 1889 } 1890 1891 static void 1892 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1893 { 1894 1895 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1896 } 1897 1898 /* 1899 * Change media according to request. 1900 */ 1901 static int 1902 fxp_ifmedia_upd(struct ifnet *ifp) 1903 { 1904 struct fxp_softc *sc = ifp->if_softc; 1905 struct mii_data *mii; 1906 1907 mii = device_get_softc(sc->miibus); 1908 mii_mediachg(mii); 1909 return (0); 1910 } 1911 1912 /* 1913 * Notify the world which media we're using. 1914 */ 1915 static void 1916 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1917 { 1918 struct fxp_softc *sc = ifp->if_softc; 1919 struct mii_data *mii; 1920 1921 mii = device_get_softc(sc->miibus); 1922 mii_pollstat(mii); 1923 ifmr->ifm_active = mii->mii_media_active; 1924 ifmr->ifm_status = mii->mii_media_status; 1925 1926 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1927 sc->cu_resume_bug = 1; 1928 else 1929 sc->cu_resume_bug = 0; 1930 } 1931 1932 /* 1933 * Add a buffer to the end of the RFA buffer list. 1934 * Return 0 if successful, 1 for failure. A failure results in 1935 * adding the 'oldm' (if non-NULL) on to the end of the list - 1936 * tossing out its old contents and recycling it. 1937 * The RFA struct is stuck at the beginning of mbuf cluster and the 1938 * data pointer is fixed up to point just past it. 1939 */ 1940 static int 1941 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1942 { 1943 u_int32_t v; 1944 struct mbuf *m; 1945 struct fxp_rfa *rfa, *p_rfa; 1946 1947 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1948 if (m == NULL) { /* try to recycle the old mbuf instead */ 1949 if (oldm == NULL) 1950 return 1; 1951 m = oldm; 1952 m->m_data = m->m_ext.ext_buf; 1953 } 1954 1955 /* 1956 * Move the data pointer up so that the incoming data packet 1957 * will be 32-bit aligned. 1958 */ 1959 m->m_data += RFA_ALIGNMENT_FUDGE; 1960 1961 /* 1962 * Get a pointer to the base of the mbuf cluster and move 1963 * data start past it. 1964 */ 1965 rfa = mtod(m, struct fxp_rfa *); 1966 m->m_data += sizeof(struct fxp_rfa); 1967 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1968 1969 /* 1970 * Initialize the rest of the RFA. Note that since the RFA 1971 * is misaligned, we cannot store values directly. Instead, 1972 * we use an optimized, inline copy. 1973 */ 1974 1975 rfa->rfa_status = 0; 1976 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1977 rfa->actual_size = 0; 1978 1979 v = -1; 1980 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1981 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1982 1983 /* 1984 * If there are other buffers already on the list, attach this 1985 * one to the end by fixing up the tail to point to this one. 1986 */ 1987 if (sc->rfa_headm != NULL) { 1988 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1989 RFA_ALIGNMENT_FUDGE); 1990 sc->rfa_tailm->m_next = m; 1991 v = vtophys(rfa); 1992 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1993 p_rfa->rfa_control = 0; 1994 } else { 1995 sc->rfa_headm = m; 1996 } 1997 sc->rfa_tailm = m; 1998 1999 return (m == oldm); 2000 } 2001 2002 static int 2003 fxp_miibus_readreg(device_t dev, int phy, int reg) 2004 { 2005 struct fxp_softc *sc = device_get_softc(dev); 2006 int count = 10000; 2007 int value; 2008 2009 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2010 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2011 2012 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2013 && count--) 2014 DELAY(10); 2015 2016 if (count <= 0) 2017 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2018 2019 return (value & 0xffff); 2020 } 2021 2022 static void 2023 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2024 { 2025 struct fxp_softc *sc = device_get_softc(dev); 2026 int count = 10000; 2027 2028 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2029 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2030 (value & 0xffff)); 2031 2032 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2033 count--) 2034 DELAY(10); 2035 2036 if (count <= 0) 2037 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2038 } 2039 2040 static int 2041 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2042 { 2043 struct fxp_softc *sc = ifp->if_softc; 2044 struct ifreq *ifr = (struct ifreq *)data; 2045 struct mii_data *mii; 2046 int error = 0; 2047 2048 switch (command) { 2049 2050 case SIOCSIFFLAGS: 2051 if (ifp->if_flags & IFF_ALLMULTI) 2052 sc->flags |= FXP_FLAG_ALL_MCAST; 2053 else 2054 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2055 2056 /* 2057 * If interface is marked up and not running, then start it. 2058 * If it is marked down and running, stop it. 2059 * XXX If it's up then re-initialize it. This is so flags 2060 * such as IFF_PROMISC are handled. 2061 */ 2062 if (ifp->if_flags & IFF_UP) { 2063 fxp_init(sc); 2064 } else { 2065 if (ifp->if_flags & IFF_RUNNING) 2066 fxp_stop(sc); 2067 } 2068 break; 2069 2070 case SIOCADDMULTI: 2071 case SIOCDELMULTI: 2072 if (ifp->if_flags & IFF_ALLMULTI) 2073 sc->flags |= FXP_FLAG_ALL_MCAST; 2074 else 2075 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2076 /* 2077 * Multicast list has changed; set the hardware filter 2078 * accordingly. 2079 */ 2080 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2081 fxp_mc_setup(sc); 2082 /* 2083 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2084 * again rather than else {}. 2085 */ 2086 if (sc->flags & FXP_FLAG_ALL_MCAST) 2087 fxp_init(sc); 2088 error = 0; 2089 break; 2090 2091 case SIOCSIFMEDIA: 2092 case SIOCGIFMEDIA: 2093 if (sc->miibus != NULL) { 2094 mii = device_get_softc(sc->miibus); 2095 error = ifmedia_ioctl(ifp, ifr, 2096 &mii->mii_media, command); 2097 } else { 2098 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2099 } 2100 break; 2101 2102 default: 2103 error = ether_ioctl(ifp, command, data); 2104 break; 2105 } 2106 return (error); 2107 } 2108 2109 /* 2110 * Fill in the multicast address list and return number of entries. 2111 */ 2112 static int 2113 fxp_mc_addrs(struct fxp_softc *sc) 2114 { 2115 struct fxp_cb_mcs *mcsp = sc->mcsp; 2116 struct ifnet *ifp = &sc->arpcom.ac_if; 2117 struct ifmultiaddr *ifma; 2118 int nmcasts; 2119 2120 nmcasts = 0; 2121 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2122 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2123 if (ifma->ifma_addr->sa_family != AF_LINK) 2124 continue; 2125 if (nmcasts >= MAXMCADDR) { 2126 sc->flags |= FXP_FLAG_ALL_MCAST; 2127 nmcasts = 0; 2128 break; 2129 } 2130 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2131 (void *)(uintptr_t)(volatile void *) 2132 &sc->mcsp->mc_addr[nmcasts][0], 6); 2133 nmcasts++; 2134 } 2135 } 2136 mcsp->mc_cnt = nmcasts * 6; 2137 return (nmcasts); 2138 } 2139 2140 /* 2141 * Program the multicast filter. 2142 * 2143 * We have an artificial restriction that the multicast setup command 2144 * must be the first command in the chain, so we take steps to ensure 2145 * this. By requiring this, it allows us to keep up the performance of 2146 * the pre-initialized command ring (esp. link pointers) by not actually 2147 * inserting the mcsetup command in the ring - i.e. its link pointer 2148 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2149 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2150 * lead into the regular TxCB ring when it completes. 2151 * 2152 * This function must be called at splimp. 2153 */ 2154 static void 2155 fxp_mc_setup(struct fxp_softc *sc) 2156 { 2157 struct fxp_cb_mcs *mcsp = sc->mcsp; 2158 struct ifnet *ifp = &sc->arpcom.ac_if; 2159 int count; 2160 2161 /* 2162 * If there are queued commands, we must wait until they are all 2163 * completed. If we are already waiting, then add a NOP command 2164 * with interrupt option so that we're notified when all commands 2165 * have been completed - fxp_start() ensures that no additional 2166 * TX commands will be added when need_mcsetup is true. 2167 */ 2168 if (sc->tx_queued) { 2169 struct fxp_cb_tx *txp; 2170 2171 /* 2172 * need_mcsetup will be true if we are already waiting for the 2173 * NOP command to be completed (see below). In this case, bail. 2174 */ 2175 if (sc->need_mcsetup) 2176 return; 2177 sc->need_mcsetup = 1; 2178 2179 /* 2180 * Add a NOP command with interrupt so that we are notified 2181 * when all TX commands have been processed. 2182 */ 2183 txp = sc->cbl_last->next; 2184 txp->mb_head = NULL; 2185 txp->cb_status = 0; 2186 txp->cb_command = FXP_CB_COMMAND_NOP | 2187 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2188 /* 2189 * Advance the end of list forward. 2190 */ 2191 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2192 sc->cbl_last = txp; 2193 sc->tx_queued++; 2194 /* 2195 * Issue a resume in case the CU has just suspended. 2196 */ 2197 fxp_scb_wait(sc); 2198 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2199 /* 2200 * Set a 5 second timer just in case we don't hear from the 2201 * card again. 2202 */ 2203 ifp->if_timer = 5; 2204 2205 return; 2206 } 2207 sc->need_mcsetup = 0; 2208 2209 /* 2210 * Initialize multicast setup descriptor. 2211 */ 2212 mcsp->next = sc->cbl_base; 2213 mcsp->mb_head = NULL; 2214 mcsp->cb_status = 0; 2215 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2216 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2217 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2218 fxp_mc_addrs(sc); 2219 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2220 sc->tx_queued = 1; 2221 2222 /* 2223 * Wait until command unit is not active. This should never 2224 * be the case when nothing is queued, but make sure anyway. 2225 */ 2226 count = 100; 2227 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2228 FXP_SCB_CUS_ACTIVE && --count) 2229 DELAY(10); 2230 if (count == 0) { 2231 if_printf(&sc->arpcom.ac_if, "command queue timeout\n"); 2232 return; 2233 } 2234 2235 /* 2236 * Start the multicast setup command. 2237 */ 2238 fxp_scb_wait(sc); 2239 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2240 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2241 2242 ifp->if_timer = 2; 2243 return; 2244 } 2245 2246 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2247 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2248 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2249 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2250 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2251 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2252 2253 #define UCODE(x) x, sizeof(x) 2254 2255 struct ucode { 2256 u_int32_t revision; 2257 u_int32_t *ucode; 2258 int length; 2259 u_short int_delay_offset; 2260 u_short bundle_max_offset; 2261 } ucode_table[] = { 2262 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2263 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2264 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2265 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2266 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2267 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2268 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2269 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2270 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2271 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2272 { 0, NULL, 0, 0, 0 } 2273 }; 2274 2275 static void 2276 fxp_load_ucode(struct fxp_softc *sc) 2277 { 2278 struct ucode *uc; 2279 struct fxp_cb_ucode *cbp; 2280 2281 for (uc = ucode_table; uc->ucode != NULL; uc++) 2282 if (sc->revision == uc->revision) 2283 break; 2284 if (uc->ucode == NULL) 2285 return; 2286 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2287 cbp->cb_status = 0; 2288 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2289 cbp->link_addr = -1; /* (no) next command */ 2290 memcpy(cbp->ucode, uc->ucode, uc->length); 2291 if (uc->int_delay_offset) 2292 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2293 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2294 if (uc->bundle_max_offset) 2295 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2296 sc->tunable_bundle_max; 2297 /* 2298 * Download the ucode to the chip. 2299 */ 2300 fxp_scb_wait(sc); 2301 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2302 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2303 /* ...and wait for it to complete. */ 2304 fxp_dma_wait(&cbp->cb_status, sc); 2305 if_printf(&sc->arpcom.ac_if, 2306 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2307 sc->tunable_int_delay, 2308 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2309 sc->flags |= FXP_FLAG_UCODE; 2310 } 2311 2312 static int 2313 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2314 { 2315 int error, value; 2316 2317 value = *(int *)arg1; 2318 error = sysctl_handle_int(oidp, &value, 0, req); 2319 if (error || !req->newptr) 2320 return (error); 2321 if (value < low || value > high) 2322 return (EINVAL); 2323 *(int *)arg1 = value; 2324 return (0); 2325 } 2326 2327 /* 2328 * Interrupt delay is expressed in microseconds, a multiplier is used 2329 * to convert this to the appropriate clock ticks before using. 2330 */ 2331 static int 2332 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2333 { 2334 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2335 } 2336 2337 static int 2338 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2339 { 2340 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2341 } 2342