1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82541EI Gigabit Ethernet Controller 37 * 82541ER Gigabit Ethernet Controller 38 * 82541GI Gigabit Ethernet Controller 39 * 82541PI Gigabit Ethernet Controller 40 * 82547EI Gigabit Ethernet Controller 41 * 82547GI Gigabit Ethernet Controller 42 */ 43 44 #include "e1000_api.h" 45 46 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw); 47 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); 48 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw); 49 static s32 e1000_reset_hw_82541(struct e1000_hw *hw); 50 static s32 e1000_init_hw_82541(struct e1000_hw *hw); 51 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 52 u16 *duplex); 53 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); 54 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); 55 static s32 e1000_check_for_link_82541(struct e1000_hw *hw); 56 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); 57 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, 58 bool active); 59 static s32 e1000_setup_led_82541(struct e1000_hw *hw); 60 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw); 61 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); 62 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 63 bool link_up); 64 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw); 65 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw); 66 67 static const u16 e1000_igp_cable_length_table[] = 68 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 69 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 70 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 71 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 72 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 73 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 74 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 75 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 76 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ 77 (sizeof(e1000_igp_cable_length_table) / \ 78 sizeof(e1000_igp_cable_length_table[0])) 79 80 /** 81 * e1000_init_phy_params_82541 - Init PHY func ptrs. 82 * @hw: pointer to the HW structure 83 **/ 84 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw) 85 { 86 struct e1000_phy_info *phy = &hw->phy; 87 s32 ret_val = E1000_SUCCESS; 88 89 DEBUGFUNC("e1000_init_phy_params_82541"); 90 91 phy->addr = 1; 92 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 93 phy->reset_delay_us = 10000; 94 phy->type = e1000_phy_igp; 95 96 /* Function Pointers */ 97 phy->ops.check_polarity = e1000_check_polarity_igp; 98 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 99 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; 100 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 101 phy->ops.get_info = e1000_get_phy_info_igp; 102 phy->ops.read_reg = e1000_read_phy_reg_igp; 103 phy->ops.reset = e1000_phy_hw_reset_82541; 104 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 105 phy->ops.write_reg = e1000_write_phy_reg_igp; 106 phy->ops.power_up = e1000_power_up_phy_copper; 107 phy->ops.power_down = e1000_power_down_phy_copper_82541; 108 109 ret_val = e1000_get_phy_id(hw); 110 if (ret_val) 111 goto out; 112 113 /* Verify phy id */ 114 if (phy->id != IGP01E1000_I_PHY_ID) { 115 ret_val = -E1000_ERR_PHY; 116 goto out; 117 } 118 119 out: 120 return ret_val; 121 } 122 123 /** 124 * e1000_init_nvm_params_82541 - Init NVM func ptrs. 125 * @hw: pointer to the HW structure 126 **/ 127 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw) 128 { 129 struct e1000_nvm_info *nvm = &hw->nvm; 130 s32 ret_val = E1000_SUCCESS; 131 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 132 u16 size; 133 134 DEBUGFUNC("e1000_init_nvm_params_82541"); 135 136 switch (nvm->override) { 137 case e1000_nvm_override_spi_large: 138 nvm->type = e1000_nvm_eeprom_spi; 139 eecd |= E1000_EECD_ADDR_BITS; 140 break; 141 case e1000_nvm_override_spi_small: 142 nvm->type = e1000_nvm_eeprom_spi; 143 eecd &= ~E1000_EECD_ADDR_BITS; 144 break; 145 case e1000_nvm_override_microwire_large: 146 nvm->type = e1000_nvm_eeprom_microwire; 147 eecd |= E1000_EECD_SIZE; 148 break; 149 case e1000_nvm_override_microwire_small: 150 nvm->type = e1000_nvm_eeprom_microwire; 151 eecd &= ~E1000_EECD_SIZE; 152 break; 153 default: 154 nvm->type = eecd & E1000_EECD_TYPE 155 ? e1000_nvm_eeprom_spi 156 : e1000_nvm_eeprom_microwire; 157 break; 158 } 159 160 if (nvm->type == e1000_nvm_eeprom_spi) { 161 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 162 ? 16 : 8; 163 nvm->delay_usec = 1; 164 nvm->opcode_bits = 8; 165 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) 166 ? 32 : 8; 167 168 /* Function Pointers */ 169 nvm->ops.acquire = e1000_acquire_nvm_generic; 170 nvm->ops.read = e1000_read_nvm_spi; 171 nvm->ops.release = e1000_release_nvm_generic; 172 nvm->ops.update = e1000_update_nvm_checksum_generic; 173 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 174 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 175 nvm->ops.write = e1000_write_nvm_spi; 176 177 /* 178 * nvm->word_size must be discovered after the pointers 179 * are set so we can verify the size from the nvm image 180 * itself. Temporarily set it to a dummy value so the 181 * read will work. 182 */ 183 nvm->word_size = 64; 184 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size); 185 if (ret_val) 186 goto out; 187 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 188 /* 189 * if size != 0, it can be added to a constant and become 190 * the left-shift value to set the word_size. Otherwise, 191 * word_size stays at 64. 192 */ 193 if (size) { 194 size += NVM_WORD_SIZE_BASE_SHIFT_82541; 195 nvm->word_size = 1 << size; 196 } 197 } else { 198 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 199 ? 8 : 6; 200 nvm->delay_usec = 50; 201 nvm->opcode_bits = 3; 202 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) 203 ? 256 : 64; 204 205 /* Function Pointers */ 206 nvm->ops.acquire = e1000_acquire_nvm_generic; 207 nvm->ops.read = e1000_read_nvm_microwire; 208 nvm->ops.release = e1000_release_nvm_generic; 209 nvm->ops.update = e1000_update_nvm_checksum_generic; 210 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 211 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 212 nvm->ops.write = e1000_write_nvm_microwire; 213 } 214 215 out: 216 return ret_val; 217 } 218 219 /** 220 * e1000_init_mac_params_82541 - Init MAC func ptrs. 221 * @hw: pointer to the HW structure 222 **/ 223 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw) 224 { 225 struct e1000_mac_info *mac = &hw->mac; 226 227 DEBUGFUNC("e1000_init_mac_params_82541"); 228 229 /* Set media type */ 230 hw->phy.media_type = e1000_media_type_copper; 231 /* Set mta register count */ 232 mac->mta_reg_count = 128; 233 /* Set rar entry count */ 234 mac->rar_entry_count = E1000_RAR_ENTRIES; 235 /* Set if part includes ASF firmware */ 236 mac->asf_firmware_present = TRUE; 237 238 /* Function Pointers */ 239 240 /* bus type/speed/width */ 241 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 242 /* function id */ 243 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 244 /* reset */ 245 mac->ops.reset_hw = e1000_reset_hw_82541; 246 /* hw initialization */ 247 mac->ops.init_hw = e1000_init_hw_82541; 248 /* link setup */ 249 mac->ops.setup_link = e1000_setup_link_generic; 250 /* physical interface link setup */ 251 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541; 252 /* check for link */ 253 mac->ops.check_for_link = e1000_check_for_link_82541; 254 /* link info */ 255 mac->ops.get_link_up_info = e1000_get_link_up_info_82541; 256 /* multicast address update */ 257 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 258 /* writing VFTA */ 259 mac->ops.write_vfta = e1000_write_vfta_generic; 260 /* clearing VFTA */ 261 mac->ops.clear_vfta = e1000_clear_vfta_generic; 262 /* setting MTA */ 263 mac->ops.mta_set = e1000_mta_set_generic; 264 /* setup LED */ 265 mac->ops.setup_led = e1000_setup_led_82541; 266 /* cleanup LED */ 267 mac->ops.cleanup_led = e1000_cleanup_led_82541; 268 /* turn on/off LED */ 269 mac->ops.led_on = e1000_led_on_generic; 270 mac->ops.led_off = e1000_led_off_generic; 271 /* clear hardware counters */ 272 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 273 274 return E1000_SUCCESS; 275 } 276 277 /** 278 * e1000_init_function_pointers_82541 - Init func ptrs. 279 * @hw: pointer to the HW structure 280 * 281 * Called to initialize all function pointers and parameters. 282 **/ 283 void e1000_init_function_pointers_82541(struct e1000_hw *hw) 284 { 285 DEBUGFUNC("e1000_init_function_pointers_82541"); 286 287 hw->mac.ops.init_params = e1000_init_mac_params_82541; 288 hw->nvm.ops.init_params = e1000_init_nvm_params_82541; 289 hw->phy.ops.init_params = e1000_init_phy_params_82541; 290 } 291 292 /** 293 * e1000_reset_hw_82541 - Reset hardware 294 * @hw: pointer to the HW structure 295 * 296 * This resets the hardware into a known state. 297 **/ 298 static s32 e1000_reset_hw_82541(struct e1000_hw *hw) 299 { 300 u32 ledctl, ctrl, icr, manc; 301 302 DEBUGFUNC("e1000_reset_hw_82541"); 303 304 DEBUGOUT("Masking off all interrupts\n"); 305 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 306 307 E1000_WRITE_REG(hw, E1000_RCTL, 0); 308 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 309 E1000_WRITE_FLUSH(hw); 310 311 /* 312 * Delay to allow any outstanding PCI transactions to complete 313 * before resetting the device. 314 */ 315 msec_delay(10); 316 317 ctrl = E1000_READ_REG(hw, E1000_CTRL); 318 319 /* Must reset the Phy before resetting the MAC */ 320 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 321 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 322 msec_delay(5); 323 } 324 325 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 326 switch (hw->mac.type) { 327 case e1000_82541: 328 case e1000_82541_rev_2: 329 /* 330 * These controllers can't ack the 64-bit write when 331 * issuing the reset, so we use IO-mapping as a 332 * workaround to issue the reset. 333 */ 334 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 335 break; 336 default: 337 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 338 break; 339 } 340 341 /* Wait for NVM reload */ 342 msec_delay(20); 343 344 /* Disable HW ARPs on ASF enabled adapters */ 345 manc = E1000_READ_REG(hw, E1000_MANC); 346 manc &= ~E1000_MANC_ARP_EN; 347 E1000_WRITE_REG(hw, E1000_MANC, manc); 348 349 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 350 e1000_phy_init_script_82541(hw); 351 352 /* Configure activity LED after Phy reset */ 353 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 354 ledctl &= IGP_ACTIVITY_LED_MASK; 355 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 356 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 357 } 358 359 /* Once again, mask the interrupts */ 360 DEBUGOUT("Masking off all interrupts\n"); 361 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 362 363 /* Clear any pending interrupt events. */ 364 icr = E1000_READ_REG(hw, E1000_ICR); 365 366 return E1000_SUCCESS; 367 } 368 369 /** 370 * e1000_init_hw_82541 - Initialize hardware 371 * @hw: pointer to the HW structure 372 * 373 * This inits the hardware readying it for operation. 374 **/ 375 static s32 e1000_init_hw_82541(struct e1000_hw *hw) 376 { 377 struct e1000_mac_info *mac = &hw->mac; 378 u32 i, txdctl; 379 s32 ret_val; 380 381 DEBUGFUNC("e1000_init_hw_82541"); 382 383 /* Initialize identification LED */ 384 ret_val = e1000_id_led_init_generic(hw); 385 if (ret_val) { 386 DEBUGOUT("Error initializing identification LED\n"); 387 /* This is not fatal and we should not stop init due to this */ 388 } 389 390 /* Disabling VLAN filtering */ 391 DEBUGOUT("Initializing the IEEE VLAN\n"); 392 mac->ops.clear_vfta(hw); 393 394 /* Setup the receive address. */ 395 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 396 397 /* Zero out the Multicast HASH table */ 398 DEBUGOUT("Zeroing the MTA\n"); 399 for (i = 0; i < mac->mta_reg_count; i++) { 400 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 401 /* 402 * Avoid back to back register writes by adding the register 403 * read (flush). This is to protect against some strange 404 * bridge configurations that may issue Memory Write Block 405 * (MWB) to our register space. 406 */ 407 E1000_WRITE_FLUSH(hw); 408 } 409 410 /* Setup link and flow control */ 411 ret_val = mac->ops.setup_link(hw); 412 413 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 414 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 415 E1000_TXDCTL_FULL_TX_DESC_WB; 416 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 417 418 /* 419 * Clear all of the statistics registers (clear on read). It is 420 * important that we do this after we have tried to establish link 421 * because the symbol error count will increment wildly if there 422 * is no link. 423 */ 424 e1000_clear_hw_cntrs_82541(hw); 425 426 return ret_val; 427 } 428 429 /** 430 * e1000_get_link_up_info_82541 - Report speed and duplex 431 * @hw: pointer to the HW structure 432 * @speed: pointer to speed buffer 433 * @duplex: pointer to duplex buffer 434 * 435 * Retrieve the current speed and duplex configuration. 436 **/ 437 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 438 u16 *duplex) 439 { 440 struct e1000_phy_info *phy = &hw->phy; 441 s32 ret_val; 442 u16 data; 443 444 DEBUGFUNC("e1000_get_link_up_info_82541"); 445 446 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 447 if (ret_val) 448 goto out; 449 450 if (!phy->speed_downgraded) 451 goto out; 452 453 /* 454 * IGP01 PHY may advertise full duplex operation after speed 455 * downgrade even if it is operating at half duplex. 456 * Here we set the duplex settings to match the duplex in the 457 * link partner's capabilities. 458 */ 459 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data); 460 if (ret_val) 461 goto out; 462 463 if (!(data & NWAY_ER_LP_NWAY_CAPS)) { 464 *duplex = HALF_DUPLEX; 465 } else { 466 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data); 467 if (ret_val) 468 goto out; 469 470 if (*speed == SPEED_100) { 471 if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 472 *duplex = HALF_DUPLEX; 473 } else if (*speed == SPEED_10) { 474 if (!(data & NWAY_LPAR_10T_FD_CAPS)) 475 *duplex = HALF_DUPLEX; 476 } 477 } 478 479 out: 480 return ret_val; 481 } 482 483 /** 484 * e1000_phy_hw_reset_82541 - PHY hardware reset 485 * @hw: pointer to the HW structure 486 * 487 * Verify the reset block is not blocking us from resetting. Acquire 488 * semaphore (if necessary) and read/set/write the device control reset 489 * bit in the PHY. Wait the appropriate delay time for the device to 490 * reset and release the semaphore (if necessary). 491 **/ 492 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw) 493 { 494 s32 ret_val; 495 u32 ledctl; 496 497 DEBUGFUNC("e1000_phy_hw_reset_82541"); 498 499 ret_val = e1000_phy_hw_reset_generic(hw); 500 if (ret_val) 501 goto out; 502 503 e1000_phy_init_script_82541(hw); 504 505 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 506 /* Configure activity LED after PHY reset */ 507 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 508 ledctl &= IGP_ACTIVITY_LED_MASK; 509 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 510 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 511 } 512 513 out: 514 return ret_val; 515 } 516 517 /** 518 * e1000_setup_copper_link_82541 - Configure copper link settings 519 * @hw: pointer to the HW structure 520 * 521 * Calls the appropriate function to configure the link for auto-neg or forced 522 * speed and duplex. Then we check for link, once link is established calls 523 * to configure collision distance and flow control are called. If link is 524 * not established, we return -E1000_ERR_PHY (-2). 525 **/ 526 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw) 527 { 528 struct e1000_phy_info *phy = &hw->phy; 529 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 530 s32 ret_val; 531 u32 ctrl, ledctl; 532 533 DEBUGFUNC("e1000_setup_copper_link_82541"); 534 535 ctrl = E1000_READ_REG(hw, E1000_CTRL); 536 ctrl |= E1000_CTRL_SLU; 537 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 538 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 539 540 hw->phy.reset_disable = FALSE; 541 542 /* Earlier revs of the IGP phy require us to force MDI. */ 543 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 544 dev_spec->dsp_config = e1000_dsp_config_disabled; 545 phy->mdix = 1; 546 } else { 547 dev_spec->dsp_config = e1000_dsp_config_enabled; 548 } 549 550 ret_val = e1000_copper_link_setup_igp(hw); 551 if (ret_val) 552 goto out; 553 554 if (hw->mac.autoneg) { 555 if (dev_spec->ffe_config == e1000_ffe_config_active) 556 dev_spec->ffe_config = e1000_ffe_config_enabled; 557 } 558 559 /* Configure activity LED after Phy reset */ 560 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 561 ledctl &= IGP_ACTIVITY_LED_MASK; 562 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 563 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 564 565 ret_val = e1000_setup_copper_link_generic(hw); 566 567 out: 568 return ret_val; 569 } 570 571 /** 572 * e1000_check_for_link_82541 - Check/Store link connection 573 * @hw: pointer to the HW structure 574 * 575 * This checks the link condition of the adapter and stores the 576 * results in the hw->mac structure. 577 **/ 578 static s32 e1000_check_for_link_82541(struct e1000_hw *hw) 579 { 580 struct e1000_mac_info *mac = &hw->mac; 581 s32 ret_val; 582 bool link; 583 584 DEBUGFUNC("e1000_check_for_link_82541"); 585 586 /* 587 * We only want to go out to the PHY registers to see if Auto-Neg 588 * has completed and/or if our link status has changed. The 589 * get_link_status flag is set upon receiving a Link Status 590 * Change or Rx Sequence Error interrupt. 591 */ 592 if (!mac->get_link_status) { 593 ret_val = E1000_SUCCESS; 594 goto out; 595 } 596 597 /* 598 * First we want to see if the MII Status Register reports 599 * link. If so, then we want to get the current speed/duplex 600 * of the PHY. 601 */ 602 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 603 if (ret_val) 604 goto out; 605 606 if (!link) { 607 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE); 608 goto out; /* No link detected */ 609 } 610 611 mac->get_link_status = FALSE; 612 613 /* 614 * Check if there was DownShift, must be checked 615 * immediately after link-up 616 */ 617 e1000_check_downshift_generic(hw); 618 619 /* 620 * If we are forcing speed/duplex, then we simply return since 621 * we have already determined whether we have link or not. 622 */ 623 if (!mac->autoneg) { 624 ret_val = -E1000_ERR_CONFIG; 625 goto out; 626 } 627 628 ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE); 629 630 /* 631 * Auto-Neg is enabled. Auto Speed Detection takes care 632 * of MAC speed/duplex configuration. So we only need to 633 * configure Collision Distance in the MAC. 634 */ 635 e1000_config_collision_dist_generic(hw); 636 637 /* 638 * Configure Flow Control now that Auto-Neg has completed. 639 * First, we need to restore the desired flow control 640 * settings because we may have had to re-autoneg with a 641 * different link partner. 642 */ 643 ret_val = e1000_config_fc_after_link_up_generic(hw); 644 if (ret_val) { 645 DEBUGOUT("Error configuring flow control\n"); 646 } 647 648 out: 649 return ret_val; 650 } 651 652 /** 653 * e1000_config_dsp_after_link_change_82541 - Config DSP after link 654 * @hw: pointer to the HW structure 655 * @link_up: boolean flag for link up status 656 * 657 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS 658 * at any other case. 659 * 660 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 661 * gigabit link is achieved to improve link quality. 662 **/ 663 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 664 bool link_up) 665 { 666 struct e1000_phy_info *phy = &hw->phy; 667 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 668 s32 ret_val; 669 u32 idle_errs = 0; 670 u16 phy_data, phy_saved_data, speed, duplex, i; 671 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 672 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 673 {IGP01E1000_PHY_AGC_PARAM_A, 674 IGP01E1000_PHY_AGC_PARAM_B, 675 IGP01E1000_PHY_AGC_PARAM_C, 676 IGP01E1000_PHY_AGC_PARAM_D}; 677 678 DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); 679 680 if (link_up) { 681 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 682 if (ret_val) { 683 DEBUGOUT("Error getting link speed and duplex\n"); 684 goto out; 685 } 686 687 if (speed != SPEED_1000) { 688 ret_val = E1000_SUCCESS; 689 goto out; 690 } 691 692 ret_val = phy->ops.get_cable_length(hw); 693 if (ret_val) 694 goto out; 695 696 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && 697 phy->min_cable_length >= 50) { 698 699 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 700 ret_val = phy->ops.read_reg(hw, 701 dsp_reg_array[i], 702 &phy_data); 703 if (ret_val) 704 goto out; 705 706 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 707 708 ret_val = phy->ops.write_reg(hw, 709 dsp_reg_array[i], 710 phy_data); 711 if (ret_val) 712 goto out; 713 } 714 dev_spec->dsp_config = e1000_dsp_config_activated; 715 } 716 717 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || 718 (phy->min_cable_length >= 50)) { 719 ret_val = E1000_SUCCESS; 720 goto out; 721 } 722 723 /* clear previous idle error counts */ 724 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 725 if (ret_val) 726 goto out; 727 728 for (i = 0; i < ffe_idle_err_timeout; i++) { 729 usec_delay(1000); 730 ret_val = phy->ops.read_reg(hw, 731 PHY_1000T_STATUS, 732 &phy_data); 733 if (ret_val) 734 goto out; 735 736 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 737 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 738 dev_spec->ffe_config = e1000_ffe_config_active; 739 740 ret_val = phy->ops.write_reg(hw, 741 IGP01E1000_PHY_DSP_FFE, 742 IGP01E1000_PHY_DSP_FFE_CM_CP); 743 if (ret_val) 744 goto out; 745 break; 746 } 747 748 if (idle_errs) 749 ffe_idle_err_timeout = 750 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 751 } 752 } else { 753 if (dev_spec->dsp_config == e1000_dsp_config_activated) { 754 /* 755 * Save off the current value of register 0x2F5B 756 * to be restored at the end of the routines. 757 */ 758 ret_val = phy->ops.read_reg(hw, 759 0x2F5B, 760 &phy_saved_data); 761 if (ret_val) 762 goto out; 763 764 /* Disable the PHY transmitter */ 765 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 766 if (ret_val) 767 goto out; 768 769 msec_delay_irq(20); 770 771 ret_val = phy->ops.write_reg(hw, 772 0x0000, 773 IGP01E1000_IEEE_FORCE_GIG); 774 if (ret_val) 775 goto out; 776 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 777 ret_val = phy->ops.read_reg(hw, 778 dsp_reg_array[i], 779 &phy_data); 780 if (ret_val) 781 goto out; 782 783 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 784 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 785 786 ret_val = phy->ops.write_reg(hw, 787 dsp_reg_array[i], 788 phy_data); 789 if (ret_val) 790 goto out; 791 } 792 793 ret_val = phy->ops.write_reg(hw, 794 0x0000, 795 IGP01E1000_IEEE_RESTART_AUTONEG); 796 if (ret_val) 797 goto out; 798 799 msec_delay_irq(20); 800 801 /* Now enable the transmitter */ 802 ret_val = phy->ops.write_reg(hw, 803 0x2F5B, 804 phy_saved_data); 805 if (ret_val) 806 goto out; 807 808 dev_spec->dsp_config = e1000_dsp_config_enabled; 809 } 810 811 if (dev_spec->ffe_config != e1000_ffe_config_active) { 812 ret_val = E1000_SUCCESS; 813 goto out; 814 } 815 816 /* 817 * Save off the current value of register 0x2F5B 818 * to be restored at the end of the routines. 819 */ 820 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data); 821 if (ret_val) 822 goto out; 823 824 /* Disable the PHY transmitter */ 825 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 826 if (ret_val) 827 goto out; 828 829 msec_delay_irq(20); 830 831 ret_val = phy->ops.write_reg(hw, 832 0x0000, 833 IGP01E1000_IEEE_FORCE_GIG); 834 if (ret_val) 835 goto out; 836 837 ret_val = phy->ops.write_reg(hw, 838 IGP01E1000_PHY_DSP_FFE, 839 IGP01E1000_PHY_DSP_FFE_DEFAULT); 840 if (ret_val) 841 goto out; 842 843 ret_val = phy->ops.write_reg(hw, 844 0x0000, 845 IGP01E1000_IEEE_RESTART_AUTONEG); 846 if (ret_val) 847 goto out; 848 849 msec_delay_irq(20); 850 851 /* Now enable the transmitter */ 852 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data); 853 854 if (ret_val) 855 goto out; 856 857 dev_spec->ffe_config = e1000_ffe_config_enabled; 858 } 859 860 out: 861 return ret_val; 862 } 863 864 /** 865 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY 866 * @hw: pointer to the HW structure 867 * 868 * The automatic gain control (agc) normalizes the amplitude of the 869 * received signal, adjusting for the attenuation produced by the 870 * cable. By reading the AGC registers, which represent the 871 * combination of coarse and fine gain value, the value can be put 872 * into a lookup table to obtain the approximate cable length 873 * for each channel. 874 **/ 875 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw) 876 { 877 struct e1000_phy_info *phy = &hw->phy; 878 s32 ret_val = E1000_SUCCESS; 879 u16 i, data; 880 u16 cur_agc_value, agc_value = 0; 881 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 882 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 883 {IGP01E1000_PHY_AGC_A, 884 IGP01E1000_PHY_AGC_B, 885 IGP01E1000_PHY_AGC_C, 886 IGP01E1000_PHY_AGC_D}; 887 888 DEBUGFUNC("e1000_get_cable_length_igp_82541"); 889 890 /* Read the AGC registers for all channels */ 891 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 892 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data); 893 if (ret_val) 894 goto out; 895 896 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; 897 898 /* Bounds checking */ 899 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 900 (cur_agc_value == 0)) { 901 ret_val = -E1000_ERR_PHY; 902 goto out; 903 } 904 905 agc_value += cur_agc_value; 906 907 if (min_agc_value > cur_agc_value) 908 min_agc_value = cur_agc_value; 909 } 910 911 /* Remove the minimal AGC result for length < 50m */ 912 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { 913 agc_value -= min_agc_value; 914 /* Average the three remaining channels for the length. */ 915 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 916 } else { 917 /* Average the channels for the length. */ 918 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 919 } 920 921 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > 922 IGP01E1000_AGC_RANGE) 923 ? (e1000_igp_cable_length_table[agc_value] - 924 IGP01E1000_AGC_RANGE) 925 : 0; 926 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + 927 IGP01E1000_AGC_RANGE; 928 929 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 930 931 out: 932 return ret_val; 933 } 934 935 /** 936 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 937 * @hw: pointer to the HW structure 938 * @active: boolean used to enable/disable lplu 939 * 940 * Success returns 0, Failure returns 1 941 * 942 * The low power link up (lplu) state is set to the power management level D3 943 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 944 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 945 * is used during Dx states where the power conservation is most important. 946 * During driver activity, SmartSpeed should be enabled so performance is 947 * maintained. 948 **/ 949 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active) 950 { 951 struct e1000_phy_info *phy = &hw->phy; 952 s32 ret_val; 953 u16 data; 954 955 DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 956 957 switch (hw->mac.type) { 958 case e1000_82541_rev_2: 959 case e1000_82547_rev_2: 960 break; 961 default: 962 ret_val = e1000_set_d3_lplu_state_generic(hw, active); 963 goto out; 964 break; 965 } 966 967 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data); 968 if (ret_val) 969 goto out; 970 971 if (!active) { 972 data &= ~IGP01E1000_GMII_FLEX_SPD; 973 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 974 if (ret_val) 975 goto out; 976 977 /* 978 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 979 * during Dx states where the power conservation is most 980 * important. During driver activity we should enable 981 * SmartSpeed, so performance is maintained. 982 */ 983 if (phy->smart_speed == e1000_smart_speed_on) { 984 ret_val = phy->ops.read_reg(hw, 985 IGP01E1000_PHY_PORT_CONFIG, 986 &data); 987 if (ret_val) 988 goto out; 989 990 data |= IGP01E1000_PSCFR_SMART_SPEED; 991 ret_val = phy->ops.write_reg(hw, 992 IGP01E1000_PHY_PORT_CONFIG, 993 data); 994 if (ret_val) 995 goto out; 996 } else if (phy->smart_speed == e1000_smart_speed_off) { 997 ret_val = phy->ops.read_reg(hw, 998 IGP01E1000_PHY_PORT_CONFIG, 999 &data); 1000 if (ret_val) 1001 goto out; 1002 1003 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1004 ret_val = phy->ops.write_reg(hw, 1005 IGP01E1000_PHY_PORT_CONFIG, 1006 data); 1007 if (ret_val) 1008 goto out; 1009 } 1010 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1011 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1012 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1013 data |= IGP01E1000_GMII_FLEX_SPD; 1014 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 1015 if (ret_val) 1016 goto out; 1017 1018 /* When LPLU is enabled, we should disable SmartSpeed */ 1019 ret_val = phy->ops.read_reg(hw, 1020 IGP01E1000_PHY_PORT_CONFIG, 1021 &data); 1022 if (ret_val) 1023 goto out; 1024 1025 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1026 ret_val = phy->ops.write_reg(hw, 1027 IGP01E1000_PHY_PORT_CONFIG, 1028 data); 1029 } 1030 1031 out: 1032 return ret_val; 1033 } 1034 1035 /** 1036 * e1000_setup_led_82541 - Configures SW controllable LED 1037 * @hw: pointer to the HW structure 1038 * 1039 * This prepares the SW controllable LED for use and saves the current state 1040 * of the LED so it can be later restored. 1041 **/ 1042 static s32 e1000_setup_led_82541(struct e1000_hw *hw) 1043 { 1044 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1045 s32 ret_val; 1046 1047 DEBUGFUNC("e1000_setup_led_82541"); 1048 1049 ret_val = hw->phy.ops.read_reg(hw, 1050 IGP01E1000_GMII_FIFO, 1051 &dev_spec->spd_default); 1052 if (ret_val) 1053 goto out; 1054 1055 ret_val = hw->phy.ops.write_reg(hw, 1056 IGP01E1000_GMII_FIFO, 1057 (u16)(dev_spec->spd_default & 1058 ~IGP01E1000_GMII_SPD)); 1059 if (ret_val) 1060 goto out; 1061 1062 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1063 1064 out: 1065 return ret_val; 1066 } 1067 1068 /** 1069 * e1000_cleanup_led_82541 - Set LED config to default operation 1070 * @hw: pointer to the HW structure 1071 * 1072 * Remove the current LED configuration and set the LED configuration 1073 * to the default value, saved from the EEPROM. 1074 **/ 1075 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw) 1076 { 1077 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1078 s32 ret_val; 1079 1080 DEBUGFUNC("e1000_cleanup_led_82541"); 1081 1082 ret_val = hw->phy.ops.write_reg(hw, 1083 IGP01E1000_GMII_FIFO, 1084 dev_spec->spd_default); 1085 if (ret_val) 1086 goto out; 1087 1088 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1089 1090 out: 1091 return ret_val; 1092 } 1093 1094 /** 1095 * e1000_phy_init_script_82541 - Initialize GbE PHY 1096 * @hw: pointer to the HW structure 1097 * 1098 * Initializes the IGP PHY. 1099 **/ 1100 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw) 1101 { 1102 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1103 u32 ret_val; 1104 u16 phy_saved_data; 1105 1106 DEBUGFUNC("e1000_phy_init_script_82541"); 1107 1108 if (!dev_spec->phy_init_script) { 1109 ret_val = E1000_SUCCESS; 1110 goto out; 1111 } 1112 1113 /* Delay after phy reset to enable NVM configuration to load */ 1114 msec_delay(20); 1115 1116 /* 1117 * Save off the current value of register 0x2F5B to be restored at 1118 * the end of this routine. 1119 */ 1120 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data); 1121 1122 /* Disabled the PHY transmitter */ 1123 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003); 1124 1125 msec_delay(20); 1126 1127 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 1128 1129 msec_delay(5); 1130 1131 switch (hw->mac.type) { 1132 case e1000_82541: 1133 case e1000_82547: 1134 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001); 1135 1136 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21); 1137 1138 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018); 1139 1140 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600); 1141 1142 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014); 1143 1144 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C); 1145 1146 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003); 1147 1148 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F); 1149 1150 hw->phy.ops.write_reg(hw, 0x2010, 0x0008); 1151 break; 1152 case e1000_82541_rev_2: 1153 case e1000_82547_rev_2: 1154 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099); 1155 break; 1156 default: 1157 break; 1158 } 1159 1160 hw->phy.ops.write_reg(hw, 0x0000, 0x3300); 1161 1162 msec_delay(20); 1163 1164 /* Now enable the transmitter */ 1165 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data); 1166 1167 if (hw->mac.type == e1000_82547) { 1168 u16 fused, fine, coarse; 1169 1170 /* Move to analog registers page */ 1171 hw->phy.ops.read_reg(hw, 1172 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 1173 &fused); 1174 1175 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 1176 hw->phy.ops.read_reg(hw, 1177 IGP01E1000_ANALOG_FUSE_STATUS, 1178 &fused); 1179 1180 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 1181 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 1182 1183 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 1184 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 1185 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 1186 } else if (coarse == 1187 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 1188 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 1189 1190 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 1191 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 1192 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 1193 1194 hw->phy.ops.write_reg(hw, 1195 IGP01E1000_ANALOG_FUSE_CONTROL, 1196 fused); 1197 hw->phy.ops.write_reg(hw, 1198 IGP01E1000_ANALOG_FUSE_BYPASS, 1199 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 1200 } 1201 } 1202 1203 out: 1204 return ret_val; 1205 } 1206 1207 /** 1208 * e1000_init_script_state_82541 - Enable/Disable PHY init script 1209 * @hw: pointer to the HW structure 1210 * @state: boolean value used to enable/disable PHY init script 1211 * 1212 * Allows the driver to enable/disable the PHY init script, if the PHY is an 1213 * IGP PHY. 1214 **/ 1215 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state) 1216 { 1217 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1218 1219 DEBUGFUNC("e1000_init_script_state_82541"); 1220 1221 if (hw->phy.type != e1000_phy_igp) { 1222 DEBUGOUT("Initialization script not necessary.\n"); 1223 goto out; 1224 } 1225 1226 dev_spec->phy_init_script = state; 1227 1228 out: 1229 return; 1230 } 1231 1232 /** 1233 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down 1234 * @hw: pointer to the HW structure 1235 * 1236 * In the case of a PHY power down to save power, or to turn off link during a 1237 * driver unload, or wake on lan is not enabled, remove the link. 1238 **/ 1239 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw) 1240 { 1241 /* If the management interface is not enabled, then power down */ 1242 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 1243 e1000_power_down_phy_copper(hw); 1244 1245 return; 1246 } 1247 1248 /** 1249 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters 1250 * @hw: pointer to the HW structure 1251 * 1252 * Clears the hardware counters by reading the counter registers. 1253 **/ 1254 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) 1255 { 1256 DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 1257 1258 e1000_clear_hw_cntrs_base_generic(hw); 1259 1260 E1000_READ_REG(hw, E1000_PRC64); 1261 E1000_READ_REG(hw, E1000_PRC127); 1262 E1000_READ_REG(hw, E1000_PRC255); 1263 E1000_READ_REG(hw, E1000_PRC511); 1264 E1000_READ_REG(hw, E1000_PRC1023); 1265 E1000_READ_REG(hw, E1000_PRC1522); 1266 E1000_READ_REG(hw, E1000_PTC64); 1267 E1000_READ_REG(hw, E1000_PTC127); 1268 E1000_READ_REG(hw, E1000_PTC255); 1269 E1000_READ_REG(hw, E1000_PTC511); 1270 E1000_READ_REG(hw, E1000_PTC1023); 1271 E1000_READ_REG(hw, E1000_PTC1522); 1272 1273 E1000_READ_REG(hw, E1000_ALGNERRC); 1274 E1000_READ_REG(hw, E1000_RXERRC); 1275 E1000_READ_REG(hw, E1000_TNCRS); 1276 E1000_READ_REG(hw, E1000_CEXTERR); 1277 E1000_READ_REG(hw, E1000_TSCTC); 1278 E1000_READ_REG(hw, E1000_TSCTFC); 1279 1280 E1000_READ_REG(hw, E1000_MGTPRC); 1281 E1000_READ_REG(hw, E1000_MGTPDC); 1282 E1000_READ_REG(hw, E1000_MGTPTC); 1283 } 1284