1 /****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #ifndef NO_82542_SUPPORT 45 #define E1000_DEV_ID_82542 0x1000 46 #endif 47 #define E1000_DEV_ID_82543GC_FIBER 0x1001 48 #define E1000_DEV_ID_82543GC_COPPER 0x1004 49 #define E1000_DEV_ID_82544EI_COPPER 0x1008 50 #define E1000_DEV_ID_82544EI_FIBER 0x1009 51 #define E1000_DEV_ID_82544GC_COPPER 0x100C 52 #define E1000_DEV_ID_82544GC_LOM 0x100D 53 #define E1000_DEV_ID_82540EM 0x100E 54 #define E1000_DEV_ID_82540EM_LOM 0x1015 55 #define E1000_DEV_ID_82540EP_LOM 0x1016 56 #define E1000_DEV_ID_82540EP 0x1017 57 #define E1000_DEV_ID_82540EP_LP 0x101E 58 #define E1000_DEV_ID_82545EM_COPPER 0x100F 59 #define E1000_DEV_ID_82545EM_FIBER 0x1011 60 #define E1000_DEV_ID_82545GM_COPPER 0x1026 61 #define E1000_DEV_ID_82545GM_FIBER 0x1027 62 #define E1000_DEV_ID_82545GM_SERDES 0x1028 63 #define E1000_DEV_ID_82546EB_COPPER 0x1010 64 #define E1000_DEV_ID_82546EB_FIBER 0x1012 65 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 66 #define E1000_DEV_ID_82546GB_COPPER 0x1079 67 #define E1000_DEV_ID_82546GB_FIBER 0x107A 68 #define E1000_DEV_ID_82546GB_SERDES 0x107B 69 #define E1000_DEV_ID_82546GB_PCIE 0x108A 70 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 71 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 72 #define E1000_DEV_ID_82541EI 0x1013 73 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 74 #define E1000_DEV_ID_82541ER_LOM 0x1014 75 #define E1000_DEV_ID_82541ER 0x1078 76 #define E1000_DEV_ID_82541GI 0x1076 77 #define E1000_DEV_ID_82541GI_LF 0x107C 78 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 79 #define E1000_DEV_ID_82547EI 0x1019 80 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 81 #define E1000_DEV_ID_82547GI 0x1075 82 #define E1000_DEV_ID_82571EB_COPPER 0x105E 83 #define E1000_DEV_ID_82571EB_FIBER 0x105F 84 #define E1000_DEV_ID_82571EB_SERDES 0x1060 85 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 86 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 87 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 88 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 89 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 90 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 91 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP 0x10A0 92 #define E1000_DEV_ID_82572EI_COPPER 0x107D 93 #define E1000_DEV_ID_82572EI_FIBER 0x107E 94 #define E1000_DEV_ID_82572EI_SERDES 0x107F 95 #define E1000_DEV_ID_82572EI 0x10B9 96 #define E1000_DEV_ID_82573E 0x108B 97 #define E1000_DEV_ID_82573E_IAMT 0x108C 98 #define E1000_DEV_ID_82573L 0x109A 99 #define E1000_DEV_ID_82574L 0x10D3 100 #define E1000_DEV_ID_82574LA 0x10F6 101 #define E1000_DEV_ID_82583V 0x150C 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 104 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 105 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 106 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 107 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 108 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 109 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 110 #define E1000_DEV_ID_ICH8_IFE 0x104C 111 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 112 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 113 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 114 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 115 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 116 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 117 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 118 #define E1000_DEV_ID_ICH9_BM 0x10E5 119 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 120 #define E1000_DEV_ID_ICH9_IFE 0x10C0 121 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 122 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 123 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 124 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 125 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 126 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 127 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 128 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 129 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 130 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 131 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 132 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 133 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 134 #define E1000_DEV_ID_PCH2_LV_V 0x1503 135 #define E1000_DEV_ID_82576 0x10C9 136 #define E1000_DEV_ID_82576_FIBER 0x10E6 137 #define E1000_DEV_ID_82576_SERDES 0x10E7 138 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 139 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 140 #define E1000_DEV_ID_82576_NS 0x150A 141 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 142 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 143 #define E1000_DEV_ID_82576_VF 0x10CA 144 #define E1000_DEV_ID_I350_VF 0x1520 145 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 146 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 147 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 148 #define E1000_DEV_ID_82580_COPPER 0x150E 149 #define E1000_DEV_ID_82580_FIBER 0x150F 150 #define E1000_DEV_ID_82580_SERDES 0x1510 151 #define E1000_DEV_ID_82580_SGMII 0x1511 152 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 153 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 154 #define E1000_DEV_ID_I350_COPPER 0x1521 155 #define E1000_DEV_ID_I350_FIBER 0x1522 156 #define E1000_DEV_ID_I350_SERDES 0x1523 157 #define E1000_DEV_ID_I350_SGMII 0x1524 158 #define E1000_DEV_ID_I350_DA4 0x1546 159 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 160 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 161 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 162 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 163 #define E1000_REVISION_0 0 164 #define E1000_REVISION_1 1 165 #define E1000_REVISION_2 2 166 #define E1000_REVISION_3 3 167 #define E1000_REVISION_4 4 168 169 #define E1000_FUNC_0 0 170 #define E1000_FUNC_1 1 171 #define E1000_FUNC_2 2 172 #define E1000_FUNC_3 3 173 174 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 175 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 176 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 177 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 178 179 enum e1000_mac_type { 180 e1000_undefined = 0, 181 #ifndef NO_82542_SUPPORT 182 e1000_82542, 183 #endif 184 e1000_82543, 185 e1000_82544, 186 e1000_82540, 187 e1000_82545, 188 e1000_82545_rev_3, 189 e1000_82546, 190 e1000_82546_rev_3, 191 e1000_82541, 192 e1000_82541_rev_2, 193 e1000_82547, 194 e1000_82547_rev_2, 195 e1000_82571, 196 e1000_82572, 197 e1000_82573, 198 e1000_82574, 199 e1000_82583, 200 e1000_80003es2lan, 201 e1000_ich8lan, 202 e1000_ich9lan, 203 e1000_ich10lan, 204 e1000_pchlan, 205 e1000_pch2lan, 206 e1000_82575, 207 e1000_82576, 208 e1000_82580, 209 e1000_i350, 210 e1000_vfadapt, 211 e1000_vfadapt_i350, 212 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 213 }; 214 215 enum e1000_media_type { 216 e1000_media_type_unknown = 0, 217 e1000_media_type_copper = 1, 218 e1000_media_type_fiber = 2, 219 e1000_media_type_internal_serdes = 3, 220 e1000_num_media_types 221 }; 222 223 enum e1000_nvm_type { 224 e1000_nvm_unknown = 0, 225 e1000_nvm_none, 226 e1000_nvm_eeprom_spi, 227 e1000_nvm_eeprom_microwire, 228 e1000_nvm_flash_hw, 229 e1000_nvm_flash_sw 230 }; 231 232 enum e1000_nvm_override { 233 e1000_nvm_override_none = 0, 234 e1000_nvm_override_spi_small, 235 e1000_nvm_override_spi_large, 236 e1000_nvm_override_microwire_small, 237 e1000_nvm_override_microwire_large 238 }; 239 240 enum e1000_phy_type { 241 e1000_phy_unknown = 0, 242 e1000_phy_none, 243 e1000_phy_m88, 244 e1000_phy_igp, 245 e1000_phy_igp_2, 246 e1000_phy_gg82563, 247 e1000_phy_igp_3, 248 e1000_phy_ife, 249 e1000_phy_bm, 250 e1000_phy_82578, 251 e1000_phy_82577, 252 e1000_phy_82579, 253 e1000_phy_82580, 254 e1000_phy_vf, 255 }; 256 257 enum e1000_bus_type { 258 e1000_bus_type_unknown = 0, 259 e1000_bus_type_pci, 260 e1000_bus_type_pcix, 261 e1000_bus_type_pci_express, 262 e1000_bus_type_reserved 263 }; 264 265 enum e1000_bus_speed { 266 e1000_bus_speed_unknown = 0, 267 e1000_bus_speed_33, 268 e1000_bus_speed_66, 269 e1000_bus_speed_100, 270 e1000_bus_speed_120, 271 e1000_bus_speed_133, 272 e1000_bus_speed_2500, 273 e1000_bus_speed_5000, 274 e1000_bus_speed_reserved 275 }; 276 277 enum e1000_bus_width { 278 e1000_bus_width_unknown = 0, 279 e1000_bus_width_pcie_x1, 280 e1000_bus_width_pcie_x2, 281 e1000_bus_width_pcie_x4 = 4, 282 e1000_bus_width_pcie_x8 = 8, 283 e1000_bus_width_32, 284 e1000_bus_width_64, 285 e1000_bus_width_reserved 286 }; 287 288 enum e1000_1000t_rx_status { 289 e1000_1000t_rx_status_not_ok = 0, 290 e1000_1000t_rx_status_ok, 291 e1000_1000t_rx_status_undefined = 0xFF 292 }; 293 294 enum e1000_rev_polarity { 295 e1000_rev_polarity_normal = 0, 296 e1000_rev_polarity_reversed, 297 e1000_rev_polarity_undefined = 0xFF 298 }; 299 300 enum e1000_fc_mode { 301 e1000_fc_none = 0, 302 e1000_fc_rx_pause, 303 e1000_fc_tx_pause, 304 e1000_fc_full, 305 e1000_fc_default = 0xFF 306 }; 307 308 enum e1000_ffe_config { 309 e1000_ffe_config_enabled = 0, 310 e1000_ffe_config_active, 311 e1000_ffe_config_blocked 312 }; 313 314 enum e1000_dsp_config { 315 e1000_dsp_config_disabled = 0, 316 e1000_dsp_config_enabled, 317 e1000_dsp_config_activated, 318 e1000_dsp_config_undefined = 0xFF 319 }; 320 321 enum e1000_ms_type { 322 e1000_ms_hw_default = 0, 323 e1000_ms_force_master, 324 e1000_ms_force_slave, 325 e1000_ms_auto 326 }; 327 328 enum e1000_smart_speed { 329 e1000_smart_speed_default = 0, 330 e1000_smart_speed_on, 331 e1000_smart_speed_off 332 }; 333 334 enum e1000_serdes_link_state { 335 e1000_serdes_link_down = 0, 336 e1000_serdes_link_autoneg_progress, 337 e1000_serdes_link_autoneg_complete, 338 e1000_serdes_link_forced_up 339 }; 340 341 #define __le16 u16 342 #define __le32 u32 343 #define __le64 u64 344 /* Receive Descriptor */ 345 struct e1000_rx_desc { 346 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 347 __le16 length; /* Length of data DMAed into data buffer */ 348 __le16 csum; /* Packet checksum */ 349 u8 status; /* Descriptor status */ 350 u8 errors; /* Descriptor Errors */ 351 __le16 special; 352 }; 353 354 /* Receive Descriptor - Extended */ 355 union e1000_rx_desc_extended { 356 struct { 357 __le64 buffer_addr; 358 __le64 reserved; 359 } read; 360 struct { 361 struct { 362 __le32 mrq; /* Multiple Rx Queues */ 363 union { 364 __le32 rss; /* RSS Hash */ 365 struct { 366 __le16 ip_id; /* IP id */ 367 __le16 csum; /* Packet Checksum */ 368 } csum_ip; 369 } hi_dword; 370 } lower; 371 struct { 372 __le32 status_error; /* ext status/error */ 373 __le16 length; 374 __le16 vlan; /* VLAN tag */ 375 } upper; 376 } wb; /* writeback */ 377 }; 378 379 #define MAX_PS_BUFFERS 4 380 /* Receive Descriptor - Packet Split */ 381 union e1000_rx_desc_packet_split { 382 struct { 383 /* one buffer for protocol header(s), three data buffers */ 384 __le64 buffer_addr[MAX_PS_BUFFERS]; 385 } read; 386 struct { 387 struct { 388 __le32 mrq; /* Multiple Rx Queues */ 389 union { 390 __le32 rss; /* RSS Hash */ 391 struct { 392 __le16 ip_id; /* IP id */ 393 __le16 csum; /* Packet Checksum */ 394 } csum_ip; 395 } hi_dword; 396 } lower; 397 struct { 398 __le32 status_error; /* ext status/error */ 399 __le16 length0; /* length of buffer 0 */ 400 __le16 vlan; /* VLAN tag */ 401 } middle; 402 struct { 403 __le16 header_status; 404 __le16 length[3]; /* length of buffers 1-3 */ 405 } upper; 406 __le64 reserved; 407 } wb; /* writeback */ 408 }; 409 410 /* Transmit Descriptor */ 411 struct e1000_tx_desc { 412 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 413 union { 414 __le32 data; 415 struct { 416 __le16 length; /* Data buffer length */ 417 u8 cso; /* Checksum offset */ 418 u8 cmd; /* Descriptor control */ 419 } flags; 420 } lower; 421 union { 422 __le32 data; 423 struct { 424 u8 status; /* Descriptor status */ 425 u8 css; /* Checksum start */ 426 __le16 special; 427 } fields; 428 } upper; 429 }; 430 431 /* Offload Context Descriptor */ 432 struct e1000_context_desc { 433 union { 434 __le32 ip_config; 435 struct { 436 u8 ipcss; /* IP checksum start */ 437 u8 ipcso; /* IP checksum offset */ 438 __le16 ipcse; /* IP checksum end */ 439 } ip_fields; 440 } lower_setup; 441 union { 442 __le32 tcp_config; 443 struct { 444 u8 tucss; /* TCP checksum start */ 445 u8 tucso; /* TCP checksum offset */ 446 __le16 tucse; /* TCP checksum end */ 447 } tcp_fields; 448 } upper_setup; 449 __le32 cmd_and_length; 450 union { 451 __le32 data; 452 struct { 453 u8 status; /* Descriptor status */ 454 u8 hdr_len; /* Header length */ 455 __le16 mss; /* Maximum segment size */ 456 } fields; 457 } tcp_seg_setup; 458 }; 459 460 /* Offload data descriptor */ 461 struct e1000_data_desc { 462 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 463 union { 464 __le32 data; 465 struct { 466 __le16 length; /* Data buffer length */ 467 u8 typ_len_ext; 468 u8 cmd; 469 } flags; 470 } lower; 471 union { 472 __le32 data; 473 struct { 474 u8 status; /* Descriptor status */ 475 u8 popts; /* Packet Options */ 476 __le16 special; 477 } fields; 478 } upper; 479 }; 480 481 /* Statistics counters collected by the MAC */ 482 struct e1000_hw_stats { 483 u64 crcerrs; 484 u64 algnerrc; 485 u64 symerrs; 486 u64 rxerrc; 487 u64 mpc; 488 u64 scc; 489 u64 ecol; 490 u64 mcc; 491 u64 latecol; 492 u64 colc; 493 u64 dc; 494 u64 tncrs; 495 u64 sec; 496 u64 cexterr; 497 u64 rlec; 498 u64 xonrxc; 499 u64 xontxc; 500 u64 xoffrxc; 501 u64 xofftxc; 502 u64 fcruc; 503 u64 prc64; 504 u64 prc127; 505 u64 prc255; 506 u64 prc511; 507 u64 prc1023; 508 u64 prc1522; 509 u64 gprc; 510 u64 bprc; 511 u64 mprc; 512 u64 gptc; 513 u64 gorc; 514 u64 gotc; 515 u64 rnbc; 516 u64 ruc; 517 u64 rfc; 518 u64 roc; 519 u64 rjc; 520 u64 mgprc; 521 u64 mgpdc; 522 u64 mgptc; 523 u64 tor; 524 u64 tot; 525 u64 tpr; 526 u64 tpt; 527 u64 ptc64; 528 u64 ptc127; 529 u64 ptc255; 530 u64 ptc511; 531 u64 ptc1023; 532 u64 ptc1522; 533 u64 mptc; 534 u64 bptc; 535 u64 tsctc; 536 u64 tsctfc; 537 u64 iac; 538 u64 icrxptc; 539 u64 icrxatc; 540 u64 ictxptc; 541 u64 ictxatc; 542 u64 ictxqec; 543 u64 ictxqmtc; 544 u64 icrxdmtc; 545 u64 icrxoc; 546 u64 cbtmpc; 547 u64 htdpmc; 548 u64 cbrdpc; 549 u64 cbrmpc; 550 u64 rpthc; 551 u64 hgptc; 552 u64 htcbdpc; 553 u64 hgorc; 554 u64 hgotc; 555 u64 lenerrs; 556 u64 scvpc; 557 u64 hrmpc; 558 u64 doosync; 559 }; 560 561 struct e1000_vf_stats { 562 u64 base_gprc; 563 u64 base_gptc; 564 u64 base_gorc; 565 u64 base_gotc; 566 u64 base_mprc; 567 u64 base_gotlbc; 568 u64 base_gptlbc; 569 u64 base_gorlbc; 570 u64 base_gprlbc; 571 572 u32 last_gprc; 573 u32 last_gptc; 574 u32 last_gorc; 575 u32 last_gotc; 576 u32 last_mprc; 577 u32 last_gotlbc; 578 u32 last_gptlbc; 579 u32 last_gorlbc; 580 u32 last_gprlbc; 581 582 u64 gprc; 583 u64 gptc; 584 u64 gorc; 585 u64 gotc; 586 u64 mprc; 587 u64 gotlbc; 588 u64 gptlbc; 589 u64 gorlbc; 590 u64 gprlbc; 591 }; 592 593 struct e1000_phy_stats { 594 u32 idle_errors; 595 u32 receive_errors; 596 }; 597 598 struct e1000_host_mng_dhcp_cookie { 599 u32 signature; 600 u8 status; 601 u8 reserved0; 602 u16 vlan_id; 603 u32 reserved1; 604 u16 reserved2; 605 u8 reserved3; 606 u8 checksum; 607 }; 608 609 /* Host Interface "Rev 1" */ 610 struct e1000_host_command_header { 611 u8 command_id; 612 u8 command_length; 613 u8 command_options; 614 u8 checksum; 615 }; 616 617 #define E1000_HI_MAX_DATA_LENGTH 252 618 struct e1000_host_command_info { 619 struct e1000_host_command_header command_header; 620 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 621 }; 622 623 /* Host Interface "Rev 2" */ 624 struct e1000_host_mng_command_header { 625 u8 command_id; 626 u8 checksum; 627 u16 reserved1; 628 u16 reserved2; 629 u16 command_length; 630 }; 631 632 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 633 struct e1000_host_mng_command_info { 634 struct e1000_host_mng_command_header command_header; 635 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 636 }; 637 638 #include "e1000_mac.h" 639 #include "e1000_phy.h" 640 #include "e1000_nvm.h" 641 #include "e1000_manage.h" 642 #include "e1000_mbx.h" 643 644 struct e1000_mac_operations { 645 /* Function pointers for the MAC. */ 646 s32 (*init_params)(struct e1000_hw *); 647 s32 (*id_led_init)(struct e1000_hw *); 648 s32 (*blink_led)(struct e1000_hw *); 649 s32 (*check_for_link)(struct e1000_hw *); 650 bool (*check_mng_mode)(struct e1000_hw *hw); 651 s32 (*cleanup_led)(struct e1000_hw *); 652 void (*clear_hw_cntrs)(struct e1000_hw *); 653 void (*clear_vfta)(struct e1000_hw *); 654 s32 (*get_bus_info)(struct e1000_hw *); 655 void (*set_lan_id)(struct e1000_hw *); 656 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 657 s32 (*led_on)(struct e1000_hw *); 658 s32 (*led_off)(struct e1000_hw *); 659 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 660 s32 (*reset_hw)(struct e1000_hw *); 661 s32 (*init_hw)(struct e1000_hw *); 662 void (*shutdown_serdes)(struct e1000_hw *); 663 void (*power_up_serdes)(struct e1000_hw *); 664 s32 (*setup_link)(struct e1000_hw *); 665 s32 (*setup_physical_interface)(struct e1000_hw *); 666 s32 (*setup_led)(struct e1000_hw *); 667 void (*write_vfta)(struct e1000_hw *, u32, u32); 668 void (*config_collision_dist)(struct e1000_hw *); 669 void (*rar_set)(struct e1000_hw *, u8*, u32); 670 s32 (*read_mac_addr)(struct e1000_hw *); 671 s32 (*validate_mdi_setting)(struct e1000_hw *); 672 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); 673 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 674 struct e1000_host_mng_command_header*); 675 s32 (*mng_enable_host_if)(struct e1000_hw *); 676 s32 (*wait_autoneg)(struct e1000_hw *); 677 }; 678 679 /* 680 * When to use various PHY register access functions: 681 * 682 * Func Caller 683 * Function Does Does When to use 684 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 685 * X_reg L,P,A n/a for simple PHY reg accesses 686 * X_reg_locked P,A L for multiple accesses of different regs 687 * on different pages 688 * X_reg_page A L,P for multiple accesses of different regs 689 * on the same page 690 * 691 * Where X=[read|write], L=locking, P=sets page, A=register access 692 * 693 */ 694 struct e1000_phy_operations { 695 s32 (*init_params)(struct e1000_hw *); 696 s32 (*acquire)(struct e1000_hw *); 697 s32 (*cfg_on_link_up)(struct e1000_hw *); 698 s32 (*check_polarity)(struct e1000_hw *); 699 s32 (*check_reset_block)(struct e1000_hw *); 700 s32 (*commit)(struct e1000_hw *); 701 s32 (*force_speed_duplex)(struct e1000_hw *); 702 s32 (*get_cfg_done)(struct e1000_hw *hw); 703 s32 (*get_cable_length)(struct e1000_hw *); 704 s32 (*get_info)(struct e1000_hw *); 705 s32 (*set_page)(struct e1000_hw *, u16); 706 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 707 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 708 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 709 void (*release)(struct e1000_hw *); 710 s32 (*reset)(struct e1000_hw *); 711 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 712 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 713 s32 (*write_reg)(struct e1000_hw *, u32, u16); 714 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 715 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 716 void (*power_up)(struct e1000_hw *); 717 void (*power_down)(struct e1000_hw *); 718 }; 719 720 struct e1000_nvm_operations { 721 s32 (*init_params)(struct e1000_hw *); 722 s32 (*acquire)(struct e1000_hw *); 723 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 724 void (*release)(struct e1000_hw *); 725 void (*reload)(struct e1000_hw *); 726 s32 (*update)(struct e1000_hw *); 727 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 728 s32 (*validate)(struct e1000_hw *); 729 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 730 }; 731 732 struct e1000_mac_info { 733 struct e1000_mac_operations ops; 734 u8 addr[ETH_ADDR_LEN]; 735 u8 perm_addr[ETH_ADDR_LEN]; 736 737 enum e1000_mac_type type; 738 739 u32 collision_delta; 740 u32 ledctl_default; 741 u32 ledctl_mode1; 742 u32 ledctl_mode2; 743 u32 mc_filter_type; 744 u32 tx_packet_delta; 745 u32 txcw; 746 747 u16 current_ifs_val; 748 u16 ifs_max_val; 749 u16 ifs_min_val; 750 u16 ifs_ratio; 751 u16 ifs_step_size; 752 u16 mta_reg_count; 753 u16 uta_reg_count; 754 755 /* Maximum size of the MTA register table in all supported adapters */ 756 #define MAX_MTA_REG 128 757 u32 mta_shadow[MAX_MTA_REG]; 758 u16 rar_entry_count; 759 760 u8 forced_speed_duplex; 761 762 bool adaptive_ifs; 763 bool has_fwsm; 764 bool arc_subsystem_valid; 765 bool asf_firmware_present; 766 bool autoneg; 767 bool autoneg_failed; 768 bool get_link_status; 769 bool in_ifs_mode; 770 #ifndef NO_82542_SUPPORT 771 bool report_tx_early; 772 #endif 773 enum e1000_serdes_link_state serdes_link_state; 774 bool serdes_has_link; 775 bool tx_pkt_filtering; 776 }; 777 778 struct e1000_phy_info { 779 struct e1000_phy_operations ops; 780 enum e1000_phy_type type; 781 782 enum e1000_1000t_rx_status local_rx; 783 enum e1000_1000t_rx_status remote_rx; 784 enum e1000_ms_type ms_type; 785 enum e1000_ms_type original_ms_type; 786 enum e1000_rev_polarity cable_polarity; 787 enum e1000_smart_speed smart_speed; 788 789 u32 addr; 790 u32 id; 791 u32 reset_delay_us; /* in usec */ 792 u32 revision; 793 794 enum e1000_media_type media_type; 795 796 u16 autoneg_advertised; 797 u16 autoneg_mask; 798 u16 cable_length; 799 u16 max_cable_length; 800 u16 min_cable_length; 801 802 u8 mdix; 803 804 bool disable_polarity_correction; 805 bool is_mdix; 806 bool polarity_correction; 807 bool reset_disable; 808 bool speed_downgraded; 809 bool autoneg_wait_to_complete; 810 }; 811 812 struct e1000_nvm_info { 813 struct e1000_nvm_operations ops; 814 enum e1000_nvm_type type; 815 enum e1000_nvm_override override; 816 817 u32 flash_bank_size; 818 u32 flash_base_addr; 819 820 u16 word_size; 821 u16 delay_usec; 822 u16 address_bits; 823 u16 opcode_bits; 824 u16 page_size; 825 }; 826 827 struct e1000_bus_info { 828 enum e1000_bus_type type; 829 enum e1000_bus_speed speed; 830 enum e1000_bus_width width; 831 832 u16 func; 833 u16 pci_cmd_word; 834 }; 835 836 struct e1000_fc_info { 837 u32 high_water; /* Flow control high-water mark */ 838 u32 low_water; /* Flow control low-water mark */ 839 u16 pause_time; /* Flow control pause timer */ 840 u16 refresh_time; /* Flow control refresh timer */ 841 bool send_xon; /* Flow control send XON */ 842 bool strict_ieee; /* Strict IEEE mode */ 843 enum e1000_fc_mode current_mode; /* FC mode in effect */ 844 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 845 }; 846 847 struct e1000_mbx_operations { 848 s32 (*init_params)(struct e1000_hw *hw); 849 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 850 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 851 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 852 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 853 s32 (*check_for_msg)(struct e1000_hw *, u16); 854 s32 (*check_for_ack)(struct e1000_hw *, u16); 855 s32 (*check_for_rst)(struct e1000_hw *, u16); 856 }; 857 858 struct e1000_mbx_stats { 859 u32 msgs_tx; 860 u32 msgs_rx; 861 862 u32 acks; 863 u32 reqs; 864 u32 rsts; 865 }; 866 867 struct e1000_mbx_info { 868 struct e1000_mbx_operations ops; 869 struct e1000_mbx_stats stats; 870 u32 timeout; 871 u32 usec_delay; 872 u16 size; 873 }; 874 875 struct e1000_dev_spec_82541 { 876 enum e1000_dsp_config dsp_config; 877 enum e1000_ffe_config ffe_config; 878 u16 spd_default; 879 bool phy_init_script; 880 }; 881 882 #ifndef NO_82542_SUPPORT 883 struct e1000_dev_spec_82542 { 884 bool dma_fairness; 885 }; 886 887 #endif /* NO_82542_SUPPORT */ 888 struct e1000_dev_spec_82543 { 889 u32 tbi_compatibility; 890 bool dma_fairness; 891 bool init_phy_disabled; 892 }; 893 894 struct e1000_dev_spec_82571 { 895 bool laa_is_present; 896 u32 smb_counter; 897 }; 898 899 struct e1000_dev_spec_80003es2lan { 900 bool mdic_wa_enable; 901 }; 902 903 struct e1000_shadow_ram { 904 u16 value; 905 bool modified; 906 }; 907 908 #define E1000_SHADOW_RAM_WORDS 2048 909 910 struct e1000_dev_spec_ich8lan { 911 bool kmrn_lock_loss_workaround_enabled; 912 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 913 bool nvm_k1_enabled; 914 bool eee_disable; 915 }; 916 917 struct e1000_dev_spec_82575 { 918 bool sgmii_active; 919 bool global_device_reset; 920 bool eee_disable; 921 }; 922 923 struct e1000_dev_spec_vf { 924 u32 vf_number; 925 u32 v2p_mailbox; 926 }; 927 928 struct e1000_hw { 929 void *back; 930 931 u8 *hw_addr; 932 u8 *flash_address; 933 unsigned long io_base; 934 935 struct e1000_mac_info mac; 936 struct e1000_fc_info fc; 937 struct e1000_phy_info phy; 938 struct e1000_nvm_info nvm; 939 struct e1000_bus_info bus; 940 struct e1000_mbx_info mbx; 941 struct e1000_host_mng_dhcp_cookie mng_cookie; 942 943 union { 944 struct e1000_dev_spec_82541 _82541; 945 #ifndef NO_82542_SUPPORT 946 struct e1000_dev_spec_82542 _82542; 947 #endif 948 struct e1000_dev_spec_82543 _82543; 949 struct e1000_dev_spec_82571 _82571; 950 struct e1000_dev_spec_80003es2lan _80003es2lan; 951 struct e1000_dev_spec_ich8lan ich8lan; 952 struct e1000_dev_spec_82575 _82575; 953 struct e1000_dev_spec_vf vf; 954 } dev_spec; 955 956 u16 device_id; 957 u16 subsystem_vendor_id; 958 u16 subsystem_device_id; 959 u16 vendor_id; 960 961 u8 revision_id; 962 }; 963 964 #include "e1000_82541.h" 965 #include "e1000_82543.h" 966 #include "e1000_82571.h" 967 #include "e1000_80003es2lan.h" 968 #include "e1000_ich8lan.h" 969 #include "e1000_82575.h" 970 971 /* These functions must be implemented by drivers */ 972 #ifndef NO_82542_SUPPORT 973 void e1000_pci_clear_mwi(struct e1000_hw *hw); 974 void e1000_pci_set_mwi(struct e1000_hw *hw); 975 #endif 976 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 977 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 978 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 979 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 980 981 #endif 982