1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP 0x10A0 90 #define E1000_DEV_ID_82572EI_COPPER 0x107D 91 #define E1000_DEV_ID_82572EI_FIBER 0x107E 92 #define E1000_DEV_ID_82572EI_SERDES 0x107F 93 #define E1000_DEV_ID_82572EI 0x10B9 94 #define E1000_DEV_ID_82573E 0x108B 95 #define E1000_DEV_ID_82573E_IAMT 0x108C 96 #define E1000_DEV_ID_82573L 0x109A 97 #define E1000_DEV_ID_82574L 0x10D3 98 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 99 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 102 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 103 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 104 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 105 #define E1000_DEV_ID_ICH8_IFE 0x104C 106 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 107 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 108 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 109 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 110 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 111 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 112 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 113 #define E1000_DEV_ID_ICH9_BM 0x10E5 114 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 115 #define E1000_DEV_ID_ICH9_IFE 0x10C0 116 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 117 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 118 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 119 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 120 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 121 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 122 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 123 #define E1000_DEV_ID_82576 0x10C9 124 #define E1000_DEV_ID_82576_FIBER 0x10E6 125 #define E1000_DEV_ID_82576_SERDES 0x10E7 126 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 127 #define E1000_DEV_ID_82576_VF 0x10CA 128 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 129 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 130 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 131 #define E1000_REVISION_0 0 132 #define E1000_REVISION_1 1 133 #define E1000_REVISION_2 2 134 #define E1000_REVISION_3 3 135 #define E1000_REVISION_4 4 136 137 #define E1000_FUNC_0 0 138 #define E1000_FUNC_1 1 139 140 enum e1000_mac_type { 141 e1000_undefined = 0, 142 e1000_82542, 143 e1000_82543, 144 e1000_82544, 145 e1000_82540, 146 e1000_82545, 147 e1000_82545_rev_3, 148 e1000_82546, 149 e1000_82546_rev_3, 150 e1000_82541, 151 e1000_82541_rev_2, 152 e1000_82547, 153 e1000_82547_rev_2, 154 e1000_82571, 155 e1000_82572, 156 e1000_82573, 157 e1000_82574, 158 e1000_80003es2lan, 159 e1000_ich8lan, 160 e1000_ich9lan, 161 e1000_ich10lan, 162 e1000_82575, 163 e1000_82576, 164 e1000_vfadapt, 165 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 166 }; 167 168 enum e1000_media_type { 169 e1000_media_type_unknown = 0, 170 e1000_media_type_copper = 1, 171 e1000_media_type_fiber = 2, 172 e1000_media_type_internal_serdes = 3, 173 e1000_num_media_types 174 }; 175 176 enum e1000_nvm_type { 177 e1000_nvm_unknown = 0, 178 e1000_nvm_none, 179 e1000_nvm_eeprom_spi, 180 e1000_nvm_eeprom_microwire, 181 e1000_nvm_flash_hw, 182 e1000_nvm_flash_sw 183 }; 184 185 enum e1000_nvm_override { 186 e1000_nvm_override_none = 0, 187 e1000_nvm_override_spi_small, 188 e1000_nvm_override_spi_large, 189 e1000_nvm_override_microwire_small, 190 e1000_nvm_override_microwire_large 191 }; 192 193 enum e1000_phy_type { 194 e1000_phy_unknown = 0, 195 e1000_phy_none, 196 e1000_phy_m88, 197 e1000_phy_igp, 198 e1000_phy_igp_2, 199 e1000_phy_gg82563, 200 e1000_phy_igp_3, 201 e1000_phy_ife, 202 e1000_phy_bm, 203 e1000_phy_vf, 204 }; 205 206 enum e1000_bus_type { 207 e1000_bus_type_unknown = 0, 208 e1000_bus_type_pci, 209 e1000_bus_type_pcix, 210 e1000_bus_type_pci_express, 211 e1000_bus_type_reserved 212 }; 213 214 enum e1000_bus_speed { 215 e1000_bus_speed_unknown = 0, 216 e1000_bus_speed_33, 217 e1000_bus_speed_66, 218 e1000_bus_speed_100, 219 e1000_bus_speed_120, 220 e1000_bus_speed_133, 221 e1000_bus_speed_2500, 222 e1000_bus_speed_5000, 223 e1000_bus_speed_reserved 224 }; 225 226 enum e1000_bus_width { 227 e1000_bus_width_unknown = 0, 228 e1000_bus_width_pcie_x1, 229 e1000_bus_width_pcie_x2, 230 e1000_bus_width_pcie_x4 = 4, 231 e1000_bus_width_pcie_x8 = 8, 232 e1000_bus_width_32, 233 e1000_bus_width_64, 234 e1000_bus_width_reserved 235 }; 236 237 enum e1000_1000t_rx_status { 238 e1000_1000t_rx_status_not_ok = 0, 239 e1000_1000t_rx_status_ok, 240 e1000_1000t_rx_status_undefined = 0xFF 241 }; 242 243 enum e1000_rev_polarity { 244 e1000_rev_polarity_normal = 0, 245 e1000_rev_polarity_reversed, 246 e1000_rev_polarity_undefined = 0xFF 247 }; 248 249 enum e1000_fc_mode { 250 e1000_fc_none = 0, 251 e1000_fc_rx_pause, 252 e1000_fc_tx_pause, 253 e1000_fc_full, 254 e1000_fc_default = 0xFF 255 }; 256 257 enum e1000_ffe_config { 258 e1000_ffe_config_enabled = 0, 259 e1000_ffe_config_active, 260 e1000_ffe_config_blocked 261 }; 262 263 enum e1000_dsp_config { 264 e1000_dsp_config_disabled = 0, 265 e1000_dsp_config_enabled, 266 e1000_dsp_config_activated, 267 e1000_dsp_config_undefined = 0xFF 268 }; 269 270 enum e1000_ms_type { 271 e1000_ms_hw_default = 0, 272 e1000_ms_force_master, 273 e1000_ms_force_slave, 274 e1000_ms_auto 275 }; 276 277 enum e1000_smart_speed { 278 e1000_smart_speed_default = 0, 279 e1000_smart_speed_on, 280 e1000_smart_speed_off 281 }; 282 283 /* Receive Descriptor */ 284 struct e1000_rx_desc { 285 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 286 __le16 length; /* Length of data DMAed into data buffer */ 287 __le16 csum; /* Packet checksum */ 288 u8 status; /* Descriptor status */ 289 u8 errors; /* Descriptor Errors */ 290 __le16 special; 291 }; 292 293 /* Receive Descriptor - Extended */ 294 union e1000_rx_desc_extended { 295 struct { 296 __le64 buffer_addr; 297 __le64 reserved; 298 } read; 299 struct { 300 struct { 301 __le32 mrq; /* Multiple Rx Queues */ 302 union { 303 __le32 rss; /* RSS Hash */ 304 struct { 305 __le16 ip_id; /* IP id */ 306 __le16 csum; /* Packet Checksum */ 307 } csum_ip; 308 } hi_dword; 309 } lower; 310 struct { 311 __le32 status_error; /* ext status/error */ 312 __le16 length; 313 __le16 vlan; /* VLAN tag */ 314 } upper; 315 } wb; /* writeback */ 316 }; 317 318 #define MAX_PS_BUFFERS 4 319 /* Receive Descriptor - Packet Split */ 320 union e1000_rx_desc_packet_split { 321 struct { 322 /* one buffer for protocol header(s), three data buffers */ 323 __le64 buffer_addr[MAX_PS_BUFFERS]; 324 } read; 325 struct { 326 struct { 327 __le32 mrq; /* Multiple Rx Queues */ 328 union { 329 __le32 rss; /* RSS Hash */ 330 struct { 331 __le16 ip_id; /* IP id */ 332 __le16 csum; /* Packet Checksum */ 333 } csum_ip; 334 } hi_dword; 335 } lower; 336 struct { 337 __le32 status_error; /* ext status/error */ 338 __le16 length0; /* length of buffer 0 */ 339 __le16 vlan; /* VLAN tag */ 340 } middle; 341 struct { 342 __le16 header_status; 343 __le16 length[3]; /* length of buffers 1-3 */ 344 } upper; 345 __le64 reserved; 346 } wb; /* writeback */ 347 }; 348 349 /* Transmit Descriptor */ 350 struct e1000_tx_desc { 351 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 352 union { 353 __le32 data; 354 struct { 355 __le16 length; /* Data buffer length */ 356 u8 cso; /* Checksum offset */ 357 u8 cmd; /* Descriptor control */ 358 } flags; 359 } lower; 360 union { 361 __le32 data; 362 struct { 363 u8 status; /* Descriptor status */ 364 u8 css; /* Checksum start */ 365 __le16 special; 366 } fields; 367 } upper; 368 }; 369 370 /* Offload Context Descriptor */ 371 struct e1000_context_desc { 372 union { 373 __le32 ip_config; 374 struct { 375 u8 ipcss; /* IP checksum start */ 376 u8 ipcso; /* IP checksum offset */ 377 __le16 ipcse; /* IP checksum end */ 378 } ip_fields; 379 } lower_setup; 380 union { 381 __le32 tcp_config; 382 struct { 383 u8 tucss; /* TCP checksum start */ 384 u8 tucso; /* TCP checksum offset */ 385 __le16 tucse; /* TCP checksum end */ 386 } tcp_fields; 387 } upper_setup; 388 __le32 cmd_and_length; 389 union { 390 __le32 data; 391 struct { 392 u8 status; /* Descriptor status */ 393 u8 hdr_len; /* Header length */ 394 __le16 mss; /* Maximum segment size */ 395 } fields; 396 } tcp_seg_setup; 397 }; 398 399 /* Offload data descriptor */ 400 struct e1000_data_desc { 401 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 402 union { 403 __le32 data; 404 struct { 405 __le16 length; /* Data buffer length */ 406 u8 typ_len_ext; 407 u8 cmd; 408 } flags; 409 } lower; 410 union { 411 __le32 data; 412 struct { 413 u8 status; /* Descriptor status */ 414 u8 popts; /* Packet Options */ 415 __le16 special; 416 } fields; 417 } upper; 418 }; 419 420 /* Statistics counters collected by the MAC */ 421 struct e1000_hw_stats { 422 u64 crcerrs; 423 u64 algnerrc; 424 u64 symerrs; 425 u64 rxerrc; 426 u64 mpc; 427 u64 scc; 428 u64 ecol; 429 u64 mcc; 430 u64 latecol; 431 u64 colc; 432 u64 dc; 433 u64 tncrs; 434 u64 sec; 435 u64 cexterr; 436 u64 rlec; 437 u64 xonrxc; 438 u64 xontxc; 439 u64 xoffrxc; 440 u64 xofftxc; 441 u64 fcruc; 442 u64 prc64; 443 u64 prc127; 444 u64 prc255; 445 u64 prc511; 446 u64 prc1023; 447 u64 prc1522; 448 u64 gprc; 449 u64 bprc; 450 u64 mprc; 451 u64 gptc; 452 u64 gorc; 453 u64 gotc; 454 u64 rnbc; 455 u64 ruc; 456 u64 rfc; 457 u64 roc; 458 u64 rjc; 459 u64 mgprc; 460 u64 mgpdc; 461 u64 mgptc; 462 u64 tor; 463 u64 tot; 464 u64 tpr; 465 u64 tpt; 466 u64 ptc64; 467 u64 ptc127; 468 u64 ptc255; 469 u64 ptc511; 470 u64 ptc1023; 471 u64 ptc1522; 472 u64 mptc; 473 u64 bptc; 474 u64 tsctc; 475 u64 tsctfc; 476 u64 iac; 477 u64 icrxptc; 478 u64 icrxatc; 479 u64 ictxptc; 480 u64 ictxatc; 481 u64 ictxqec; 482 u64 ictxqmtc; 483 u64 icrxdmtc; 484 u64 icrxoc; 485 u64 cbtmpc; 486 u64 htdpmc; 487 u64 cbrdpc; 488 u64 cbrmpc; 489 u64 rpthc; 490 u64 hgptc; 491 u64 htcbdpc; 492 u64 hgorc; 493 u64 hgotc; 494 u64 lenerrs; 495 u64 scvpc; 496 u64 hrmpc; 497 u64 doosync; 498 }; 499 500 struct e1000_vf_stats { 501 u64 base_gprc; 502 u64 base_gptc; 503 u64 base_gorc; 504 u64 base_gotc; 505 u64 base_mprc; 506 u64 base_gotlbc; 507 u64 base_gptlbc; 508 u64 base_gorlbc; 509 u64 base_gprlbc; 510 511 u32 last_gprc; 512 u32 last_gptc; 513 u32 last_gorc; 514 u32 last_gotc; 515 u32 last_mprc; 516 u32 last_gotlbc; 517 u32 last_gptlbc; 518 u32 last_gorlbc; 519 u32 last_gprlbc; 520 521 u64 gprc; 522 u64 gptc; 523 u64 gorc; 524 u64 gotc; 525 u64 mprc; 526 u64 gotlbc; 527 u64 gptlbc; 528 u64 gorlbc; 529 u64 gprlbc; 530 }; 531 532 struct e1000_phy_stats { 533 u32 idle_errors; 534 u32 receive_errors; 535 }; 536 537 struct e1000_host_mng_dhcp_cookie { 538 u32 signature; 539 u8 status; 540 u8 reserved0; 541 u16 vlan_id; 542 u32 reserved1; 543 u16 reserved2; 544 u8 reserved3; 545 u8 checksum; 546 }; 547 548 /* Host Interface "Rev 1" */ 549 struct e1000_host_command_header { 550 u8 command_id; 551 u8 command_length; 552 u8 command_options; 553 u8 checksum; 554 }; 555 556 #define E1000_HI_MAX_DATA_LENGTH 252 557 struct e1000_host_command_info { 558 struct e1000_host_command_header command_header; 559 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 560 }; 561 562 /* Host Interface "Rev 2" */ 563 struct e1000_host_mng_command_header { 564 u8 command_id; 565 u8 checksum; 566 u16 reserved1; 567 u16 reserved2; 568 u16 command_length; 569 }; 570 571 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 572 struct e1000_host_mng_command_info { 573 struct e1000_host_mng_command_header command_header; 574 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 575 }; 576 577 #include "e1000_mac.h" 578 #include "e1000_phy.h" 579 #include "e1000_nvm.h" 580 #include "e1000_manage.h" 581 582 struct e1000_mac_operations { 583 /* Function pointers for the MAC. */ 584 s32 (*init_params)(struct e1000_hw *); 585 s32 (*blink_led)(struct e1000_hw *); 586 s32 (*check_for_link)(struct e1000_hw *); 587 bool (*check_mng_mode)(struct e1000_hw *hw); 588 s32 (*cleanup_led)(struct e1000_hw *); 589 void (*clear_hw_cntrs)(struct e1000_hw *); 590 void (*clear_vfta)(struct e1000_hw *); 591 s32 (*get_bus_info)(struct e1000_hw *); 592 void (*set_lan_id)(struct e1000_hw *); 593 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 594 s32 (*led_on)(struct e1000_hw *); 595 s32 (*led_off)(struct e1000_hw *); 596 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32); 597 s32 (*reset_hw)(struct e1000_hw *); 598 s32 (*init_hw)(struct e1000_hw *); 599 void (*shutdown_serdes)(struct e1000_hw *); 600 s32 (*setup_link)(struct e1000_hw *); 601 s32 (*setup_physical_interface)(struct e1000_hw *); 602 s32 (*setup_led)(struct e1000_hw *); 603 void (*write_vfta)(struct e1000_hw *, u32, u32); 604 void (*mta_set)(struct e1000_hw *, u32); 605 void (*config_collision_dist)(struct e1000_hw *); 606 void (*rar_set)(struct e1000_hw *, u8*, u32); 607 s32 (*read_mac_addr)(struct e1000_hw *); 608 s32 (*validate_mdi_setting)(struct e1000_hw *); 609 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); 610 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 611 struct e1000_host_mng_command_header*); 612 s32 (*mng_enable_host_if)(struct e1000_hw *); 613 s32 (*wait_autoneg)(struct e1000_hw *); 614 }; 615 616 struct e1000_phy_operations { 617 s32 (*init_params)(struct e1000_hw *); 618 s32 (*acquire)(struct e1000_hw *); 619 s32 (*cfg_on_link_up)(struct e1000_hw *); 620 s32 (*check_polarity)(struct e1000_hw *); 621 s32 (*check_reset_block)(struct e1000_hw *); 622 s32 (*commit)(struct e1000_hw *); 623 s32 (*force_speed_duplex)(struct e1000_hw *); 624 s32 (*get_cfg_done)(struct e1000_hw *hw); 625 s32 (*get_cable_length)(struct e1000_hw *); 626 s32 (*get_info)(struct e1000_hw *); 627 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 628 void (*release)(struct e1000_hw *); 629 s32 (*reset)(struct e1000_hw *); 630 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 631 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 632 s32 (*write_reg)(struct e1000_hw *, u32, u16); 633 void (*power_up)(struct e1000_hw *); 634 void (*power_down)(struct e1000_hw *); 635 }; 636 637 struct e1000_nvm_operations { 638 s32 (*init_params)(struct e1000_hw *); 639 s32 (*acquire)(struct e1000_hw *); 640 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 641 void (*release)(struct e1000_hw *); 642 void (*reload)(struct e1000_hw *); 643 s32 (*update)(struct e1000_hw *); 644 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 645 s32 (*validate)(struct e1000_hw *); 646 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 647 }; 648 649 struct e1000_mac_info { 650 struct e1000_mac_operations ops; 651 u8 addr[6]; 652 u8 perm_addr[6]; 653 654 enum e1000_mac_type type; 655 656 u32 collision_delta; 657 u32 ledctl_default; 658 u32 ledctl_mode1; 659 u32 ledctl_mode2; 660 u32 mc_filter_type; 661 u32 tx_packet_delta; 662 u32 txcw; 663 664 u16 current_ifs_val; 665 u16 ifs_max_val; 666 u16 ifs_min_val; 667 u16 ifs_ratio; 668 u16 ifs_step_size; 669 u16 mta_reg_count; 670 u16 rar_entry_count; 671 672 u8 forced_speed_duplex; 673 674 bool adaptive_ifs; 675 bool arc_subsystem_valid; 676 bool asf_firmware_present; 677 bool autoneg; 678 bool autoneg_failed; 679 bool get_link_status; 680 bool in_ifs_mode; 681 bool report_tx_early; 682 bool serdes_has_link; 683 bool tx_pkt_filtering; 684 }; 685 686 struct e1000_phy_info { 687 struct e1000_phy_operations ops; 688 enum e1000_phy_type type; 689 690 enum e1000_1000t_rx_status local_rx; 691 enum e1000_1000t_rx_status remote_rx; 692 enum e1000_ms_type ms_type; 693 enum e1000_ms_type original_ms_type; 694 enum e1000_rev_polarity cable_polarity; 695 enum e1000_smart_speed smart_speed; 696 697 u32 addr; 698 u32 id; 699 u32 reset_delay_us; /* in usec */ 700 u32 revision; 701 702 enum e1000_media_type media_type; 703 704 u16 autoneg_advertised; 705 u16 autoneg_mask; 706 u16 cable_length; 707 u16 max_cable_length; 708 u16 min_cable_length; 709 710 u8 mdix; 711 712 bool disable_polarity_correction; 713 bool is_mdix; 714 bool polarity_correction; 715 bool reset_disable; 716 bool speed_downgraded; 717 bool autoneg_wait_to_complete; 718 }; 719 720 struct e1000_nvm_info { 721 struct e1000_nvm_operations ops; 722 enum e1000_nvm_type type; 723 enum e1000_nvm_override override; 724 725 u32 flash_bank_size; 726 u32 flash_base_addr; 727 728 u16 word_size; 729 u16 delay_usec; 730 u16 address_bits; 731 u16 opcode_bits; 732 u16 page_size; 733 }; 734 735 struct e1000_bus_info { 736 enum e1000_bus_type type; 737 enum e1000_bus_speed speed; 738 enum e1000_bus_width width; 739 740 u16 func; 741 u16 pci_cmd_word; 742 }; 743 744 struct e1000_fc_info { 745 u32 high_water; /* Flow control high-water mark */ 746 u32 low_water; /* Flow control low-water mark */ 747 u16 pause_time; /* Flow control pause timer */ 748 bool send_xon; /* Flow control send XON */ 749 bool strict_ieee; /* Strict IEEE mode */ 750 enum e1000_fc_mode current_mode; /* FC mode in effect */ 751 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 752 }; 753 754 struct e1000_dev_spec_82541 { 755 enum e1000_dsp_config dsp_config; 756 enum e1000_ffe_config ffe_config; 757 u16 spd_default; 758 bool phy_init_script; 759 }; 760 761 struct e1000_dev_spec_82542 { 762 bool dma_fairness; 763 }; 764 765 struct e1000_dev_spec_82543 { 766 u32 tbi_compatibility; 767 bool dma_fairness; 768 bool init_phy_disabled; 769 }; 770 771 struct e1000_dev_spec_82571 { 772 bool laa_is_present; 773 }; 774 775 struct e1000_shadow_ram { 776 u16 value; 777 bool modified; 778 }; 779 780 #define E1000_SHADOW_RAM_WORDS 2048 781 782 struct e1000_dev_spec_ich8lan { 783 bool kmrn_lock_loss_workaround_enabled; 784 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 785 }; 786 787 struct e1000_dev_spec_82575 { 788 bool sgmii_active; 789 }; 790 791 struct e1000_dev_spec_vf { 792 u32 vf_number; 793 }; 794 795 struct e1000_hw { 796 void *back; 797 798 u8 *hw_addr; 799 u8 *flash_address; 800 unsigned long io_base; 801 802 struct e1000_mac_info mac; 803 struct e1000_fc_info fc; 804 struct e1000_phy_info phy; 805 struct e1000_nvm_info nvm; 806 struct e1000_bus_info bus; 807 struct e1000_host_mng_dhcp_cookie mng_cookie; 808 809 union { 810 struct e1000_dev_spec_82541 _82541; 811 struct e1000_dev_spec_82542 _82542; 812 struct e1000_dev_spec_82543 _82543; 813 struct e1000_dev_spec_82571 _82571; 814 struct e1000_dev_spec_ich8lan ich8lan; 815 struct e1000_dev_spec_82575 _82575; 816 struct e1000_dev_spec_vf vf; 817 } dev_spec; 818 819 u16 device_id; 820 u16 subsystem_vendor_id; 821 u16 subsystem_device_id; 822 u16 vendor_id; 823 824 u8 revision_id; 825 }; 826 827 #include "e1000_82541.h" 828 #include "e1000_82543.h" 829 #include "e1000_82571.h" 830 #include "e1000_80003es2lan.h" 831 #include "e1000_ich8lan.h" 832 #include "e1000_82575.h" 833 834 /* These functions must be implemented by drivers */ 835 void e1000_pci_clear_mwi(struct e1000_hw *hw); 836 void e1000_pci_set_mwi(struct e1000_hw *hw); 837 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 838 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 839 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 840 841 #endif 842