xref: /dragonfly/sys/dev/netif/ig_hal/e1000_manage.h (revision 2038fb68)
1 /******************************************************************************
2 
3   Copyright (c) 2001-2008, Intel Corporation
4   All rights reserved.
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6   Redistribution and use in source and binary forms, with or without
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18       this software without specific prior written permission.
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32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _E1000_MANAGE_H_
36 #define _E1000_MANAGE_H_
37 
38 bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
39 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
40 s32  e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
41 s32  e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
42                                      u16 length, u16 offset, u8 *sum);
43 s32  e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
44                                     struct e1000_host_mng_command_header *hdr);
45 s32  e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
46                                        u8 *buffer, u16 length);
47 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
48 
49 enum e1000_mng_mode {
50 	e1000_mng_mode_none = 0,
51 	e1000_mng_mode_asf,
52 	e1000_mng_mode_pt,
53 	e1000_mng_mode_ipmi,
54 	e1000_mng_mode_host_if_only
55 };
56 
57 #define E1000_FACTPS_MNGCG    0x20000000
58 
59 #define E1000_FWSM_MODE_MASK  0xE
60 #define E1000_FWSM_MODE_SHIFT 1
61 
62 #define E1000_MNG_IAMT_MODE                  0x3
63 #define E1000_MNG_DHCP_COOKIE_LENGTH         0x10
64 #define E1000_MNG_DHCP_COOKIE_OFFSET         0x6F0
65 #define E1000_MNG_DHCP_COMMAND_TIMEOUT       10
66 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD        64
67 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
68 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN    0x2
69 
70 #define E1000_VFTA_ENTRY_SHIFT               5
71 #define E1000_VFTA_ENTRY_MASK                0x7F
72 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK      0x1F
73 
74 #define E1000_HI_MAX_BLOCK_BYTE_LENGTH       1792 /* Num of bytes in range */
75 #define E1000_HI_MAX_BLOCK_DWORD_LENGTH      448 /* Num of dwords in range */
76 #define E1000_HI_COMMAND_TIMEOUT             500 /* Process HI command limit */
77 
78 #define E1000_HICR_EN              0x01  /* Enable bit - RO */
79 /* Driver sets this bit when done to put command in RAM */
80 #define E1000_HICR_C               0x02
81 #define E1000_HICR_SV              0x04  /* Status Validity */
82 #define E1000_HICR_FW_RESET_ENABLE 0x40
83 #define E1000_HICR_FW_RESET        0x80
84 
85 /* Intel(R) Active Management Technology signature */
86 #define E1000_IAMT_SIGNATURE  0x544D4149
87 
88 #endif
89