1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 #include "e1000_api.h" 36 37 static s32 e1000_wait_autoneg(struct e1000_hw *hw); 38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read, bool page_set); 40 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44 /* Cable length tables */ 45 static const u16 e1000_m88_cable_length_table[] = { 46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 (sizeof(e1000_m88_cable_length_table) / \ 49 sizeof(e1000_m88_cable_length_table[0])) 50 51 static const u16 e1000_igp_2_cable_length_table[] = { 52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 59 124}; 60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61 (sizeof(e1000_igp_2_cable_length_table) / \ 62 sizeof(e1000_igp_2_cable_length_table[0])) 63 64 /** 65 * e1000_init_phy_ops_generic - Initialize PHY function pointers 66 * @hw: pointer to the HW structure 67 * 68 * Setups up the function pointers to no-op functions 69 **/ 70 void e1000_init_phy_ops_generic(struct e1000_hw *hw) 71 { 72 struct e1000_phy_info *phy = &hw->phy; 73 DEBUGFUNC("e1000_init_phy_ops_generic"); 74 75 /* Initialize function pointers */ 76 phy->ops.init_params = e1000_null_ops_generic; 77 phy->ops.acquire = e1000_null_ops_generic; 78 phy->ops.check_polarity = e1000_null_ops_generic; 79 phy->ops.check_reset_block = e1000_null_ops_generic; 80 phy->ops.commit = e1000_null_ops_generic; 81 phy->ops.force_speed_duplex = e1000_null_ops_generic; 82 phy->ops.get_cfg_done = e1000_null_ops_generic; 83 phy->ops.get_cable_length = e1000_null_ops_generic; 84 phy->ops.get_info = e1000_null_ops_generic; 85 phy->ops.set_page = e1000_null_set_page; 86 phy->ops.read_reg = e1000_null_read_reg; 87 phy->ops.read_reg_locked = e1000_null_read_reg; 88 phy->ops.read_reg_page = e1000_null_read_reg; 89 phy->ops.release = e1000_null_phy_generic; 90 phy->ops.reset = e1000_null_ops_generic; 91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 93 phy->ops.write_reg = e1000_null_write_reg; 94 phy->ops.write_reg_locked = e1000_null_write_reg; 95 phy->ops.write_reg_page = e1000_null_write_reg; 96 phy->ops.power_up = e1000_null_phy_generic; 97 phy->ops.power_down = e1000_null_phy_generic; 98 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 99 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null; 100 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null; 101 } 102 103 /** 104 * e1000_null_set_page - No-op function, return 0 105 * @hw: pointer to the HW structure 106 **/ 107 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw, 108 u16 E1000_UNUSEDARG data) 109 { 110 DEBUGFUNC("e1000_null_set_page"); 111 return E1000_SUCCESS; 112 } 113 114 /** 115 * e1000_null_read_reg - No-op function, return 0 116 * @hw: pointer to the HW structure 117 **/ 118 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw, 119 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data) 120 { 121 DEBUGFUNC("e1000_null_read_reg"); 122 return E1000_SUCCESS; 123 } 124 125 /** 126 * e1000_null_phy_generic - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw) 130 { 131 DEBUGFUNC("e1000_null_phy_generic"); 132 return; 133 } 134 135 /** 136 * e1000_null_lplu_state - No-op function, return 0 137 * @hw: pointer to the HW structure 138 **/ 139 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw, 140 bool E1000_UNUSEDARG active) 141 { 142 DEBUGFUNC("e1000_null_lplu_state"); 143 return E1000_SUCCESS; 144 } 145 146 /** 147 * e1000_null_write_reg - No-op function, return 0 148 * @hw: pointer to the HW structure 149 **/ 150 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw, 151 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data) 152 { 153 DEBUGFUNC("e1000_null_write_reg"); 154 return E1000_SUCCESS; 155 } 156 157 /** 158 * e1000_read_i2c_byte_null - No-op function, return 0 159 * @hw: pointer to hardware structure 160 * @byte_offset: byte offset to write 161 * @dev_addr: device address 162 * @data: data value read 163 * 164 **/ 165 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw, 166 u8 E1000_UNUSEDARG byte_offset, 167 u8 E1000_UNUSEDARG dev_addr, 168 u8 E1000_UNUSEDARG *data) 169 { 170 DEBUGFUNC("e1000_read_i2c_byte_null"); 171 return E1000_SUCCESS; 172 } 173 174 /** 175 * e1000_write_i2c_byte_null - No-op function, return 0 176 * @hw: pointer to hardware structure 177 * @byte_offset: byte offset to write 178 * @dev_addr: device address 179 * @data: data value to write 180 * 181 **/ 182 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw, 183 u8 E1000_UNUSEDARG byte_offset, 184 u8 E1000_UNUSEDARG dev_addr, 185 u8 E1000_UNUSEDARG data) 186 { 187 DEBUGFUNC("e1000_write_i2c_byte_null"); 188 return E1000_SUCCESS; 189 } 190 191 /** 192 * e1000_check_reset_block_generic - Check if PHY reset is blocked 193 * @hw: pointer to the HW structure 194 * 195 * Read the PHY management control register and check whether a PHY reset 196 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 197 * return E1000_BLK_PHY_RESET (12). 198 **/ 199 s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 200 { 201 u32 manc; 202 203 DEBUGFUNC("e1000_check_reset_block"); 204 205 manc = E1000_READ_REG(hw, E1000_MANC); 206 207 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 208 E1000_BLK_PHY_RESET : E1000_SUCCESS; 209 } 210 211 /** 212 * e1000_get_phy_id - Retrieve the PHY ID and revision 213 * @hw: pointer to the HW structure 214 * 215 * Reads the PHY registers and stores the PHY ID and possibly the PHY 216 * revision in the hardware structure. 217 **/ 218 s32 e1000_get_phy_id(struct e1000_hw *hw) 219 { 220 struct e1000_phy_info *phy = &hw->phy; 221 s32 ret_val = E1000_SUCCESS; 222 u16 phy_id; 223 u16 retry_count = 0; 224 225 DEBUGFUNC("e1000_get_phy_id"); 226 227 if (!phy->ops.read_reg) 228 return E1000_SUCCESS; 229 230 while (retry_count < 2) { 231 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 232 if (ret_val) 233 return ret_val; 234 235 phy->id = (u32)(phy_id << 16); 236 usec_delay(20); 237 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 238 if (ret_val) 239 return ret_val; 240 241 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 242 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 243 244 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 245 return E1000_SUCCESS; 246 247 retry_count++; 248 } 249 250 return E1000_SUCCESS; 251 } 252 253 /** 254 * e1000_phy_reset_dsp_generic - Reset PHY DSP 255 * @hw: pointer to the HW structure 256 * 257 * Reset the digital signal processor. 258 **/ 259 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 260 { 261 s32 ret_val; 262 263 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 264 265 if (!hw->phy.ops.write_reg) 266 return E1000_SUCCESS; 267 268 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 269 if (ret_val) 270 return ret_val; 271 272 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 273 } 274 275 /** 276 * e1000_read_phy_reg_mdic - Read MDI control register 277 * @hw: pointer to the HW structure 278 * @offset: register offset to be read 279 * @data: pointer to the read data 280 * 281 * Reads the MDI control register in the PHY at offset and stores the 282 * information read to data. 283 **/ 284 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 285 { 286 struct e1000_phy_info *phy = &hw->phy; 287 u32 i, mdic = 0; 288 289 DEBUGFUNC("e1000_read_phy_reg_mdic"); 290 291 if (offset > MAX_PHY_REG_ADDRESS) { 292 DEBUGOUT1("PHY Address %d is out of range\n", offset); 293 return -E1000_ERR_PARAM; 294 } 295 296 /* Set up Op-code, Phy Address, and register offset in the MDI 297 * Control register. The MAC will take care of interfacing with the 298 * PHY to retrieve the desired data. 299 */ 300 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 301 (phy->addr << E1000_MDIC_PHY_SHIFT) | 302 (E1000_MDIC_OP_READ)); 303 304 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 305 306 /* Poll the ready bit to see if the MDI read completed 307 * Increasing the time out as testing showed failures with 308 * the lower time out 309 */ 310 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 311 usec_delay_irq(50); 312 mdic = E1000_READ_REG(hw, E1000_MDIC); 313 if (mdic & E1000_MDIC_READY) 314 break; 315 } 316 if (!(mdic & E1000_MDIC_READY)) { 317 DEBUGOUT("MDI Read did not complete\n"); 318 return -E1000_ERR_PHY; 319 } 320 if (mdic & E1000_MDIC_ERROR) { 321 DEBUGOUT("MDI Error\n"); 322 return -E1000_ERR_PHY; 323 } 324 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 325 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", 326 offset, 327 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 328 return -E1000_ERR_PHY; 329 } 330 *data = (u16) mdic; 331 332 /* Allow some time after each MDIC transaction to avoid 333 * reading duplicate data in the next MDIC transaction. 334 */ 335 if (hw->mac.type == e1000_pch2lan) 336 usec_delay_irq(100); 337 338 return E1000_SUCCESS; 339 } 340 341 /** 342 * e1000_write_phy_reg_mdic - Write MDI control register 343 * @hw: pointer to the HW structure 344 * @offset: register offset to write to 345 * @data: data to write to register at offset 346 * 347 * Writes data to MDI control register in the PHY at offset. 348 **/ 349 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 350 { 351 struct e1000_phy_info *phy = &hw->phy; 352 u32 i, mdic = 0; 353 354 DEBUGFUNC("e1000_write_phy_reg_mdic"); 355 356 if (offset > MAX_PHY_REG_ADDRESS) { 357 DEBUGOUT1("PHY Address %d is out of range\n", offset); 358 return -E1000_ERR_PARAM; 359 } 360 361 /* Set up Op-code, Phy Address, and register offset in the MDI 362 * Control register. The MAC will take care of interfacing with the 363 * PHY to retrieve the desired data. 364 */ 365 mdic = (((u32)data) | 366 (offset << E1000_MDIC_REG_SHIFT) | 367 (phy->addr << E1000_MDIC_PHY_SHIFT) | 368 (E1000_MDIC_OP_WRITE)); 369 370 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 371 372 /* Poll the ready bit to see if the MDI read completed 373 * Increasing the time out as testing showed failures with 374 * the lower time out 375 */ 376 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 377 usec_delay_irq(50); 378 mdic = E1000_READ_REG(hw, E1000_MDIC); 379 if (mdic & E1000_MDIC_READY) 380 break; 381 } 382 if (!(mdic & E1000_MDIC_READY)) { 383 DEBUGOUT("MDI Write did not complete\n"); 384 return -E1000_ERR_PHY; 385 } 386 if (mdic & E1000_MDIC_ERROR) { 387 DEBUGOUT("MDI Error\n"); 388 return -E1000_ERR_PHY; 389 } 390 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 391 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n", 392 offset, 393 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 394 return -E1000_ERR_PHY; 395 } 396 397 /* Allow some time after each MDIC transaction to avoid 398 * reading duplicate data in the next MDIC transaction. 399 */ 400 if (hw->mac.type == e1000_pch2lan) 401 usec_delay_irq(100); 402 403 return E1000_SUCCESS; 404 } 405 406 /** 407 * e1000_read_phy_reg_i2c - Read PHY register using i2c 408 * @hw: pointer to the HW structure 409 * @offset: register offset to be read 410 * @data: pointer to the read data 411 * 412 * Reads the PHY register at offset using the i2c interface and stores the 413 * retrieved information in data. 414 **/ 415 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 416 { 417 struct e1000_phy_info *phy = &hw->phy; 418 u32 i, i2ccmd = 0; 419 420 DEBUGFUNC("e1000_read_phy_reg_i2c"); 421 422 /* Set up Op-code, Phy Address, and register address in the I2CCMD 423 * register. The MAC will take care of interfacing with the 424 * PHY to retrieve the desired data. 425 */ 426 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 427 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 428 (E1000_I2CCMD_OPCODE_READ)); 429 430 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 431 432 /* Poll the ready bit to see if the I2C read completed */ 433 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 434 usec_delay(50); 435 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 436 if (i2ccmd & E1000_I2CCMD_READY) 437 break; 438 } 439 if (!(i2ccmd & E1000_I2CCMD_READY)) { 440 DEBUGOUT("I2CCMD Read did not complete\n"); 441 return -E1000_ERR_PHY; 442 } 443 if (i2ccmd & E1000_I2CCMD_ERROR) { 444 DEBUGOUT("I2CCMD Error bit set\n"); 445 return -E1000_ERR_PHY; 446 } 447 448 /* Need to byte-swap the 16-bit value. */ 449 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 450 451 return E1000_SUCCESS; 452 } 453 454 /** 455 * e1000_write_phy_reg_i2c - Write PHY register using i2c 456 * @hw: pointer to the HW structure 457 * @offset: register offset to write to 458 * @data: data to write at register offset 459 * 460 * Writes the data to PHY register at the offset using the i2c interface. 461 **/ 462 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 463 { 464 struct e1000_phy_info *phy = &hw->phy; 465 u32 i, i2ccmd = 0; 466 u16 phy_data_swapped; 467 468 DEBUGFUNC("e1000_write_phy_reg_i2c"); 469 470 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 471 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 472 DEBUGOUT1("PHY I2C Address %d is out of range.\n", 473 hw->phy.addr); 474 return -E1000_ERR_CONFIG; 475 } 476 477 /* Swap the data bytes for the I2C interface */ 478 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 479 480 /* Set up Op-code, Phy Address, and register address in the I2CCMD 481 * register. The MAC will take care of interfacing with the 482 * PHY to retrieve the desired data. 483 */ 484 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 485 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 486 E1000_I2CCMD_OPCODE_WRITE | 487 phy_data_swapped); 488 489 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 490 491 /* Poll the ready bit to see if the I2C read completed */ 492 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 493 usec_delay(50); 494 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 495 if (i2ccmd & E1000_I2CCMD_READY) 496 break; 497 } 498 if (!(i2ccmd & E1000_I2CCMD_READY)) { 499 DEBUGOUT("I2CCMD Write did not complete\n"); 500 return -E1000_ERR_PHY; 501 } 502 if (i2ccmd & E1000_I2CCMD_ERROR) { 503 DEBUGOUT("I2CCMD Error bit set\n"); 504 return -E1000_ERR_PHY; 505 } 506 507 return E1000_SUCCESS; 508 } 509 510 /** 511 * e1000_read_sfp_data_byte - Reads SFP module data. 512 * @hw: pointer to the HW structure 513 * @offset: byte location offset to be read 514 * @data: read data buffer pointer 515 * 516 * Reads one byte from SFP module data stored 517 * in SFP resided EEPROM memory or SFP diagnostic area. 518 * Function should be called with 519 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 520 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 521 * access 522 **/ 523 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 524 { 525 u32 i = 0; 526 u32 i2ccmd = 0; 527 u32 data_local = 0; 528 529 DEBUGFUNC("e1000_read_sfp_data_byte"); 530 531 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 532 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 533 return -E1000_ERR_PHY; 534 } 535 536 /* Set up Op-code, EEPROM Address,in the I2CCMD 537 * register. The MAC will take care of interfacing with the 538 * EEPROM to retrieve the desired data. 539 */ 540 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 541 E1000_I2CCMD_OPCODE_READ); 542 543 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 544 545 /* Poll the ready bit to see if the I2C read completed */ 546 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 547 usec_delay(50); 548 data_local = E1000_READ_REG(hw, E1000_I2CCMD); 549 if (data_local & E1000_I2CCMD_READY) 550 break; 551 } 552 if (!(data_local & E1000_I2CCMD_READY)) { 553 DEBUGOUT("I2CCMD Read did not complete\n"); 554 return -E1000_ERR_PHY; 555 } 556 if (data_local & E1000_I2CCMD_ERROR) { 557 DEBUGOUT("I2CCMD Error bit set\n"); 558 return -E1000_ERR_PHY; 559 } 560 *data = (u8) data_local & 0xFF; 561 562 return E1000_SUCCESS; 563 } 564 565 /** 566 * e1000_write_sfp_data_byte - Writes SFP module data. 567 * @hw: pointer to the HW structure 568 * @offset: byte location offset to write to 569 * @data: data to write 570 * 571 * Writes one byte to SFP module data stored 572 * in SFP resided EEPROM memory or SFP diagnostic area. 573 * Function should be called with 574 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 575 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 576 * access 577 **/ 578 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) 579 { 580 u32 i = 0; 581 u32 i2ccmd = 0; 582 u32 data_local = 0; 583 584 DEBUGFUNC("e1000_write_sfp_data_byte"); 585 586 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 587 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 588 return -E1000_ERR_PHY; 589 } 590 /* The programming interface is 16 bits wide 591 * so we need to read the whole word first 592 * then update appropriate byte lane and write 593 * the updated word back. 594 */ 595 /* Set up Op-code, EEPROM Address,in the I2CCMD 596 * register. The MAC will take care of interfacing 597 * with an EEPROM to write the data given. 598 */ 599 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 600 E1000_I2CCMD_OPCODE_READ); 601 /* Set a command to read single word */ 602 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 603 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 604 usec_delay(50); 605 /* Poll the ready bit to see if lastly 606 * launched I2C operation completed 607 */ 608 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 609 if (i2ccmd & E1000_I2CCMD_READY) { 610 /* Check if this is READ or WRITE phase */ 611 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) == 612 E1000_I2CCMD_OPCODE_READ) { 613 /* Write the selected byte 614 * lane and update whole word 615 */ 616 data_local = i2ccmd & 0xFF00; 617 data_local |= data; 618 i2ccmd = ((offset << 619 E1000_I2CCMD_REG_ADDR_SHIFT) | 620 E1000_I2CCMD_OPCODE_WRITE | data_local); 621 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 622 } else { 623 break; 624 } 625 } 626 } 627 if (!(i2ccmd & E1000_I2CCMD_READY)) { 628 DEBUGOUT("I2CCMD Write did not complete\n"); 629 return -E1000_ERR_PHY; 630 } 631 if (i2ccmd & E1000_I2CCMD_ERROR) { 632 DEBUGOUT("I2CCMD Error bit set\n"); 633 return -E1000_ERR_PHY; 634 } 635 return E1000_SUCCESS; 636 } 637 638 /** 639 * e1000_read_phy_reg_m88 - Read m88 PHY register 640 * @hw: pointer to the HW structure 641 * @offset: register offset to be read 642 * @data: pointer to the read data 643 * 644 * Acquires semaphore, if necessary, then reads the PHY register at offset 645 * and storing the retrieved information in data. Release any acquired 646 * semaphores before exiting. 647 **/ 648 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 649 { 650 s32 ret_val; 651 652 DEBUGFUNC("e1000_read_phy_reg_m88"); 653 654 if (!hw->phy.ops.acquire) 655 return E1000_SUCCESS; 656 657 ret_val = hw->phy.ops.acquire(hw); 658 if (ret_val) 659 return ret_val; 660 661 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 662 data); 663 664 hw->phy.ops.release(hw); 665 666 return ret_val; 667 } 668 669 /** 670 * e1000_write_phy_reg_m88 - Write m88 PHY register 671 * @hw: pointer to the HW structure 672 * @offset: register offset to write to 673 * @data: data to write at register offset 674 * 675 * Acquires semaphore, if necessary, then writes the data to PHY register 676 * at the offset. Release any acquired semaphores before exiting. 677 **/ 678 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 679 { 680 s32 ret_val; 681 682 DEBUGFUNC("e1000_write_phy_reg_m88"); 683 684 if (!hw->phy.ops.acquire) 685 return E1000_SUCCESS; 686 687 ret_val = hw->phy.ops.acquire(hw); 688 if (ret_val) 689 return ret_val; 690 691 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 692 data); 693 694 hw->phy.ops.release(hw); 695 696 return ret_val; 697 } 698 699 /** 700 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 701 * @hw: pointer to the HW structure 702 * @page: page to set (shifted left when necessary) 703 * 704 * Sets PHY page required for PHY register access. Assumes semaphore is 705 * already acquired. Note, this function sets phy.addr to 1 so the caller 706 * must set it appropriately (if necessary) after this function returns. 707 **/ 708 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 709 { 710 DEBUGFUNC("e1000_set_page_igp"); 711 712 DEBUGOUT1("Setting page 0x%x\n", page); 713 714 hw->phy.addr = 1; 715 716 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 717 } 718 719 /** 720 * __e1000_read_phy_reg_igp - Read igp PHY register 721 * @hw: pointer to the HW structure 722 * @offset: register offset to be read 723 * @data: pointer to the read data 724 * @locked: semaphore has already been acquired or not 725 * 726 * Acquires semaphore, if necessary, then reads the PHY register at offset 727 * and stores the retrieved information in data. Release any acquired 728 * semaphores before exiting. 729 **/ 730 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 731 bool locked) 732 { 733 s32 ret_val = E1000_SUCCESS; 734 735 DEBUGFUNC("__e1000_read_phy_reg_igp"); 736 737 if (!locked) { 738 if (!hw->phy.ops.acquire) 739 return E1000_SUCCESS; 740 741 ret_val = hw->phy.ops.acquire(hw); 742 if (ret_val) 743 return ret_val; 744 } 745 746 if (offset > MAX_PHY_MULTI_PAGE_REG) 747 ret_val = e1000_write_phy_reg_mdic(hw, 748 IGP01E1000_PHY_PAGE_SELECT, 749 (u16)offset); 750 if (!ret_val) 751 ret_val = e1000_read_phy_reg_mdic(hw, 752 MAX_PHY_REG_ADDRESS & offset, 753 data); 754 if (!locked) 755 hw->phy.ops.release(hw); 756 757 return ret_val; 758 } 759 760 /** 761 * e1000_read_phy_reg_igp - Read igp PHY register 762 * @hw: pointer to the HW structure 763 * @offset: register offset to be read 764 * @data: pointer to the read data 765 * 766 * Acquires semaphore then reads the PHY register at offset and stores the 767 * retrieved information in data. 768 * Release the acquired semaphore before exiting. 769 **/ 770 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 771 { 772 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); 773 } 774 775 /** 776 * e1000_read_phy_reg_igp_locked - Read igp PHY register 777 * @hw: pointer to the HW structure 778 * @offset: register offset to be read 779 * @data: pointer to the read data 780 * 781 * Reads the PHY register at offset and stores the retrieved information 782 * in data. Assumes semaphore already acquired. 783 **/ 784 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 785 { 786 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); 787 } 788 789 /** 790 * e1000_write_phy_reg_igp - Write igp PHY register 791 * @hw: pointer to the HW structure 792 * @offset: register offset to write to 793 * @data: data to write at register offset 794 * @locked: semaphore has already been acquired or not 795 * 796 * Acquires semaphore, if necessary, then writes the data to PHY register 797 * at the offset. Release any acquired semaphores before exiting. 798 **/ 799 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 800 bool locked) 801 { 802 s32 ret_val = E1000_SUCCESS; 803 804 DEBUGFUNC("e1000_write_phy_reg_igp"); 805 806 if (!locked) { 807 if (!hw->phy.ops.acquire) 808 return E1000_SUCCESS; 809 810 ret_val = hw->phy.ops.acquire(hw); 811 if (ret_val) 812 return ret_val; 813 } 814 815 if (offset > MAX_PHY_MULTI_PAGE_REG) 816 ret_val = e1000_write_phy_reg_mdic(hw, 817 IGP01E1000_PHY_PAGE_SELECT, 818 (u16)offset); 819 if (!ret_val) 820 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & 821 offset, 822 data); 823 if (!locked) 824 hw->phy.ops.release(hw); 825 826 return ret_val; 827 } 828 829 /** 830 * e1000_write_phy_reg_igp - Write igp PHY register 831 * @hw: pointer to the HW structure 832 * @offset: register offset to write to 833 * @data: data to write at register offset 834 * 835 * Acquires semaphore then writes the data to PHY register 836 * at the offset. Release any acquired semaphores before exiting. 837 **/ 838 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 839 { 840 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); 841 } 842 843 /** 844 * e1000_write_phy_reg_igp_locked - Write igp PHY register 845 * @hw: pointer to the HW structure 846 * @offset: register offset to write to 847 * @data: data to write at register offset 848 * 849 * Writes the data to PHY register at the offset. 850 * Assumes semaphore already acquired. 851 **/ 852 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 853 { 854 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); 855 } 856 857 /** 858 * __e1000_read_kmrn_reg - Read kumeran register 859 * @hw: pointer to the HW structure 860 * @offset: register offset to be read 861 * @data: pointer to the read data 862 * @locked: semaphore has already been acquired or not 863 * 864 * Acquires semaphore, if necessary. Then reads the PHY register at offset 865 * using the kumeran interface. The information retrieved is stored in data. 866 * Release any acquired semaphores before exiting. 867 **/ 868 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 869 bool locked) 870 { 871 u32 kmrnctrlsta; 872 873 DEBUGFUNC("__e1000_read_kmrn_reg"); 874 875 if (!locked) { 876 s32 ret_val = E1000_SUCCESS; 877 878 if (!hw->phy.ops.acquire) 879 return E1000_SUCCESS; 880 881 ret_val = hw->phy.ops.acquire(hw); 882 if (ret_val) 883 return ret_val; 884 } 885 886 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 887 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 888 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 889 E1000_WRITE_FLUSH(hw); 890 891 usec_delay(2); 892 893 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 894 *data = (u16)kmrnctrlsta; 895 896 if (!locked) 897 hw->phy.ops.release(hw); 898 899 return E1000_SUCCESS; 900 } 901 902 /** 903 * e1000_read_kmrn_reg_generic - Read kumeran register 904 * @hw: pointer to the HW structure 905 * @offset: register offset to be read 906 * @data: pointer to the read data 907 * 908 * Acquires semaphore then reads the PHY register at offset using the 909 * kumeran interface. The information retrieved is stored in data. 910 * Release the acquired semaphore before exiting. 911 **/ 912 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 913 { 914 return __e1000_read_kmrn_reg(hw, offset, data, FALSE); 915 } 916 917 /** 918 * e1000_read_kmrn_reg_locked - Read kumeran register 919 * @hw: pointer to the HW structure 920 * @offset: register offset to be read 921 * @data: pointer to the read data 922 * 923 * Reads the PHY register at offset using the kumeran interface. The 924 * information retrieved is stored in data. 925 * Assumes semaphore already acquired. 926 **/ 927 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 928 { 929 return __e1000_read_kmrn_reg(hw, offset, data, TRUE); 930 } 931 932 /** 933 * __e1000_write_kmrn_reg - Write kumeran register 934 * @hw: pointer to the HW structure 935 * @offset: register offset to write to 936 * @data: data to write at register offset 937 * @locked: semaphore has already been acquired or not 938 * 939 * Acquires semaphore, if necessary. Then write the data to PHY register 940 * at the offset using the kumeran interface. Release any acquired semaphores 941 * before exiting. 942 **/ 943 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 944 bool locked) 945 { 946 u32 kmrnctrlsta; 947 948 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 949 950 if (!locked) { 951 s32 ret_val = E1000_SUCCESS; 952 953 if (!hw->phy.ops.acquire) 954 return E1000_SUCCESS; 955 956 ret_val = hw->phy.ops.acquire(hw); 957 if (ret_val) 958 return ret_val; 959 } 960 961 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 962 E1000_KMRNCTRLSTA_OFFSET) | data; 963 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 964 E1000_WRITE_FLUSH(hw); 965 966 usec_delay(2); 967 968 if (!locked) 969 hw->phy.ops.release(hw); 970 971 return E1000_SUCCESS; 972 } 973 974 /** 975 * e1000_write_kmrn_reg_generic - Write kumeran register 976 * @hw: pointer to the HW structure 977 * @offset: register offset to write to 978 * @data: data to write at register offset 979 * 980 * Acquires semaphore then writes the data to the PHY register at the offset 981 * using the kumeran interface. Release the acquired semaphore before exiting. 982 **/ 983 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 984 { 985 return __e1000_write_kmrn_reg(hw, offset, data, FALSE); 986 } 987 988 /** 989 * e1000_write_kmrn_reg_locked - Write kumeran register 990 * @hw: pointer to the HW structure 991 * @offset: register offset to write to 992 * @data: data to write at register offset 993 * 994 * Write the data to PHY register at the offset using the kumeran interface. 995 * Assumes semaphore already acquired. 996 **/ 997 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 998 { 999 return __e1000_write_kmrn_reg(hw, offset, data, TRUE); 1000 } 1001 1002 /** 1003 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode 1004 * @hw: pointer to the HW structure 1005 * 1006 * Sets up Master/slave mode 1007 **/ 1008 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) 1009 { 1010 s32 ret_val; 1011 u16 phy_data; 1012 1013 /* Resolve Master/Slave mode */ 1014 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 1015 if (ret_val) 1016 return ret_val; 1017 1018 /* load defaults for future use */ 1019 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 1020 ((phy_data & CR_1000T_MS_VALUE) ? 1021 e1000_ms_force_master : 1022 e1000_ms_force_slave) : e1000_ms_auto; 1023 1024 switch (hw->phy.ms_type) { 1025 case e1000_ms_force_master: 1026 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1027 break; 1028 case e1000_ms_force_slave: 1029 phy_data |= CR_1000T_MS_ENABLE; 1030 phy_data &= ~(CR_1000T_MS_VALUE); 1031 break; 1032 case e1000_ms_auto: 1033 phy_data &= ~CR_1000T_MS_ENABLE; 1034 /* fall-through */ 1035 default: 1036 break; 1037 } 1038 1039 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 1040 } 1041 1042 /** 1043 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 1044 * @hw: pointer to the HW structure 1045 * 1046 * Sets up Carrier-sense on Transmit and downshift values. 1047 **/ 1048 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 1049 { 1050 s32 ret_val; 1051 u16 phy_data; 1052 1053 DEBUGFUNC("e1000_copper_link_setup_82577"); 1054 1055 if (hw->phy.type == e1000_phy_82580) { 1056 ret_val = hw->phy.ops.reset(hw); 1057 if (ret_val) { 1058 DEBUGOUT("Error resetting the PHY.\n"); 1059 return ret_val; 1060 } 1061 } 1062 1063 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1064 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); 1065 if (ret_val) 1066 return ret_val; 1067 1068 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 1069 1070 /* Enable downshift */ 1071 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 1072 1073 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 1074 if (ret_val) 1075 return ret_val; 1076 1077 /* Set MDI/MDIX mode */ 1078 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); 1079 if (ret_val) 1080 return ret_val; 1081 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; 1082 /* Options: 1083 * 0 - Auto (default) 1084 * 1 - MDI mode 1085 * 2 - MDI-X mode 1086 */ 1087 switch (hw->phy.mdix) { 1088 case 1: 1089 break; 1090 case 2: 1091 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; 1092 break; 1093 case 0: 1094 default: 1095 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; 1096 break; 1097 } 1098 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); 1099 if (ret_val) 1100 return ret_val; 1101 1102 return e1000_set_master_slave_mode(hw); 1103 } 1104 1105 /** 1106 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 1107 * @hw: pointer to the HW structure 1108 * 1109 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 1110 * and downshift values are set also. 1111 **/ 1112 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 1113 { 1114 struct e1000_phy_info *phy = &hw->phy; 1115 s32 ret_val; 1116 u16 phy_data; 1117 1118 DEBUGFUNC("e1000_copper_link_setup_m88"); 1119 1120 1121 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1122 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1123 if (ret_val) 1124 return ret_val; 1125 1126 /* For BM PHY this bit is downshift enable */ 1127 if (phy->type != e1000_phy_bm) 1128 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1129 1130 /* Options: 1131 * MDI/MDI-X = 0 (default) 1132 * 0 - Auto for all speeds 1133 * 1 - MDI mode 1134 * 2 - MDI-X mode 1135 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1136 */ 1137 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1138 1139 switch (phy->mdix) { 1140 case 1: 1141 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1142 break; 1143 case 2: 1144 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1145 break; 1146 case 3: 1147 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1148 break; 1149 case 0: 1150 default: 1151 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1152 break; 1153 } 1154 1155 /* Options: 1156 * disable_polarity_correction = 0 (default) 1157 * Automatic Correction for Reversed Cable Polarity 1158 * 0 - Disabled 1159 * 1 - Enabled 1160 */ 1161 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1162 if (phy->disable_polarity_correction) 1163 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1164 1165 /* Enable downshift on BM (disabled by default) */ 1166 if (phy->type == e1000_phy_bm) { 1167 /* For 82574/82583, first disable then enable downshift */ 1168 if (phy->id == BME1000_E_PHY_ID_R2) { 1169 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; 1170 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1171 phy_data); 1172 if (ret_val) 1173 return ret_val; 1174 /* Commit the changes. */ 1175 ret_val = phy->ops.commit(hw); 1176 if (ret_val) { 1177 DEBUGOUT("Error committing the PHY changes\n"); 1178 return ret_val; 1179 } 1180 } 1181 1182 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 1183 } 1184 1185 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1186 if (ret_val) 1187 return ret_val; 1188 1189 if ((phy->type == e1000_phy_m88) && 1190 (phy->revision < E1000_REVISION_4) && 1191 (phy->id != BME1000_E_PHY_ID_R2)) { 1192 /* Force TX_CLK in the Extended PHY Specific Control Register 1193 * to 25MHz clock. 1194 */ 1195 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1196 &phy_data); 1197 if (ret_val) 1198 return ret_val; 1199 1200 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1201 1202 if ((phy->revision == E1000_REVISION_2) && 1203 (phy->id == M88E1111_I_PHY_ID)) { 1204 /* 82573L PHY - set the downshift counter to 5x. */ 1205 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 1206 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1207 } else { 1208 /* Configure Master and Slave downshift values */ 1209 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1210 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1211 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1212 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1213 } 1214 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1215 phy_data); 1216 if (ret_val) 1217 return ret_val; 1218 } 1219 1220 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 1221 /* Set PHY page 0, register 29 to 0x0003 */ 1222 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 1223 if (ret_val) 1224 return ret_val; 1225 1226 /* Set PHY page 0, register 30 to 0x0000 */ 1227 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 1228 if (ret_val) 1229 return ret_val; 1230 } 1231 1232 /* Commit the changes. */ 1233 ret_val = phy->ops.commit(hw); 1234 if (ret_val) { 1235 DEBUGOUT("Error committing the PHY changes\n"); 1236 return ret_val; 1237 } 1238 1239 if (phy->type == e1000_phy_82578) { 1240 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1241 &phy_data); 1242 if (ret_val) 1243 return ret_val; 1244 1245 /* 82578 PHY - set the downshift count to 1x. */ 1246 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 1247 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 1248 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1249 phy_data); 1250 if (ret_val) 1251 return ret_val; 1252 } 1253 1254 if (phy->type == e1000_phy_i210) { 1255 ret_val = e1000_set_master_slave_mode(hw); 1256 if (ret_val) 1257 return ret_val; 1258 } 1259 1260 return E1000_SUCCESS; 1261 } 1262 1263 /** 1264 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 1265 * @hw: pointer to the HW structure 1266 * 1267 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 1268 * Also enables and sets the downshift parameters. 1269 **/ 1270 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) 1271 { 1272 struct e1000_phy_info *phy = &hw->phy; 1273 s32 ret_val; 1274 u16 phy_data; 1275 1276 DEBUGFUNC("e1000_copper_link_setup_m88_gen2"); 1277 1278 1279 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1280 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1281 if (ret_val) 1282 return ret_val; 1283 1284 /* Options: 1285 * MDI/MDI-X = 0 (default) 1286 * 0 - Auto for all speeds 1287 * 1 - MDI mode 1288 * 2 - MDI-X mode 1289 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1290 */ 1291 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1292 1293 switch (phy->mdix) { 1294 case 1: 1295 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1296 break; 1297 case 2: 1298 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1299 break; 1300 case 3: 1301 /* M88E1112 does not support this mode) */ 1302 if (phy->id != M88E1112_E_PHY_ID) { 1303 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1304 break; 1305 } 1306 case 0: 1307 default: 1308 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1309 break; 1310 } 1311 1312 /* Options: 1313 * disable_polarity_correction = 0 (default) 1314 * Automatic Correction for Reversed Cable Polarity 1315 * 0 - Disabled 1316 * 1 - Enabled 1317 */ 1318 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1319 if (phy->disable_polarity_correction) 1320 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1321 1322 /* Enable downshift and setting it to X6 */ 1323 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 1324 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 1325 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 1326 1327 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1328 if (ret_val) 1329 return ret_val; 1330 1331 /* Commit the changes. */ 1332 ret_val = phy->ops.commit(hw); 1333 if (ret_val) { 1334 DEBUGOUT("Error committing the PHY changes\n"); 1335 return ret_val; 1336 } 1337 1338 ret_val = e1000_set_master_slave_mode(hw); 1339 if (ret_val) 1340 return ret_val; 1341 1342 return E1000_SUCCESS; 1343 } 1344 1345 /** 1346 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 1347 * @hw: pointer to the HW structure 1348 * 1349 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 1350 * igp PHY's. 1351 **/ 1352 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 1353 { 1354 struct e1000_phy_info *phy = &hw->phy; 1355 s32 ret_val; 1356 u16 data; 1357 1358 DEBUGFUNC("e1000_copper_link_setup_igp"); 1359 1360 1361 ret_val = hw->phy.ops.reset(hw); 1362 if (ret_val) { 1363 DEBUGOUT("Error resetting the PHY.\n"); 1364 return ret_val; 1365 } 1366 1367 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 1368 * timeout issues when LFS is enabled. 1369 */ 1370 msec_delay(100); 1371 1372 /* The NVM settings will configure LPLU in D3 for 1373 * non-IGP1 PHYs. 1374 */ 1375 if (phy->type == e1000_phy_igp) { 1376 /* disable lplu d3 during driver init */ 1377 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 1378 if (ret_val) { 1379 DEBUGOUT("Error Disabling LPLU D3\n"); 1380 return ret_val; 1381 } 1382 } 1383 1384 /* disable lplu d0 during driver init */ 1385 if (hw->phy.ops.set_d0_lplu_state) { 1386 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 1387 if (ret_val) { 1388 DEBUGOUT("Error Disabling LPLU D0\n"); 1389 return ret_val; 1390 } 1391 } 1392 /* Configure mdi-mdix settings */ 1393 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1394 if (ret_val) 1395 return ret_val; 1396 1397 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1398 1399 switch (phy->mdix) { 1400 case 1: 1401 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1402 break; 1403 case 2: 1404 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1405 break; 1406 case 0: 1407 default: 1408 data |= IGP01E1000_PSCR_AUTO_MDIX; 1409 break; 1410 } 1411 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1412 if (ret_val) 1413 return ret_val; 1414 1415 /* set auto-master slave resolution settings */ 1416 if (hw->mac.autoneg) { 1417 /* when autonegotiation advertisement is only 1000Mbps then we 1418 * should disable SmartSpeed and enable Auto MasterSlave 1419 * resolution as hardware default. 1420 */ 1421 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1422 /* Disable SmartSpeed */ 1423 ret_val = phy->ops.read_reg(hw, 1424 IGP01E1000_PHY_PORT_CONFIG, 1425 &data); 1426 if (ret_val) 1427 return ret_val; 1428 1429 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1430 ret_val = phy->ops.write_reg(hw, 1431 IGP01E1000_PHY_PORT_CONFIG, 1432 data); 1433 if (ret_val) 1434 return ret_val; 1435 1436 /* Set auto Master/Slave resolution process */ 1437 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1438 if (ret_val) 1439 return ret_val; 1440 1441 data &= ~CR_1000T_MS_ENABLE; 1442 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1443 if (ret_val) 1444 return ret_val; 1445 } 1446 1447 ret_val = e1000_set_master_slave_mode(hw); 1448 } 1449 1450 return ret_val; 1451 } 1452 1453 /** 1454 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1455 * @hw: pointer to the HW structure 1456 * 1457 * Reads the MII auto-neg advertisement register and/or the 1000T control 1458 * register and if the PHY is already setup for auto-negotiation, then 1459 * return successful. Otherwise, setup advertisement and flow control to 1460 * the appropriate values for the wanted auto-negotiation. 1461 **/ 1462 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1463 { 1464 struct e1000_phy_info *phy = &hw->phy; 1465 s32 ret_val; 1466 u16 mii_autoneg_adv_reg; 1467 u16 mii_1000t_ctrl_reg = 0; 1468 1469 DEBUGFUNC("e1000_phy_setup_autoneg"); 1470 1471 phy->autoneg_advertised &= phy->autoneg_mask; 1472 1473 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1474 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1475 if (ret_val) 1476 return ret_val; 1477 1478 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1479 /* Read the MII 1000Base-T Control Register (Address 9). */ 1480 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1481 &mii_1000t_ctrl_reg); 1482 if (ret_val) 1483 return ret_val; 1484 } 1485 1486 /* Need to parse both autoneg_advertised and fc and set up 1487 * the appropriate PHY registers. First we will parse for 1488 * autoneg_advertised software override. Since we can advertise 1489 * a plethora of combinations, we need to check each bit 1490 * individually. 1491 */ 1492 1493 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1494 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1495 * the 1000Base-T Control Register (Address 9). 1496 */ 1497 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1498 NWAY_AR_100TX_HD_CAPS | 1499 NWAY_AR_10T_FD_CAPS | 1500 NWAY_AR_10T_HD_CAPS); 1501 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1502 1503 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1504 1505 /* Do we want to advertise 10 Mb Half Duplex? */ 1506 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1507 DEBUGOUT("Advertise 10mb Half duplex\n"); 1508 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1509 } 1510 1511 /* Do we want to advertise 10 Mb Full Duplex? */ 1512 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1513 DEBUGOUT("Advertise 10mb Full duplex\n"); 1514 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1515 } 1516 1517 /* Do we want to advertise 100 Mb Half Duplex? */ 1518 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1519 DEBUGOUT("Advertise 100mb Half duplex\n"); 1520 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1521 } 1522 1523 /* Do we want to advertise 100 Mb Full Duplex? */ 1524 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1525 DEBUGOUT("Advertise 100mb Full duplex\n"); 1526 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1527 } 1528 1529 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1530 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1531 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1532 1533 /* Do we want to advertise 1000 Mb Full Duplex? */ 1534 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1535 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1536 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1537 } 1538 1539 /* Check for a software override of the flow control settings, and 1540 * setup the PHY advertisement registers accordingly. If 1541 * auto-negotiation is enabled, then software will have to set the 1542 * "PAUSE" bits to the correct value in the Auto-Negotiation 1543 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1544 * negotiation. 1545 * 1546 * The possible values of the "fc" parameter are: 1547 * 0: Flow control is completely disabled 1548 * 1: Rx flow control is enabled (we can receive pause frames 1549 * but not send pause frames). 1550 * 2: Tx flow control is enabled (we can send pause frames 1551 * but we do not support receiving pause frames). 1552 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1553 * other: No software override. The flow control configuration 1554 * in the EEPROM is used. 1555 */ 1556 switch (hw->fc.current_mode) { 1557 case e1000_fc_none: 1558 /* Flow control (Rx & Tx) is completely disabled by a 1559 * software over-ride. 1560 */ 1561 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1562 break; 1563 case e1000_fc_rx_pause: 1564 /* Rx Flow control is enabled, and Tx Flow control is 1565 * disabled, by a software over-ride. 1566 * 1567 * Since there really isn't a way to advertise that we are 1568 * capable of Rx Pause ONLY, we will advertise that we 1569 * support both symmetric and asymmetric Rx PAUSE. Later 1570 * (in e1000_config_fc_after_link_up) we will disable the 1571 * hw's ability to send PAUSE frames. 1572 */ 1573 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1574 break; 1575 case e1000_fc_tx_pause: 1576 /* Tx Flow control is enabled, and Rx Flow control is 1577 * disabled, by a software over-ride. 1578 */ 1579 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1580 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1581 break; 1582 case e1000_fc_full: 1583 /* Flow control (both Rx and Tx) is enabled by a software 1584 * over-ride. 1585 */ 1586 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1587 break; 1588 default: 1589 DEBUGOUT("Flow control param set incorrectly\n"); 1590 return -E1000_ERR_CONFIG; 1591 } 1592 1593 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1594 if (ret_val) 1595 return ret_val; 1596 1597 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1598 1599 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1600 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 1601 mii_1000t_ctrl_reg); 1602 1603 return ret_val; 1604 } 1605 1606 /** 1607 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1608 * @hw: pointer to the HW structure 1609 * 1610 * Performs initial bounds checking on autoneg advertisement parameter, then 1611 * configure to advertise the full capability. Setup the PHY to autoneg 1612 * and restart the negotiation process between the link partner. If 1613 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1614 **/ 1615 s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1616 { 1617 struct e1000_phy_info *phy = &hw->phy; 1618 s32 ret_val; 1619 u16 phy_ctrl; 1620 1621 DEBUGFUNC("e1000_copper_link_autoneg"); 1622 1623 /* Perform some bounds checking on the autoneg advertisement 1624 * parameter. 1625 */ 1626 phy->autoneg_advertised &= phy->autoneg_mask; 1627 1628 /* If autoneg_advertised is zero, we assume it was not defaulted 1629 * by the calling code so we set to advertise full capability. 1630 */ 1631 if (!phy->autoneg_advertised) 1632 phy->autoneg_advertised = phy->autoneg_mask; 1633 1634 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1635 ret_val = e1000_phy_setup_autoneg(hw); 1636 if (ret_val) { 1637 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1638 return ret_val; 1639 } 1640 DEBUGOUT("Restarting Auto-Neg\n"); 1641 1642 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1643 * the Auto Neg Restart bit in the PHY control register. 1644 */ 1645 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1646 if (ret_val) 1647 return ret_val; 1648 1649 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1650 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1651 if (ret_val) 1652 return ret_val; 1653 1654 /* Does the user want to wait for Auto-Neg to complete here, or 1655 * check at a later time (for example, callback routine). 1656 */ 1657 if (phy->autoneg_wait_to_complete) { 1658 ret_val = e1000_wait_autoneg(hw); 1659 if (ret_val) { 1660 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1661 return ret_val; 1662 } 1663 } 1664 1665 hw->mac.get_link_status = TRUE; 1666 1667 return ret_val; 1668 } 1669 1670 /** 1671 * e1000_setup_copper_link_generic - Configure copper link settings 1672 * @hw: pointer to the HW structure 1673 * 1674 * Calls the appropriate function to configure the link for auto-neg or forced 1675 * speed and duplex. Then we check for link, once link is established calls 1676 * to configure collision distance and flow control are called. If link is 1677 * not established, we return -E1000_ERR_PHY (-2). 1678 **/ 1679 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1680 { 1681 s32 ret_val; 1682 bool link; 1683 1684 DEBUGFUNC("e1000_setup_copper_link_generic"); 1685 1686 if (hw->mac.autoneg) { 1687 /* Setup autoneg and flow control advertisement and perform 1688 * autonegotiation. 1689 */ 1690 ret_val = e1000_copper_link_autoneg(hw); 1691 if (ret_val) 1692 return ret_val; 1693 } else { 1694 /* PHY will be set to 10H, 10F, 100H or 100F 1695 * depending on user settings. 1696 */ 1697 DEBUGOUT("Forcing Speed and Duplex\n"); 1698 ret_val = hw->phy.ops.force_speed_duplex(hw); 1699 if (ret_val) { 1700 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1701 return ret_val; 1702 } 1703 } 1704 1705 /* Check link status. Wait up to 100 microseconds for link to become 1706 * valid. 1707 */ 1708 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1709 &link); 1710 if (ret_val) 1711 return ret_val; 1712 1713 if (link) { 1714 DEBUGOUT("Valid link established!!!\n"); 1715 hw->mac.ops.config_collision_dist(hw); 1716 ret_val = e1000_config_fc_after_link_up_generic(hw); 1717 } else { 1718 DEBUGOUT("Unable to establish link!!!\n"); 1719 } 1720 1721 return ret_val; 1722 } 1723 1724 /** 1725 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1726 * @hw: pointer to the HW structure 1727 * 1728 * Calls the PHY setup function to force speed and duplex. Clears the 1729 * auto-crossover to force MDI manually. Waits for link and returns 1730 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1731 **/ 1732 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1733 { 1734 struct e1000_phy_info *phy = &hw->phy; 1735 s32 ret_val; 1736 u16 phy_data; 1737 bool link; 1738 1739 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1740 1741 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1742 if (ret_val) 1743 return ret_val; 1744 1745 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1746 1747 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1748 if (ret_val) 1749 return ret_val; 1750 1751 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1752 * forced whenever speed and duplex are forced. 1753 */ 1754 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1755 if (ret_val) 1756 return ret_val; 1757 1758 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1759 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1760 1761 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1762 if (ret_val) 1763 return ret_val; 1764 1765 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1766 1767 usec_delay(1); 1768 1769 if (phy->autoneg_wait_to_complete) { 1770 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1771 1772 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1773 100000, &link); 1774 if (ret_val) 1775 return ret_val; 1776 1777 if (!link) 1778 DEBUGOUT("Link taking longer than expected.\n"); 1779 1780 /* Try once more */ 1781 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1782 100000, &link); 1783 } 1784 1785 return ret_val; 1786 } 1787 1788 /** 1789 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1790 * @hw: pointer to the HW structure 1791 * 1792 * Calls the PHY setup function to force speed and duplex. Clears the 1793 * auto-crossover to force MDI manually. Resets the PHY to commit the 1794 * changes. If time expires while waiting for link up, we reset the DSP. 1795 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1796 * successful completion, else return corresponding error code. 1797 **/ 1798 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1799 { 1800 struct e1000_phy_info *phy = &hw->phy; 1801 s32 ret_val; 1802 u16 phy_data; 1803 bool link; 1804 1805 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1806 1807 /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1808 if (phy->type != e1000_phy_i210) { 1809 /* Clear Auto-Crossover to force MDI manually. M88E1000 1810 * requires MDI forced whenever speed and duplex are forced. 1811 */ 1812 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1813 &phy_data); 1814 if (ret_val) 1815 return ret_val; 1816 1817 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1818 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1819 phy_data); 1820 if (ret_val) 1821 return ret_val; 1822 } 1823 1824 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1825 1826 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1827 if (ret_val) 1828 return ret_val; 1829 1830 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1831 1832 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1833 if (ret_val) 1834 return ret_val; 1835 1836 /* Reset the phy to commit changes. */ 1837 ret_val = hw->phy.ops.commit(hw); 1838 if (ret_val) 1839 return ret_val; 1840 1841 if (phy->autoneg_wait_to_complete) { 1842 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1843 1844 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1845 100000, &link); 1846 if (ret_val) 1847 return ret_val; 1848 1849 if (!link) { 1850 bool reset_dsp = TRUE; 1851 1852 switch (hw->phy.id) { 1853 case I347AT4_E_PHY_ID: 1854 case M88E1340M_E_PHY_ID: 1855 case M88E1112_E_PHY_ID: 1856 case M88E1545_E_PHY_ID: 1857 case I210_I_PHY_ID: 1858 reset_dsp = FALSE; 1859 break; 1860 default: 1861 if (hw->phy.type != e1000_phy_m88) 1862 reset_dsp = FALSE; 1863 break; 1864 } 1865 1866 if (!reset_dsp) { 1867 DEBUGOUT("Link taking longer than expected.\n"); 1868 } else { 1869 /* We didn't get link. 1870 * Reset the DSP and cross our fingers. 1871 */ 1872 ret_val = phy->ops.write_reg(hw, 1873 M88E1000_PHY_PAGE_SELECT, 1874 0x001d); 1875 if (ret_val) 1876 return ret_val; 1877 ret_val = e1000_phy_reset_dsp_generic(hw); 1878 if (ret_val) 1879 return ret_val; 1880 } 1881 } 1882 1883 /* Try once more */ 1884 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1885 100000, &link); 1886 if (ret_val) 1887 return ret_val; 1888 } 1889 1890 if (hw->phy.type != e1000_phy_m88) 1891 return E1000_SUCCESS; 1892 1893 if (hw->phy.id == I347AT4_E_PHY_ID || 1894 hw->phy.id == M88E1340M_E_PHY_ID || 1895 hw->phy.id == M88E1112_E_PHY_ID) 1896 return E1000_SUCCESS; 1897 if (hw->phy.id == I210_I_PHY_ID) 1898 return E1000_SUCCESS; 1899 if (hw->phy.id == M88E1545_E_PHY_ID) 1900 return E1000_SUCCESS; 1901 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1902 if (ret_val) 1903 return ret_val; 1904 1905 /* Resetting the phy means we need to re-force TX_CLK in the 1906 * Extended PHY Specific Control Register to 25MHz clock from 1907 * the reset value of 2.5MHz. 1908 */ 1909 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1910 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1911 if (ret_val) 1912 return ret_val; 1913 1914 /* In addition, we must re-enable CRS on Tx for both half and full 1915 * duplex. 1916 */ 1917 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1918 if (ret_val) 1919 return ret_val; 1920 1921 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1922 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1923 1924 return ret_val; 1925 } 1926 1927 /** 1928 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1929 * @hw: pointer to the HW structure 1930 * 1931 * Forces the speed and duplex settings of the PHY. 1932 * This is a function pointer entry point only called by 1933 * PHY setup routines. 1934 **/ 1935 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1936 { 1937 struct e1000_phy_info *phy = &hw->phy; 1938 s32 ret_val; 1939 u16 data; 1940 bool link; 1941 1942 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1943 1944 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1945 if (ret_val) 1946 return ret_val; 1947 1948 e1000_phy_force_speed_duplex_setup(hw, &data); 1949 1950 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1951 if (ret_val) 1952 return ret_val; 1953 1954 /* Disable MDI-X support for 10/100 */ 1955 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1956 if (ret_val) 1957 return ret_val; 1958 1959 data &= ~IFE_PMC_AUTO_MDIX; 1960 data &= ~IFE_PMC_FORCE_MDIX; 1961 1962 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1963 if (ret_val) 1964 return ret_val; 1965 1966 DEBUGOUT1("IFE PMC: %X\n", data); 1967 1968 usec_delay(1); 1969 1970 if (phy->autoneg_wait_to_complete) { 1971 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1972 1973 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1974 100000, &link); 1975 if (ret_val) 1976 return ret_val; 1977 1978 if (!link) 1979 DEBUGOUT("Link taking longer than expected.\n"); 1980 1981 /* Try once more */ 1982 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1983 100000, &link); 1984 if (ret_val) 1985 return ret_val; 1986 } 1987 1988 return E1000_SUCCESS; 1989 } 1990 1991 /** 1992 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1993 * @hw: pointer to the HW structure 1994 * @phy_ctrl: pointer to current value of PHY_CONTROL 1995 * 1996 * Forces speed and duplex on the PHY by doing the following: disable flow 1997 * control, force speed/duplex on the MAC, disable auto speed detection, 1998 * disable auto-negotiation, configure duplex, configure speed, configure 1999 * the collision distance, write configuration to CTRL register. The 2000 * caller must write to the PHY_CONTROL register for these settings to 2001 * take affect. 2002 **/ 2003 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 2004 { 2005 struct e1000_mac_info *mac = &hw->mac; 2006 u32 ctrl; 2007 2008 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 2009 2010 /* Turn off flow control when forcing speed/duplex */ 2011 hw->fc.current_mode = e1000_fc_none; 2012 2013 /* Force speed/duplex on the mac */ 2014 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2015 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2016 ctrl &= ~E1000_CTRL_SPD_SEL; 2017 2018 /* Disable Auto Speed Detection */ 2019 ctrl &= ~E1000_CTRL_ASDE; 2020 2021 /* Disable autoneg on the phy */ 2022 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 2023 2024 /* Forcing Full or Half Duplex? */ 2025 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 2026 ctrl &= ~E1000_CTRL_FD; 2027 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 2028 DEBUGOUT("Half Duplex\n"); 2029 } else { 2030 ctrl |= E1000_CTRL_FD; 2031 *phy_ctrl |= MII_CR_FULL_DUPLEX; 2032 DEBUGOUT("Full Duplex\n"); 2033 } 2034 2035 /* Forcing 10mb or 100mb? */ 2036 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 2037 ctrl |= E1000_CTRL_SPD_100; 2038 *phy_ctrl |= MII_CR_SPEED_100; 2039 *phy_ctrl &= ~MII_CR_SPEED_1000; 2040 DEBUGOUT("Forcing 100mb\n"); 2041 } else { 2042 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2043 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 2044 DEBUGOUT("Forcing 10mb\n"); 2045 } 2046 2047 hw->mac.ops.config_collision_dist(hw); 2048 2049 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2050 } 2051 2052 /** 2053 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 2054 * @hw: pointer to the HW structure 2055 * @active: boolean used to enable/disable lplu 2056 * 2057 * Success returns 0, Failure returns 1 2058 * 2059 * The low power link up (lplu) state is set to the power management level D3 2060 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 2061 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 2062 * is used during Dx states where the power conservation is most important. 2063 * During driver activity, SmartSpeed should be enabled so performance is 2064 * maintained. 2065 **/ 2066 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 2067 { 2068 struct e1000_phy_info *phy = &hw->phy; 2069 s32 ret_val; 2070 u16 data; 2071 2072 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 2073 2074 if (!hw->phy.ops.read_reg) 2075 return E1000_SUCCESS; 2076 2077 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 2078 if (ret_val) 2079 return ret_val; 2080 2081 if (!active) { 2082 data &= ~IGP02E1000_PM_D3_LPLU; 2083 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2084 data); 2085 if (ret_val) 2086 return ret_val; 2087 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2088 * during Dx states where the power conservation is most 2089 * important. During driver activity we should enable 2090 * SmartSpeed, so performance is maintained. 2091 */ 2092 if (phy->smart_speed == e1000_smart_speed_on) { 2093 ret_val = phy->ops.read_reg(hw, 2094 IGP01E1000_PHY_PORT_CONFIG, 2095 &data); 2096 if (ret_val) 2097 return ret_val; 2098 2099 data |= IGP01E1000_PSCFR_SMART_SPEED; 2100 ret_val = phy->ops.write_reg(hw, 2101 IGP01E1000_PHY_PORT_CONFIG, 2102 data); 2103 if (ret_val) 2104 return ret_val; 2105 } else if (phy->smart_speed == e1000_smart_speed_off) { 2106 ret_val = phy->ops.read_reg(hw, 2107 IGP01E1000_PHY_PORT_CONFIG, 2108 &data); 2109 if (ret_val) 2110 return ret_val; 2111 2112 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2113 ret_val = phy->ops.write_reg(hw, 2114 IGP01E1000_PHY_PORT_CONFIG, 2115 data); 2116 if (ret_val) 2117 return ret_val; 2118 } 2119 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2120 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2121 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2122 data |= IGP02E1000_PM_D3_LPLU; 2123 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2124 data); 2125 if (ret_val) 2126 return ret_val; 2127 2128 /* When LPLU is enabled, we should disable SmartSpeed */ 2129 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2130 &data); 2131 if (ret_val) 2132 return ret_val; 2133 2134 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2135 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2136 data); 2137 } 2138 2139 return ret_val; 2140 } 2141 2142 /** 2143 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 2144 * @hw: pointer to the HW structure 2145 * 2146 * Success returns 0, Failure returns 1 2147 * 2148 * A downshift is detected by querying the PHY link health. 2149 **/ 2150 s32 e1000_check_downshift_generic(struct e1000_hw *hw) 2151 { 2152 struct e1000_phy_info *phy = &hw->phy; 2153 s32 ret_val; 2154 u16 phy_data, offset, mask; 2155 2156 DEBUGFUNC("e1000_check_downshift_generic"); 2157 2158 switch (phy->type) { 2159 case e1000_phy_i210: 2160 case e1000_phy_m88: 2161 case e1000_phy_gg82563: 2162 case e1000_phy_bm: 2163 case e1000_phy_82578: 2164 offset = M88E1000_PHY_SPEC_STATUS; 2165 mask = M88E1000_PSSR_DOWNSHIFT; 2166 break; 2167 case e1000_phy_igp: 2168 case e1000_phy_igp_2: 2169 case e1000_phy_igp_3: 2170 offset = IGP01E1000_PHY_LINK_HEALTH; 2171 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 2172 break; 2173 default: 2174 /* speed downshift not supported */ 2175 phy->speed_downgraded = FALSE; 2176 return E1000_SUCCESS; 2177 } 2178 2179 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2180 2181 if (!ret_val) 2182 phy->speed_downgraded = !!(phy_data & mask); 2183 2184 return ret_val; 2185 } 2186 2187 /** 2188 * e1000_check_polarity_m88 - Checks the polarity. 2189 * @hw: pointer to the HW structure 2190 * 2191 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2192 * 2193 * Polarity is determined based on the PHY specific status register. 2194 **/ 2195 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 2196 { 2197 struct e1000_phy_info *phy = &hw->phy; 2198 s32 ret_val; 2199 u16 data; 2200 2201 DEBUGFUNC("e1000_check_polarity_m88"); 2202 2203 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 2204 2205 if (!ret_val) 2206 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY) 2207 ? e1000_rev_polarity_reversed 2208 : e1000_rev_polarity_normal); 2209 2210 return ret_val; 2211 } 2212 2213 /** 2214 * e1000_check_polarity_igp - Checks the polarity. 2215 * @hw: pointer to the HW structure 2216 * 2217 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2218 * 2219 * Polarity is determined based on the PHY port status register, and the 2220 * current speed (since there is no polarity at 100Mbps). 2221 **/ 2222 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 2223 { 2224 struct e1000_phy_info *phy = &hw->phy; 2225 s32 ret_val; 2226 u16 data, offset, mask; 2227 2228 DEBUGFUNC("e1000_check_polarity_igp"); 2229 2230 /* Polarity is determined based on the speed of 2231 * our connection. 2232 */ 2233 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2234 if (ret_val) 2235 return ret_val; 2236 2237 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2238 IGP01E1000_PSSR_SPEED_1000MBPS) { 2239 offset = IGP01E1000_PHY_PCS_INIT_REG; 2240 mask = IGP01E1000_PHY_POLARITY_MASK; 2241 } else { 2242 /* This really only applies to 10Mbps since 2243 * there is no polarity for 100Mbps (always 0). 2244 */ 2245 offset = IGP01E1000_PHY_PORT_STATUS; 2246 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 2247 } 2248 2249 ret_val = phy->ops.read_reg(hw, offset, &data); 2250 2251 if (!ret_val) 2252 phy->cable_polarity = ((data & mask) 2253 ? e1000_rev_polarity_reversed 2254 : e1000_rev_polarity_normal); 2255 2256 return ret_val; 2257 } 2258 2259 /** 2260 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 2261 * @hw: pointer to the HW structure 2262 * 2263 * Polarity is determined on the polarity reversal feature being enabled. 2264 **/ 2265 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 2266 { 2267 struct e1000_phy_info *phy = &hw->phy; 2268 s32 ret_val; 2269 u16 phy_data, offset, mask; 2270 2271 DEBUGFUNC("e1000_check_polarity_ife"); 2272 2273 /* Polarity is determined based on the reversal feature being enabled. 2274 */ 2275 if (phy->polarity_correction) { 2276 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 2277 mask = IFE_PESC_POLARITY_REVERSED; 2278 } else { 2279 offset = IFE_PHY_SPECIAL_CONTROL; 2280 mask = IFE_PSC_FORCE_POLARITY; 2281 } 2282 2283 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2284 2285 if (!ret_val) 2286 phy->cable_polarity = ((phy_data & mask) 2287 ? e1000_rev_polarity_reversed 2288 : e1000_rev_polarity_normal); 2289 2290 return ret_val; 2291 } 2292 2293 /** 2294 * e1000_wait_autoneg - Wait for auto-neg completion 2295 * @hw: pointer to the HW structure 2296 * 2297 * Waits for auto-negotiation to complete or for the auto-negotiation time 2298 * limit to expire, which ever happens first. 2299 **/ 2300 static s32 e1000_wait_autoneg(struct e1000_hw *hw) 2301 { 2302 s32 ret_val = E1000_SUCCESS; 2303 u16 i, phy_status; 2304 2305 DEBUGFUNC("e1000_wait_autoneg"); 2306 2307 if (!hw->phy.ops.read_reg) 2308 return E1000_SUCCESS; 2309 2310 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 2311 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 2312 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2313 if (ret_val) 2314 break; 2315 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2316 if (ret_val) 2317 break; 2318 if (phy_status & MII_SR_AUTONEG_COMPLETE) 2319 break; 2320 msec_delay(100); 2321 } 2322 2323 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2324 * has completed. 2325 */ 2326 return ret_val; 2327 } 2328 2329 /** 2330 * e1000_phy_has_link_generic - Polls PHY for link 2331 * @hw: pointer to the HW structure 2332 * @iterations: number of times to poll for link 2333 * @usec_interval: delay between polling attempts 2334 * @success: pointer to whether polling was successful or not 2335 * 2336 * Polls the PHY status register for link, 'iterations' number of times. 2337 **/ 2338 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2339 u32 usec_interval, bool *success) 2340 { 2341 s32 ret_val = E1000_SUCCESS; 2342 u16 i, phy_status; 2343 2344 DEBUGFUNC("e1000_phy_has_link_generic"); 2345 2346 if (!hw->phy.ops.read_reg) 2347 return E1000_SUCCESS; 2348 2349 for (i = 0; i < iterations; i++) { 2350 /* Some PHYs require the PHY_STATUS register to be read 2351 * twice due to the link bit being sticky. No harm doing 2352 * it across the board. 2353 */ 2354 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2355 if (ret_val) { 2356 /* If the first read fails, another entity may have 2357 * ownership of the resources, wait and try again to 2358 * see if they have relinquished the resources yet. 2359 */ 2360 if (usec_interval >= 1000) 2361 msec_delay(usec_interval/1000); 2362 else 2363 usec_delay(usec_interval); 2364 } 2365 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2366 if (ret_val) 2367 break; 2368 if (phy_status & MII_SR_LINK_STATUS) 2369 break; 2370 if (usec_interval >= 1000) 2371 msec_delay(usec_interval/1000); 2372 else 2373 usec_delay(usec_interval); 2374 } 2375 2376 *success = (i < iterations); 2377 2378 return ret_val; 2379 } 2380 2381 /** 2382 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2383 * @hw: pointer to the HW structure 2384 * 2385 * Reads the PHY specific status register to retrieve the cable length 2386 * information. The cable length is determined by averaging the minimum and 2387 * maximum values to get the "average" cable length. The m88 PHY has four 2388 * possible cable length values, which are: 2389 * Register Value Cable Length 2390 * 0 < 50 meters 2391 * 1 50 - 80 meters 2392 * 2 80 - 110 meters 2393 * 3 110 - 140 meters 2394 * 4 > 140 meters 2395 **/ 2396 s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2397 { 2398 struct e1000_phy_info *phy = &hw->phy; 2399 s32 ret_val; 2400 u16 phy_data, index; 2401 2402 DEBUGFUNC("e1000_get_cable_length_m88"); 2403 2404 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2405 if (ret_val) 2406 return ret_val; 2407 2408 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2409 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 2410 2411 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2412 return -E1000_ERR_PHY; 2413 2414 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2415 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2416 2417 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2418 2419 return E1000_SUCCESS; 2420 } 2421 2422 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) 2423 { 2424 struct e1000_phy_info *phy = &hw->phy; 2425 s32 ret_val; 2426 u16 phy_data, phy_data2, is_cm; 2427 u16 index, default_page; 2428 2429 DEBUGFUNC("e1000_get_cable_length_m88_gen2"); 2430 2431 switch (hw->phy.id) { 2432 case I210_I_PHY_ID: 2433 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2434 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2435 (I347AT4_PCDL + phy->addr), 2436 &phy_data); 2437 if (ret_val) 2438 return ret_val; 2439 2440 /* Check if the unit of cable length is meters or cm */ 2441 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2442 I347AT4_PCDC, &phy_data2); 2443 if (ret_val) 2444 return ret_val; 2445 2446 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2447 2448 /* Populate the phy structure with cable length in meters */ 2449 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2450 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2451 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2452 break; 2453 case M88E1545_E_PHY_ID: 2454 case M88E1340M_E_PHY_ID: 2455 case I347AT4_E_PHY_ID: 2456 /* Remember the original page select and set it to 7 */ 2457 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2458 &default_page); 2459 if (ret_val) 2460 return ret_val; 2461 2462 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 2463 if (ret_val) 2464 return ret_val; 2465 2466 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2467 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 2468 &phy_data); 2469 if (ret_val) 2470 return ret_val; 2471 2472 /* Check if the unit of cable length is meters or cm */ 2473 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 2474 if (ret_val) 2475 return ret_val; 2476 2477 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2478 2479 /* Populate the phy structure with cable length in meters */ 2480 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2481 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2482 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2483 2484 /* Reset the page select to its original value */ 2485 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2486 default_page); 2487 if (ret_val) 2488 return ret_val; 2489 break; 2490 2491 case M88E1112_E_PHY_ID: 2492 /* Remember the original page select and set it to 5 */ 2493 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2494 &default_page); 2495 if (ret_val) 2496 return ret_val; 2497 2498 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 2499 if (ret_val) 2500 return ret_val; 2501 2502 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 2503 &phy_data); 2504 if (ret_val) 2505 return ret_val; 2506 2507 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2508 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2509 2510 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2511 return -E1000_ERR_PHY; 2512 2513 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2514 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2515 2516 phy->cable_length = (phy->min_cable_length + 2517 phy->max_cable_length) / 2; 2518 2519 /* Reset the page select to its original value */ 2520 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2521 default_page); 2522 if (ret_val) 2523 return ret_val; 2524 2525 break; 2526 default: 2527 return -E1000_ERR_PHY; 2528 } 2529 2530 return ret_val; 2531 } 2532 2533 /** 2534 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2535 * @hw: pointer to the HW structure 2536 * 2537 * The automatic gain control (agc) normalizes the amplitude of the 2538 * received signal, adjusting for the attenuation produced by the 2539 * cable. By reading the AGC registers, which represent the 2540 * combination of coarse and fine gain value, the value can be put 2541 * into a lookup table to obtain the approximate cable length 2542 * for each channel. 2543 **/ 2544 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2545 { 2546 struct e1000_phy_info *phy = &hw->phy; 2547 s32 ret_val; 2548 u16 phy_data, i, agc_value = 0; 2549 u16 cur_agc_index, max_agc_index = 0; 2550 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2551 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 2552 IGP02E1000_PHY_AGC_A, 2553 IGP02E1000_PHY_AGC_B, 2554 IGP02E1000_PHY_AGC_C, 2555 IGP02E1000_PHY_AGC_D 2556 }; 2557 2558 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2559 2560 /* Read the AGC registers for all channels */ 2561 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2562 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2563 if (ret_val) 2564 return ret_val; 2565 2566 /* Getting bits 15:9, which represent the combination of 2567 * coarse and fine gain values. The result is a number 2568 * that can be put into the lookup table to obtain the 2569 * approximate cable length. 2570 */ 2571 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2572 IGP02E1000_AGC_LENGTH_MASK); 2573 2574 /* Array index bound check. */ 2575 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2576 (cur_agc_index == 0)) 2577 return -E1000_ERR_PHY; 2578 2579 /* Remove min & max AGC values from calculation. */ 2580 if (e1000_igp_2_cable_length_table[min_agc_index] > 2581 e1000_igp_2_cable_length_table[cur_agc_index]) 2582 min_agc_index = cur_agc_index; 2583 if (e1000_igp_2_cable_length_table[max_agc_index] < 2584 e1000_igp_2_cable_length_table[cur_agc_index]) 2585 max_agc_index = cur_agc_index; 2586 2587 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2588 } 2589 2590 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2591 e1000_igp_2_cable_length_table[max_agc_index]); 2592 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2593 2594 /* Calculate cable length with the error range of +/- 10 meters. */ 2595 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2596 (agc_value - IGP02E1000_AGC_RANGE) : 0); 2597 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2598 2599 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2600 2601 return E1000_SUCCESS; 2602 } 2603 2604 /** 2605 * e1000_get_phy_info_m88 - Retrieve PHY information 2606 * @hw: pointer to the HW structure 2607 * 2608 * Valid for only copper links. Read the PHY status register (sticky read) 2609 * to verify that link is up. Read the PHY special control register to 2610 * determine the polarity and 10base-T extended distance. Read the PHY 2611 * special status register to determine MDI/MDIx and current speed. If 2612 * speed is 1000, then determine cable length, local and remote receiver. 2613 **/ 2614 s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2615 { 2616 struct e1000_phy_info *phy = &hw->phy; 2617 s32 ret_val; 2618 u16 phy_data; 2619 bool link; 2620 2621 DEBUGFUNC("e1000_get_phy_info_m88"); 2622 2623 if (phy->media_type != e1000_media_type_copper) { 2624 DEBUGOUT("Phy info is only valid for copper media\n"); 2625 return -E1000_ERR_CONFIG; 2626 } 2627 2628 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2629 if (ret_val) 2630 return ret_val; 2631 2632 if (!link) { 2633 DEBUGOUT("Phy info is only valid if link is up\n"); 2634 return -E1000_ERR_CONFIG; 2635 } 2636 2637 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2638 if (ret_val) 2639 return ret_val; 2640 2641 phy->polarity_correction = !!(phy_data & 2642 M88E1000_PSCR_POLARITY_REVERSAL); 2643 2644 ret_val = e1000_check_polarity_m88(hw); 2645 if (ret_val) 2646 return ret_val; 2647 2648 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2649 if (ret_val) 2650 return ret_val; 2651 2652 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); 2653 2654 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2655 ret_val = hw->phy.ops.get_cable_length(hw); 2656 if (ret_val) 2657 return ret_val; 2658 2659 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2660 if (ret_val) 2661 return ret_val; 2662 2663 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2664 ? e1000_1000t_rx_status_ok 2665 : e1000_1000t_rx_status_not_ok; 2666 2667 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2668 ? e1000_1000t_rx_status_ok 2669 : e1000_1000t_rx_status_not_ok; 2670 } else { 2671 /* Set values to "undefined" */ 2672 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2673 phy->local_rx = e1000_1000t_rx_status_undefined; 2674 phy->remote_rx = e1000_1000t_rx_status_undefined; 2675 } 2676 2677 return ret_val; 2678 } 2679 2680 /** 2681 * e1000_get_phy_info_igp - Retrieve igp PHY information 2682 * @hw: pointer to the HW structure 2683 * 2684 * Read PHY status to determine if link is up. If link is up, then 2685 * set/determine 10base-T extended distance and polarity correction. Read 2686 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2687 * determine on the cable length, local and remote receiver. 2688 **/ 2689 s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2690 { 2691 struct e1000_phy_info *phy = &hw->phy; 2692 s32 ret_val; 2693 u16 data; 2694 bool link; 2695 2696 DEBUGFUNC("e1000_get_phy_info_igp"); 2697 2698 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2699 if (ret_val) 2700 return ret_val; 2701 2702 if (!link) { 2703 DEBUGOUT("Phy info is only valid if link is up\n"); 2704 return -E1000_ERR_CONFIG; 2705 } 2706 2707 phy->polarity_correction = TRUE; 2708 2709 ret_val = e1000_check_polarity_igp(hw); 2710 if (ret_val) 2711 return ret_val; 2712 2713 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2714 if (ret_val) 2715 return ret_val; 2716 2717 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); 2718 2719 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2720 IGP01E1000_PSSR_SPEED_1000MBPS) { 2721 ret_val = phy->ops.get_cable_length(hw); 2722 if (ret_val) 2723 return ret_val; 2724 2725 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2726 if (ret_val) 2727 return ret_val; 2728 2729 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2730 ? e1000_1000t_rx_status_ok 2731 : e1000_1000t_rx_status_not_ok; 2732 2733 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2734 ? e1000_1000t_rx_status_ok 2735 : e1000_1000t_rx_status_not_ok; 2736 } else { 2737 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2738 phy->local_rx = e1000_1000t_rx_status_undefined; 2739 phy->remote_rx = e1000_1000t_rx_status_undefined; 2740 } 2741 2742 return ret_val; 2743 } 2744 2745 /** 2746 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2747 * @hw: pointer to the HW structure 2748 * 2749 * Populates "phy" structure with various feature states. 2750 **/ 2751 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2752 { 2753 struct e1000_phy_info *phy = &hw->phy; 2754 s32 ret_val; 2755 u16 data; 2756 bool link; 2757 2758 DEBUGFUNC("e1000_get_phy_info_ife"); 2759 2760 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2761 if (ret_val) 2762 return ret_val; 2763 2764 if (!link) { 2765 DEBUGOUT("Phy info is only valid if link is up\n"); 2766 return -E1000_ERR_CONFIG; 2767 } 2768 2769 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2770 if (ret_val) 2771 return ret_val; 2772 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); 2773 2774 if (phy->polarity_correction) { 2775 ret_val = e1000_check_polarity_ife(hw); 2776 if (ret_val) 2777 return ret_val; 2778 } else { 2779 /* Polarity is forced */ 2780 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY) 2781 ? e1000_rev_polarity_reversed 2782 : e1000_rev_polarity_normal); 2783 } 2784 2785 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2786 if (ret_val) 2787 return ret_val; 2788 2789 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); 2790 2791 /* The following parameters are undefined for 10/100 operation. */ 2792 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2793 phy->local_rx = e1000_1000t_rx_status_undefined; 2794 phy->remote_rx = e1000_1000t_rx_status_undefined; 2795 2796 return E1000_SUCCESS; 2797 } 2798 2799 /** 2800 * e1000_phy_sw_reset_generic - PHY software reset 2801 * @hw: pointer to the HW structure 2802 * 2803 * Does a software reset of the PHY by reading the PHY control register and 2804 * setting/write the control register reset bit to the PHY. 2805 **/ 2806 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2807 { 2808 s32 ret_val; 2809 u16 phy_ctrl; 2810 2811 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2812 2813 if (!hw->phy.ops.read_reg) 2814 return E1000_SUCCESS; 2815 2816 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2817 if (ret_val) 2818 return ret_val; 2819 2820 phy_ctrl |= MII_CR_RESET; 2821 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2822 if (ret_val) 2823 return ret_val; 2824 2825 usec_delay(1); 2826 2827 return ret_val; 2828 } 2829 2830 /** 2831 * e1000_phy_hw_reset_generic - PHY hardware reset 2832 * @hw: pointer to the HW structure 2833 * 2834 * Verify the reset block is not blocking us from resetting. Acquire 2835 * semaphore (if necessary) and read/set/write the device control reset 2836 * bit in the PHY. Wait the appropriate delay time for the device to 2837 * reset and release the semaphore (if necessary). 2838 **/ 2839 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2840 { 2841 struct e1000_phy_info *phy = &hw->phy; 2842 s32 ret_val; 2843 u32 ctrl; 2844 2845 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2846 2847 if (phy->ops.check_reset_block) { 2848 ret_val = phy->ops.check_reset_block(hw); 2849 if (ret_val) 2850 return E1000_SUCCESS; 2851 } 2852 2853 ret_val = phy->ops.acquire(hw); 2854 if (ret_val) 2855 return ret_val; 2856 2857 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2858 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2859 E1000_WRITE_FLUSH(hw); 2860 2861 usec_delay(phy->reset_delay_us); 2862 2863 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2864 E1000_WRITE_FLUSH(hw); 2865 2866 usec_delay(150); 2867 2868 phy->ops.release(hw); 2869 2870 return phy->ops.get_cfg_done(hw); 2871 } 2872 2873 /** 2874 * e1000_get_cfg_done_generic - Generic configuration done 2875 * @hw: pointer to the HW structure 2876 * 2877 * Generic function to wait 10 milli-seconds for configuration to complete 2878 * and return success. 2879 **/ 2880 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2881 { 2882 DEBUGFUNC("e1000_get_cfg_done_generic"); 2883 2884 msec_delay_irq(10); 2885 2886 return E1000_SUCCESS; 2887 } 2888 2889 /** 2890 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2891 * @hw: pointer to the HW structure 2892 * 2893 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2894 **/ 2895 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2896 { 2897 DEBUGOUT("Running IGP 3 PHY init script\n"); 2898 2899 /* PHY init IGP 3 */ 2900 /* Enable rise/fall, 10-mode work in class-A */ 2901 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2902 /* Remove all caps from Replica path filter */ 2903 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2904 /* Bias trimming for ADC, AFE and Driver (Default) */ 2905 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2906 /* Increase Hybrid poly bias */ 2907 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2908 /* Add 4% to Tx amplitude in Gig mode */ 2909 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2910 /* Disable trimming (TTT) */ 2911 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2912 /* Poly DC correction to 94.6% + 2% for all channels */ 2913 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2914 /* ABS DC correction to 95.9% */ 2915 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2916 /* BG temp curve trim */ 2917 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2918 /* Increasing ADC OPAMP stage 1 currents to max */ 2919 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2920 /* Force 1000 ( required for enabling PHY regs configuration) */ 2921 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2922 /* Set upd_freq to 6 */ 2923 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2924 /* Disable NPDFE */ 2925 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2926 /* Disable adaptive fixed FFE (Default) */ 2927 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2928 /* Enable FFE hysteresis */ 2929 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2930 /* Fixed FFE for short cable lengths */ 2931 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2932 /* Fixed FFE for medium cable lengths */ 2933 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2934 /* Fixed FFE for long cable lengths */ 2935 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2936 /* Enable Adaptive Clip Threshold */ 2937 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2938 /* AHT reset limit to 1 */ 2939 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2940 /* Set AHT master delay to 127 msec */ 2941 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2942 /* Set scan bits for AHT */ 2943 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2944 /* Set AHT Preset bits */ 2945 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2946 /* Change integ_factor of channel A to 3 */ 2947 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2948 /* Change prop_factor of channels BCD to 8 */ 2949 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2950 /* Change cg_icount + enable integbp for channels BCD */ 2951 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2952 /* Change cg_icount + enable integbp + change prop_factor_master 2953 * to 8 for channel A 2954 */ 2955 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2956 /* Disable AHT in Slave mode on channel A */ 2957 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2958 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2959 * Enable SPD+B2B 2960 */ 2961 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2962 /* Enable restart AN on an1000_dis change */ 2963 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2964 /* Enable wh_fifo read clock in 10/100 modes */ 2965 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2966 /* Restart AN, Speed selection is 1000 */ 2967 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2968 2969 return E1000_SUCCESS; 2970 } 2971 2972 /** 2973 * e1000_get_phy_type_from_id - Get PHY type from id 2974 * @phy_id: phy_id read from the phy 2975 * 2976 * Returns the phy type from the id. 2977 **/ 2978 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2979 { 2980 enum e1000_phy_type phy_type = e1000_phy_unknown; 2981 2982 switch (phy_id) { 2983 case M88E1000_I_PHY_ID: 2984 case M88E1000_E_PHY_ID: 2985 case M88E1111_I_PHY_ID: 2986 case M88E1011_I_PHY_ID: 2987 case M88E1545_E_PHY_ID: 2988 case I347AT4_E_PHY_ID: 2989 case M88E1112_E_PHY_ID: 2990 case M88E1340M_E_PHY_ID: 2991 phy_type = e1000_phy_m88; 2992 break; 2993 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2994 phy_type = e1000_phy_igp_2; 2995 break; 2996 case GG82563_E_PHY_ID: 2997 phy_type = e1000_phy_gg82563; 2998 break; 2999 case IGP03E1000_E_PHY_ID: 3000 phy_type = e1000_phy_igp_3; 3001 break; 3002 case IFE_E_PHY_ID: 3003 case IFE_PLUS_E_PHY_ID: 3004 case IFE_C_E_PHY_ID: 3005 phy_type = e1000_phy_ife; 3006 break; 3007 case BME1000_E_PHY_ID: 3008 case BME1000_E_PHY_ID_R2: 3009 phy_type = e1000_phy_bm; 3010 break; 3011 case I82578_E_PHY_ID: 3012 phy_type = e1000_phy_82578; 3013 break; 3014 case I82577_E_PHY_ID: 3015 phy_type = e1000_phy_82577; 3016 break; 3017 case I82579_E_PHY_ID: 3018 phy_type = e1000_phy_82579; 3019 break; 3020 case I82580_I_PHY_ID: 3021 phy_type = e1000_phy_82580; 3022 break; 3023 case I210_I_PHY_ID: 3024 phy_type = e1000_phy_i210; 3025 break; 3026 case I217_E_PHY_ID: 3027 phy_type = e1000_phy_i217; 3028 break; 3029 default: 3030 phy_type = e1000_phy_unknown; 3031 break; 3032 } 3033 return phy_type; 3034 } 3035 3036 /** 3037 * e1000_determine_phy_address - Determines PHY address. 3038 * @hw: pointer to the HW structure 3039 * 3040 * This uses a trial and error method to loop through possible PHY 3041 * addresses. It tests each by reading the PHY ID registers and 3042 * checking for a match. 3043 **/ 3044 s32 e1000_determine_phy_address(struct e1000_hw *hw) 3045 { 3046 u32 phy_addr = 0; 3047 u32 i; 3048 enum e1000_phy_type phy_type = e1000_phy_unknown; 3049 3050 hw->phy.id = phy_type; 3051 3052 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 3053 hw->phy.addr = phy_addr; 3054 i = 0; 3055 3056 do { 3057 e1000_get_phy_id(hw); 3058 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 3059 3060 /* If phy_type is valid, break - we found our 3061 * PHY address 3062 */ 3063 if (phy_type != e1000_phy_unknown) 3064 return E1000_SUCCESS; 3065 3066 msec_delay(1); 3067 i++; 3068 } while (i < 10); 3069 } 3070 3071 return -E1000_ERR_PHY_TYPE; 3072 } 3073 3074 /** 3075 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 3076 * @page: page to access 3077 * 3078 * Returns the phy address for the page requested. 3079 **/ 3080 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 3081 { 3082 u32 phy_addr = 2; 3083 3084 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 3085 phy_addr = 1; 3086 3087 return phy_addr; 3088 } 3089 3090 /** 3091 * e1000_write_phy_reg_bm - Write BM PHY register 3092 * @hw: pointer to the HW structure 3093 * @offset: register offset to write to 3094 * @data: data to write at register offset 3095 * 3096 * Acquires semaphore, if necessary, then writes the data to PHY register 3097 * at the offset. Release any acquired semaphores before exiting. 3098 **/ 3099 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 3100 { 3101 s32 ret_val; 3102 u32 page = offset >> IGP_PAGE_SHIFT; 3103 3104 DEBUGFUNC("e1000_write_phy_reg_bm"); 3105 3106 ret_val = hw->phy.ops.acquire(hw); 3107 if (ret_val) 3108 return ret_val; 3109 3110 /* Page 800 works differently than the rest so it has its own func */ 3111 if (page == BM_WUC_PAGE) { 3112 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3113 FALSE, FALSE); 3114 goto release; 3115 } 3116 3117 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3118 3119 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3120 u32 page_shift, page_select; 3121 3122 /* Page select is register 31 for phy address 1 and 22 for 3123 * phy address 2 and 3. Page select is shifted only for 3124 * phy address 1. 3125 */ 3126 if (hw->phy.addr == 1) { 3127 page_shift = IGP_PAGE_SHIFT; 3128 page_select = IGP01E1000_PHY_PAGE_SELECT; 3129 } else { 3130 page_shift = 0; 3131 page_select = BM_PHY_PAGE_SELECT; 3132 } 3133 3134 /* Page is shifted left, PHY expects (page x 32) */ 3135 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3136 (page << page_shift)); 3137 if (ret_val) 3138 goto release; 3139 } 3140 3141 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3142 data); 3143 3144 release: 3145 hw->phy.ops.release(hw); 3146 return ret_val; 3147 } 3148 3149 /** 3150 * e1000_read_phy_reg_bm - Read BM PHY register 3151 * @hw: pointer to the HW structure 3152 * @offset: register offset to be read 3153 * @data: pointer to the read data 3154 * 3155 * Acquires semaphore, if necessary, then reads the PHY register at offset 3156 * and storing the retrieved information in data. Release any acquired 3157 * semaphores before exiting. 3158 **/ 3159 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 3160 { 3161 s32 ret_val; 3162 u32 page = offset >> IGP_PAGE_SHIFT; 3163 3164 DEBUGFUNC("e1000_read_phy_reg_bm"); 3165 3166 ret_val = hw->phy.ops.acquire(hw); 3167 if (ret_val) 3168 return ret_val; 3169 3170 /* Page 800 works differently than the rest so it has its own func */ 3171 if (page == BM_WUC_PAGE) { 3172 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3173 TRUE, FALSE); 3174 goto release; 3175 } 3176 3177 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3178 3179 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3180 u32 page_shift, page_select; 3181 3182 /* Page select is register 31 for phy address 1 and 22 for 3183 * phy address 2 and 3. Page select is shifted only for 3184 * phy address 1. 3185 */ 3186 if (hw->phy.addr == 1) { 3187 page_shift = IGP_PAGE_SHIFT; 3188 page_select = IGP01E1000_PHY_PAGE_SELECT; 3189 } else { 3190 page_shift = 0; 3191 page_select = BM_PHY_PAGE_SELECT; 3192 } 3193 3194 /* Page is shifted left, PHY expects (page x 32) */ 3195 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3196 (page << page_shift)); 3197 if (ret_val) 3198 goto release; 3199 } 3200 3201 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3202 data); 3203 release: 3204 hw->phy.ops.release(hw); 3205 return ret_val; 3206 } 3207 3208 /** 3209 * e1000_read_phy_reg_bm2 - Read BM PHY register 3210 * @hw: pointer to the HW structure 3211 * @offset: register offset to be read 3212 * @data: pointer to the read data 3213 * 3214 * Acquires semaphore, if necessary, then reads the PHY register at offset 3215 * and storing the retrieved information in data. Release any acquired 3216 * semaphores before exiting. 3217 **/ 3218 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 3219 { 3220 s32 ret_val; 3221 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3222 3223 DEBUGFUNC("e1000_read_phy_reg_bm2"); 3224 3225 ret_val = hw->phy.ops.acquire(hw); 3226 if (ret_val) 3227 return ret_val; 3228 3229 /* Page 800 works differently than the rest so it has its own func */ 3230 if (page == BM_WUC_PAGE) { 3231 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3232 TRUE, FALSE); 3233 goto release; 3234 } 3235 3236 hw->phy.addr = 1; 3237 3238 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3239 /* Page is shifted left, PHY expects (page x 32) */ 3240 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3241 page); 3242 3243 if (ret_val) 3244 goto release; 3245 } 3246 3247 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3248 data); 3249 release: 3250 hw->phy.ops.release(hw); 3251 return ret_val; 3252 } 3253 3254 /** 3255 * e1000_write_phy_reg_bm2 - Write BM PHY register 3256 * @hw: pointer to the HW structure 3257 * @offset: register offset to write to 3258 * @data: data to write at register offset 3259 * 3260 * Acquires semaphore, if necessary, then writes the data to PHY register 3261 * at the offset. Release any acquired semaphores before exiting. 3262 **/ 3263 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 3264 { 3265 s32 ret_val; 3266 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3267 3268 DEBUGFUNC("e1000_write_phy_reg_bm2"); 3269 3270 ret_val = hw->phy.ops.acquire(hw); 3271 if (ret_val) 3272 return ret_val; 3273 3274 /* Page 800 works differently than the rest so it has its own func */ 3275 if (page == BM_WUC_PAGE) { 3276 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3277 FALSE, FALSE); 3278 goto release; 3279 } 3280 3281 hw->phy.addr = 1; 3282 3283 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3284 /* Page is shifted left, PHY expects (page x 32) */ 3285 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3286 page); 3287 3288 if (ret_val) 3289 goto release; 3290 } 3291 3292 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3293 data); 3294 3295 release: 3296 hw->phy.ops.release(hw); 3297 return ret_val; 3298 } 3299 3300 /** 3301 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 3302 * @hw: pointer to the HW structure 3303 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 3304 * 3305 * Assumes semaphore already acquired and phy_reg points to a valid memory 3306 * address to store contents of the BM_WUC_ENABLE_REG register. 3307 **/ 3308 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3309 { 3310 s32 ret_val; 3311 u16 temp; 3312 3313 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm"); 3314 3315 if (!phy_reg) 3316 return -E1000_ERR_PARAM; 3317 3318 /* All page select, port ctrl and wakeup registers use phy address 1 */ 3319 hw->phy.addr = 1; 3320 3321 /* Select Port Control Registers page */ 3322 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3323 if (ret_val) { 3324 DEBUGOUT("Could not set Port Control page\n"); 3325 return ret_val; 3326 } 3327 3328 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3329 if (ret_val) { 3330 DEBUGOUT2("Could not read PHY register %d.%d\n", 3331 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3332 return ret_val; 3333 } 3334 3335 /* Enable both PHY wakeup mode and Wakeup register page writes. 3336 * Prevent a power state change by disabling ME and Host PHY wakeup. 3337 */ 3338 temp = *phy_reg; 3339 temp |= BM_WUC_ENABLE_BIT; 3340 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 3341 3342 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 3343 if (ret_val) { 3344 DEBUGOUT2("Could not write PHY register %d.%d\n", 3345 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3346 return ret_val; 3347 } 3348 3349 /* Select Host Wakeup Registers page - caller now able to write 3350 * registers on the Wakeup registers page 3351 */ 3352 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 3353 } 3354 3355 /** 3356 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 3357 * @hw: pointer to the HW structure 3358 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 3359 * 3360 * Restore BM_WUC_ENABLE_REG to its original value. 3361 * 3362 * Assumes semaphore already acquired and *phy_reg is the contents of the 3363 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 3364 * caller. 3365 **/ 3366 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3367 { 3368 s32 ret_val; 3369 3370 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm"); 3371 3372 if (!phy_reg) 3373 return -E1000_ERR_PARAM; 3374 3375 /* Select Port Control Registers page */ 3376 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3377 if (ret_val) { 3378 DEBUGOUT("Could not set Port Control page\n"); 3379 return ret_val; 3380 } 3381 3382 /* Restore 769.17 to its original value */ 3383 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 3384 if (ret_val) 3385 DEBUGOUT2("Could not restore PHY register %d.%d\n", 3386 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3387 3388 return ret_val; 3389 } 3390 3391 /** 3392 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 3393 * @hw: pointer to the HW structure 3394 * @offset: register offset to be read or written 3395 * @data: pointer to the data to read or write 3396 * @read: determines if operation is read or write 3397 * @page_set: BM_WUC_PAGE already set and access enabled 3398 * 3399 * Read the PHY register at offset and store the retrieved information in 3400 * data, or write data to PHY register at offset. Note the procedure to 3401 * access the PHY wakeup registers is different than reading the other PHY 3402 * registers. It works as such: 3403 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 3404 * 2) Set page to 800 for host (801 if we were manageability) 3405 * 3) Write the address using the address opcode (0x11) 3406 * 4) Read or write the data using the data opcode (0x12) 3407 * 5) Restore 769.17.2 to its original value 3408 * 3409 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 3410 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 3411 * 3412 * Assumes semaphore is already acquired. When page_set==TRUE, assumes 3413 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 3414 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 3415 **/ 3416 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 3417 u16 *data, bool read, bool page_set) 3418 { 3419 s32 ret_val; 3420 u16 reg, page; 3421 u16 phy_reg = 0; 3422 3423 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 3424 reg = BM_PHY_REG_NUM(offset); 3425 page = BM_PHY_REG_PAGE(offset); 3426 3427 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 3428 if ((hw->mac.type == e1000_pchlan) && 3429 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 3430 DEBUGOUT1("Attempting to access page %d while gig enabled.\n", 3431 page); 3432 3433 if (!page_set) { 3434 /* Enable access to PHY wakeup registers */ 3435 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3436 if (ret_val) { 3437 DEBUGOUT("Could not enable PHY wakeup reg access\n"); 3438 return ret_val; 3439 } 3440 } 3441 3442 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg); 3443 3444 /* Write the Wakeup register page offset value using opcode 0x11 */ 3445 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 3446 if (ret_val) { 3447 DEBUGOUT1("Could not write address opcode to page %d\n", page); 3448 return ret_val; 3449 } 3450 3451 if (read) { 3452 /* Read the Wakeup register page value using opcode 0x12 */ 3453 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3454 data); 3455 } else { 3456 /* Write the Wakeup register page value using opcode 0x12 */ 3457 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3458 *data); 3459 } 3460 3461 if (ret_val) { 3462 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg); 3463 return ret_val; 3464 } 3465 3466 if (!page_set) 3467 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3468 3469 return ret_val; 3470 } 3471 3472 /** 3473 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 3474 * @hw: pointer to the HW structure 3475 * 3476 * In the case of a PHY power down to save power, or to turn off link during a 3477 * driver unload, or wake on lan is not enabled, restore the link to previous 3478 * settings. 3479 **/ 3480 void e1000_power_up_phy_copper(struct e1000_hw *hw) 3481 { 3482 u16 mii_reg = 0; 3483 u16 power_reg = 0; 3484 3485 /* The PHY will retain its settings across a power down/up cycle */ 3486 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3487 mii_reg &= ~MII_CR_POWER_DOWN; 3488 if (hw->phy.type == e1000_phy_i210) { 3489 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 3490 power_reg &= ~GS40G_CS_POWER_DOWN; 3491 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 3492 } 3493 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3494 } 3495 3496 /** 3497 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 3498 * @hw: pointer to the HW structure 3499 * 3500 * In the case of a PHY power down to save power, or to turn off link during a 3501 * driver unload, or wake on lan is not enabled, restore the link to previous 3502 * settings. 3503 **/ 3504 void e1000_power_down_phy_copper(struct e1000_hw *hw) 3505 { 3506 u16 mii_reg = 0; 3507 u16 power_reg = 0; 3508 3509 /* The PHY will retain its settings across a power down/up cycle */ 3510 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3511 mii_reg |= MII_CR_POWER_DOWN; 3512 /* i210 Phy requires an additional bit for power up/down */ 3513 if (hw->phy.type == e1000_phy_i210) { 3514 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 3515 power_reg |= GS40G_CS_POWER_DOWN; 3516 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 3517 } 3518 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3519 msec_delay(1); 3520 } 3521 3522 /** 3523 * __e1000_read_phy_reg_hv - Read HV PHY register 3524 * @hw: pointer to the HW structure 3525 * @offset: register offset to be read 3526 * @data: pointer to the read data 3527 * @locked: semaphore has already been acquired or not 3528 * 3529 * Acquires semaphore, if necessary, then reads the PHY register at offset 3530 * and stores the retrieved information in data. Release any acquired 3531 * semaphore before exiting. 3532 **/ 3533 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 3534 bool locked, bool page_set) 3535 { 3536 s32 ret_val; 3537 u16 page = BM_PHY_REG_PAGE(offset); 3538 u16 reg = BM_PHY_REG_NUM(offset); 3539 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3540 3541 DEBUGFUNC("__e1000_read_phy_reg_hv"); 3542 3543 if (!locked) { 3544 ret_val = hw->phy.ops.acquire(hw); 3545 if (ret_val) 3546 return ret_val; 3547 } 3548 3549 /* Page 800 works differently than the rest so it has its own func */ 3550 if (page == BM_WUC_PAGE) { 3551 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3552 TRUE, page_set); 3553 goto out; 3554 } 3555 3556 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3557 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3558 data, TRUE); 3559 goto out; 3560 } 3561 3562 if (!page_set) { 3563 if (page == HV_INTC_FC_PAGE_START) 3564 page = 0; 3565 3566 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3567 /* Page is shifted left, PHY expects (page x 32) */ 3568 ret_val = e1000_set_page_igp(hw, 3569 (page << IGP_PAGE_SHIFT)); 3570 3571 hw->phy.addr = phy_addr; 3572 3573 if (ret_val) 3574 goto out; 3575 } 3576 } 3577 3578 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3579 page << IGP_PAGE_SHIFT, reg); 3580 3581 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3582 data); 3583 out: 3584 if (!locked) 3585 hw->phy.ops.release(hw); 3586 3587 return ret_val; 3588 } 3589 3590 /** 3591 * e1000_read_phy_reg_hv - Read HV PHY register 3592 * @hw: pointer to the HW structure 3593 * @offset: register offset to be read 3594 * @data: pointer to the read data 3595 * 3596 * Acquires semaphore then reads the PHY register at offset and stores 3597 * the retrieved information in data. Release the acquired semaphore 3598 * before exiting. 3599 **/ 3600 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3601 { 3602 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE); 3603 } 3604 3605 /** 3606 * e1000_read_phy_reg_hv_locked - Read HV PHY register 3607 * @hw: pointer to the HW structure 3608 * @offset: register offset to be read 3609 * @data: pointer to the read data 3610 * 3611 * Reads the PHY register at offset and stores the retrieved information 3612 * in data. Assumes semaphore already acquired. 3613 **/ 3614 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3615 { 3616 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3617 } 3618 3619 /** 3620 * e1000_read_phy_reg_page_hv - Read HV PHY register 3621 * @hw: pointer to the HW structure 3622 * @offset: register offset to write to 3623 * @data: data to write at register offset 3624 * 3625 * Reads the PHY register at offset and stores the retrieved information 3626 * in data. Assumes semaphore already acquired and page already set. 3627 **/ 3628 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3629 { 3630 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, TRUE); 3631 } 3632 3633 /** 3634 * __e1000_write_phy_reg_hv - Write HV PHY register 3635 * @hw: pointer to the HW structure 3636 * @offset: register offset to write to 3637 * @data: data to write at register offset 3638 * @locked: semaphore has already been acquired or not 3639 * 3640 * Acquires semaphore, if necessary, then writes the data to PHY register 3641 * at the offset. Release any acquired semaphores before exiting. 3642 **/ 3643 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3644 bool locked, bool page_set) 3645 { 3646 s32 ret_val; 3647 u16 page = BM_PHY_REG_PAGE(offset); 3648 u16 reg = BM_PHY_REG_NUM(offset); 3649 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3650 3651 DEBUGFUNC("__e1000_write_phy_reg_hv"); 3652 3653 if (!locked) { 3654 ret_val = hw->phy.ops.acquire(hw); 3655 if (ret_val) 3656 return ret_val; 3657 } 3658 3659 /* Page 800 works differently than the rest so it has its own func */ 3660 if (page == BM_WUC_PAGE) { 3661 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3662 FALSE, page_set); 3663 goto out; 3664 } 3665 3666 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3667 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3668 &data, FALSE); 3669 goto out; 3670 } 3671 3672 if (!page_set) { 3673 if (page == HV_INTC_FC_PAGE_START) 3674 page = 0; 3675 3676 /* Workaround MDIO accesses being disabled after entering IEEE 3677 * Power Down (when bit 11 of the PHY Control register is set) 3678 */ 3679 if ((hw->phy.type == e1000_phy_82578) && 3680 (hw->phy.revision >= 1) && 3681 (hw->phy.addr == 2) && 3682 !(MAX_PHY_REG_ADDRESS & reg) && 3683 (data & (1 << 11))) { 3684 u16 data2 = 0x7EFF; 3685 ret_val = e1000_access_phy_debug_regs_hv(hw, 3686 (1 << 6) | 0x3, 3687 &data2, FALSE); 3688 if (ret_val) 3689 goto out; 3690 } 3691 3692 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3693 /* Page is shifted left, PHY expects (page x 32) */ 3694 ret_val = e1000_set_page_igp(hw, 3695 (page << IGP_PAGE_SHIFT)); 3696 3697 hw->phy.addr = phy_addr; 3698 3699 if (ret_val) 3700 goto out; 3701 } 3702 } 3703 3704 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3705 page << IGP_PAGE_SHIFT, reg); 3706 3707 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3708 data); 3709 3710 out: 3711 if (!locked) 3712 hw->phy.ops.release(hw); 3713 3714 return ret_val; 3715 } 3716 3717 /** 3718 * e1000_write_phy_reg_hv - Write HV PHY register 3719 * @hw: pointer to the HW structure 3720 * @offset: register offset to write to 3721 * @data: data to write at register offset 3722 * 3723 * Acquires semaphore then writes the data to PHY register at the offset. 3724 * Release the acquired semaphores before exiting. 3725 **/ 3726 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3727 { 3728 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE); 3729 } 3730 3731 /** 3732 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3733 * @hw: pointer to the HW structure 3734 * @offset: register offset to write to 3735 * @data: data to write at register offset 3736 * 3737 * Writes the data to PHY register at the offset. Assumes semaphore 3738 * already acquired. 3739 **/ 3740 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3741 { 3742 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3743 } 3744 3745 /** 3746 * e1000_write_phy_reg_page_hv - Write HV PHY register 3747 * @hw: pointer to the HW structure 3748 * @offset: register offset to write to 3749 * @data: data to write at register offset 3750 * 3751 * Writes the data to PHY register at the offset. Assumes semaphore 3752 * already acquired and page already set. 3753 **/ 3754 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 3755 { 3756 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, TRUE); 3757 } 3758 3759 /** 3760 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3761 * @page: page to be accessed 3762 **/ 3763 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3764 { 3765 u32 phy_addr = 2; 3766 3767 if (page >= HV_INTC_FC_PAGE_START) 3768 phy_addr = 1; 3769 3770 return phy_addr; 3771 } 3772 3773 /** 3774 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3775 * @hw: pointer to the HW structure 3776 * @offset: register offset to be read or written 3777 * @data: pointer to the data to be read or written 3778 * @read: determines if operation is read or write 3779 * 3780 * Reads the PHY register at offset and stores the retreived information 3781 * in data. Assumes semaphore already acquired. Note that the procedure 3782 * to access these regs uses the address port and data port to read/write. 3783 * These accesses done with PHY address 2 and without using pages. 3784 **/ 3785 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3786 u16 *data, bool read) 3787 { 3788 s32 ret_val; 3789 u32 addr_reg; 3790 u32 data_reg; 3791 3792 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3793 3794 /* This takes care of the difference with desktop vs mobile phy */ 3795 addr_reg = ((hw->phy.type == e1000_phy_82578) ? 3796 I82578_ADDR_REG : I82577_ADDR_REG); 3797 data_reg = addr_reg + 1; 3798 3799 /* All operations in this function are phy address 2 */ 3800 hw->phy.addr = 2; 3801 3802 /* masking with 0x3F to remove the page from offset */ 3803 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3804 if (ret_val) { 3805 DEBUGOUT("Could not write the Address Offset port register\n"); 3806 return ret_val; 3807 } 3808 3809 /* Read or write the data value next */ 3810 if (read) 3811 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3812 else 3813 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3814 3815 if (ret_val) 3816 DEBUGOUT("Could not access the Data port register\n"); 3817 3818 return ret_val; 3819 } 3820 3821 /** 3822 * e1000_link_stall_workaround_hv - Si workaround 3823 * @hw: pointer to the HW structure 3824 * 3825 * This function works around a Si bug where the link partner can get 3826 * a link up indication before the PHY does. If small packets are sent 3827 * by the link partner they can be placed in the packet buffer without 3828 * being properly accounted for by the PHY and will stall preventing 3829 * further packets from being received. The workaround is to clear the 3830 * packet buffer after the PHY detects link up. 3831 **/ 3832 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3833 { 3834 s32 ret_val = E1000_SUCCESS; 3835 u16 data; 3836 3837 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3838 3839 if (hw->phy.type != e1000_phy_82578) 3840 return E1000_SUCCESS; 3841 3842 /* Do not apply workaround if in PHY loopback bit 14 set */ 3843 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3844 if (data & PHY_CONTROL_LB) 3845 return E1000_SUCCESS; 3846 3847 /* check if link is up and at 1Gbps */ 3848 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3849 if (ret_val) 3850 return ret_val; 3851 3852 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3853 BM_CS_STATUS_SPEED_MASK); 3854 3855 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3856 BM_CS_STATUS_SPEED_1000)) 3857 return E1000_SUCCESS; 3858 3859 msec_delay(200); 3860 3861 /* flush the packets in the fifo buffer */ 3862 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3863 (HV_MUX_DATA_CTRL_GEN_TO_MAC | 3864 HV_MUX_DATA_CTRL_FORCE_SPEED)); 3865 if (ret_val) 3866 return ret_val; 3867 3868 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3869 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3870 } 3871 3872 /** 3873 * e1000_check_polarity_82577 - Checks the polarity. 3874 * @hw: pointer to the HW structure 3875 * 3876 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3877 * 3878 * Polarity is determined based on the PHY specific status register. 3879 **/ 3880 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3881 { 3882 struct e1000_phy_info *phy = &hw->phy; 3883 s32 ret_val; 3884 u16 data; 3885 3886 DEBUGFUNC("e1000_check_polarity_82577"); 3887 3888 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3889 3890 if (!ret_val) 3891 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY) 3892 ? e1000_rev_polarity_reversed 3893 : e1000_rev_polarity_normal); 3894 3895 return ret_val; 3896 } 3897 3898 /** 3899 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3900 * @hw: pointer to the HW structure 3901 * 3902 * Calls the PHY setup function to force speed and duplex. 3903 **/ 3904 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3905 { 3906 struct e1000_phy_info *phy = &hw->phy; 3907 s32 ret_val; 3908 u16 phy_data; 3909 bool link; 3910 3911 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3912 3913 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3914 if (ret_val) 3915 return ret_val; 3916 3917 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3918 3919 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3920 if (ret_val) 3921 return ret_val; 3922 3923 usec_delay(1); 3924 3925 if (phy->autoneg_wait_to_complete) { 3926 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3927 3928 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3929 100000, &link); 3930 if (ret_val) 3931 return ret_val; 3932 3933 if (!link) 3934 DEBUGOUT("Link taking longer than expected.\n"); 3935 3936 /* Try once more */ 3937 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3938 100000, &link); 3939 } 3940 3941 return ret_val; 3942 } 3943 3944 /** 3945 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3946 * @hw: pointer to the HW structure 3947 * 3948 * Read PHY status to determine if link is up. If link is up, then 3949 * set/determine 10base-T extended distance and polarity correction. Read 3950 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3951 * determine on the cable length, local and remote receiver. 3952 **/ 3953 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3954 { 3955 struct e1000_phy_info *phy = &hw->phy; 3956 s32 ret_val; 3957 u16 data; 3958 bool link; 3959 3960 DEBUGFUNC("e1000_get_phy_info_82577"); 3961 3962 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3963 if (ret_val) 3964 return ret_val; 3965 3966 if (!link) { 3967 DEBUGOUT("Phy info is only valid if link is up\n"); 3968 return -E1000_ERR_CONFIG; 3969 } 3970 3971 phy->polarity_correction = TRUE; 3972 3973 ret_val = e1000_check_polarity_82577(hw); 3974 if (ret_val) 3975 return ret_val; 3976 3977 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3978 if (ret_val) 3979 return ret_val; 3980 3981 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); 3982 3983 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3984 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3985 ret_val = hw->phy.ops.get_cable_length(hw); 3986 if (ret_val) 3987 return ret_val; 3988 3989 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3990 if (ret_val) 3991 return ret_val; 3992 3993 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3994 ? e1000_1000t_rx_status_ok 3995 : e1000_1000t_rx_status_not_ok; 3996 3997 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3998 ? e1000_1000t_rx_status_ok 3999 : e1000_1000t_rx_status_not_ok; 4000 } else { 4001 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 4002 phy->local_rx = e1000_1000t_rx_status_undefined; 4003 phy->remote_rx = e1000_1000t_rx_status_undefined; 4004 } 4005 4006 return E1000_SUCCESS; 4007 } 4008 4009 /** 4010 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 4011 * @hw: pointer to the HW structure 4012 * 4013 * Reads the diagnostic status register and verifies result is valid before 4014 * placing it in the phy_cable_length field. 4015 **/ 4016 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 4017 { 4018 struct e1000_phy_info *phy = &hw->phy; 4019 s32 ret_val; 4020 u16 phy_data, length; 4021 4022 DEBUGFUNC("e1000_get_cable_length_82577"); 4023 4024 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 4025 if (ret_val) 4026 return ret_val; 4027 4028 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 4029 I82577_DSTATUS_CABLE_LENGTH_SHIFT); 4030 4031 if (length == E1000_CABLE_LENGTH_UNDEFINED) 4032 return -E1000_ERR_PHY; 4033 4034 phy->cable_length = length; 4035 4036 return E1000_SUCCESS; 4037 } 4038 4039 /** 4040 * e1000_write_phy_reg_gs40g - Write GS40G PHY register 4041 * @hw: pointer to the HW structure 4042 * @offset: register offset to write to 4043 * @data: data to write at register offset 4044 * 4045 * Acquires semaphore, if necessary, then writes the data to PHY register 4046 * at the offset. Release any acquired semaphores before exiting. 4047 **/ 4048 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 4049 { 4050 s32 ret_val; 4051 u16 page = offset >> GS40G_PAGE_SHIFT; 4052 4053 DEBUGFUNC("e1000_write_phy_reg_gs40g"); 4054 4055 offset = offset & GS40G_OFFSET_MASK; 4056 ret_val = hw->phy.ops.acquire(hw); 4057 if (ret_val) 4058 return ret_val; 4059 4060 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4061 if (ret_val) 4062 goto release; 4063 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 4064 4065 release: 4066 hw->phy.ops.release(hw); 4067 return ret_val; 4068 } 4069 4070 /** 4071 * e1000_read_phy_reg_gs40g - Read GS40G PHY register 4072 * @hw: pointer to the HW structure 4073 * @offset: lower half is register offset to read to 4074 * upper half is page to use. 4075 * @data: data to read at register offset 4076 * 4077 * Acquires semaphore, if necessary, then reads the data in the PHY register 4078 * at the offset. Release any acquired semaphores before exiting. 4079 **/ 4080 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 4081 { 4082 s32 ret_val; 4083 u16 page = offset >> GS40G_PAGE_SHIFT; 4084 4085 DEBUGFUNC("e1000_read_phy_reg_gs40g"); 4086 4087 offset = offset & GS40G_OFFSET_MASK; 4088 ret_val = hw->phy.ops.acquire(hw); 4089 if (ret_val) 4090 return ret_val; 4091 4092 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4093 if (ret_val) 4094 goto release; 4095 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 4096 4097 release: 4098 hw->phy.ops.release(hw); 4099 return ret_val; 4100 } 4101 4102 /** 4103 * e1000_read_phy_reg_mphy - Read mPHY control register 4104 * @hw: pointer to the HW structure 4105 * @address: address to be read 4106 * @data: pointer to the read data 4107 * 4108 * Reads the mPHY control register in the PHY at offset and stores the 4109 * information read to data. 4110 **/ 4111 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data) 4112 { 4113 u32 mphy_ctrl = 0; 4114 bool locked = FALSE; 4115 bool ready = FALSE; 4116 4117 DEBUGFUNC("e1000_read_phy_reg_mphy"); 4118 4119 /* Check if mPHY is ready to read/write operations */ 4120 ready = e1000_is_mphy_ready(hw); 4121 if (!ready) 4122 return -E1000_ERR_PHY; 4123 4124 /* Check if mPHY access is disabled and enable it if so */ 4125 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4126 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) { 4127 locked = TRUE; 4128 ready = e1000_is_mphy_ready(hw); 4129 if (!ready) 4130 return -E1000_ERR_PHY; 4131 mphy_ctrl |= E1000_MPHY_ENA_ACCESS; 4132 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4133 } 4134 4135 /* Set the address that we want to read */ 4136 ready = e1000_is_mphy_ready(hw); 4137 if (!ready) 4138 return -E1000_ERR_PHY; 4139 mphy_ctrl |= (address & E1000_MPHY_ADDRESS_MASK); 4140 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4141 4142 /* Read data from the address */ 4143 ready = e1000_is_mphy_ready(hw); 4144 if (!ready) 4145 return -E1000_ERR_PHY; 4146 *data = E1000_READ_REG(hw, E1000_MPHY_DATA); 4147 4148 /* Disable access to mPHY if it was originally disabled */ 4149 if (locked) { 4150 ready = e1000_is_mphy_ready(hw); 4151 if (!ready) 4152 return -E1000_ERR_PHY; 4153 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, 4154 E1000_MPHY_DIS_ACCESS); 4155 } 4156 4157 return E1000_SUCCESS; 4158 } 4159 4160 /** 4161 * e1000_write_phy_reg_mphy - Write mPHY control register 4162 * @hw: pointer to the HW structure 4163 * @address: address to write to 4164 * @data: data to write to register at offset 4165 * 4166 * Writes data to mPHY control register. 4167 **/ 4168 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data) 4169 { 4170 u32 mphy_ctrl = 0; 4171 bool locked = FALSE; 4172 bool ready = FALSE; 4173 4174 DEBUGFUNC("e1000_write_phy_reg_mphy"); 4175 4176 /* Check if mPHY is ready to read/write operations */ 4177 ready = e1000_is_mphy_ready(hw); 4178 if (!ready) 4179 return -E1000_ERR_PHY; 4180 4181 /* Check if mPHY access is disabled and enable it if so */ 4182 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4183 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) { 4184 locked = TRUE; 4185 ready = e1000_is_mphy_ready(hw); 4186 if (!ready) 4187 return -E1000_ERR_PHY; 4188 mphy_ctrl |= E1000_MPHY_ENA_ACCESS; 4189 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4190 } 4191 4192 /* Set the address that we want to read */ 4193 ready = e1000_is_mphy_ready(hw); 4194 if (!ready) 4195 return -E1000_ERR_PHY; 4196 mphy_ctrl |= (address & E1000_MPHY_ADDRESS_MASK); 4197 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4198 4199 /* Read data from the address */ 4200 ready = e1000_is_mphy_ready(hw); 4201 if (!ready) 4202 return -E1000_ERR_PHY; 4203 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data); 4204 4205 /* Disable access to mPHY if it was originally disabled */ 4206 if (locked) { 4207 ready = e1000_is_mphy_ready(hw); 4208 if (!ready) 4209 return -E1000_ERR_PHY; 4210 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, 4211 E1000_MPHY_DIS_ACCESS); 4212 } 4213 4214 return E1000_SUCCESS; 4215 } 4216 4217 /** 4218 * e1000_is_mphy_ready - Check if mPHY control register is not busy 4219 * @hw: pointer to the HW structure 4220 * 4221 * Returns mPHY control register status. 4222 **/ 4223 bool e1000_is_mphy_ready(struct e1000_hw *hw) 4224 { 4225 u16 retry_count = 0; 4226 u32 mphy_ctrl = 0; 4227 bool ready = FALSE; 4228 4229 while (retry_count < 2) { 4230 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4231 if (mphy_ctrl & E1000_MPHY_BUSY) { 4232 usec_delay(20); 4233 retry_count++; 4234 continue; 4235 } 4236 ready = TRUE; 4237 break; 4238 } 4239 4240 if (!ready) 4241 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n"); 4242 4243 return ready; 4244 } 4245