1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: $*/ 34 35 #include "e1000_api.h" 36 37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read, bool page_set); 40 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44 /* Cable length tables */ 45 static const u16 e1000_m88_cable_length_table[] = { 46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 (sizeof(e1000_m88_cable_length_table) / \ 49 sizeof(e1000_m88_cable_length_table[0])) 50 51 static const u16 e1000_igp_2_cable_length_table[] = { 52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 59 124}; 60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61 (sizeof(e1000_igp_2_cable_length_table) / \ 62 sizeof(e1000_igp_2_cable_length_table[0])) 63 64 /** 65 * e1000_init_phy_ops_generic - Initialize PHY function pointers 66 * @hw: pointer to the HW structure 67 * 68 * Setups up the function pointers to no-op functions 69 **/ 70 void e1000_init_phy_ops_generic(struct e1000_hw *hw) 71 { 72 struct e1000_phy_info *phy = &hw->phy; 73 DEBUGFUNC("e1000_init_phy_ops_generic"); 74 75 /* Initialize function pointers */ 76 phy->ops.init_params = e1000_null_ops_generic; 77 phy->ops.acquire = e1000_null_ops_generic; 78 phy->ops.check_polarity = e1000_null_ops_generic; 79 phy->ops.check_reset_block = e1000_null_ops_generic; 80 phy->ops.commit = e1000_null_ops_generic; 81 phy->ops.force_speed_duplex = e1000_null_ops_generic; 82 phy->ops.get_cfg_done = e1000_null_ops_generic; 83 phy->ops.get_cable_length = e1000_null_ops_generic; 84 phy->ops.get_info = e1000_null_ops_generic; 85 phy->ops.set_page = e1000_null_set_page; 86 phy->ops.read_reg = e1000_null_read_reg; 87 phy->ops.read_reg_locked = e1000_null_read_reg; 88 phy->ops.read_reg_page = e1000_null_read_reg; 89 phy->ops.release = e1000_null_phy_generic; 90 phy->ops.reset = e1000_null_ops_generic; 91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 93 phy->ops.write_reg = e1000_null_write_reg; 94 phy->ops.write_reg_locked = e1000_null_write_reg; 95 phy->ops.write_reg_page = e1000_null_write_reg; 96 phy->ops.power_up = e1000_null_phy_generic; 97 phy->ops.power_down = e1000_null_phy_generic; 98 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 99 } 100 101 /** 102 * e1000_null_set_page - No-op function, return 0 103 * @hw: pointer to the HW structure 104 **/ 105 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data) 106 { 107 DEBUGFUNC("e1000_null_set_page"); 108 return E1000_SUCCESS; 109 } 110 111 /** 112 * e1000_null_read_reg - No-op function, return 0 113 * @hw: pointer to the HW structure 114 **/ 115 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) 116 { 117 DEBUGFUNC("e1000_null_read_reg"); 118 return E1000_SUCCESS; 119 } 120 121 /** 122 * e1000_null_phy_generic - No-op function, return void 123 * @hw: pointer to the HW structure 124 **/ 125 void e1000_null_phy_generic(struct e1000_hw *hw) 126 { 127 DEBUGFUNC("e1000_null_phy_generic"); 128 return; 129 } 130 131 /** 132 * e1000_null_lplu_state - No-op function, return 0 133 * @hw: pointer to the HW structure 134 **/ 135 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active) 136 { 137 DEBUGFUNC("e1000_null_lplu_state"); 138 return E1000_SUCCESS; 139 } 140 141 /** 142 * e1000_null_write_reg - No-op function, return 0 143 * @hw: pointer to the HW structure 144 **/ 145 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) 146 { 147 DEBUGFUNC("e1000_null_write_reg"); 148 return E1000_SUCCESS; 149 } 150 151 /** 152 * e1000_check_reset_block_generic - Check if PHY reset is blocked 153 * @hw: pointer to the HW structure 154 * 155 * Read the PHY management control register and check whether a PHY reset 156 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 157 * return E1000_BLK_PHY_RESET (12). 158 **/ 159 s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 160 { 161 u32 manc; 162 163 DEBUGFUNC("e1000_check_reset_block"); 164 165 manc = E1000_READ_REG(hw, E1000_MANC); 166 167 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 168 E1000_BLK_PHY_RESET : E1000_SUCCESS; 169 } 170 171 /** 172 * e1000_get_phy_id - Retrieve the PHY ID and revision 173 * @hw: pointer to the HW structure 174 * 175 * Reads the PHY registers and stores the PHY ID and possibly the PHY 176 * revision in the hardware structure. 177 **/ 178 s32 e1000_get_phy_id(struct e1000_hw *hw) 179 { 180 struct e1000_phy_info *phy = &hw->phy; 181 s32 ret_val = E1000_SUCCESS; 182 u16 phy_id; 183 u16 retry_count = 0; 184 185 DEBUGFUNC("e1000_get_phy_id"); 186 187 if (!(phy->ops.read_reg)) 188 goto out; 189 190 while (retry_count < 2) { 191 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 192 if (ret_val) 193 goto out; 194 195 phy->id = (u32)(phy_id << 16); 196 usec_delay(20); 197 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 198 if (ret_val) 199 goto out; 200 201 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 202 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 203 204 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 205 goto out; 206 207 retry_count++; 208 } 209 out: 210 return ret_val; 211 } 212 213 /** 214 * e1000_phy_reset_dsp_generic - Reset PHY DSP 215 * @hw: pointer to the HW structure 216 * 217 * Reset the digital signal processor. 218 **/ 219 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 220 { 221 s32 ret_val = E1000_SUCCESS; 222 223 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 224 225 if (!(hw->phy.ops.write_reg)) 226 goto out; 227 228 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 229 if (ret_val) 230 goto out; 231 232 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 233 234 out: 235 return ret_val; 236 } 237 238 /** 239 * e1000_read_phy_reg_mdic - Read MDI control register 240 * @hw: pointer to the HW structure 241 * @offset: register offset to be read 242 * @data: pointer to the read data 243 * 244 * Reads the MDI control register in the PHY at offset and stores the 245 * information read to data. 246 **/ 247 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 248 { 249 struct e1000_phy_info *phy = &hw->phy; 250 u32 i, mdic = 0; 251 s32 ret_val = E1000_SUCCESS; 252 253 DEBUGFUNC("e1000_read_phy_reg_mdic"); 254 255 if (offset > MAX_PHY_REG_ADDRESS) { 256 DEBUGOUT1("PHY Address %d is out of range\n", offset); 257 return -E1000_ERR_PARAM; 258 } 259 260 /* 261 * Set up Op-code, Phy Address, and register offset in the MDI 262 * Control register. The MAC will take care of interfacing with the 263 * PHY to retrieve the desired data. 264 */ 265 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 266 (phy->addr << E1000_MDIC_PHY_SHIFT) | 267 (E1000_MDIC_OP_READ)); 268 269 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 270 271 /* 272 * Poll the ready bit to see if the MDI read completed 273 * Increasing the time out as testing showed failures with 274 * the lower time out 275 */ 276 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 277 usec_delay(50); 278 mdic = E1000_READ_REG(hw, E1000_MDIC); 279 if (mdic & E1000_MDIC_READY) 280 break; 281 } 282 if (!(mdic & E1000_MDIC_READY)) { 283 DEBUGOUT("MDI Read did not complete\n"); 284 ret_val = -E1000_ERR_PHY; 285 goto out; 286 } 287 if (mdic & E1000_MDIC_ERROR) { 288 DEBUGOUT("MDI Error\n"); 289 ret_val = -E1000_ERR_PHY; 290 goto out; 291 } 292 *data = (u16) mdic; 293 294 /* 295 * Allow some time after each MDIC transaction to avoid 296 * reading duplicate data in the next MDIC transaction. 297 */ 298 if (hw->mac.type == e1000_pch2lan) 299 usec_delay(100); 300 301 out: 302 return ret_val; 303 } 304 305 /** 306 * e1000_write_phy_reg_mdic - Write MDI control register 307 * @hw: pointer to the HW structure 308 * @offset: register offset to write to 309 * @data: data to write to register at offset 310 * 311 * Writes data to MDI control register in the PHY at offset. 312 **/ 313 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 314 { 315 struct e1000_phy_info *phy = &hw->phy; 316 u32 i, mdic = 0; 317 s32 ret_val = E1000_SUCCESS; 318 319 DEBUGFUNC("e1000_write_phy_reg_mdic"); 320 321 if (offset > MAX_PHY_REG_ADDRESS) { 322 DEBUGOUT1("PHY Address %d is out of range\n", offset); 323 return -E1000_ERR_PARAM; 324 } 325 326 /* 327 * Set up Op-code, Phy Address, and register offset in the MDI 328 * Control register. The MAC will take care of interfacing with the 329 * PHY to retrieve the desired data. 330 */ 331 mdic = (((u32)data) | 332 (offset << E1000_MDIC_REG_SHIFT) | 333 (phy->addr << E1000_MDIC_PHY_SHIFT) | 334 (E1000_MDIC_OP_WRITE)); 335 336 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 337 338 /* 339 * Poll the ready bit to see if the MDI read completed 340 * Increasing the time out as testing showed failures with 341 * the lower time out 342 */ 343 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 344 usec_delay(50); 345 mdic = E1000_READ_REG(hw, E1000_MDIC); 346 if (mdic & E1000_MDIC_READY) 347 break; 348 } 349 if (!(mdic & E1000_MDIC_READY)) { 350 DEBUGOUT("MDI Write did not complete\n"); 351 ret_val = -E1000_ERR_PHY; 352 goto out; 353 } 354 if (mdic & E1000_MDIC_ERROR) { 355 DEBUGOUT("MDI Error\n"); 356 ret_val = -E1000_ERR_PHY; 357 goto out; 358 } 359 360 /* 361 * Allow some time after each MDIC transaction to avoid 362 * reading duplicate data in the next MDIC transaction. 363 */ 364 if (hw->mac.type == e1000_pch2lan) 365 usec_delay(100); 366 367 out: 368 return ret_val; 369 } 370 371 /** 372 * e1000_read_phy_reg_i2c - Read PHY register using i2c 373 * @hw: pointer to the HW structure 374 * @offset: register offset to be read 375 * @data: pointer to the read data 376 * 377 * Reads the PHY register at offset using the i2c interface and stores the 378 * retrieved information in data. 379 **/ 380 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 381 { 382 struct e1000_phy_info *phy = &hw->phy; 383 u32 i, i2ccmd = 0; 384 385 DEBUGFUNC("e1000_read_phy_reg_i2c"); 386 387 /* 388 * Set up Op-code, Phy Address, and register address in the I2CCMD 389 * register. The MAC will take care of interfacing with the 390 * PHY to retrieve the desired data. 391 */ 392 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 393 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 394 (E1000_I2CCMD_OPCODE_READ)); 395 396 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 397 398 /* Poll the ready bit to see if the I2C read completed */ 399 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 400 usec_delay(50); 401 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 402 if (i2ccmd & E1000_I2CCMD_READY) 403 break; 404 } 405 if (!(i2ccmd & E1000_I2CCMD_READY)) { 406 DEBUGOUT("I2CCMD Read did not complete\n"); 407 return -E1000_ERR_PHY; 408 } 409 if (i2ccmd & E1000_I2CCMD_ERROR) { 410 DEBUGOUT("I2CCMD Error bit set\n"); 411 return -E1000_ERR_PHY; 412 } 413 414 /* Need to byte-swap the 16-bit value. */ 415 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 416 417 return E1000_SUCCESS; 418 } 419 420 /** 421 * e1000_write_phy_reg_i2c - Write PHY register using i2c 422 * @hw: pointer to the HW structure 423 * @offset: register offset to write to 424 * @data: data to write at register offset 425 * 426 * Writes the data to PHY register at the offset using the i2c interface. 427 **/ 428 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 429 { 430 struct e1000_phy_info *phy = &hw->phy; 431 u32 i, i2ccmd = 0; 432 u16 phy_data_swapped; 433 434 DEBUGFUNC("e1000_write_phy_reg_i2c"); 435 436 /* Swap the data bytes for the I2C interface */ 437 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 438 439 /* 440 * Set up Op-code, Phy Address, and register address in the I2CCMD 441 * register. The MAC will take care of interfacing with the 442 * PHY to retrieve the desired data. 443 */ 444 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 445 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 446 E1000_I2CCMD_OPCODE_WRITE | 447 phy_data_swapped); 448 449 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 450 451 /* Poll the ready bit to see if the I2C read completed */ 452 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 453 usec_delay(50); 454 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 455 if (i2ccmd & E1000_I2CCMD_READY) 456 break; 457 } 458 if (!(i2ccmd & E1000_I2CCMD_READY)) { 459 DEBUGOUT("I2CCMD Write did not complete\n"); 460 return -E1000_ERR_PHY; 461 } 462 if (i2ccmd & E1000_I2CCMD_ERROR) { 463 DEBUGOUT("I2CCMD Error bit set\n"); 464 return -E1000_ERR_PHY; 465 } 466 467 return E1000_SUCCESS; 468 } 469 470 /** 471 * e1000_read_phy_reg_m88 - Read m88 PHY register 472 * @hw: pointer to the HW structure 473 * @offset: register offset to be read 474 * @data: pointer to the read data 475 * 476 * Acquires semaphore, if necessary, then reads the PHY register at offset 477 * and storing the retrieved information in data. Release any acquired 478 * semaphores before exiting. 479 **/ 480 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 481 { 482 s32 ret_val = E1000_SUCCESS; 483 484 DEBUGFUNC("e1000_read_phy_reg_m88"); 485 486 if (!(hw->phy.ops.acquire)) 487 goto out; 488 489 ret_val = hw->phy.ops.acquire(hw); 490 if (ret_val) 491 goto out; 492 493 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 494 data); 495 496 hw->phy.ops.release(hw); 497 498 out: 499 return ret_val; 500 } 501 502 /** 503 * e1000_write_phy_reg_m88 - Write m88 PHY register 504 * @hw: pointer to the HW structure 505 * @offset: register offset to write to 506 * @data: data to write at register offset 507 * 508 * Acquires semaphore, if necessary, then writes the data to PHY register 509 * at the offset. Release any acquired semaphores before exiting. 510 **/ 511 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 512 { 513 s32 ret_val = E1000_SUCCESS; 514 515 DEBUGFUNC("e1000_write_phy_reg_m88"); 516 517 if (!(hw->phy.ops.acquire)) 518 goto out; 519 520 ret_val = hw->phy.ops.acquire(hw); 521 if (ret_val) 522 goto out; 523 524 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 525 data); 526 527 hw->phy.ops.release(hw); 528 529 out: 530 return ret_val; 531 } 532 533 /** 534 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 535 * @hw: pointer to the HW structure 536 * @page: page to set (shifted left when necessary) 537 * 538 * Sets PHY page required for PHY register access. Assumes semaphore is 539 * already acquired. Note, this function sets phy.addr to 1 so the caller 540 * must set it appropriately (if necessary) after this function returns. 541 **/ 542 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 543 { 544 DEBUGFUNC("e1000_set_page_igp"); 545 546 DEBUGOUT1("Setting page 0x%x\n", page); 547 548 hw->phy.addr = 1; 549 550 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 551 } 552 553 /** 554 * __e1000_read_phy_reg_igp - Read igp PHY register 555 * @hw: pointer to the HW structure 556 * @offset: register offset to be read 557 * @data: pointer to the read data 558 * @locked: semaphore has already been acquired or not 559 * 560 * Acquires semaphore, if necessary, then reads the PHY register at offset 561 * and stores the retrieved information in data. Release any acquired 562 * semaphores before exiting. 563 **/ 564 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 565 bool locked) 566 { 567 s32 ret_val = E1000_SUCCESS; 568 569 DEBUGFUNC("__e1000_read_phy_reg_igp"); 570 571 if (!locked) { 572 if (!(hw->phy.ops.acquire)) 573 goto out; 574 575 ret_val = hw->phy.ops.acquire(hw); 576 if (ret_val) 577 goto out; 578 } 579 580 if (offset > MAX_PHY_MULTI_PAGE_REG) { 581 ret_val = e1000_write_phy_reg_mdic(hw, 582 IGP01E1000_PHY_PAGE_SELECT, 583 (u16)offset); 584 if (ret_val) 585 goto release; 586 } 587 588 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 589 data); 590 591 release: 592 if (!locked) 593 hw->phy.ops.release(hw); 594 out: 595 return ret_val; 596 } 597 598 /** 599 * e1000_read_phy_reg_igp - Read igp PHY register 600 * @hw: pointer to the HW structure 601 * @offset: register offset to be read 602 * @data: pointer to the read data 603 * 604 * Acquires semaphore then reads the PHY register at offset and stores the 605 * retrieved information in data. 606 * Release the acquired semaphore before exiting. 607 **/ 608 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 609 { 610 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); 611 } 612 613 /** 614 * e1000_read_phy_reg_igp_locked - Read igp PHY register 615 * @hw: pointer to the HW structure 616 * @offset: register offset to be read 617 * @data: pointer to the read data 618 * 619 * Reads the PHY register at offset and stores the retrieved information 620 * in data. Assumes semaphore already acquired. 621 **/ 622 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 623 { 624 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); 625 } 626 627 /** 628 * e1000_write_phy_reg_igp - Write igp PHY register 629 * @hw: pointer to the HW structure 630 * @offset: register offset to write to 631 * @data: data to write at register offset 632 * @locked: semaphore has already been acquired or not 633 * 634 * Acquires semaphore, if necessary, then writes the data to PHY register 635 * at the offset. Release any acquired semaphores before exiting. 636 **/ 637 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 638 bool locked) 639 { 640 s32 ret_val = E1000_SUCCESS; 641 642 DEBUGFUNC("e1000_write_phy_reg_igp"); 643 644 if (!locked) { 645 if (!(hw->phy.ops.acquire)) 646 goto out; 647 648 ret_val = hw->phy.ops.acquire(hw); 649 if (ret_val) 650 goto out; 651 } 652 653 if (offset > MAX_PHY_MULTI_PAGE_REG) { 654 ret_val = e1000_write_phy_reg_mdic(hw, 655 IGP01E1000_PHY_PAGE_SELECT, 656 (u16)offset); 657 if (ret_val) 658 goto release; 659 } 660 661 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 662 data); 663 664 release: 665 if (!locked) 666 hw->phy.ops.release(hw); 667 668 out: 669 return ret_val; 670 } 671 672 /** 673 * e1000_write_phy_reg_igp - Write igp PHY register 674 * @hw: pointer to the HW structure 675 * @offset: register offset to write to 676 * @data: data to write at register offset 677 * 678 * Acquires semaphore then writes the data to PHY register 679 * at the offset. Release any acquired semaphores before exiting. 680 **/ 681 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 682 { 683 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); 684 } 685 686 /** 687 * e1000_write_phy_reg_igp_locked - Write igp PHY register 688 * @hw: pointer to the HW structure 689 * @offset: register offset to write to 690 * @data: data to write at register offset 691 * 692 * Writes the data to PHY register at the offset. 693 * Assumes semaphore already acquired. 694 **/ 695 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 696 { 697 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); 698 } 699 700 /** 701 * __e1000_read_kmrn_reg - Read kumeran register 702 * @hw: pointer to the HW structure 703 * @offset: register offset to be read 704 * @data: pointer to the read data 705 * @locked: semaphore has already been acquired or not 706 * 707 * Acquires semaphore, if necessary. Then reads the PHY register at offset 708 * using the kumeran interface. The information retrieved is stored in data. 709 * Release any acquired semaphores before exiting. 710 **/ 711 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 712 bool locked) 713 { 714 u32 kmrnctrlsta; 715 s32 ret_val = E1000_SUCCESS; 716 717 DEBUGFUNC("__e1000_read_kmrn_reg"); 718 719 if (!locked) { 720 if (!(hw->phy.ops.acquire)) 721 goto out; 722 723 ret_val = hw->phy.ops.acquire(hw); 724 if (ret_val) 725 goto out; 726 } 727 728 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 729 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 730 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 731 732 usec_delay(2); 733 734 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 735 *data = (u16)kmrnctrlsta; 736 737 if (!locked) 738 hw->phy.ops.release(hw); 739 740 out: 741 return ret_val; 742 } 743 744 /** 745 * e1000_read_kmrn_reg_generic - Read kumeran register 746 * @hw: pointer to the HW structure 747 * @offset: register offset to be read 748 * @data: pointer to the read data 749 * 750 * Acquires semaphore then reads the PHY register at offset using the 751 * kumeran interface. The information retrieved is stored in data. 752 * Release the acquired semaphore before exiting. 753 **/ 754 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 755 { 756 return __e1000_read_kmrn_reg(hw, offset, data, FALSE); 757 } 758 759 /** 760 * e1000_read_kmrn_reg_locked - Read kumeran register 761 * @hw: pointer to the HW structure 762 * @offset: register offset to be read 763 * @data: pointer to the read data 764 * 765 * Reads the PHY register at offset using the kumeran interface. The 766 * information retrieved is stored in data. 767 * Assumes semaphore already acquired. 768 **/ 769 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 770 { 771 return __e1000_read_kmrn_reg(hw, offset, data, TRUE); 772 } 773 774 /** 775 * __e1000_write_kmrn_reg - Write kumeran register 776 * @hw: pointer to the HW structure 777 * @offset: register offset to write to 778 * @data: data to write at register offset 779 * @locked: semaphore has already been acquired or not 780 * 781 * Acquires semaphore, if necessary. Then write the data to PHY register 782 * at the offset using the kumeran interface. Release any acquired semaphores 783 * before exiting. 784 **/ 785 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 786 bool locked) 787 { 788 u32 kmrnctrlsta; 789 s32 ret_val = E1000_SUCCESS; 790 791 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 792 793 if (!locked) { 794 if (!(hw->phy.ops.acquire)) 795 goto out; 796 797 ret_val = hw->phy.ops.acquire(hw); 798 if (ret_val) 799 goto out; 800 } 801 802 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 803 E1000_KMRNCTRLSTA_OFFSET) | data; 804 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 805 806 usec_delay(2); 807 808 if (!locked) 809 hw->phy.ops.release(hw); 810 811 out: 812 return ret_val; 813 } 814 815 /** 816 * e1000_write_kmrn_reg_generic - Write kumeran register 817 * @hw: pointer to the HW structure 818 * @offset: register offset to write to 819 * @data: data to write at register offset 820 * 821 * Acquires semaphore then writes the data to the PHY register at the offset 822 * using the kumeran interface. Release the acquired semaphore before exiting. 823 **/ 824 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 825 { 826 return __e1000_write_kmrn_reg(hw, offset, data, FALSE); 827 } 828 829 /** 830 * e1000_write_kmrn_reg_locked - Write kumeran register 831 * @hw: pointer to the HW structure 832 * @offset: register offset to write to 833 * @data: data to write at register offset 834 * 835 * Write the data to PHY register at the offset using the kumeran interface. 836 * Assumes semaphore already acquired. 837 **/ 838 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 839 { 840 return __e1000_write_kmrn_reg(hw, offset, data, TRUE); 841 } 842 843 /** 844 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 845 * @hw: pointer to the HW structure 846 * 847 * Sets up Carrier-sense on Transmit and downshift values. 848 **/ 849 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 850 { 851 s32 ret_val; 852 u16 phy_data; 853 854 DEBUGFUNC("e1000_copper_link_setup_82577"); 855 856 if (hw->phy.reset_disable) { 857 ret_val = E1000_SUCCESS; 858 goto out; 859 } 860 861 if (hw->phy.type == e1000_phy_82580) { 862 ret_val = hw->phy.ops.reset(hw); 863 if (ret_val) { 864 DEBUGOUT("Error resetting the PHY.\n"); 865 goto out; 866 } 867 } 868 869 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 870 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); 871 if (ret_val) 872 goto out; 873 874 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 875 876 /* Enable downshift */ 877 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 878 879 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 880 881 out: 882 return ret_val; 883 } 884 885 /** 886 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 887 * @hw: pointer to the HW structure 888 * 889 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 890 * and downshift values are set also. 891 **/ 892 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 893 { 894 struct e1000_phy_info *phy = &hw->phy; 895 s32 ret_val; 896 u16 phy_data; 897 898 DEBUGFUNC("e1000_copper_link_setup_m88"); 899 900 if (phy->reset_disable) { 901 ret_val = E1000_SUCCESS; 902 goto out; 903 } 904 905 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 906 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 907 if (ret_val) 908 goto out; 909 910 /* For BM PHY this bit is downshift enable */ 911 if (phy->type != e1000_phy_bm) 912 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 913 914 /* 915 * Options: 916 * MDI/MDI-X = 0 (default) 917 * 0 - Auto for all speeds 918 * 1 - MDI mode 919 * 2 - MDI-X mode 920 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 921 */ 922 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 923 924 switch (phy->mdix) { 925 case 1: 926 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 927 break; 928 case 2: 929 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 930 break; 931 case 3: 932 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 933 break; 934 case 0: 935 default: 936 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 937 break; 938 } 939 940 /* 941 * Options: 942 * disable_polarity_correction = 0 (default) 943 * Automatic Correction for Reversed Cable Polarity 944 * 0 - Disabled 945 * 1 - Enabled 946 */ 947 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 948 if (phy->disable_polarity_correction == 1) 949 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 950 951 /* Enable downshift on BM (disabled by default) */ 952 if (phy->type == e1000_phy_bm) 953 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 954 955 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 956 if (ret_val) 957 goto out; 958 959 if ((phy->type == e1000_phy_m88) && 960 (phy->revision < E1000_REVISION_4) && 961 (phy->id != BME1000_E_PHY_ID_R2)) { 962 /* 963 * Force TX_CLK in the Extended PHY Specific Control Register 964 * to 25MHz clock. 965 */ 966 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 967 &phy_data); 968 if (ret_val) 969 goto out; 970 971 phy_data |= M88E1000_EPSCR_TX_CLK_25; 972 973 if ((phy->revision == E1000_REVISION_2) && 974 (phy->id == M88E1111_I_PHY_ID)) { 975 /* 82573L PHY - set the downshift counter to 5x. */ 976 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 977 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 978 } else { 979 /* Configure Master and Slave downshift values */ 980 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 981 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 982 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 983 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 984 } 985 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 986 phy_data); 987 if (ret_val) 988 goto out; 989 } 990 991 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 992 /* Set PHY page 0, register 29 to 0x0003 */ 993 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 994 if (ret_val) 995 goto out; 996 997 /* Set PHY page 0, register 30 to 0x0000 */ 998 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 999 if (ret_val) 1000 goto out; 1001 } 1002 1003 /* Commit the changes. */ 1004 ret_val = phy->ops.commit(hw); 1005 if (ret_val) { 1006 DEBUGOUT("Error committing the PHY changes\n"); 1007 goto out; 1008 } 1009 1010 if (phy->type == e1000_phy_82578) { 1011 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1012 &phy_data); 1013 if (ret_val) 1014 goto out; 1015 1016 /* 82578 PHY - set the downshift count to 1x. */ 1017 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 1018 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 1019 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1020 phy_data); 1021 if (ret_val) 1022 goto out; 1023 } 1024 1025 out: 1026 return ret_val; 1027 } 1028 1029 /** 1030 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 1031 * @hw: pointer to the HW structure 1032 * 1033 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 1034 * Also enables and sets the downshift parameters. 1035 **/ 1036 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) 1037 { 1038 struct e1000_phy_info *phy = &hw->phy; 1039 s32 ret_val; 1040 u16 phy_data; 1041 1042 DEBUGFUNC("e1000_copper_link_setup_m88_gen2"); 1043 1044 if (phy->reset_disable) { 1045 ret_val = E1000_SUCCESS; 1046 goto out; 1047 } 1048 1049 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1050 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1051 if (ret_val) 1052 goto out; 1053 1054 /* 1055 * Options: 1056 * MDI/MDI-X = 0 (default) 1057 * 0 - Auto for all speeds 1058 * 1 - MDI mode 1059 * 2 - MDI-X mode 1060 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1061 */ 1062 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1063 1064 switch (phy->mdix) { 1065 case 1: 1066 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1067 break; 1068 case 2: 1069 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1070 break; 1071 case 3: 1072 /* M88E1112 does not support this mode) */ 1073 if (phy->id != M88E1112_E_PHY_ID) { 1074 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1075 break; 1076 } 1077 case 0: 1078 default: 1079 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1080 break; 1081 } 1082 1083 /* 1084 * Options: 1085 * disable_polarity_correction = 0 (default) 1086 * Automatic Correction for Reversed Cable Polarity 1087 * 0 - Disabled 1088 * 1 - Enabled 1089 */ 1090 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1091 if (phy->disable_polarity_correction == 1) 1092 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1093 1094 /* Enable downshift and setting it to X6 */ 1095 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 1096 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 1097 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 1098 1099 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1100 if (ret_val) 1101 goto out; 1102 1103 /* Commit the changes. */ 1104 ret_val = phy->ops.commit(hw); 1105 if (ret_val) { 1106 DEBUGOUT("Error committing the PHY changes\n"); 1107 goto out; 1108 } 1109 1110 out: 1111 return ret_val; 1112 } 1113 1114 /** 1115 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 1116 * @hw: pointer to the HW structure 1117 * 1118 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 1119 * igp PHY's. 1120 **/ 1121 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 1122 { 1123 struct e1000_phy_info *phy = &hw->phy; 1124 s32 ret_val; 1125 u16 data; 1126 1127 DEBUGFUNC("e1000_copper_link_setup_igp"); 1128 1129 if (phy->reset_disable) { 1130 ret_val = E1000_SUCCESS; 1131 goto out; 1132 } 1133 1134 ret_val = hw->phy.ops.reset(hw); 1135 if (ret_val) { 1136 DEBUGOUT("Error resetting the PHY.\n"); 1137 goto out; 1138 } 1139 1140 /* 1141 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 1142 * timeout issues when LFS is enabled. 1143 */ 1144 msec_delay(100); 1145 1146 /* 1147 * The NVM settings will configure LPLU in D3 for 1148 * non-IGP1 PHYs. 1149 */ 1150 if (phy->type == e1000_phy_igp) { 1151 /* disable lplu d3 during driver init */ 1152 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 1153 if (ret_val) { 1154 DEBUGOUT("Error Disabling LPLU D3\n"); 1155 goto out; 1156 } 1157 } 1158 1159 /* disable lplu d0 during driver init */ 1160 if (hw->phy.ops.set_d0_lplu_state) { 1161 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 1162 if (ret_val) { 1163 DEBUGOUT("Error Disabling LPLU D0\n"); 1164 goto out; 1165 } 1166 } 1167 /* Configure mdi-mdix settings */ 1168 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1169 if (ret_val) 1170 goto out; 1171 1172 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1173 1174 switch (phy->mdix) { 1175 case 1: 1176 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1177 break; 1178 case 2: 1179 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1180 break; 1181 case 0: 1182 default: 1183 data |= IGP01E1000_PSCR_AUTO_MDIX; 1184 break; 1185 } 1186 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1187 if (ret_val) 1188 goto out; 1189 1190 /* set auto-master slave resolution settings */ 1191 if (hw->mac.autoneg) { 1192 /* 1193 * when autonegotiation advertisement is only 1000Mbps then we 1194 * should disable SmartSpeed and enable Auto MasterSlave 1195 * resolution as hardware default. 1196 */ 1197 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1198 /* Disable SmartSpeed */ 1199 ret_val = phy->ops.read_reg(hw, 1200 IGP01E1000_PHY_PORT_CONFIG, 1201 &data); 1202 if (ret_val) 1203 goto out; 1204 1205 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1206 ret_val = phy->ops.write_reg(hw, 1207 IGP01E1000_PHY_PORT_CONFIG, 1208 data); 1209 if (ret_val) 1210 goto out; 1211 1212 /* Set auto Master/Slave resolution process */ 1213 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1214 if (ret_val) 1215 goto out; 1216 1217 data &= ~CR_1000T_MS_ENABLE; 1218 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1219 if (ret_val) 1220 goto out; 1221 } 1222 1223 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1224 if (ret_val) 1225 goto out; 1226 1227 /* load defaults for future use */ 1228 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 1229 ((data & CR_1000T_MS_VALUE) ? 1230 e1000_ms_force_master : 1231 e1000_ms_force_slave) : 1232 e1000_ms_auto; 1233 1234 switch (phy->ms_type) { 1235 case e1000_ms_force_master: 1236 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1237 break; 1238 case e1000_ms_force_slave: 1239 data |= CR_1000T_MS_ENABLE; 1240 data &= ~(CR_1000T_MS_VALUE); 1241 break; 1242 case e1000_ms_auto: 1243 data &= ~CR_1000T_MS_ENABLE; 1244 default: 1245 break; 1246 } 1247 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1248 if (ret_val) 1249 goto out; 1250 } 1251 1252 out: 1253 return ret_val; 1254 } 1255 1256 /** 1257 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1258 * @hw: pointer to the HW structure 1259 * 1260 * Performs initial bounds checking on autoneg advertisement parameter, then 1261 * configure to advertise the full capability. Setup the PHY to autoneg 1262 * and restart the negotiation process between the link partner. If 1263 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1264 **/ 1265 s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1266 { 1267 struct e1000_phy_info *phy = &hw->phy; 1268 s32 ret_val; 1269 u16 phy_ctrl; 1270 1271 DEBUGFUNC("e1000_copper_link_autoneg"); 1272 1273 /* 1274 * Perform some bounds checking on the autoneg advertisement 1275 * parameter. 1276 */ 1277 phy->autoneg_advertised &= phy->autoneg_mask; 1278 1279 /* 1280 * If autoneg_advertised is zero, we assume it was not defaulted 1281 * by the calling code so we set to advertise full capability. 1282 */ 1283 if (phy->autoneg_advertised == 0) 1284 phy->autoneg_advertised = phy->autoneg_mask; 1285 1286 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1287 ret_val = e1000_phy_setup_autoneg(hw); 1288 if (ret_val) { 1289 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1290 goto out; 1291 } 1292 DEBUGOUT("Restarting Auto-Neg\n"); 1293 1294 /* 1295 * Restart auto-negotiation by setting the Auto Neg Enable bit and 1296 * the Auto Neg Restart bit in the PHY control register. 1297 */ 1298 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1299 if (ret_val) 1300 goto out; 1301 1302 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1303 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1304 if (ret_val) 1305 goto out; 1306 1307 /* 1308 * Does the user want to wait for Auto-Neg to complete here, or 1309 * check at a later time (for example, callback routine). 1310 */ 1311 if (phy->autoneg_wait_to_complete) { 1312 ret_val = hw->mac.ops.wait_autoneg(hw); 1313 if (ret_val) { 1314 DEBUGOUT("Error while waiting for " 1315 "autoneg to complete\n"); 1316 goto out; 1317 } 1318 } 1319 1320 hw->mac.get_link_status = TRUE; 1321 1322 out: 1323 return ret_val; 1324 } 1325 1326 /** 1327 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1328 * @hw: pointer to the HW structure 1329 * 1330 * Reads the MII auto-neg advertisement register and/or the 1000T control 1331 * register and if the PHY is already setup for auto-negotiation, then 1332 * return successful. Otherwise, setup advertisement and flow control to 1333 * the appropriate values for the wanted auto-negotiation. 1334 **/ 1335 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1336 { 1337 struct e1000_phy_info *phy = &hw->phy; 1338 s32 ret_val; 1339 u16 mii_autoneg_adv_reg; 1340 u16 mii_1000t_ctrl_reg = 0; 1341 1342 DEBUGFUNC("e1000_phy_setup_autoneg"); 1343 1344 phy->autoneg_advertised &= phy->autoneg_mask; 1345 1346 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1347 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1348 if (ret_val) 1349 goto out; 1350 1351 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1352 /* Read the MII 1000Base-T Control Register (Address 9). */ 1353 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1354 &mii_1000t_ctrl_reg); 1355 if (ret_val) 1356 goto out; 1357 } 1358 1359 /* 1360 * Need to parse both autoneg_advertised and fc and set up 1361 * the appropriate PHY registers. First we will parse for 1362 * autoneg_advertised software override. Since we can advertise 1363 * a plethora of combinations, we need to check each bit 1364 * individually. 1365 */ 1366 1367 /* 1368 * First we clear all the 10/100 mb speed bits in the Auto-Neg 1369 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1370 * the 1000Base-T Control Register (Address 9). 1371 */ 1372 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1373 NWAY_AR_100TX_HD_CAPS | 1374 NWAY_AR_10T_FD_CAPS | 1375 NWAY_AR_10T_HD_CAPS); 1376 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1377 1378 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1379 1380 /* Do we want to advertise 10 Mb Half Duplex? */ 1381 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1382 DEBUGOUT("Advertise 10mb Half duplex\n"); 1383 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1384 } 1385 1386 /* Do we want to advertise 10 Mb Full Duplex? */ 1387 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1388 DEBUGOUT("Advertise 10mb Full duplex\n"); 1389 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1390 } 1391 1392 /* Do we want to advertise 100 Mb Half Duplex? */ 1393 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1394 DEBUGOUT("Advertise 100mb Half duplex\n"); 1395 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1396 } 1397 1398 /* Do we want to advertise 100 Mb Full Duplex? */ 1399 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1400 DEBUGOUT("Advertise 100mb Full duplex\n"); 1401 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1402 } 1403 1404 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1405 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1406 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1407 1408 /* Do we want to advertise 1000 Mb Full Duplex? */ 1409 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1410 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1411 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1412 } 1413 1414 /* 1415 * Check for a software override of the flow control settings, and 1416 * setup the PHY advertisement registers accordingly. If 1417 * auto-negotiation is enabled, then software will have to set the 1418 * "PAUSE" bits to the correct value in the Auto-Negotiation 1419 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1420 * negotiation. 1421 * 1422 * The possible values of the "fc" parameter are: 1423 * 0: Flow control is completely disabled 1424 * 1: Rx flow control is enabled (we can receive pause frames 1425 * but not send pause frames). 1426 * 2: Tx flow control is enabled (we can send pause frames 1427 * but we do not support receiving pause frames). 1428 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1429 * other: No software override. The flow control configuration 1430 * in the EEPROM is used. 1431 */ 1432 switch (hw->fc.current_mode) { 1433 case e1000_fc_none: 1434 /* 1435 * Flow control (Rx & Tx) is completely disabled by a 1436 * software over-ride. 1437 */ 1438 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1439 break; 1440 case e1000_fc_rx_pause: 1441 /* 1442 * Rx Flow control is enabled, and Tx Flow control is 1443 * disabled, by a software over-ride. 1444 * 1445 * Since there really isn't a way to advertise that we are 1446 * capable of Rx Pause ONLY, we will advertise that we 1447 * support both symmetric and asymmetric Rx PAUSE. Later 1448 * (in e1000_config_fc_after_link_up) we will disable the 1449 * hw's ability to send PAUSE frames. 1450 */ 1451 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1452 break; 1453 case e1000_fc_tx_pause: 1454 /* 1455 * Tx Flow control is enabled, and Rx Flow control is 1456 * disabled, by a software over-ride. 1457 */ 1458 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1459 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1460 break; 1461 case e1000_fc_full: 1462 /* 1463 * Flow control (both Rx and Tx) is enabled by a software 1464 * over-ride. 1465 */ 1466 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1467 break; 1468 default: 1469 DEBUGOUT("Flow control param set incorrectly\n"); 1470 ret_val = -E1000_ERR_CONFIG; 1471 goto out; 1472 } 1473 1474 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1475 if (ret_val) 1476 goto out; 1477 1478 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1479 1480 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1481 ret_val = phy->ops.write_reg(hw, 1482 PHY_1000T_CTRL, 1483 mii_1000t_ctrl_reg); 1484 if (ret_val) 1485 goto out; 1486 } 1487 1488 out: 1489 return ret_val; 1490 } 1491 1492 /** 1493 * e1000_setup_copper_link_generic - Configure copper link settings 1494 * @hw: pointer to the HW structure 1495 * 1496 * Calls the appropriate function to configure the link for auto-neg or forced 1497 * speed and duplex. Then we check for link, once link is established calls 1498 * to configure collision distance and flow control are called. If link is 1499 * not established, we return -E1000_ERR_PHY (-2). 1500 **/ 1501 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1502 { 1503 s32 ret_val; 1504 bool link; 1505 1506 DEBUGFUNC("e1000_setup_copper_link_generic"); 1507 1508 if (hw->mac.autoneg) { 1509 /* 1510 * Setup autoneg and flow control advertisement and perform 1511 * autonegotiation. 1512 */ 1513 ret_val = e1000_copper_link_autoneg(hw); 1514 if (ret_val) 1515 goto out; 1516 } else { 1517 /* 1518 * PHY will be set to 10H, 10F, 100H or 100F 1519 * depending on user settings. 1520 */ 1521 DEBUGOUT("Forcing Speed and Duplex\n"); 1522 ret_val = hw->phy.ops.force_speed_duplex(hw); 1523 if (ret_val) { 1524 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1525 goto out; 1526 } 1527 } 1528 1529 /* 1530 * Check link status. Wait up to 100 microseconds for link to become 1531 * valid. 1532 */ 1533 ret_val = e1000_phy_has_link_generic(hw, 1534 COPPER_LINK_UP_LIMIT, 1535 10, 1536 &link); 1537 if (ret_val) 1538 goto out; 1539 1540 if (link) { 1541 DEBUGOUT("Valid link established!!!\n"); 1542 e1000_config_collision_dist_generic(hw); 1543 ret_val = e1000_config_fc_after_link_up_generic(hw); 1544 } else { 1545 DEBUGOUT("Unable to establish link!!!\n"); 1546 } 1547 1548 out: 1549 return ret_val; 1550 } 1551 1552 /** 1553 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1554 * @hw: pointer to the HW structure 1555 * 1556 * Calls the PHY setup function to force speed and duplex. Clears the 1557 * auto-crossover to force MDI manually. Waits for link and returns 1558 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1559 **/ 1560 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1561 { 1562 struct e1000_phy_info *phy = &hw->phy; 1563 s32 ret_val; 1564 u16 phy_data; 1565 bool link; 1566 1567 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1568 1569 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1570 if (ret_val) 1571 goto out; 1572 1573 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1574 1575 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1576 if (ret_val) 1577 goto out; 1578 1579 /* 1580 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1581 * forced whenever speed and duplex are forced. 1582 */ 1583 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1584 if (ret_val) 1585 goto out; 1586 1587 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1588 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1589 1590 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1591 if (ret_val) 1592 goto out; 1593 1594 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1595 1596 usec_delay(1); 1597 1598 if (phy->autoneg_wait_to_complete) { 1599 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1600 1601 ret_val = e1000_phy_has_link_generic(hw, 1602 PHY_FORCE_LIMIT, 1603 100000, 1604 &link); 1605 if (ret_val) 1606 goto out; 1607 1608 if (!link) 1609 DEBUGOUT("Link taking longer than expected.\n"); 1610 1611 /* Try once more */ 1612 ret_val = e1000_phy_has_link_generic(hw, 1613 PHY_FORCE_LIMIT, 1614 100000, 1615 &link); 1616 if (ret_val) 1617 goto out; 1618 } 1619 1620 out: 1621 return ret_val; 1622 } 1623 1624 /** 1625 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1626 * @hw: pointer to the HW structure 1627 * 1628 * Calls the PHY setup function to force speed and duplex. Clears the 1629 * auto-crossover to force MDI manually. Resets the PHY to commit the 1630 * changes. If time expires while waiting for link up, we reset the DSP. 1631 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1632 * successful completion, else return corresponding error code. 1633 **/ 1634 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1635 { 1636 struct e1000_phy_info *phy = &hw->phy; 1637 s32 ret_val; 1638 u16 phy_data; 1639 bool link; 1640 1641 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1642 1643 /* 1644 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1645 * forced whenever speed and duplex are forced. 1646 */ 1647 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1648 if (ret_val) 1649 goto out; 1650 1651 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1652 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1653 if (ret_val) 1654 goto out; 1655 1656 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1657 1658 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1659 if (ret_val) 1660 goto out; 1661 1662 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1663 1664 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1665 if (ret_val) 1666 goto out; 1667 1668 /* Reset the phy to commit changes. */ 1669 ret_val = hw->phy.ops.commit(hw); 1670 if (ret_val) 1671 goto out; 1672 1673 if (phy->autoneg_wait_to_complete) { 1674 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1675 1676 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1677 100000, &link); 1678 if (ret_val) 1679 goto out; 1680 1681 if (!link) { 1682 if (hw->phy.type != e1000_phy_m88 || 1683 hw->phy.id == I347AT4_E_PHY_ID || 1684 hw->phy.id == M88E1340M_E_PHY_ID || 1685 hw->phy.id == M88E1112_E_PHY_ID) { 1686 DEBUGOUT("Link taking longer than expected.\n"); 1687 } else { 1688 /* 1689 * We didn't get link. 1690 * Reset the DSP and cross our fingers. 1691 */ 1692 ret_val = phy->ops.write_reg(hw, 1693 M88E1000_PHY_PAGE_SELECT, 1694 0x001d); 1695 if (ret_val) 1696 goto out; 1697 ret_val = e1000_phy_reset_dsp_generic(hw); 1698 if (ret_val) 1699 goto out; 1700 } 1701 } 1702 1703 /* Try once more */ 1704 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1705 100000, &link); 1706 if (ret_val) 1707 goto out; 1708 } 1709 1710 if (hw->phy.type != e1000_phy_m88 || 1711 hw->phy.id == I347AT4_E_PHY_ID || 1712 hw->phy.id == M88E1340M_E_PHY_ID || 1713 hw->phy.id == M88E1112_E_PHY_ID) 1714 goto out; 1715 1716 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1717 if (ret_val) 1718 goto out; 1719 1720 /* 1721 * Resetting the phy means we need to re-force TX_CLK in the 1722 * Extended PHY Specific Control Register to 25MHz clock from 1723 * the reset value of 2.5MHz. 1724 */ 1725 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1726 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1727 if (ret_val) 1728 goto out; 1729 1730 /* 1731 * In addition, we must re-enable CRS on Tx for both half and full 1732 * duplex. 1733 */ 1734 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1735 if (ret_val) 1736 goto out; 1737 1738 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1739 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1740 1741 out: 1742 return ret_val; 1743 } 1744 1745 /** 1746 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1747 * @hw: pointer to the HW structure 1748 * 1749 * Forces the speed and duplex settings of the PHY. 1750 * This is a function pointer entry point only called by 1751 * PHY setup routines. 1752 **/ 1753 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1754 { 1755 struct e1000_phy_info *phy = &hw->phy; 1756 s32 ret_val; 1757 u16 data; 1758 bool link; 1759 1760 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1761 1762 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1763 if (ret_val) 1764 goto out; 1765 1766 e1000_phy_force_speed_duplex_setup(hw, &data); 1767 1768 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1769 if (ret_val) 1770 goto out; 1771 1772 /* Disable MDI-X support for 10/100 */ 1773 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1774 if (ret_val) 1775 goto out; 1776 1777 data &= ~IFE_PMC_AUTO_MDIX; 1778 data &= ~IFE_PMC_FORCE_MDIX; 1779 1780 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1781 if (ret_val) 1782 goto out; 1783 1784 DEBUGOUT1("IFE PMC: %X\n", data); 1785 1786 usec_delay(1); 1787 1788 if (phy->autoneg_wait_to_complete) { 1789 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1790 1791 ret_val = e1000_phy_has_link_generic(hw, 1792 PHY_FORCE_LIMIT, 1793 100000, 1794 &link); 1795 if (ret_val) 1796 goto out; 1797 1798 if (!link) 1799 DEBUGOUT("Link taking longer than expected.\n"); 1800 1801 /* Try once more */ 1802 ret_val = e1000_phy_has_link_generic(hw, 1803 PHY_FORCE_LIMIT, 1804 100000, 1805 &link); 1806 if (ret_val) 1807 goto out; 1808 } 1809 1810 out: 1811 return ret_val; 1812 } 1813 1814 /** 1815 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1816 * @hw: pointer to the HW structure 1817 * @phy_ctrl: pointer to current value of PHY_CONTROL 1818 * 1819 * Forces speed and duplex on the PHY by doing the following: disable flow 1820 * control, force speed/duplex on the MAC, disable auto speed detection, 1821 * disable auto-negotiation, configure duplex, configure speed, configure 1822 * the collision distance, write configuration to CTRL register. The 1823 * caller must write to the PHY_CONTROL register for these settings to 1824 * take affect. 1825 **/ 1826 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1827 { 1828 struct e1000_mac_info *mac = &hw->mac; 1829 u32 ctrl; 1830 1831 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1832 1833 /* Turn off flow control when forcing speed/duplex */ 1834 hw->fc.current_mode = e1000_fc_none; 1835 1836 /* Force speed/duplex on the mac */ 1837 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1838 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1839 ctrl &= ~E1000_CTRL_SPD_SEL; 1840 1841 /* Disable Auto Speed Detection */ 1842 ctrl &= ~E1000_CTRL_ASDE; 1843 1844 /* Disable autoneg on the phy */ 1845 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1846 1847 /* Forcing Full or Half Duplex? */ 1848 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1849 ctrl &= ~E1000_CTRL_FD; 1850 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1851 DEBUGOUT("Half Duplex\n"); 1852 } else { 1853 ctrl |= E1000_CTRL_FD; 1854 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1855 DEBUGOUT("Full Duplex\n"); 1856 } 1857 1858 /* Forcing 10mb or 100mb? */ 1859 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1860 ctrl |= E1000_CTRL_SPD_100; 1861 *phy_ctrl |= MII_CR_SPEED_100; 1862 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1863 DEBUGOUT("Forcing 100mb\n"); 1864 } else { 1865 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1866 *phy_ctrl |= MII_CR_SPEED_10; 1867 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1868 DEBUGOUT("Forcing 10mb\n"); 1869 } 1870 1871 e1000_config_collision_dist_generic(hw); 1872 1873 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1874 } 1875 1876 /** 1877 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1878 * @hw: pointer to the HW structure 1879 * @active: boolean used to enable/disable lplu 1880 * 1881 * Success returns 0, Failure returns 1 1882 * 1883 * The low power link up (lplu) state is set to the power management level D3 1884 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 1885 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1886 * is used during Dx states where the power conservation is most important. 1887 * During driver activity, SmartSpeed should be enabled so performance is 1888 * maintained. 1889 **/ 1890 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 1891 { 1892 struct e1000_phy_info *phy = &hw->phy; 1893 s32 ret_val = E1000_SUCCESS; 1894 u16 data; 1895 1896 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1897 1898 if (!(hw->phy.ops.read_reg)) 1899 goto out; 1900 1901 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1902 if (ret_val) 1903 goto out; 1904 1905 if (!active) { 1906 data &= ~IGP02E1000_PM_D3_LPLU; 1907 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1908 data); 1909 if (ret_val) 1910 goto out; 1911 /* 1912 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1913 * during Dx states where the power conservation is most 1914 * important. During driver activity we should enable 1915 * SmartSpeed, so performance is maintained. 1916 */ 1917 if (phy->smart_speed == e1000_smart_speed_on) { 1918 ret_val = phy->ops.read_reg(hw, 1919 IGP01E1000_PHY_PORT_CONFIG, 1920 &data); 1921 if (ret_val) 1922 goto out; 1923 1924 data |= IGP01E1000_PSCFR_SMART_SPEED; 1925 ret_val = phy->ops.write_reg(hw, 1926 IGP01E1000_PHY_PORT_CONFIG, 1927 data); 1928 if (ret_val) 1929 goto out; 1930 } else if (phy->smart_speed == e1000_smart_speed_off) { 1931 ret_val = phy->ops.read_reg(hw, 1932 IGP01E1000_PHY_PORT_CONFIG, 1933 &data); 1934 if (ret_val) 1935 goto out; 1936 1937 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1938 ret_val = phy->ops.write_reg(hw, 1939 IGP01E1000_PHY_PORT_CONFIG, 1940 data); 1941 if (ret_val) 1942 goto out; 1943 } 1944 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1945 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1946 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1947 data |= IGP02E1000_PM_D3_LPLU; 1948 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1949 data); 1950 if (ret_val) 1951 goto out; 1952 1953 /* When LPLU is enabled, we should disable SmartSpeed */ 1954 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1955 &data); 1956 if (ret_val) 1957 goto out; 1958 1959 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1960 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1961 data); 1962 } 1963 1964 out: 1965 return ret_val; 1966 } 1967 1968 /** 1969 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 1970 * @hw: pointer to the HW structure 1971 * 1972 * Success returns 0, Failure returns 1 1973 * 1974 * A downshift is detected by querying the PHY link health. 1975 **/ 1976 s32 e1000_check_downshift_generic(struct e1000_hw *hw) 1977 { 1978 struct e1000_phy_info *phy = &hw->phy; 1979 s32 ret_val; 1980 u16 phy_data, offset, mask; 1981 1982 DEBUGFUNC("e1000_check_downshift_generic"); 1983 1984 switch (phy->type) { 1985 case e1000_phy_m88: 1986 case e1000_phy_gg82563: 1987 case e1000_phy_bm: 1988 case e1000_phy_82578: 1989 offset = M88E1000_PHY_SPEC_STATUS; 1990 mask = M88E1000_PSSR_DOWNSHIFT; 1991 break; 1992 case e1000_phy_igp: 1993 case e1000_phy_igp_2: 1994 case e1000_phy_igp_3: 1995 offset = IGP01E1000_PHY_LINK_HEALTH; 1996 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1997 break; 1998 default: 1999 /* speed downshift not supported */ 2000 phy->speed_downgraded = FALSE; 2001 ret_val = E1000_SUCCESS; 2002 goto out; 2003 } 2004 2005 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2006 2007 if (!ret_val) 2008 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; 2009 2010 out: 2011 return ret_val; 2012 } 2013 2014 /** 2015 * e1000_check_polarity_m88 - Checks the polarity. 2016 * @hw: pointer to the HW structure 2017 * 2018 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2019 * 2020 * Polarity is determined based on the PHY specific status register. 2021 **/ 2022 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 2023 { 2024 struct e1000_phy_info *phy = &hw->phy; 2025 s32 ret_val; 2026 u16 data; 2027 2028 DEBUGFUNC("e1000_check_polarity_m88"); 2029 2030 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 2031 2032 if (!ret_val) 2033 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 2034 ? e1000_rev_polarity_reversed 2035 : e1000_rev_polarity_normal; 2036 2037 return ret_val; 2038 } 2039 2040 /** 2041 * e1000_check_polarity_igp - Checks the polarity. 2042 * @hw: pointer to the HW structure 2043 * 2044 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2045 * 2046 * Polarity is determined based on the PHY port status register, and the 2047 * current speed (since there is no polarity at 100Mbps). 2048 **/ 2049 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 2050 { 2051 struct e1000_phy_info *phy = &hw->phy; 2052 s32 ret_val; 2053 u16 data, offset, mask; 2054 2055 DEBUGFUNC("e1000_check_polarity_igp"); 2056 2057 /* 2058 * Polarity is determined based on the speed of 2059 * our connection. 2060 */ 2061 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2062 if (ret_val) 2063 goto out; 2064 2065 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2066 IGP01E1000_PSSR_SPEED_1000MBPS) { 2067 offset = IGP01E1000_PHY_PCS_INIT_REG; 2068 mask = IGP01E1000_PHY_POLARITY_MASK; 2069 } else { 2070 /* 2071 * This really only applies to 10Mbps since 2072 * there is no polarity for 100Mbps (always 0). 2073 */ 2074 offset = IGP01E1000_PHY_PORT_STATUS; 2075 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 2076 } 2077 2078 ret_val = phy->ops.read_reg(hw, offset, &data); 2079 2080 if (!ret_val) 2081 phy->cable_polarity = (data & mask) 2082 ? e1000_rev_polarity_reversed 2083 : e1000_rev_polarity_normal; 2084 2085 out: 2086 return ret_val; 2087 } 2088 2089 /** 2090 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 2091 * @hw: pointer to the HW structure 2092 * 2093 * Polarity is determined on the polarity reversal feature being enabled. 2094 **/ 2095 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 2096 { 2097 struct e1000_phy_info *phy = &hw->phy; 2098 s32 ret_val; 2099 u16 phy_data, offset, mask; 2100 2101 DEBUGFUNC("e1000_check_polarity_ife"); 2102 2103 /* 2104 * Polarity is determined based on the reversal feature being enabled. 2105 */ 2106 if (phy->polarity_correction) { 2107 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 2108 mask = IFE_PESC_POLARITY_REVERSED; 2109 } else { 2110 offset = IFE_PHY_SPECIAL_CONTROL; 2111 mask = IFE_PSC_FORCE_POLARITY; 2112 } 2113 2114 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2115 2116 if (!ret_val) 2117 phy->cable_polarity = (phy_data & mask) 2118 ? e1000_rev_polarity_reversed 2119 : e1000_rev_polarity_normal; 2120 2121 return ret_val; 2122 } 2123 2124 /** 2125 * e1000_wait_autoneg_generic - Wait for auto-neg completion 2126 * @hw: pointer to the HW structure 2127 * 2128 * Waits for auto-negotiation to complete or for the auto-negotiation time 2129 * limit to expire, which ever happens first. 2130 **/ 2131 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) 2132 { 2133 s32 ret_val = E1000_SUCCESS; 2134 u16 i, phy_status; 2135 2136 DEBUGFUNC("e1000_wait_autoneg_generic"); 2137 2138 if (!(hw->phy.ops.read_reg)) 2139 return E1000_SUCCESS; 2140 2141 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 2142 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 2143 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2144 if (ret_val) 2145 break; 2146 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2147 if (ret_val) 2148 break; 2149 if (phy_status & MII_SR_AUTONEG_COMPLETE) 2150 break; 2151 msec_delay(100); 2152 } 2153 2154 /* 2155 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2156 * has completed. 2157 */ 2158 return ret_val; 2159 } 2160 2161 /** 2162 * e1000_phy_has_link_generic - Polls PHY for link 2163 * @hw: pointer to the HW structure 2164 * @iterations: number of times to poll for link 2165 * @usec_interval: delay between polling attempts 2166 * @success: pointer to whether polling was successful or not 2167 * 2168 * Polls the PHY status register for link, 'iterations' number of times. 2169 **/ 2170 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2171 u32 usec_interval, bool *success) 2172 { 2173 s32 ret_val = E1000_SUCCESS; 2174 u16 i, phy_status; 2175 2176 DEBUGFUNC("e1000_phy_has_link_generic"); 2177 2178 if (!(hw->phy.ops.read_reg)) 2179 return E1000_SUCCESS; 2180 2181 for (i = 0; i < iterations; i++) { 2182 /* 2183 * Some PHYs require the PHY_STATUS register to be read 2184 * twice due to the link bit being sticky. No harm doing 2185 * it across the board. 2186 */ 2187 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2188 if (ret_val) 2189 /* 2190 * If the first read fails, another entity may have 2191 * ownership of the resources, wait and try again to 2192 * see if they have relinquished the resources yet. 2193 */ 2194 usec_delay(usec_interval); 2195 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2196 if (ret_val) 2197 break; 2198 if (phy_status & MII_SR_LINK_STATUS) 2199 break; 2200 if (usec_interval >= 1000) 2201 msec_delay_irq(usec_interval/1000); 2202 else 2203 usec_delay(usec_interval); 2204 } 2205 2206 *success = (i < iterations) ? TRUE : FALSE; 2207 2208 return ret_val; 2209 } 2210 2211 /** 2212 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2213 * @hw: pointer to the HW structure 2214 * 2215 * Reads the PHY specific status register to retrieve the cable length 2216 * information. The cable length is determined by averaging the minimum and 2217 * maximum values to get the "average" cable length. The m88 PHY has four 2218 * possible cable length values, which are: 2219 * Register Value Cable Length 2220 * 0 < 50 meters 2221 * 1 50 - 80 meters 2222 * 2 80 - 110 meters 2223 * 3 110 - 140 meters 2224 * 4 > 140 meters 2225 **/ 2226 s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2227 { 2228 struct e1000_phy_info *phy = &hw->phy; 2229 s32 ret_val; 2230 u16 phy_data, index; 2231 2232 DEBUGFUNC("e1000_get_cable_length_m88"); 2233 2234 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2235 if (ret_val) 2236 goto out; 2237 2238 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2239 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2240 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 2241 ret_val = -E1000_ERR_PHY; 2242 goto out; 2243 } 2244 2245 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2246 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2247 2248 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2249 2250 out: 2251 return ret_val; 2252 } 2253 2254 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) 2255 { 2256 struct e1000_phy_info *phy = &hw->phy; 2257 s32 ret_val; 2258 u16 phy_data, phy_data2, index, default_page, is_cm; 2259 2260 DEBUGFUNC("e1000_get_cable_length_m88_gen2"); 2261 2262 switch (hw->phy.id) { 2263 case M88E1340M_E_PHY_ID: 2264 case I347AT4_E_PHY_ID: 2265 /* Remember the original page select and set it to 7 */ 2266 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2267 &default_page); 2268 if (ret_val) 2269 goto out; 2270 2271 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 2272 if (ret_val) 2273 goto out; 2274 2275 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2276 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 2277 &phy_data); 2278 if (ret_val) 2279 goto out; 2280 2281 /* Check if the unit of cable length is meters or cm */ 2282 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 2283 if (ret_val) 2284 goto out; 2285 2286 is_cm = !(phy_data & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2287 2288 /* Populate the phy structure with cable length in meters */ 2289 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2290 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2291 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2292 2293 /* Reset the page selec to its original value */ 2294 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2295 default_page); 2296 if (ret_val) 2297 goto out; 2298 break; 2299 case M88E1112_E_PHY_ID: 2300 /* Remember the original page select and set it to 5 */ 2301 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2302 &default_page); 2303 if (ret_val) 2304 goto out; 2305 2306 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 2307 if (ret_val) 2308 goto out; 2309 2310 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 2311 &phy_data); 2312 if (ret_val) 2313 goto out; 2314 2315 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2316 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2317 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 2318 ret_val = -E1000_ERR_PHY; 2319 goto out; 2320 } 2321 2322 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2323 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2324 2325 phy->cable_length = (phy->min_cable_length + 2326 phy->max_cable_length) / 2; 2327 2328 /* Reset the page select to its original value */ 2329 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2330 default_page); 2331 if (ret_val) 2332 goto out; 2333 2334 break; 2335 default: 2336 ret_val = -E1000_ERR_PHY; 2337 goto out; 2338 } 2339 2340 out: 2341 return ret_val; 2342 } 2343 2344 /** 2345 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2346 * @hw: pointer to the HW structure 2347 * 2348 * The automatic gain control (agc) normalizes the amplitude of the 2349 * received signal, adjusting for the attenuation produced by the 2350 * cable. By reading the AGC registers, which represent the 2351 * combination of coarse and fine gain value, the value can be put 2352 * into a lookup table to obtain the approximate cable length 2353 * for each channel. 2354 **/ 2355 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2356 { 2357 struct e1000_phy_info *phy = &hw->phy; 2358 s32 ret_val = E1000_SUCCESS; 2359 u16 phy_data, i, agc_value = 0; 2360 u16 cur_agc_index, max_agc_index = 0; 2361 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2362 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 2363 IGP02E1000_PHY_AGC_A, 2364 IGP02E1000_PHY_AGC_B, 2365 IGP02E1000_PHY_AGC_C, 2366 IGP02E1000_PHY_AGC_D 2367 }; 2368 2369 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2370 2371 /* Read the AGC registers for all channels */ 2372 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2373 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2374 if (ret_val) 2375 goto out; 2376 2377 /* 2378 * Getting bits 15:9, which represent the combination of 2379 * coarse and fine gain values. The result is a number 2380 * that can be put into the lookup table to obtain the 2381 * approximate cable length. 2382 */ 2383 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2384 IGP02E1000_AGC_LENGTH_MASK; 2385 2386 /* Array index bound check. */ 2387 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2388 (cur_agc_index == 0)) { 2389 ret_val = -E1000_ERR_PHY; 2390 goto out; 2391 } 2392 2393 /* Remove min & max AGC values from calculation. */ 2394 if (e1000_igp_2_cable_length_table[min_agc_index] > 2395 e1000_igp_2_cable_length_table[cur_agc_index]) 2396 min_agc_index = cur_agc_index; 2397 if (e1000_igp_2_cable_length_table[max_agc_index] < 2398 e1000_igp_2_cable_length_table[cur_agc_index]) 2399 max_agc_index = cur_agc_index; 2400 2401 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2402 } 2403 2404 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2405 e1000_igp_2_cable_length_table[max_agc_index]); 2406 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2407 2408 /* Calculate cable length with the error range of +/- 10 meters. */ 2409 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2410 (agc_value - IGP02E1000_AGC_RANGE) : 0; 2411 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2412 2413 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2414 2415 out: 2416 return ret_val; 2417 } 2418 2419 /** 2420 * e1000_get_phy_info_m88 - Retrieve PHY information 2421 * @hw: pointer to the HW structure 2422 * 2423 * Valid for only copper links. Read the PHY status register (sticky read) 2424 * to verify that link is up. Read the PHY special control register to 2425 * determine the polarity and 10base-T extended distance. Read the PHY 2426 * special status register to determine MDI/MDIx and current speed. If 2427 * speed is 1000, then determine cable length, local and remote receiver. 2428 **/ 2429 s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2430 { 2431 struct e1000_phy_info *phy = &hw->phy; 2432 s32 ret_val; 2433 u16 phy_data; 2434 bool link; 2435 2436 DEBUGFUNC("e1000_get_phy_info_m88"); 2437 2438 if (phy->media_type != e1000_media_type_copper) { 2439 DEBUGOUT("Phy info is only valid for copper media\n"); 2440 ret_val = -E1000_ERR_CONFIG; 2441 goto out; 2442 } 2443 2444 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2445 if (ret_val) 2446 goto out; 2447 2448 if (!link) { 2449 DEBUGOUT("Phy info is only valid if link is up\n"); 2450 ret_val = -E1000_ERR_CONFIG; 2451 goto out; 2452 } 2453 2454 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2455 if (ret_val) 2456 goto out; 2457 2458 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 2459 ? TRUE : FALSE; 2460 2461 ret_val = e1000_check_polarity_m88(hw); 2462 if (ret_val) 2463 goto out; 2464 2465 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2466 if (ret_val) 2467 goto out; 2468 2469 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; 2470 2471 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2472 ret_val = hw->phy.ops.get_cable_length(hw); 2473 if (ret_val) 2474 goto out; 2475 2476 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2477 if (ret_val) 2478 goto out; 2479 2480 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2481 ? e1000_1000t_rx_status_ok 2482 : e1000_1000t_rx_status_not_ok; 2483 2484 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2485 ? e1000_1000t_rx_status_ok 2486 : e1000_1000t_rx_status_not_ok; 2487 } else { 2488 /* Set values to "undefined" */ 2489 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2490 phy->local_rx = e1000_1000t_rx_status_undefined; 2491 phy->remote_rx = e1000_1000t_rx_status_undefined; 2492 } 2493 2494 out: 2495 return ret_val; 2496 } 2497 2498 /** 2499 * e1000_get_phy_info_igp - Retrieve igp PHY information 2500 * @hw: pointer to the HW structure 2501 * 2502 * Read PHY status to determine if link is up. If link is up, then 2503 * set/determine 10base-T extended distance and polarity correction. Read 2504 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2505 * determine on the cable length, local and remote receiver. 2506 **/ 2507 s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2508 { 2509 struct e1000_phy_info *phy = &hw->phy; 2510 s32 ret_val; 2511 u16 data; 2512 bool link; 2513 2514 DEBUGFUNC("e1000_get_phy_info_igp"); 2515 2516 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2517 if (ret_val) 2518 goto out; 2519 2520 if (!link) { 2521 DEBUGOUT("Phy info is only valid if link is up\n"); 2522 ret_val = -E1000_ERR_CONFIG; 2523 goto out; 2524 } 2525 2526 phy->polarity_correction = TRUE; 2527 2528 ret_val = e1000_check_polarity_igp(hw); 2529 if (ret_val) 2530 goto out; 2531 2532 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2533 if (ret_val) 2534 goto out; 2535 2536 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; 2537 2538 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2539 IGP01E1000_PSSR_SPEED_1000MBPS) { 2540 ret_val = phy->ops.get_cable_length(hw); 2541 if (ret_val) 2542 goto out; 2543 2544 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2545 if (ret_val) 2546 goto out; 2547 2548 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2549 ? e1000_1000t_rx_status_ok 2550 : e1000_1000t_rx_status_not_ok; 2551 2552 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2553 ? e1000_1000t_rx_status_ok 2554 : e1000_1000t_rx_status_not_ok; 2555 } else { 2556 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2557 phy->local_rx = e1000_1000t_rx_status_undefined; 2558 phy->remote_rx = e1000_1000t_rx_status_undefined; 2559 } 2560 2561 out: 2562 return ret_val; 2563 } 2564 2565 /** 2566 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2567 * @hw: pointer to the HW structure 2568 * 2569 * Populates "phy" structure with various feature states. 2570 **/ 2571 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2572 { 2573 struct e1000_phy_info *phy = &hw->phy; 2574 s32 ret_val; 2575 u16 data; 2576 bool link; 2577 2578 DEBUGFUNC("e1000_get_phy_info_ife"); 2579 2580 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2581 if (ret_val) 2582 goto out; 2583 2584 if (!link) { 2585 DEBUGOUT("Phy info is only valid if link is up\n"); 2586 ret_val = -E1000_ERR_CONFIG; 2587 goto out; 2588 } 2589 2590 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2591 if (ret_val) 2592 goto out; 2593 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 2594 ? FALSE : TRUE; 2595 2596 if (phy->polarity_correction) { 2597 ret_val = e1000_check_polarity_ife(hw); 2598 if (ret_val) 2599 goto out; 2600 } else { 2601 /* Polarity is forced */ 2602 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 2603 ? e1000_rev_polarity_reversed 2604 : e1000_rev_polarity_normal; 2605 } 2606 2607 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2608 if (ret_val) 2609 goto out; 2610 2611 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 2612 2613 /* The following parameters are undefined for 10/100 operation. */ 2614 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2615 phy->local_rx = e1000_1000t_rx_status_undefined; 2616 phy->remote_rx = e1000_1000t_rx_status_undefined; 2617 2618 out: 2619 return ret_val; 2620 } 2621 2622 /** 2623 * e1000_phy_sw_reset_generic - PHY software reset 2624 * @hw: pointer to the HW structure 2625 * 2626 * Does a software reset of the PHY by reading the PHY control register and 2627 * setting/write the control register reset bit to the PHY. 2628 **/ 2629 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2630 { 2631 s32 ret_val = E1000_SUCCESS; 2632 u16 phy_ctrl; 2633 2634 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2635 2636 if (!(hw->phy.ops.read_reg)) 2637 goto out; 2638 2639 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2640 if (ret_val) 2641 goto out; 2642 2643 phy_ctrl |= MII_CR_RESET; 2644 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2645 if (ret_val) 2646 goto out; 2647 2648 usec_delay(1); 2649 2650 out: 2651 return ret_val; 2652 } 2653 2654 /** 2655 * e1000_phy_hw_reset_generic - PHY hardware reset 2656 * @hw: pointer to the HW structure 2657 * 2658 * Verify the reset block is not blocking us from resetting. Acquire 2659 * semaphore (if necessary) and read/set/write the device control reset 2660 * bit in the PHY. Wait the appropriate delay time for the device to 2661 * reset and release the semaphore (if necessary). 2662 **/ 2663 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2664 { 2665 struct e1000_phy_info *phy = &hw->phy; 2666 s32 ret_val = E1000_SUCCESS; 2667 u32 ctrl; 2668 2669 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2670 2671 ret_val = phy->ops.check_reset_block(hw); 2672 if (ret_val) { 2673 ret_val = E1000_SUCCESS; 2674 goto out; 2675 } 2676 2677 ret_val = phy->ops.acquire(hw); 2678 if (ret_val) 2679 goto out; 2680 2681 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2682 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2683 E1000_WRITE_FLUSH(hw); 2684 2685 usec_delay(phy->reset_delay_us); 2686 2687 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2688 E1000_WRITE_FLUSH(hw); 2689 2690 usec_delay(150); 2691 2692 phy->ops.release(hw); 2693 2694 ret_val = phy->ops.get_cfg_done(hw); 2695 2696 out: 2697 return ret_val; 2698 } 2699 2700 /** 2701 * e1000_get_cfg_done_generic - Generic configuration done 2702 * @hw: pointer to the HW structure 2703 * 2704 * Generic function to wait 10 milli-seconds for configuration to complete 2705 * and return success. 2706 **/ 2707 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw) 2708 { 2709 DEBUGFUNC("e1000_get_cfg_done_generic"); 2710 2711 msec_delay_irq(10); 2712 2713 return E1000_SUCCESS; 2714 } 2715 2716 /** 2717 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2718 * @hw: pointer to the HW structure 2719 * 2720 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2721 **/ 2722 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2723 { 2724 DEBUGOUT("Running IGP 3 PHY init script\n"); 2725 2726 /* PHY init IGP 3 */ 2727 /* Enable rise/fall, 10-mode work in class-A */ 2728 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2729 /* Remove all caps from Replica path filter */ 2730 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2731 /* Bias trimming for ADC, AFE and Driver (Default) */ 2732 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2733 /* Increase Hybrid poly bias */ 2734 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2735 /* Add 4% to Tx amplitude in Gig mode */ 2736 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2737 /* Disable trimming (TTT) */ 2738 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2739 /* Poly DC correction to 94.6% + 2% for all channels */ 2740 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2741 /* ABS DC correction to 95.9% */ 2742 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2743 /* BG temp curve trim */ 2744 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2745 /* Increasing ADC OPAMP stage 1 currents to max */ 2746 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2747 /* Force 1000 ( required for enabling PHY regs configuration) */ 2748 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2749 /* Set upd_freq to 6 */ 2750 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2751 /* Disable NPDFE */ 2752 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2753 /* Disable adaptive fixed FFE (Default) */ 2754 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2755 /* Enable FFE hysteresis */ 2756 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2757 /* Fixed FFE for short cable lengths */ 2758 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2759 /* Fixed FFE for medium cable lengths */ 2760 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2761 /* Fixed FFE for long cable lengths */ 2762 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2763 /* Enable Adaptive Clip Threshold */ 2764 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2765 /* AHT reset limit to 1 */ 2766 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2767 /* Set AHT master delay to 127 msec */ 2768 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2769 /* Set scan bits for AHT */ 2770 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2771 /* Set AHT Preset bits */ 2772 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2773 /* Change integ_factor of channel A to 3 */ 2774 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2775 /* Change prop_factor of channels BCD to 8 */ 2776 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2777 /* Change cg_icount + enable integbp for channels BCD */ 2778 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2779 /* 2780 * Change cg_icount + enable integbp + change prop_factor_master 2781 * to 8 for channel A 2782 */ 2783 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2784 /* Disable AHT in Slave mode on channel A */ 2785 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2786 /* 2787 * Enable LPLU and disable AN to 1000 in non-D0a states, 2788 * Enable SPD+B2B 2789 */ 2790 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2791 /* Enable restart AN on an1000_dis change */ 2792 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2793 /* Enable wh_fifo read clock in 10/100 modes */ 2794 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2795 /* Restart AN, Speed selection is 1000 */ 2796 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2797 2798 return E1000_SUCCESS; 2799 } 2800 2801 /** 2802 * e1000_get_phy_type_from_id - Get PHY type from id 2803 * @phy_id: phy_id read from the phy 2804 * 2805 * Returns the phy type from the id. 2806 **/ 2807 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2808 { 2809 enum e1000_phy_type phy_type = e1000_phy_unknown; 2810 2811 switch (phy_id) { 2812 case M88E1000_I_PHY_ID: 2813 case M88E1000_E_PHY_ID: 2814 case M88E1111_I_PHY_ID: 2815 case M88E1011_I_PHY_ID: 2816 case I347AT4_E_PHY_ID: 2817 case M88E1112_E_PHY_ID: 2818 case M88E1340M_E_PHY_ID: 2819 phy_type = e1000_phy_m88; 2820 break; 2821 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2822 phy_type = e1000_phy_igp_2; 2823 break; 2824 case GG82563_E_PHY_ID: 2825 phy_type = e1000_phy_gg82563; 2826 break; 2827 case IGP03E1000_E_PHY_ID: 2828 phy_type = e1000_phy_igp_3; 2829 break; 2830 case IFE_E_PHY_ID: 2831 case IFE_PLUS_E_PHY_ID: 2832 case IFE_C_E_PHY_ID: 2833 phy_type = e1000_phy_ife; 2834 break; 2835 case BME1000_E_PHY_ID: 2836 case BME1000_E_PHY_ID_R2: 2837 phy_type = e1000_phy_bm; 2838 break; 2839 case I82578_E_PHY_ID: 2840 phy_type = e1000_phy_82578; 2841 break; 2842 case I82577_E_PHY_ID: 2843 phy_type = e1000_phy_82577; 2844 break; 2845 case I82579_E_PHY_ID: 2846 phy_type = e1000_phy_82579; 2847 break; 2848 case I82580_I_PHY_ID: 2849 phy_type = e1000_phy_82580; 2850 break; 2851 default: 2852 phy_type = e1000_phy_unknown; 2853 break; 2854 } 2855 return phy_type; 2856 } 2857 2858 /** 2859 * e1000_determine_phy_address - Determines PHY address. 2860 * @hw: pointer to the HW structure 2861 * 2862 * This uses a trial and error method to loop through possible PHY 2863 * addresses. It tests each by reading the PHY ID registers and 2864 * checking for a match. 2865 **/ 2866 s32 e1000_determine_phy_address(struct e1000_hw *hw) 2867 { 2868 s32 ret_val = -E1000_ERR_PHY_TYPE; 2869 u32 phy_addr = 0; 2870 u32 i; 2871 enum e1000_phy_type phy_type = e1000_phy_unknown; 2872 2873 hw->phy.id = phy_type; 2874 2875 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2876 hw->phy.addr = phy_addr; 2877 i = 0; 2878 2879 do { 2880 e1000_get_phy_id(hw); 2881 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 2882 2883 /* 2884 * If phy_type is valid, break - we found our 2885 * PHY address 2886 */ 2887 if (phy_type != e1000_phy_unknown) { 2888 ret_val = E1000_SUCCESS; 2889 goto out; 2890 } 2891 msec_delay(1); 2892 i++; 2893 } while (i < 10); 2894 } 2895 2896 out: 2897 return ret_val; 2898 } 2899 2900 /** 2901 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2902 * @page: page to access 2903 * 2904 * Returns the phy address for the page requested. 2905 **/ 2906 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2907 { 2908 u32 phy_addr = 2; 2909 2910 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2911 phy_addr = 1; 2912 2913 return phy_addr; 2914 } 2915 2916 /** 2917 * e1000_write_phy_reg_bm - Write BM PHY register 2918 * @hw: pointer to the HW structure 2919 * @offset: register offset to write to 2920 * @data: data to write at register offset 2921 * 2922 * Acquires semaphore, if necessary, then writes the data to PHY register 2923 * at the offset. Release any acquired semaphores before exiting. 2924 **/ 2925 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2926 { 2927 s32 ret_val; 2928 u32 page = offset >> IGP_PAGE_SHIFT; 2929 2930 DEBUGFUNC("e1000_write_phy_reg_bm"); 2931 2932 ret_val = hw->phy.ops.acquire(hw); 2933 if (ret_val) 2934 return ret_val; 2935 2936 /* Page 800 works differently than the rest so it has its own func */ 2937 if (page == BM_WUC_PAGE) { 2938 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2939 FALSE, FALSE); 2940 goto out; 2941 } 2942 2943 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2944 2945 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2946 u32 page_shift, page_select; 2947 2948 /* 2949 * Page select is register 31 for phy address 1 and 22 for 2950 * phy address 2 and 3. Page select is shifted only for 2951 * phy address 1. 2952 */ 2953 if (hw->phy.addr == 1) { 2954 page_shift = IGP_PAGE_SHIFT; 2955 page_select = IGP01E1000_PHY_PAGE_SELECT; 2956 } else { 2957 page_shift = 0; 2958 page_select = BM_PHY_PAGE_SELECT; 2959 } 2960 2961 /* Page is shifted left, PHY expects (page x 32) */ 2962 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2963 (page << page_shift)); 2964 if (ret_val) 2965 goto out; 2966 } 2967 2968 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2969 data); 2970 2971 out: 2972 hw->phy.ops.release(hw); 2973 return ret_val; 2974 } 2975 2976 /** 2977 * e1000_read_phy_reg_bm - Read BM PHY register 2978 * @hw: pointer to the HW structure 2979 * @offset: register offset to be read 2980 * @data: pointer to the read data 2981 * 2982 * Acquires semaphore, if necessary, then reads the PHY register at offset 2983 * and storing the retrieved information in data. Release any acquired 2984 * semaphores before exiting. 2985 **/ 2986 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2987 { 2988 s32 ret_val; 2989 u32 page = offset >> IGP_PAGE_SHIFT; 2990 2991 DEBUGFUNC("e1000_read_phy_reg_bm"); 2992 2993 ret_val = hw->phy.ops.acquire(hw); 2994 if (ret_val) 2995 return ret_val; 2996 2997 /* Page 800 works differently than the rest so it has its own func */ 2998 if (page == BM_WUC_PAGE) { 2999 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3000 TRUE, FALSE); 3001 goto out; 3002 } 3003 3004 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3005 3006 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3007 u32 page_shift, page_select; 3008 3009 /* 3010 * Page select is register 31 for phy address 1 and 22 for 3011 * phy address 2 and 3. Page select is shifted only for 3012 * phy address 1. 3013 */ 3014 if (hw->phy.addr == 1) { 3015 page_shift = IGP_PAGE_SHIFT; 3016 page_select = IGP01E1000_PHY_PAGE_SELECT; 3017 } else { 3018 page_shift = 0; 3019 page_select = BM_PHY_PAGE_SELECT; 3020 } 3021 3022 /* Page is shifted left, PHY expects (page x 32) */ 3023 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3024 (page << page_shift)); 3025 if (ret_val) 3026 goto out; 3027 } 3028 3029 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3030 data); 3031 out: 3032 hw->phy.ops.release(hw); 3033 return ret_val; 3034 } 3035 3036 /** 3037 * e1000_read_phy_reg_bm2 - Read BM PHY register 3038 * @hw: pointer to the HW structure 3039 * @offset: register offset to be read 3040 * @data: pointer to the read data 3041 * 3042 * Acquires semaphore, if necessary, then reads the PHY register at offset 3043 * and storing the retrieved information in data. Release any acquired 3044 * semaphores before exiting. 3045 **/ 3046 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 3047 { 3048 s32 ret_val; 3049 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3050 3051 DEBUGFUNC("e1000_read_phy_reg_bm2"); 3052 3053 ret_val = hw->phy.ops.acquire(hw); 3054 if (ret_val) 3055 return ret_val; 3056 3057 /* Page 800 works differently than the rest so it has its own func */ 3058 if (page == BM_WUC_PAGE) { 3059 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3060 TRUE, FALSE); 3061 goto out; 3062 } 3063 3064 hw->phy.addr = 1; 3065 3066 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3067 3068 /* Page is shifted left, PHY expects (page x 32) */ 3069 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3070 page); 3071 3072 if (ret_val) 3073 goto out; 3074 } 3075 3076 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3077 data); 3078 out: 3079 hw->phy.ops.release(hw); 3080 return ret_val; 3081 } 3082 3083 /** 3084 * e1000_write_phy_reg_bm2 - Write BM PHY register 3085 * @hw: pointer to the HW structure 3086 * @offset: register offset to write to 3087 * @data: data to write at register offset 3088 * 3089 * Acquires semaphore, if necessary, then writes the data to PHY register 3090 * at the offset. Release any acquired semaphores before exiting. 3091 **/ 3092 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 3093 { 3094 s32 ret_val; 3095 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3096 3097 DEBUGFUNC("e1000_write_phy_reg_bm2"); 3098 3099 ret_val = hw->phy.ops.acquire(hw); 3100 if (ret_val) 3101 return ret_val; 3102 3103 /* Page 800 works differently than the rest so it has its own func */ 3104 if (page == BM_WUC_PAGE) { 3105 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3106 FALSE, FALSE); 3107 goto out; 3108 } 3109 3110 hw->phy.addr = 1; 3111 3112 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3113 /* Page is shifted left, PHY expects (page x 32) */ 3114 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3115 page); 3116 3117 if (ret_val) 3118 goto out; 3119 } 3120 3121 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3122 data); 3123 3124 out: 3125 hw->phy.ops.release(hw); 3126 return ret_val; 3127 } 3128 3129 /** 3130 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 3131 * @hw: pointer to the HW structure 3132 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 3133 * 3134 * Assumes semaphore already acquired and phy_reg points to a valid memory 3135 * address to store contents of the BM_WUC_ENABLE_REG register. 3136 **/ 3137 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3138 { 3139 s32 ret_val; 3140 u16 temp; 3141 3142 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm"); 3143 3144 if (!phy_reg) { 3145 ret_val = -E1000_ERR_PARAM; 3146 goto out; 3147 } 3148 3149 /* All page select, port ctrl and wakeup registers use phy address 1 */ 3150 hw->phy.addr = 1; 3151 3152 /* Select Port Control Registers page */ 3153 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3154 if (ret_val) { 3155 DEBUGOUT("Could not set Port Control page\n"); 3156 goto out; 3157 } 3158 3159 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3160 if (ret_val) { 3161 DEBUGOUT2("Could not read PHY register %d.%d\n", 3162 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3163 goto out; 3164 } 3165 3166 /* 3167 * Enable both PHY wakeup mode and Wakeup register page writes. 3168 * Prevent a power state change by disabling ME and Host PHY wakeup. 3169 */ 3170 temp = *phy_reg; 3171 temp |= BM_WUC_ENABLE_BIT; 3172 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 3173 3174 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 3175 if (ret_val) { 3176 DEBUGOUT2("Could not write PHY register %d.%d\n", 3177 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3178 goto out; 3179 } 3180 3181 /* Select Host Wakeup Registers page */ 3182 ret_val = e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 3183 3184 /* caller now able to write registers on the Wakeup registers page */ 3185 out: 3186 return ret_val; 3187 } 3188 3189 /** 3190 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 3191 * @hw: pointer to the HW structure 3192 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 3193 * 3194 * Restore BM_WUC_ENABLE_REG to its original value. 3195 * 3196 * Assumes semaphore already acquired and *phy_reg is the contents of the 3197 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 3198 * caller. 3199 **/ 3200 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3201 { 3202 s32 ret_val = E1000_SUCCESS; 3203 3204 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm"); 3205 3206 if (!phy_reg) 3207 return -E1000_ERR_PARAM; 3208 3209 /* Select Port Control Registers page */ 3210 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3211 if (ret_val) { 3212 DEBUGOUT("Could not set Port Control page\n"); 3213 goto out; 3214 } 3215 3216 /* Restore 769.17 to its original value */ 3217 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 3218 if (ret_val) 3219 DEBUGOUT2("Could not restore PHY register %d.%d\n", 3220 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3221 out: 3222 return ret_val; 3223 } 3224 3225 /** 3226 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 3227 * @hw: pointer to the HW structure 3228 * @offset: register offset to be read or written 3229 * @data: pointer to the data to read or write 3230 * @read: determines if operation is read or write 3231 * @page_set: BM_WUC_PAGE already set and access enabled 3232 * 3233 * Read the PHY register at offset and store the retrieved information in 3234 * data, or write data to PHY register at offset. Note the procedure to 3235 * access the PHY wakeup registers is different than reading the other PHY 3236 * registers. It works as such: 3237 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 3238 * 2) Set page to 800 for host (801 if we were manageability) 3239 * 3) Write the address using the address opcode (0x11) 3240 * 4) Read or write the data using the data opcode (0x12) 3241 * 5) Restore 769.17.2 to its original value 3242 * 3243 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 3244 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 3245 * 3246 * Assumes semaphore is already acquired. When page_set==TRUE, assumes 3247 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 3248 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 3249 **/ 3250 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 3251 u16 *data, bool read, bool page_set) 3252 { 3253 s32 ret_val; 3254 u16 reg = BM_PHY_REG_NUM(offset); 3255 u16 phy_reg = 0; 3256 3257 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 3258 3259 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 3260 if ((hw->mac.type == e1000_pchlan) && 3261 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 3262 DEBUGOUT1("Attempting to access page %d while gig enabled.\n", 3263 page); 3264 3265 if (!page_set) { 3266 /* Enable access to PHY wakeup registers */ 3267 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3268 if (ret_val) { 3269 DEBUGOUT("Could not enable PHY wakeup reg access\n"); 3270 goto out; 3271 } 3272 } 3273 3274 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg); 3275 3276 /* Write the Wakeup register page offset value using opcode 0x11 */ 3277 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 3278 if (ret_val) { 3279 DEBUGOUT1("Could not write address opcode to page %d\n", page); 3280 goto out; 3281 } 3282 3283 if (read) { 3284 /* Read the Wakeup register page value using opcode 0x12 */ 3285 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3286 data); 3287 } else { 3288 /* Write the Wakeup register page value using opcode 0x12 */ 3289 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3290 *data); 3291 } 3292 3293 if (ret_val) { 3294 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg); 3295 goto out; 3296 } 3297 3298 if (!page_set) 3299 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3300 3301 out: 3302 return ret_val; 3303 } 3304 3305 /** 3306 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 3307 * @hw: pointer to the HW structure 3308 * 3309 * In the case of a PHY power down to save power, or to turn off link during a 3310 * driver unload, or wake on lan is not enabled, restore the link to previous 3311 * settings. 3312 **/ 3313 void e1000_power_up_phy_copper(struct e1000_hw *hw) 3314 { 3315 u16 mii_reg = 0; 3316 3317 /* The PHY will retain its settings across a power down/up cycle */ 3318 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3319 mii_reg &= ~MII_CR_POWER_DOWN; 3320 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3321 } 3322 3323 /** 3324 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 3325 * @hw: pointer to the HW structure 3326 * 3327 * In the case of a PHY power down to save power, or to turn off link during a 3328 * driver unload, or wake on lan is not enabled, restore the link to previous 3329 * settings. 3330 **/ 3331 void e1000_power_down_phy_copper(struct e1000_hw *hw) 3332 { 3333 u16 mii_reg = 0; 3334 3335 /* The PHY will retain its settings across a power down/up cycle */ 3336 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3337 mii_reg |= MII_CR_POWER_DOWN; 3338 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3339 msec_delay(1); 3340 } 3341 3342 /** 3343 * __e1000_read_phy_reg_hv - Read HV PHY register 3344 * @hw: pointer to the HW structure 3345 * @offset: register offset to be read 3346 * @data: pointer to the read data 3347 * @locked: semaphore has already been acquired or not 3348 * 3349 * Acquires semaphore, if necessary, then reads the PHY register at offset 3350 * and stores the retrieved information in data. Release any acquired 3351 * semaphore before exiting. 3352 **/ 3353 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 3354 bool locked, bool page_set) 3355 { 3356 s32 ret_val; 3357 u16 page = BM_PHY_REG_PAGE(offset); 3358 u16 reg = BM_PHY_REG_NUM(offset); 3359 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3360 3361 DEBUGFUNC("__e1000_read_phy_reg_hv"); 3362 3363 if (!locked) { 3364 ret_val = hw->phy.ops.acquire(hw); 3365 if (ret_val) 3366 return ret_val; 3367 } 3368 3369 /* Page 800 works differently than the rest so it has its own func */ 3370 if (page == BM_WUC_PAGE) { 3371 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3372 TRUE, page_set); 3373 goto out; 3374 } 3375 3376 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3377 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3378 data, TRUE); 3379 goto out; 3380 } 3381 3382 if (!page_set) { 3383 if (page == HV_INTC_FC_PAGE_START) 3384 page = 0; 3385 3386 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3387 /* Page is shifted left, PHY expects (page x 32) */ 3388 ret_val = e1000_set_page_igp(hw, 3389 (page << IGP_PAGE_SHIFT)); 3390 3391 hw->phy.addr = phy_addr; 3392 3393 if (ret_val) 3394 goto out; 3395 } 3396 } 3397 3398 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3399 page << IGP_PAGE_SHIFT, reg); 3400 3401 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3402 data); 3403 out: 3404 if (!locked) 3405 hw->phy.ops.release(hw); 3406 3407 return ret_val; 3408 } 3409 3410 /** 3411 * e1000_read_phy_reg_hv - Read HV PHY register 3412 * @hw: pointer to the HW structure 3413 * @offset: register offset to be read 3414 * @data: pointer to the read data 3415 * 3416 * Acquires semaphore then reads the PHY register at offset and stores 3417 * the retrieved information in data. Release the acquired semaphore 3418 * before exiting. 3419 **/ 3420 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3421 { 3422 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE); 3423 } 3424 3425 /** 3426 * e1000_read_phy_reg_hv_locked - Read HV PHY register 3427 * @hw: pointer to the HW structure 3428 * @offset: register offset to be read 3429 * @data: pointer to the read data 3430 * 3431 * Reads the PHY register at offset and stores the retrieved information 3432 * in data. Assumes semaphore already acquired. 3433 **/ 3434 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3435 { 3436 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3437 } 3438 3439 /** 3440 * e1000_read_phy_reg_page_hv - Read HV PHY register 3441 * @hw: pointer to the HW structure 3442 * @offset: register offset to write to 3443 * @data: data to write at register offset 3444 * 3445 * Reads the PHY register at offset and stores the retrieved information 3446 * in data. Assumes semaphore already acquired and page already set. 3447 **/ 3448 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3449 { 3450 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, TRUE); 3451 } 3452 3453 /** 3454 * __e1000_write_phy_reg_hv - Write HV PHY register 3455 * @hw: pointer to the HW structure 3456 * @offset: register offset to write to 3457 * @data: data to write at register offset 3458 * @locked: semaphore has already been acquired or not 3459 * 3460 * Acquires semaphore, if necessary, then writes the data to PHY register 3461 * at the offset. Release any acquired semaphores before exiting. 3462 **/ 3463 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3464 bool locked, bool page_set) 3465 { 3466 s32 ret_val; 3467 u16 page = BM_PHY_REG_PAGE(offset); 3468 u16 reg = BM_PHY_REG_NUM(offset); 3469 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3470 3471 DEBUGFUNC("__e1000_write_phy_reg_hv"); 3472 3473 if (!locked) { 3474 ret_val = hw->phy.ops.acquire(hw); 3475 if (ret_val) 3476 return ret_val; 3477 } 3478 3479 /* Page 800 works differently than the rest so it has its own func */ 3480 if (page == BM_WUC_PAGE) { 3481 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3482 FALSE, page_set); 3483 goto out; 3484 } 3485 3486 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3487 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3488 &data, FALSE); 3489 goto out; 3490 } 3491 3492 if (!page_set) { 3493 if (page == HV_INTC_FC_PAGE_START) 3494 page = 0; 3495 3496 /* 3497 * Workaround MDIO accesses being disabled after entering IEEE 3498 * Power Down (when bit 11 of the PHY Control register is set) 3499 */ 3500 if ((hw->phy.type == e1000_phy_82578) && 3501 (hw->phy.revision >= 1) && 3502 (hw->phy.addr == 2) && 3503 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 3504 (data & (1 << 11))) { 3505 u16 data2 = 0x7EFF; 3506 ret_val = e1000_access_phy_debug_regs_hv(hw, 3507 (1 << 6) | 0x3, 3508 &data2, FALSE); 3509 if (ret_val) 3510 goto out; 3511 } 3512 3513 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3514 /* Page is shifted left, PHY expects (page x 32) */ 3515 ret_val = e1000_set_page_igp(hw, 3516 (page << IGP_PAGE_SHIFT)); 3517 3518 hw->phy.addr = phy_addr; 3519 3520 if (ret_val) 3521 goto out; 3522 } 3523 } 3524 3525 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3526 page << IGP_PAGE_SHIFT, reg); 3527 3528 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3529 data); 3530 3531 out: 3532 if (!locked) 3533 hw->phy.ops.release(hw); 3534 3535 return ret_val; 3536 } 3537 3538 /** 3539 * e1000_write_phy_reg_hv - Write HV PHY register 3540 * @hw: pointer to the HW structure 3541 * @offset: register offset to write to 3542 * @data: data to write at register offset 3543 * 3544 * Acquires semaphore then writes the data to PHY register at the offset. 3545 * Release the acquired semaphores before exiting. 3546 **/ 3547 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3548 { 3549 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE); 3550 } 3551 3552 /** 3553 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3554 * @hw: pointer to the HW structure 3555 * @offset: register offset to write to 3556 * @data: data to write at register offset 3557 * 3558 * Writes the data to PHY register at the offset. Assumes semaphore 3559 * already acquired. 3560 **/ 3561 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3562 { 3563 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3564 } 3565 3566 /** 3567 * e1000_write_phy_reg_page_hv - Write HV PHY register 3568 * @hw: pointer to the HW structure 3569 * @offset: register offset to write to 3570 * @data: data to write at register offset 3571 * 3572 * Writes the data to PHY register at the offset. Assumes semaphore 3573 * already acquired and page already set. 3574 **/ 3575 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 3576 { 3577 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, TRUE); 3578 } 3579 3580 /** 3581 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3582 * @page: page to be accessed 3583 **/ 3584 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3585 { 3586 u32 phy_addr = 2; 3587 3588 if (page >= HV_INTC_FC_PAGE_START) 3589 phy_addr = 1; 3590 3591 return phy_addr; 3592 } 3593 3594 /** 3595 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3596 * @hw: pointer to the HW structure 3597 * @offset: register offset to be read or written 3598 * @data: pointer to the data to be read or written 3599 * @read: determines if operation is read or write 3600 * 3601 * Reads the PHY register at offset and stores the retreived information 3602 * in data. Assumes semaphore already acquired. Note that the procedure 3603 * to access these regs uses the address port and data port to read/write. 3604 * These accesses done with PHY address 2 and without using pages. 3605 **/ 3606 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3607 u16 *data, bool read) 3608 { 3609 s32 ret_val; 3610 u32 addr_reg = 0; 3611 u32 data_reg = 0; 3612 3613 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3614 3615 /* This takes care of the difference with desktop vs mobile phy */ 3616 addr_reg = (hw->phy.type == e1000_phy_82578) ? 3617 I82578_ADDR_REG : I82577_ADDR_REG; 3618 data_reg = addr_reg + 1; 3619 3620 /* All operations in this function are phy address 2 */ 3621 hw->phy.addr = 2; 3622 3623 /* masking with 0x3F to remove the page from offset */ 3624 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3625 if (ret_val) { 3626 DEBUGOUT("Could not write the Address Offset port register\n"); 3627 goto out; 3628 } 3629 3630 /* Read or write the data value next */ 3631 if (read) 3632 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3633 else 3634 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3635 3636 if (ret_val) { 3637 DEBUGOUT("Could not access the Data port register\n"); 3638 goto out; 3639 } 3640 3641 out: 3642 return ret_val; 3643 } 3644 3645 /** 3646 * e1000_link_stall_workaround_hv - Si workaround 3647 * @hw: pointer to the HW structure 3648 * 3649 * This function works around a Si bug where the link partner can get 3650 * a link up indication before the PHY does. If small packets are sent 3651 * by the link partner they can be placed in the packet buffer without 3652 * being properly accounted for by the PHY and will stall preventing 3653 * further packets from being received. The workaround is to clear the 3654 * packet buffer after the PHY detects link up. 3655 **/ 3656 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3657 { 3658 s32 ret_val = E1000_SUCCESS; 3659 u16 data; 3660 3661 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3662 3663 if (hw->phy.type != e1000_phy_82578) 3664 goto out; 3665 3666 /* Do not apply workaround if in PHY loopback bit 14 set */ 3667 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3668 if (data & PHY_CONTROL_LB) 3669 goto out; 3670 3671 /* check if link is up and at 1Gbps */ 3672 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3673 if (ret_val) 3674 goto out; 3675 3676 data &= BM_CS_STATUS_LINK_UP | 3677 BM_CS_STATUS_RESOLVED | 3678 BM_CS_STATUS_SPEED_MASK; 3679 3680 if (data != (BM_CS_STATUS_LINK_UP | 3681 BM_CS_STATUS_RESOLVED | 3682 BM_CS_STATUS_SPEED_1000)) 3683 goto out; 3684 3685 msec_delay(200); 3686 3687 /* flush the packets in the fifo buffer */ 3688 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3689 HV_MUX_DATA_CTRL_GEN_TO_MAC | 3690 HV_MUX_DATA_CTRL_FORCE_SPEED); 3691 if (ret_val) 3692 goto out; 3693 3694 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3695 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3696 3697 out: 3698 return ret_val; 3699 } 3700 3701 /** 3702 * e1000_check_polarity_82577 - Checks the polarity. 3703 * @hw: pointer to the HW structure 3704 * 3705 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3706 * 3707 * Polarity is determined based on the PHY specific status register. 3708 **/ 3709 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3710 { 3711 struct e1000_phy_info *phy = &hw->phy; 3712 s32 ret_val; 3713 u16 data; 3714 3715 DEBUGFUNC("e1000_check_polarity_82577"); 3716 3717 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3718 3719 if (!ret_val) 3720 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3721 ? e1000_rev_polarity_reversed 3722 : e1000_rev_polarity_normal; 3723 3724 return ret_val; 3725 } 3726 3727 /** 3728 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3729 * @hw: pointer to the HW structure 3730 * 3731 * Calls the PHY setup function to force speed and duplex. 3732 **/ 3733 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3734 { 3735 struct e1000_phy_info *phy = &hw->phy; 3736 s32 ret_val; 3737 u16 phy_data; 3738 bool link; 3739 3740 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3741 3742 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3743 if (ret_val) 3744 goto out; 3745 3746 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3747 3748 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3749 if (ret_val) 3750 goto out; 3751 3752 usec_delay(1); 3753 3754 if (phy->autoneg_wait_to_complete) { 3755 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3756 3757 ret_val = e1000_phy_has_link_generic(hw, 3758 PHY_FORCE_LIMIT, 3759 100000, 3760 &link); 3761 if (ret_val) 3762 goto out; 3763 3764 if (!link) 3765 DEBUGOUT("Link taking longer than expected.\n"); 3766 3767 /* Try once more */ 3768 ret_val = e1000_phy_has_link_generic(hw, 3769 PHY_FORCE_LIMIT, 3770 100000, 3771 &link); 3772 if (ret_val) 3773 goto out; 3774 } 3775 3776 out: 3777 return ret_val; 3778 } 3779 3780 /** 3781 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3782 * @hw: pointer to the HW structure 3783 * 3784 * Read PHY status to determine if link is up. If link is up, then 3785 * set/determine 10base-T extended distance and polarity correction. Read 3786 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3787 * determine on the cable length, local and remote receiver. 3788 **/ 3789 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3790 { 3791 struct e1000_phy_info *phy = &hw->phy; 3792 s32 ret_val; 3793 u16 data; 3794 bool link; 3795 3796 DEBUGFUNC("e1000_get_phy_info_82577"); 3797 3798 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3799 if (ret_val) 3800 goto out; 3801 3802 if (!link) { 3803 DEBUGOUT("Phy info is only valid if link is up\n"); 3804 ret_val = -E1000_ERR_CONFIG; 3805 goto out; 3806 } 3807 3808 phy->polarity_correction = TRUE; 3809 3810 ret_val = e1000_check_polarity_82577(hw); 3811 if (ret_val) 3812 goto out; 3813 3814 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3815 if (ret_val) 3816 goto out; 3817 3818 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE; 3819 3820 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3821 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3822 ret_val = hw->phy.ops.get_cable_length(hw); 3823 if (ret_val) 3824 goto out; 3825 3826 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3827 if (ret_val) 3828 goto out; 3829 3830 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3831 ? e1000_1000t_rx_status_ok 3832 : e1000_1000t_rx_status_not_ok; 3833 3834 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3835 ? e1000_1000t_rx_status_ok 3836 : e1000_1000t_rx_status_not_ok; 3837 } else { 3838 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3839 phy->local_rx = e1000_1000t_rx_status_undefined; 3840 phy->remote_rx = e1000_1000t_rx_status_undefined; 3841 } 3842 3843 out: 3844 return ret_val; 3845 } 3846 3847 /** 3848 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3849 * @hw: pointer to the HW structure 3850 * 3851 * Reads the diagnostic status register and verifies result is valid before 3852 * placing it in the phy_cable_length field. 3853 **/ 3854 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 3855 { 3856 struct e1000_phy_info *phy = &hw->phy; 3857 s32 ret_val; 3858 u16 phy_data, length; 3859 3860 DEBUGFUNC("e1000_get_cable_length_82577"); 3861 3862 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3863 if (ret_val) 3864 goto out; 3865 3866 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 3867 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 3868 3869 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3870 ret_val = -E1000_ERR_PHY; 3871 3872 phy->cable_length = length; 3873 3874 out: 3875 return ret_val; 3876 } 3877