1 /* 2 * Copyright (c) 2004-2006 3 * Damien Bergamini <damien.bergamini@free.fr>. 4 * Copyright (c) 2004, 2005 5 * Andrew Atrens <atrens@nortelnetworks.com>. 6 * 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/iwi/if_iwireg.h,v 1.2.2.2 2006/01/29 13:54:19 damien Exp $ 32 * $DragonFly: src/sys/dev/netif/iwi/if_iwireg.h,v 1.3 2006/12/23 09:44:26 sephe Exp $ 33 */ 34 35 #define IWI_CMD_RING_COUNT 16 36 #define IWI_TX_RING_COUNT 64 37 #define IWI_RX_RING_COUNT 32 38 39 #define IWI_TX_DESC_SIZE (sizeof (struct iwi_tx_desc)) 40 #define IWI_CMD_DESC_SIZE (sizeof (struct iwi_cmd_desc)) 41 42 #define IWI_CSR_INTR 0x0008 43 #define IWI_CSR_INTR_MASK 0x000c 44 #define IWI_CSR_INDIRECT_ADDR 0x0010 45 #define IWI_CSR_INDIRECT_DATA 0x0014 46 #define IWI_CSR_AUTOINC_ADDR 0x0018 47 #define IWI_CSR_AUTOINC_DATA 0x001c 48 #define IWI_CSR_RST 0x0020 49 #define IWI_CSR_CTL 0x0024 50 #define IWI_CSR_IO 0x0030 51 #define IWI_CSR_CMD_BASE 0x0200 52 #define IWI_CSR_CMD_SIZE 0x0204 53 #define IWI_CSR_TX1_BASE 0x0208 54 #define IWI_CSR_TX1_SIZE 0x020c 55 #define IWI_CSR_TX2_BASE 0x0210 56 #define IWI_CSR_TX2_SIZE 0x0214 57 #define IWI_CSR_TX3_BASE 0x0218 58 #define IWI_CSR_TX3_SIZE 0x021c 59 #define IWI_CSR_TX4_BASE 0x0220 60 #define IWI_CSR_TX4_SIZE 0x0224 61 #define IWI_CSR_CMD_RIDX 0x0280 62 #define IWI_CSR_TX1_RIDX 0x0284 63 #define IWI_CSR_TX2_RIDX 0x0288 64 #define IWI_CSR_TX3_RIDX 0x028c 65 #define IWI_CSR_TX4_RIDX 0x0290 66 #define IWI_CSR_RX_RIDX 0x02a0 67 #define IWI_CSR_RX_BASE 0x0500 68 #define IWI_CSR_TABLE0_SIZE 0x0700 69 #define IWI_CSR_TABLE0_BASE 0x0704 70 #define IWI_CSR_NODE_BASE 0x0c0c 71 #define IWI_CSR_CMD_WIDX 0x0f80 72 #define IWI_CSR_TX1_WIDX 0x0f84 73 #define IWI_CSR_TX2_WIDX 0x0f88 74 #define IWI_CSR_TX3_WIDX 0x0f8c 75 #define IWI_CSR_TX4_WIDX 0x0f90 76 #define IWI_CSR_RX_WIDX 0x0fa0 77 #define IWI_CSR_READ_INT 0x0ff4 78 79 /* aliases */ 80 #define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE 81 82 /* flags for IWI_CSR_INTR */ 83 #define IWI_INTR_RX_DONE 0x00000002 84 #define IWI_INTR_CMD_DONE 0x00000800 85 #define IWI_INTR_TX1_DONE 0x00001000 86 #define IWI_INTR_TX2_DONE 0x00002000 87 #define IWI_INTR_TX3_DONE 0x00004000 88 #define IWI_INTR_TX4_DONE 0x00008000 89 #define IWI_INTR_FW_INITED 0x01000000 90 #define IWI_INTR_RADIO_OFF 0x04000000 91 #define IWI_INTR_FATAL_ERROR 0x40000000 92 #define IWI_INTR_PARITY_ERROR 0x80000000 93 94 #define IWI_INTR_MASK \ 95 (IWI_INTR_RX_DONE | IWI_INTR_CMD_DONE | IWI_INTR_TX1_DONE | \ 96 IWI_INTR_TX2_DONE | IWI_INTR_TX3_DONE | IWI_INTR_TX4_DONE | \ 97 IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF | \ 98 IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR) 99 100 /* flags for IWI_CSR_RST */ 101 #define IWI_RST_PRINCETON_RESET 0x00000001 102 #define IWI_RST_SOFT_RESET 0x00000080 103 #define IWI_RST_MASTER_DISABLED 0x00000100 104 #define IWI_RST_STOP_MASTER 0x00000200 105 106 /* flags for IWI_CSR_CTL */ 107 #define IWI_CTL_CLOCK_READY 0x00000001 108 #define IWI_CTL_ALLOW_STANDBY 0x00000002 109 #define IWI_CTL_INIT 0x00000004 110 111 /* flags for IWI_CSR_IO */ 112 #define IWI_IO_RADIO_ENABLED 0x00010000 113 114 /* flags for IWI_CSR_READ_INT */ 115 #define IWI_READ_INT_INIT_HOST 0x20000000 116 117 /* constants for command blocks */ 118 #define IWI_CB_DEFAULT_CTL 0x8cea0000 119 #define IWI_CB_MAXDATALEN 8191 120 121 /* supported rates */ 122 #define IWI_RATE_DS1 10 123 #define IWI_RATE_DS2 20 124 #define IWI_RATE_DS5 55 125 #define IWI_RATE_DS11 110 126 #define IWI_RATE_OFDM6 13 127 #define IWI_RATE_OFDM9 15 128 #define IWI_RATE_OFDM12 5 129 #define IWI_RATE_OFDM18 7 130 #define IWI_RATE_OFDM24 9 131 #define IWI_RATE_OFDM36 11 132 #define IWI_RATE_OFDM48 1 133 #define IWI_RATE_OFDM54 3 134 135 /* 136 * New version firmware images contain boot, ucode and firmware 137 * all in one chunk. The header at the beginning gives the version 138 * and the size of each (sub)image, in le32 format. 139 */ 140 struct iwi_firmware_hdr { 141 uint16_t reserved; 142 uint8_t vermaj; /* major version */ 143 uint8_t vermin; /* minor version */ 144 uint32_t bsize; /* size of boot image */ 145 uint32_t usize; /* size of ucode image */ 146 uint32_t fsize; /* size of firmware image */ 147 } __packed; 148 149 struct iwi_hdr { 150 uint8_t type; 151 #define IWI_HDR_TYPE_DATA 0 152 #define IWI_HDR_TYPE_COMMAND 1 153 #define IWI_HDR_TYPE_NOTIF 3 154 #define IWI_HDR_TYPE_FRAME 9 155 156 uint8_t seq; 157 uint8_t flags; 158 #define IWI_HDR_FLAG_IRQ 0x04 159 160 uint8_t reserved; 161 } __packed; 162 163 struct iwi_notif { 164 uint32_t reserved[2]; 165 uint8_t type; 166 #define IWI_NOTIF_TYPE_ASSOCIATION 10 167 #define IWI_NOTIF_TYPE_AUTHENTICATION 11 168 #define IWI_NOTIF_TYPE_SCAN_CHANNEL 12 169 #define IWI_NOTIF_TYPE_SCAN_COMPLETE 13 170 #define IWI_NOTIF_TYPE_BEACON 17 171 #define IWI_NOTIF_TYPE_CALIBRATION 20 172 #define IWI_NOTIF_TYPE_NOISE 25 173 174 uint8_t flags; 175 uint16_t len; 176 } __packed; 177 178 /* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */ 179 struct iwi_notif_authentication { 180 uint8_t state; 181 #define IWI_DEAUTHENTICATED 0 182 #define IWI_AUTHENTICATED 9 183 } __packed; 184 185 /* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */ 186 struct iwi_notif_association { 187 uint8_t state; 188 #define IWI_DEASSOCIATED 0 189 #define IWI_ASSOCIATED 12 190 191 struct ieee80211_frame frame; 192 uint16_t capinfo; 193 uint16_t status; 194 uint16_t associd; 195 } __packed; 196 197 /* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */ 198 struct iwi_notif_scan_channel { 199 uint8_t nchan; 200 uint8_t reserved[47]; 201 } __packed; 202 203 /* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */ 204 struct iwi_notif_scan_complete { 205 uint8_t type; 206 uint8_t nchan; 207 uint8_t status; 208 uint8_t reserved; 209 } __packed; 210 211 /* received frame header */ 212 struct iwi_frame { 213 uint32_t reserved1[2]; 214 uint8_t chan; 215 uint8_t status; 216 uint8_t rate; 217 uint8_t rssi; 218 uint8_t agc; 219 uint8_t rssi_dbm; 220 uint16_t signal; 221 uint16_t noise; 222 uint8_t antenna; 223 uint8_t control; 224 uint8_t reserved2[2]; 225 uint16_t len; 226 } __packed; 227 228 /* header for transmission */ 229 struct iwi_tx_desc { 230 struct iwi_hdr hdr; 231 uint32_t reserved1; 232 uint8_t station; 233 uint8_t reserved2[3]; 234 uint8_t cmd; 235 #define IWI_DATA_CMD_TX 0x0b 236 237 uint8_t seq; 238 uint16_t len; 239 uint8_t priority; 240 uint8_t flags; 241 #define IWI_DATA_FLAG_SHPREAMBLE 0x04 242 #define IWI_DATA_FLAG_NO_WEP 0x20 243 #define IWI_DATA_FLAG_NEED_ACK 0x80 244 245 uint8_t xflags; 246 #define IWI_DATA_XFLAG_QOS 0x10 247 248 uint8_t weptxkey; 249 uint8_t wepkey[IEEE80211_KEYBUF_SIZE]; 250 uint8_t rate; 251 uint8_t antenna; 252 uint8_t reserved3[10]; 253 struct ieee80211_qosframe_addr4 wh; 254 uint32_t iv; 255 uint32_t eiv; 256 uint32_t nseg; 257 #define IWI_MAX_NSEG 6 258 259 uint32_t seg_addr[IWI_MAX_NSEG]; 260 uint16_t seg_len[IWI_MAX_NSEG]; 261 } __packed; 262 263 /* command */ 264 struct iwi_cmd_desc { 265 struct iwi_hdr hdr; 266 uint8_t type; 267 #define IWI_CMD_ENABLE 2 268 #define IWI_CMD_SET_CONFIG 6 269 #define IWI_CMD_SET_ESSID 8 270 #define IWI_CMD_SET_MAC_ADDRESS 11 271 #define IWI_CMD_SET_RTS_THRESHOLD 15 272 #define IWI_CMD_SET_FRAG_THRESHOLD 16 273 #define IWI_CMD_SET_POWER_MODE 17 274 #define IWI_CMD_SET_WEP_KEY 18 275 #define IWI_CMD_ASSOCIATE 21 276 #define IWI_CMD_SET_RATES 22 277 #define IWI_CMD_ABORT_SCAN 23 278 #define IWI_CMD_SET_WME_PARAMS 25 279 #define IWI_CMD_SCAN 26 280 #define IWI_CMD_SET_OPTIE 31 281 #define IWI_CMD_DISABLE 33 282 #define IWI_CMD_SET_IV 34 283 #define IWI_CMD_SET_TX_POWER 35 284 #define IWI_CMD_SET_SENSITIVITY 42 285 #define IWI_CMD_SET_WMEIE 84 286 287 uint8_t len; 288 uint16_t reserved; 289 uint8_t data[120]; 290 } __packed; 291 292 /* node information (IBSS) */ 293 struct iwi_ibssnode { 294 uint8_t bssid[IEEE80211_ADDR_LEN]; 295 uint8_t reserved[2]; 296 } __packed; 297 298 /* constants for 'mode' fields */ 299 #define IWI_MODE_11A 0 300 #define IWI_MODE_11B 1 301 #define IWI_MODE_11G 2 302 303 /* possible values for command IWI_CMD_SET_POWER_MODE */ 304 #define IWI_POWER_MODE_CAM 0 305 306 /* structure for command IWI_CMD_SET_RATES */ 307 struct iwi_rateset { 308 uint8_t mode; 309 uint8_t nrates; 310 uint8_t type; 311 #define IWI_RATESET_TYPE_NEGOTIATED 0 312 #define IWI_RATESET_TYPE_SUPPORTED 1 313 314 uint8_t reserved; 315 316 #define IWI_RATESET_MAXSIZE 12 317 uint8_t rates[IWI_RATESET_MAXSIZE]; 318 } __packed; 319 320 /* structure for command IWI_CMD_SET_TX_POWER */ 321 struct iwi_txpower { 322 uint8_t nchan; 323 uint8_t mode; 324 struct { 325 uint8_t chan; 326 uint8_t power; 327 #define IWI_TXPOWER_MAX 20 328 #define IWI_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX) 329 } __packed chan[37]; 330 } __packed; 331 332 /* structure for command IWI_CMD_ASSOCIATE */ 333 struct iwi_associate { 334 uint8_t chan; 335 uint8_t auth; 336 #define IWI_AUTH_OPEN 0 337 #define IWI_AUTH_SHARED 1 338 #define IWI_AUTH_NONE 3 339 340 uint8_t type; 341 uint8_t reserved1; 342 uint16_t policy; 343 #define IWI_POLICY_WME 1 344 #define IWI_POLICY_WPA 2 345 346 uint8_t plen; 347 uint8_t mode; 348 uint8_t bssid[IEEE80211_ADDR_LEN]; 349 uint8_t tstamp[8]; 350 uint16_t capinfo; 351 uint16_t lintval; 352 uint16_t intval; 353 uint8_t dst[IEEE80211_ADDR_LEN]; 354 uint32_t reserved3; 355 uint16_t reserved4; 356 } __packed; 357 358 /* structure for command IWI_CMD_SCAN */ 359 struct iwi_scan { 360 uint32_t index; 361 uint8_t channels[54]; 362 #define IWI_CHAN_5GHZ (0 << 6) 363 #define IWI_CHAN_2GHZ (1 << 6) 364 365 uint8_t type[27]; 366 #define IWI_SCAN_TYPE_PASSIVE 0x11 367 #define IWI_SCAN_TYPE_DIRECTED 0x22 368 #define IWI_SCAN_TYPE_BROADCAST 0x33 369 #define IWI_SCAN_TYPE_BDIRECTED 0x44 370 371 uint8_t reserved1; 372 uint16_t reserved2; 373 uint16_t passive; /* dwell time */ 374 uint16_t directed; /* dwell time */ 375 uint16_t broadcast; /* dwell time */ 376 uint16_t bdirected; /* dwell time */ 377 } __packed; 378 379 /* structure for command IWI_CMD_SET_CONFIG */ 380 struct iwi_configuration { 381 uint8_t bluetooth_coexistence; 382 uint8_t reserved1; 383 uint8_t answer_pbreq; 384 uint8_t allow_invalid_frames; 385 uint8_t multicast_enabled; 386 uint8_t drop_unicast_unencrypted; 387 uint8_t disable_unicast_decryption; 388 uint8_t drop_multicast_unencrypted; 389 uint8_t disable_multicast_decryption; 390 uint8_t antenna; 391 uint8_t reserved2; 392 uint8_t use_protection; 393 uint8_t protection_ctsonly; 394 uint8_t enable_multicast_filtering; 395 uint8_t bluetooth_threshold; 396 uint8_t reserved4; 397 uint8_t allow_beacon_and_probe_resp; 398 uint8_t allow_mgt; 399 uint8_t noise_reported; 400 uint8_t reserved5; 401 } __packed; 402 403 /* structure for command IWI_CMD_SET_WEP_KEY */ 404 struct iwi_wep_key { 405 uint8_t cmd; 406 #define IWI_WEP_KEY_CMD_SETKEY 0x08 407 408 uint8_t seq; 409 uint8_t idx; 410 uint8_t len; 411 uint8_t key[IEEE80211_KEYBUF_SIZE]; 412 } __packed; 413 414 /* structure for command IWI_CMD_SET_WME_PARAMS */ 415 struct iwi_wme_params { 416 uint16_t cwmin[WME_NUM_AC]; 417 uint16_t cwmax[WME_NUM_AC]; 418 uint8_t aifsn[WME_NUM_AC]; 419 uint8_t acm[WME_NUM_AC]; 420 uint16_t burst[WME_NUM_AC]; 421 } __packed; 422 423 #define IWI_MEM_EVENT_CTL 0x00300004 424 #define IWI_MEM_EEPROM_CTL 0x00300040 425 426 /* possible flags for register IWI_MEM_EVENT */ 427 #define IWI_LED_ASSOC (1 << 5) 428 #define IWI_LED_MASK 0xd9fffffb 429 430 #define IWI_EEPROM_MAC 0x21 431 432 #define IWI_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 433 434 #define IWI_EEPROM_C (1 << 0) /* Serial Clock */ 435 #define IWI_EEPROM_S (1 << 1) /* Chip Select */ 436 #define IWI_EEPROM_D (1 << 2) /* Serial data input */ 437 #define IWI_EEPROM_Q (1 << 4) /* Serial data output */ 438 439 #define IWI_EEPROM_SHIFT_D 2 440 #define IWI_EEPROM_SHIFT_Q 4 441 442 /* 443 * control and status registers access macros 444 */ 445 #define CSR_READ_1(sc, reg) \ 446 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 447 448 #define CSR_READ_2(sc, reg) \ 449 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 450 451 #define CSR_READ_4(sc, reg) \ 452 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 453 454 #define CSR_READ_REGION_4(sc, offset, datap, count) \ 455 bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 456 (datap), (count)) 457 458 #define CSR_WRITE_1(sc, reg, val) \ 459 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 460 461 #define CSR_WRITE_2(sc, reg, val) \ 462 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 463 464 #define CSR_WRITE_4(sc, reg, val) \ 465 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 466 467 #define CSR_WRITE_REGION_1(sc, offset, datap, count) \ 468 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 469 (datap), (count)) 470 471 /* 472 * indirect memory space access macros 473 */ 474 #define MEM_READ_1(sc, addr) \ 475 (CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)), \ 476 CSR_READ_1((sc), IWI_CSR_INDIRECT_DATA)) 477 478 #define MEM_READ_4(sc, addr) \ 479 (CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)), \ 480 CSR_READ_4((sc), IWI_CSR_INDIRECT_DATA)) 481 482 #define MEM_WRITE_1(sc, addr, val) do { \ 483 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 484 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 485 } while (/* CONSTCOND */0) 486 487 #define MEM_WRITE_2(sc, addr, val) do { \ 488 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 489 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 490 } while (/* CONSTCOND */0) 491 492 #define MEM_WRITE_4(sc, addr, val) do { \ 493 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 494 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 495 } while (/* CONSTCOND */0) 496 497 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 498 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 499 CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len)); \ 500 } while (/* CONSTCOND */0) 501 502 /* 503 * EEPROM access macro 504 */ 505 #define IWI_EEPROM_CTL(sc, val) do { \ 506 MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \ 507 DELAY(IWI_EEPROM_DELAY); \ 508 } while (/* CONSTCOND */0) 509