1 /*- 2 * Copyright (c) 2007-2009 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * Copyright (c) 2008 5 * Benjamin Close <benjsc@FreeBSD.org> 6 * Copyright (c) 2008 Sam Leffler, Errno Consulting 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 23 * adapters. 24 */ 25 26 /* $FreeBSD$ */ 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/sysctl.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/bus.h> 37 #include <sys/rman.h> 38 #include <sys/endian.h> 39 #include <sys/firmware.h> 40 #include <sys/limits.h> 41 #include <sys/module.h> 42 #include <sys/queue.h> 43 #include <sys/taskqueue.h> 44 #include <sys/libkern.h> 45 46 #include <sys/bus.h> 47 #include <sys/resource.h> 48 #include <machine/clock.h> 49 50 #include <bus/pci/pcireg.h> 51 #include <bus/pci/pcivar.h> 52 53 #include <net/bpf.h> 54 #include <net/if.h> 55 #include <net/if_arp.h> 56 #include <net/ifq_var.h> 57 #include <net/ethernet.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_types.h> 61 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/in_var.h> 65 #include <netinet/if_ether.h> 66 #include <netinet/ip.h> 67 68 #include <netproto/802_11/ieee80211_var.h> 69 #include <netproto/802_11/ieee80211_radiotap.h> 70 #include <netproto/802_11/ieee80211_regdomain.h> 71 #include <netproto/802_11/ieee80211_ratectl.h> 72 73 #include "if_iwnreg.h" 74 #include "if_iwnvar.h" 75 76 static int iwn_pci_probe(device_t); 77 static int iwn_pci_attach(device_t); 78 static const struct iwn_hal *iwn_hal_attach(struct iwn_softc *); 79 static void iwn_radiotap_attach(struct iwn_softc *); 80 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 81 const char name[IFNAMSIZ], int unit, int opmode, 82 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 83 const uint8_t mac[IEEE80211_ADDR_LEN]); 84 static void iwn_vap_delete(struct ieee80211vap *); 85 static int iwn_cleanup(device_t); 86 static int iwn_pci_detach(device_t); 87 static int iwn_nic_lock(struct iwn_softc *); 88 static int iwn_eeprom_lock(struct iwn_softc *); 89 static int iwn_init_otprom(struct iwn_softc *); 90 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 91 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 92 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 93 void **, bus_size_t, bus_size_t, int); 94 static void iwn_dma_contig_free(struct iwn_dma_info *); 95 static int iwn_alloc_sched(struct iwn_softc *); 96 static void iwn_free_sched(struct iwn_softc *); 97 static int iwn_alloc_kw(struct iwn_softc *); 98 static void iwn_free_kw(struct iwn_softc *); 99 static int iwn_alloc_ict(struct iwn_softc *); 100 static void iwn_free_ict(struct iwn_softc *); 101 static int iwn_alloc_fwmem(struct iwn_softc *); 102 static void iwn_free_fwmem(struct iwn_softc *); 103 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 104 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 105 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 106 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 107 int); 108 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 109 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 110 static void iwn5000_ict_reset(struct iwn_softc *); 111 static int iwn_read_eeprom(struct iwn_softc *, 112 uint8_t macaddr[IEEE80211_ADDR_LEN]); 113 static void iwn4965_read_eeprom(struct iwn_softc *); 114 static void iwn4965_print_power_group(struct iwn_softc *, int); 115 static void iwn5000_read_eeprom(struct iwn_softc *); 116 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 117 static void iwn_read_eeprom_band(struct iwn_softc *, int); 118 #if 0 /* HT */ 119 static void iwn_read_eeprom_ht40(struct iwn_softc *, int); 120 #endif 121 static void iwn_read_eeprom_channels(struct iwn_softc *, int, 122 uint32_t); 123 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 124 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 125 const uint8_t mac[IEEE80211_ADDR_LEN]); 126 static void iwn_newassoc(struct ieee80211_node *, int); 127 static int iwn_media_change(struct ifnet *); 128 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 129 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 130 struct iwn_rx_data *); 131 static void iwn_timer_callout(void *); 132 static void iwn_calib_reset(struct iwn_softc *); 133 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 134 struct iwn_rx_data *); 135 #if 0 /* HT */ 136 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 137 struct iwn_rx_data *); 138 #endif 139 static void iwn5000_rx_calib_results(struct iwn_softc *, 140 struct iwn_rx_desc *, struct iwn_rx_data *); 141 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 142 struct iwn_rx_data *); 143 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 144 struct iwn_rx_data *); 145 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 146 struct iwn_rx_data *); 147 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 148 uint8_t); 149 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 150 static void iwn_notif_intr(struct iwn_softc *); 151 static void iwn_wakeup_intr(struct iwn_softc *); 152 static void iwn_rftoggle_intr(struct iwn_softc *); 153 static void iwn_fatal_intr(struct iwn_softc *); 154 static void iwn_intr(void *); 155 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 156 uint16_t); 157 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 158 uint16_t); 159 #ifdef notyet 160 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 161 #endif 162 static uint8_t iwn_plcp_signal(int); 163 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 164 struct ieee80211_node *, struct iwn_tx_ring *); 165 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 166 const struct ieee80211_bpf_params *); 167 static void iwn_start(struct ifnet *); 168 static void iwn_start_locked(struct ifnet *); 169 static void iwn_watchdog(struct iwn_softc *sc); 170 static int iwn_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 171 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 172 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 173 int); 174 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 175 int); 176 static int iwn_set_link_quality(struct iwn_softc *, uint8_t, int); 177 static int iwn_add_broadcast_node(struct iwn_softc *, int); 178 static int iwn_wme_update(struct ieee80211com *); 179 static void iwn_update_mcast(struct ifnet *); 180 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 181 static int iwn_set_critical_temp(struct iwn_softc *); 182 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 183 static void iwn4965_power_calibration(struct iwn_softc *, int); 184 static int iwn4965_set_txpower(struct iwn_softc *, 185 struct ieee80211_channel *, int); 186 static int iwn5000_set_txpower(struct iwn_softc *, 187 struct ieee80211_channel *, int); 188 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 189 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 190 static int iwn_get_noise(const struct iwn_rx_general_stats *); 191 static int iwn4965_get_temperature(struct iwn_softc *); 192 static int iwn5000_get_temperature(struct iwn_softc *); 193 static int iwn_init_sensitivity(struct iwn_softc *); 194 static void iwn_collect_noise(struct iwn_softc *, 195 const struct iwn_rx_general_stats *); 196 static int iwn4965_init_gains(struct iwn_softc *); 197 static int iwn5000_init_gains(struct iwn_softc *); 198 static int iwn4965_set_gains(struct iwn_softc *); 199 static int iwn5000_set_gains(struct iwn_softc *); 200 static void iwn_tune_sensitivity(struct iwn_softc *, 201 const struct iwn_rx_stats *); 202 static int iwn_send_sensitivity(struct iwn_softc *); 203 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 204 static int iwn_config(struct iwn_softc *); 205 static int iwn_scan(struct iwn_softc *); 206 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 207 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 208 #if 0 /* HT */ 209 static int iwn_ampdu_rx_start(struct ieee80211com *, 210 struct ieee80211_node *, uint8_t); 211 static void iwn_ampdu_rx_stop(struct ieee80211com *, 212 struct ieee80211_node *, uint8_t); 213 static int iwn_ampdu_tx_start(struct ieee80211com *, 214 struct ieee80211_node *, uint8_t); 215 static void iwn_ampdu_tx_stop(struct ieee80211com *, 216 struct ieee80211_node *, uint8_t); 217 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 218 struct ieee80211_node *, uint8_t, uint16_t); 219 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, uint8_t, uint16_t); 220 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 221 struct ieee80211_node *, uint8_t, uint16_t); 222 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, uint8_t, uint16_t); 223 #endif 224 static int iwn5000_query_calibration(struct iwn_softc *); 225 static int iwn5000_send_calibration(struct iwn_softc *); 226 static int iwn5000_send_wimax_coex(struct iwn_softc *); 227 static int iwn4965_post_alive(struct iwn_softc *); 228 static int iwn5000_post_alive(struct iwn_softc *); 229 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 230 int); 231 static int iwn4965_load_firmware(struct iwn_softc *); 232 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 233 const uint8_t *, int); 234 static int iwn5000_load_firmware(struct iwn_softc *); 235 static int iwn_read_firmware(struct iwn_softc *); 236 static int iwn_clock_wait(struct iwn_softc *); 237 static int iwn_apm_init(struct iwn_softc *); 238 static void iwn_apm_stop_master(struct iwn_softc *); 239 static void iwn_apm_stop(struct iwn_softc *); 240 static int iwn4965_nic_config(struct iwn_softc *); 241 static int iwn5000_nic_config(struct iwn_softc *); 242 static int iwn_hw_prepare(struct iwn_softc *); 243 static int iwn_hw_init(struct iwn_softc *); 244 static void iwn_hw_stop(struct iwn_softc *); 245 static void iwn_init_locked(struct iwn_softc *); 246 static void iwn_init(void *); 247 static void iwn_stop_locked(struct iwn_softc *); 248 static void iwn_stop(struct iwn_softc *); 249 static void iwn_scan_start(struct ieee80211com *); 250 static void iwn_scan_end(struct ieee80211com *); 251 static void iwn_set_channel(struct ieee80211com *); 252 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 253 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 254 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 255 struct ieee80211_channel *); 256 static int iwn_setregdomain(struct ieee80211com *, 257 struct ieee80211_regdomain *, int, 258 struct ieee80211_channel []); 259 static void iwn_hw_reset_task(void *, int); 260 static void iwn_radio_on_task(void *, int); 261 static void iwn_radio_off_task(void *, int); 262 static void iwn_sysctlattach(struct iwn_softc *); 263 static int iwn_pci_shutdown(device_t); 264 static int iwn_pci_suspend(device_t); 265 static int iwn_pci_resume(device_t); 266 267 #define IWN_DEBUG 268 #ifdef IWN_DEBUG 269 enum { 270 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 271 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 272 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 273 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */ 274 IWN_DEBUG_RESET = 0x00000010, /* reset processing */ 275 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */ 276 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 277 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */ 278 IWN_DEBUG_INTR = 0x00000100, /* ISR */ 279 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */ 280 IWN_DEBUG_NODE = 0x00000400, /* node management */ 281 IWN_DEBUG_LED = 0x00000800, /* led management */ 282 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */ 283 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */ 284 IWN_DEBUG_ANY = 0xffffffff 285 }; 286 287 #define DPRINTF(sc, m, fmt, ...) do { \ 288 if (sc->sc_debug & (m)) \ 289 kprintf(fmt, __VA_ARGS__); \ 290 } while (0) 291 292 static const char *iwn_intr_str(uint8_t); 293 #else 294 #define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0) 295 #endif 296 297 struct iwn_ident { 298 uint16_t vendor; 299 uint16_t device; 300 const char *name; 301 }; 302 303 static const struct iwn_ident iwn_ident_table [] = { 304 { 0x8086, 0x4229, "Intel(R) PRO/Wireless 4965BGN" }, 305 { 0x8086, 0x422D, "Intel(R) PRO/Wireless 4965BGN" }, 306 { 0x8086, 0x4230, "Intel(R) PRO/Wireless 4965BGN" }, 307 { 0x8086, 0x4233, "Intel(R) PRO/Wireless 4965BGN" }, 308 { 0x8086, 0x4232, "Intel(R) PRO/Wireless 5100" }, 309 { 0x8086, 0x4237, "Intel(R) PRO/Wireless 5100" }, 310 { 0x8086, 0x423C, "Intel(R) PRO/Wireless 5150" }, 311 { 0x8086, 0x423D, "Intel(R) PRO/Wireless 5150" }, 312 { 0x8086, 0x4235, "Intel(R) PRO/Wireless 5300" }, 313 { 0x8086, 0x4236, "Intel(R) PRO/Wireless 5300" }, 314 { 0x8086, 0x423A, "Intel(R) PRO/Wireless 5350" }, 315 { 0x8086, 0x423B, "Intel(R) PRO/Wireless 5350" }, 316 { 0x8086, 0x0083, "Intel(R) PRO/Wireless 1000" }, 317 { 0x8086, 0x0084, "Intel(R) PRO/Wireless 1000" }, 318 { 0x8086, 0x008D, "Intel(R) PRO/Wireless 6000" }, 319 { 0x8086, 0x008E, "Intel(R) PRO/Wireless 6000" }, 320 { 0x8086, 0x4238, "Intel(R) PRO/Wireless 6000" }, 321 { 0x8086, 0x4239, "Intel(R) PRO/Wireless 6000" }, 322 { 0x8086, 0x422B, "Intel(R) PRO/Wireless 6000" }, 323 { 0x8086, 0x422C, "Intel(R) PRO/Wireless 6000" }, 324 { 0x8086, 0x0086, "Intel(R) PRO/Wireless 6050" }, 325 { 0x8086, 0x0087, "Intel(R) PRO/Wireless 6050" }, 326 { 0, 0, NULL } 327 }; 328 329 static const struct iwn_hal iwn4965_hal = { 330 iwn4965_load_firmware, 331 iwn4965_read_eeprom, 332 iwn4965_post_alive, 333 iwn4965_nic_config, 334 iwn4965_update_sched, 335 iwn4965_get_temperature, 336 iwn4965_get_rssi, 337 iwn4965_set_txpower, 338 iwn4965_init_gains, 339 iwn4965_set_gains, 340 iwn4965_add_node, 341 iwn4965_tx_done, 342 #if 0 /* HT */ 343 iwn4965_ampdu_tx_start, 344 iwn4965_ampdu_tx_stop, 345 #endif 346 IWN4965_NTXQUEUES, 347 IWN4965_NDMACHNLS, 348 IWN4965_ID_BROADCAST, 349 IWN4965_RXONSZ, 350 IWN4965_SCHEDSZ, 351 IWN4965_FW_TEXT_MAXSZ, 352 IWN4965_FW_DATA_MAXSZ, 353 IWN4965_FWSZ, 354 IWN4965_SCHED_TXFACT 355 }; 356 357 static const struct iwn_hal iwn5000_hal = { 358 iwn5000_load_firmware, 359 iwn5000_read_eeprom, 360 iwn5000_post_alive, 361 iwn5000_nic_config, 362 iwn5000_update_sched, 363 iwn5000_get_temperature, 364 iwn5000_get_rssi, 365 iwn5000_set_txpower, 366 iwn5000_init_gains, 367 iwn5000_set_gains, 368 iwn5000_add_node, 369 iwn5000_tx_done, 370 #if 0 /* HT */ 371 iwn5000_ampdu_tx_start, 372 iwn5000_ampdu_tx_stop, 373 #endif 374 IWN5000_NTXQUEUES, 375 IWN5000_NDMACHNLS, 376 IWN5000_ID_BROADCAST, 377 IWN5000_RXONSZ, 378 IWN5000_SCHEDSZ, 379 IWN5000_FW_TEXT_MAXSZ, 380 IWN5000_FW_DATA_MAXSZ, 381 IWN5000_FWSZ, 382 IWN5000_SCHED_TXFACT 383 }; 384 385 static int 386 iwn_pci_probe(device_t dev) 387 { 388 const struct iwn_ident *ident; 389 390 /* no wlan serializer needed */ 391 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 392 if (pci_get_vendor(dev) == ident->vendor && 393 pci_get_device(dev) == ident->device) { 394 device_set_desc(dev, ident->name); 395 return 0; 396 } 397 } 398 return ENXIO; 399 } 400 401 static int 402 iwn_pci_attach(device_t dev) 403 { 404 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 405 struct ieee80211com *ic; 406 struct ifnet *ifp; 407 const struct iwn_hal *hal; 408 uint32_t tmp; 409 int i, error, result; 410 uint8_t macaddr[IEEE80211_ADDR_LEN]; 411 412 wlan_serialize_enter(); 413 414 sc->sc_dev = dev; 415 sc->sc_dmat = NULL; 416 417 if (bus_dma_tag_create(sc->sc_dmat, 418 1, 0, 419 BUS_SPACE_MAXADDR_32BIT, 420 BUS_SPACE_MAXADDR, 421 NULL, NULL, 422 BUS_SPACE_MAXSIZE, 423 IWN_MAX_SCATTER, 424 BUS_SPACE_MAXSIZE, 425 BUS_DMA_ALLOCNOW, 426 &sc->sc_dmat)) { 427 device_printf(dev, "cannot allocate DMA tag\n"); 428 error = ENOMEM; 429 goto fail; 430 } 431 432 433 434 /* prepare sysctl tree for use in sub modules */ 435 sysctl_ctx_init(&sc->sc_sysctl_ctx); 436 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx, 437 SYSCTL_STATIC_CHILDREN(_hw), 438 OID_AUTO, 439 device_get_nameunit(sc->sc_dev), 440 CTLFLAG_RD, 0, ""); 441 442 /* 443 * Get the offset of the PCI Express Capability Structure in PCI 444 * Configuration Space. 445 */ 446 error = pci_find_extcap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 447 if (error != 0) { 448 device_printf(dev, "PCIe capability structure not found!\n"); 449 goto fail2; 450 } 451 452 /* Clear device-specific "PCI retry timeout" register (41h). */ 453 pci_write_config(dev, 0x41, 0, 1); 454 455 /* Hardware bug workaround. */ 456 tmp = pci_read_config(dev, PCIR_COMMAND, 1); 457 if (tmp & PCIM_CMD_INTxDIS) { 458 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n", 459 __func__); 460 tmp &= ~PCIM_CMD_INTxDIS; 461 pci_write_config(dev, PCIR_COMMAND, tmp, 1); 462 } 463 464 /* Enable bus-mastering. */ 465 pci_enable_busmaster(dev); 466 467 sc->mem_rid = PCIR_BAR(0); 468 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 469 RF_ACTIVE); 470 if (sc->mem == NULL ) { 471 device_printf(dev, "could not allocate memory resources\n"); 472 error = ENOMEM; 473 goto fail2; 474 } 475 476 sc->sc_st = rman_get_bustag(sc->mem); 477 sc->sc_sh = rman_get_bushandle(sc->mem); 478 sc->irq_rid = 0; 479 if ((result = pci_msi_count(dev)) == 1 && 480 pci_alloc_msi(dev, &result) == 0) 481 sc->irq_rid = 1; 482 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 483 RF_ACTIVE | RF_SHAREABLE); 484 if (sc->irq == NULL) { 485 device_printf(dev, "could not allocate interrupt resource\n"); 486 error = ENOMEM; 487 goto fail; 488 } 489 490 callout_init(&sc->sc_timer_to); 491 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset_task, sc ); 492 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on_task, sc ); 493 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off_task, sc ); 494 495 /* Attach Hardware Abstraction Layer. */ 496 hal = iwn_hal_attach(sc); 497 if (hal == NULL) { 498 error = ENXIO; /* XXX: Wrong error code? */ 499 goto fail; 500 } 501 502 error = iwn_hw_prepare(sc); 503 if (error != 0) { 504 device_printf(dev, "hardware not ready, error %d\n", error); 505 goto fail; 506 } 507 508 /* Allocate DMA memory for firmware transfers. */ 509 error = iwn_alloc_fwmem(sc); 510 if (error != 0) { 511 device_printf(dev, 512 "could not allocate memory for firmware, error %d\n", 513 error); 514 goto fail; 515 } 516 517 /* Allocate "Keep Warm" page. */ 518 error = iwn_alloc_kw(sc); 519 if (error != 0) { 520 device_printf(dev, 521 "could not allocate \"Keep Warm\" page, error %d\n", error); 522 goto fail; 523 } 524 525 /* Allocate ICT table for 5000 Series. */ 526 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 527 (error = iwn_alloc_ict(sc)) != 0) { 528 device_printf(dev, 529 "%s: could not allocate ICT table, error %d\n", 530 __func__, error); 531 goto fail; 532 } 533 534 /* Allocate TX scheduler "rings". */ 535 error = iwn_alloc_sched(sc); 536 if (error != 0) { 537 device_printf(dev, 538 "could not allocate TX scheduler rings, error %d\n", 539 error); 540 goto fail; 541 } 542 543 /* Allocate TX rings (16 on 4965AGN, 20 on 5000). */ 544 for (i = 0; i < hal->ntxqs; i++) { 545 error = iwn_alloc_tx_ring(sc, &sc->txq[i], i); 546 if (error != 0) { 547 device_printf(dev, 548 "could not allocate Tx ring %d, error %d\n", 549 i, error); 550 goto fail; 551 } 552 } 553 554 /* Allocate RX ring. */ 555 error = iwn_alloc_rx_ring(sc, &sc->rxq); 556 if (error != 0 ){ 557 device_printf(dev, 558 "could not allocate Rx ring, error %d\n", error); 559 goto fail; 560 } 561 562 /* Clear pending interrupts. */ 563 IWN_WRITE(sc, IWN_INT, 0xffffffff); 564 565 /* Count the number of available chains. */ 566 sc->ntxchains = 567 ((sc->txchainmask >> 2) & 1) + 568 ((sc->txchainmask >> 1) & 1) + 569 ((sc->txchainmask >> 0) & 1); 570 sc->nrxchains = 571 ((sc->rxchainmask >> 2) & 1) + 572 ((sc->rxchainmask >> 1) & 1) + 573 ((sc->rxchainmask >> 0) & 1); 574 575 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 576 if (ifp == NULL) { 577 device_printf(dev, "can not allocate ifnet structure\n"); 578 goto fail; 579 } 580 ic = ifp->if_l2com; 581 582 ic->ic_ifp = ifp; 583 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 584 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 585 586 /* Set device capabilities. */ 587 ic->ic_caps = 588 IEEE80211_C_STA /* station mode supported */ 589 | IEEE80211_C_MONITOR /* monitor mode supported */ 590 | IEEE80211_C_TXPMGT /* tx power management */ 591 | IEEE80211_C_SHSLOT /* short slot time supported */ 592 | IEEE80211_C_WPA 593 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 594 | IEEE80211_C_BGSCAN /* background scanning */ 595 #if 0 596 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 597 #endif 598 | IEEE80211_C_WME /* WME */ 599 ; 600 #if 0 /* HT */ 601 /* XXX disable until HT channel setup works */ 602 ic->ic_htcaps = 603 IEEE80211_HTCAP_SMPS_ENA /* SM PS mode enabled */ 604 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width */ 605 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 606 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 607 | IEEE80211_HTCAP_RXSTBC_2STREAM/* 1-2 spatial streams */ 608 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 609 /* s/w capabilities */ 610 | IEEE80211_HTC_HT /* HT operation */ 611 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 612 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 613 ; 614 615 /* Set HT capabilities. */ 616 ic->ic_htcaps = 617 #if IWN_RBUF_SIZE == 8192 618 IEEE80211_HTCAP_AMSDU7935 | 619 #endif 620 IEEE80211_HTCAP_CBW20_40 | 621 IEEE80211_HTCAP_SGI20 | 622 IEEE80211_HTCAP_SGI40; 623 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 624 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 625 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 626 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 627 else 628 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 629 #endif 630 631 /* Read MAC address, channels, etc from EEPROM. */ 632 error = iwn_read_eeprom(sc, macaddr); 633 if (error != 0) { 634 device_printf(dev, "could not read EEPROM, error %d\n", 635 error); 636 goto fail; 637 } 638 639 device_printf(sc->sc_dev, "MIMO %dT%dR, %.4s, address %6D\n", 640 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 641 macaddr, ":"); 642 643 #if 0 /* HT */ 644 /* Set supported HT rates. */ 645 ic->ic_sup_mcs[0] = 0xff; 646 if (sc->nrxchains > 1) 647 ic->ic_sup_mcs[1] = 0xff; 648 if (sc->nrxchains > 2) 649 ic->ic_sup_mcs[2] = 0xff; 650 #endif 651 652 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 653 ifp->if_softc = sc; 654 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 655 ifp->if_init = iwn_init; 656 ifp->if_ioctl = iwn_ioctl; 657 ifp->if_start = iwn_start; 658 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 659 ifq_set_ready(&ifp->if_snd); 660 661 ieee80211_ifattach(ic, macaddr); 662 ic->ic_vap_create = iwn_vap_create; 663 ic->ic_vap_delete = iwn_vap_delete; 664 ic->ic_raw_xmit = iwn_raw_xmit; 665 ic->ic_node_alloc = iwn_node_alloc; 666 ic->ic_newassoc = iwn_newassoc; 667 ic->ic_wme.wme_update = iwn_wme_update; 668 ic->ic_update_mcast = iwn_update_mcast; 669 ic->ic_scan_start = iwn_scan_start; 670 ic->ic_scan_end = iwn_scan_end; 671 ic->ic_set_channel = iwn_set_channel; 672 ic->ic_scan_curchan = iwn_scan_curchan; 673 ic->ic_scan_mindwell = iwn_scan_mindwell; 674 ic->ic_setregdomain = iwn_setregdomain; 675 #if 0 /* HT */ 676 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 677 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 678 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 679 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 680 #endif 681 682 iwn_radiotap_attach(sc); 683 iwn_sysctlattach(sc); 684 685 /* 686 * Hook our interrupt after all initialization is complete. 687 */ 688 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE, 689 iwn_intr, sc, &sc->sc_ih, 690 &wlan_global_serializer); 691 if (error != 0) { 692 device_printf(dev, "could not set up interrupt, error %d\n", 693 error); 694 goto fail; 695 } 696 697 ieee80211_announce(ic); 698 wlan_serialize_exit(); 699 return 0; 700 fail: 701 iwn_cleanup(dev); 702 fail2: 703 wlan_serialize_exit(); 704 return error; 705 } 706 707 static const struct iwn_hal * 708 iwn_hal_attach(struct iwn_softc *sc) 709 { 710 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 711 712 switch (sc->hw_type) { 713 case IWN_HW_REV_TYPE_4965: 714 sc->sc_hal = &iwn4965_hal; 715 sc->limits = &iwn4965_sensitivity_limits; 716 sc->fwname = "iwn4965fw"; 717 sc->txchainmask = IWN_ANT_AB; 718 sc->rxchainmask = IWN_ANT_ABC; 719 break; 720 case IWN_HW_REV_TYPE_5100: 721 sc->sc_hal = &iwn5000_hal; 722 sc->limits = &iwn5000_sensitivity_limits; 723 sc->fwname = "iwn5000fw"; 724 sc->txchainmask = IWN_ANT_B; 725 sc->rxchainmask = IWN_ANT_AB; 726 break; 727 case IWN_HW_REV_TYPE_5150: 728 sc->sc_hal = &iwn5000_hal; 729 sc->limits = &iwn5150_sensitivity_limits; 730 sc->fwname = "iwn5150fw"; 731 sc->txchainmask = IWN_ANT_A; 732 sc->rxchainmask = IWN_ANT_AB; 733 break; 734 case IWN_HW_REV_TYPE_5300: 735 case IWN_HW_REV_TYPE_5350: 736 sc->sc_hal = &iwn5000_hal; 737 sc->limits = &iwn5000_sensitivity_limits; 738 sc->fwname = "iwn5000fw"; 739 sc->txchainmask = IWN_ANT_ABC; 740 sc->rxchainmask = IWN_ANT_ABC; 741 break; 742 case IWN_HW_REV_TYPE_1000: 743 sc->sc_hal = &iwn5000_hal; 744 sc->limits = &iwn1000_sensitivity_limits; 745 sc->fwname = "iwn1000fw"; 746 sc->txchainmask = IWN_ANT_A; 747 sc->rxchainmask = IWN_ANT_AB; 748 break; 749 case IWN_HW_REV_TYPE_6000: 750 sc->sc_hal = &iwn5000_hal; 751 sc->limits = &iwn6000_sensitivity_limits; 752 sc->fwname = "iwn6000fw"; 753 switch (pci_get_device(sc->sc_dev)) { 754 case 0x422C: 755 case 0x4239: 756 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 757 sc->txchainmask = IWN_ANT_BC; 758 sc->rxchainmask = IWN_ANT_BC; 759 break; 760 default: 761 sc->txchainmask = IWN_ANT_ABC; 762 sc->rxchainmask = IWN_ANT_ABC; 763 break; 764 } 765 break; 766 case IWN_HW_REV_TYPE_6050: 767 sc->sc_hal = &iwn5000_hal; 768 sc->limits = &iwn6000_sensitivity_limits; 769 sc->fwname = "iwn6000fw"; 770 sc->txchainmask = IWN_ANT_AB; 771 sc->rxchainmask = IWN_ANT_AB; 772 break; 773 default: 774 device_printf(sc->sc_dev, "adapter type %d not supported\n", 775 sc->hw_type); 776 return NULL; 777 } 778 return sc->sc_hal; 779 } 780 781 /* 782 * Attach the interface to 802.11 radiotap. 783 */ 784 static void 785 iwn_radiotap_attach(struct iwn_softc *sc) 786 { 787 struct ifnet *ifp = sc->sc_ifp; 788 struct ieee80211com *ic = ifp->if_l2com; 789 790 ieee80211_radiotap_attach(ic, 791 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 792 IWN_TX_RADIOTAP_PRESENT, 793 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 794 IWN_RX_RADIOTAP_PRESENT); 795 } 796 797 static struct ieee80211vap * 798 iwn_vap_create(struct ieee80211com *ic, 799 const char name[IFNAMSIZ], int unit, int opmode, int flags, 800 const uint8_t bssid[IEEE80211_ADDR_LEN], 801 const uint8_t mac[IEEE80211_ADDR_LEN]) 802 { 803 struct iwn_vap *ivp; 804 struct ieee80211vap *vap; 805 806 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 807 return NULL; 808 ivp = (struct iwn_vap *) kmalloc(sizeof(struct iwn_vap), 809 M_80211_VAP, M_INTWAIT | M_ZERO); 810 if (ivp == NULL) 811 return NULL; 812 vap = &ivp->iv_vap; 813 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 814 vap->iv_bmissthreshold = 10; /* override default */ 815 /* Override with driver methods. */ 816 ivp->iv_newstate = vap->iv_newstate; 817 vap->iv_newstate = iwn_newstate; 818 819 ieee80211_ratectl_init(vap); 820 /* Complete setup. */ 821 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status); 822 ic->ic_opmode = opmode; 823 return vap; 824 } 825 826 static void 827 iwn_vap_delete(struct ieee80211vap *vap) 828 { 829 struct iwn_vap *ivp = IWN_VAP(vap); 830 831 ieee80211_ratectl_deinit(vap); 832 ieee80211_vap_detach(vap); 833 kfree(ivp, M_80211_VAP); 834 } 835 836 static int 837 iwn_cleanup(device_t dev) 838 { 839 struct iwn_softc *sc = device_get_softc(dev); 840 struct ifnet *ifp = sc->sc_ifp; 841 struct ieee80211com *ic; 842 int i; 843 844 if (ifp != NULL) { 845 ic = ifp->if_l2com; 846 847 ieee80211_draintask(ic, &sc->sc_reinit_task); 848 ieee80211_draintask(ic, &sc->sc_radioon_task); 849 ieee80211_draintask(ic, &sc->sc_radiooff_task); 850 851 iwn_stop(sc); 852 callout_stop(&sc->sc_timer_to); 853 ieee80211_ifdetach(ic); 854 } 855 856 /* cleanup sysctl nodes */ 857 sysctl_ctx_free(&sc->sc_sysctl_ctx); 858 859 /* Free DMA resources. */ 860 iwn_free_rx_ring(sc, &sc->rxq); 861 if (sc->sc_hal != NULL) 862 for (i = 0; i < sc->sc_hal->ntxqs; i++) 863 iwn_free_tx_ring(sc, &sc->txq[i]); 864 iwn_free_sched(sc); 865 iwn_free_kw(sc); 866 if (sc->ict != NULL) { 867 iwn_free_ict(sc); 868 sc->ict = NULL; 869 } 870 iwn_free_fwmem(sc); 871 872 if (sc->irq != NULL) { 873 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 874 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 875 if (sc->irq_rid == 1) 876 pci_release_msi(dev); 877 sc->irq = NULL; 878 } 879 880 if (sc->mem != NULL) { 881 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 882 sc->mem = NULL; 883 } 884 885 if (ifp != NULL) { 886 if_free(ifp); 887 sc->sc_ifp = NULL; 888 } 889 890 return 0; 891 } 892 893 static int 894 iwn_pci_detach(device_t dev) 895 { 896 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 897 898 wlan_serialize_enter(); 899 iwn_cleanup(dev); 900 bus_dma_tag_destroy(sc->sc_dmat); 901 wlan_serialize_exit(); 902 903 return 0; 904 } 905 906 static int 907 iwn_nic_lock(struct iwn_softc *sc) 908 { 909 int ntries; 910 911 /* Request exclusive access to NIC. */ 912 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 913 914 /* Spin until we actually get the lock. */ 915 for (ntries = 0; ntries < 1000; ntries++) { 916 if ((IWN_READ(sc, IWN_GP_CNTRL) & 917 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 918 IWN_GP_CNTRL_MAC_ACCESS_ENA) 919 return 0; 920 DELAY(10); 921 } 922 return ETIMEDOUT; 923 } 924 925 static __inline void 926 iwn_nic_unlock(struct iwn_softc *sc) 927 { 928 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 929 } 930 931 static __inline uint32_t 932 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 933 { 934 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 935 IWN_BARRIER_READ_WRITE(sc); 936 return IWN_READ(sc, IWN_PRPH_RDATA); 937 } 938 939 static __inline void 940 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 941 { 942 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 943 IWN_BARRIER_WRITE(sc); 944 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 945 } 946 947 static __inline void 948 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 949 { 950 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 951 } 952 953 static __inline void 954 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 955 { 956 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 957 } 958 959 static __inline void 960 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 961 const uint32_t *data, int count) 962 { 963 for (; count > 0; count--, data++, addr += 4) 964 iwn_prph_write(sc, addr, *data); 965 } 966 967 static __inline uint32_t 968 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 969 { 970 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 971 IWN_BARRIER_READ_WRITE(sc); 972 return IWN_READ(sc, IWN_MEM_RDATA); 973 } 974 975 static __inline void 976 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 977 { 978 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 979 IWN_BARRIER_WRITE(sc); 980 IWN_WRITE(sc, IWN_MEM_WDATA, data); 981 } 982 983 static __inline void 984 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 985 { 986 uint32_t tmp; 987 988 tmp = iwn_mem_read(sc, addr & ~3); 989 if (addr & 3) 990 tmp = (tmp & 0x0000ffff) | data << 16; 991 else 992 tmp = (tmp & 0xffff0000) | data; 993 iwn_mem_write(sc, addr & ~3, tmp); 994 } 995 996 static __inline void 997 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 998 int count) 999 { 1000 for (; count > 0; count--, addr += 4) 1001 *data++ = iwn_mem_read(sc, addr); 1002 } 1003 1004 static __inline void 1005 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1006 int count) 1007 { 1008 for (; count > 0; count--, addr += 4) 1009 iwn_mem_write(sc, addr, val); 1010 } 1011 1012 static int 1013 iwn_eeprom_lock(struct iwn_softc *sc) 1014 { 1015 int i, ntries; 1016 1017 for (i = 0; i < 100; i++) { 1018 /* Request exclusive access to EEPROM. */ 1019 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1020 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1021 1022 /* Spin until we actually get the lock. */ 1023 for (ntries = 0; ntries < 100; ntries++) { 1024 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1025 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1026 return 0; 1027 DELAY(10); 1028 } 1029 } 1030 return ETIMEDOUT; 1031 } 1032 1033 static __inline void 1034 iwn_eeprom_unlock(struct iwn_softc *sc) 1035 { 1036 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1037 } 1038 1039 /* 1040 * Initialize access by host to One Time Programmable ROM. 1041 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1042 */ 1043 static int 1044 iwn_init_otprom(struct iwn_softc *sc) 1045 { 1046 uint16_t prev, base, next; 1047 int count, error; 1048 1049 /* Wait for clock stabilization before accessing prph. */ 1050 error = iwn_clock_wait(sc); 1051 if (error != 0) 1052 return error; 1053 1054 error = iwn_nic_lock(sc); 1055 if (error != 0) 1056 return error; 1057 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1058 DELAY(5); 1059 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1060 iwn_nic_unlock(sc); 1061 1062 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1063 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1064 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1065 IWN_RESET_LINK_PWR_MGMT_DIS); 1066 } 1067 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1068 /* Clear ECC status. */ 1069 IWN_SETBITS(sc, IWN_OTP_GP, 1070 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1071 1072 /* 1073 * Find the block before last block (contains the EEPROM image) 1074 * for HW without OTP shadow RAM. 1075 */ 1076 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1077 /* Switch to absolute addressing mode. */ 1078 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1079 base = prev = 0; 1080 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1081 error = iwn_read_prom_data(sc, base, &next, 2); 1082 if (error != 0) 1083 return error; 1084 if (next == 0) /* End of linked-list. */ 1085 break; 1086 prev = base; 1087 base = le16toh(next); 1088 } 1089 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1090 return EIO; 1091 /* Skip "next" word. */ 1092 sc->prom_base = prev + 1; 1093 } 1094 return 0; 1095 } 1096 1097 static int 1098 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1099 { 1100 uint32_t val, tmp; 1101 int ntries; 1102 uint8_t *out = data; 1103 1104 addr += sc->prom_base; 1105 for (; count > 0; count -= 2, addr++) { 1106 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1107 for (ntries = 0; ntries < 10; ntries++) { 1108 val = IWN_READ(sc, IWN_EEPROM); 1109 if (val & IWN_EEPROM_READ_VALID) 1110 break; 1111 DELAY(5); 1112 } 1113 if (ntries == 10) { 1114 device_printf(sc->sc_dev, 1115 "timeout reading ROM at 0x%x\n", addr); 1116 return ETIMEDOUT; 1117 } 1118 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1119 /* OTPROM, check for ECC errors. */ 1120 tmp = IWN_READ(sc, IWN_OTP_GP); 1121 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1122 device_printf(sc->sc_dev, 1123 "OTPROM ECC error at 0x%x\n", addr); 1124 return EIO; 1125 } 1126 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1127 /* Correctable ECC error, clear bit. */ 1128 IWN_SETBITS(sc, IWN_OTP_GP, 1129 IWN_OTP_GP_ECC_CORR_STTS); 1130 } 1131 } 1132 *out++ = val >> 16; 1133 if (count > 1) 1134 *out++ = val >> 24; 1135 } 1136 return 0; 1137 } 1138 1139 static void 1140 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1141 { 1142 if (error != 0) 1143 return; 1144 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1145 *(bus_addr_t *)arg = segs[0].ds_addr; 1146 } 1147 1148 static int 1149 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1150 void **kvap, bus_size_t size, bus_size_t alignment, int flags) 1151 { 1152 int error; 1153 1154 dma->size = size; 1155 dma->tag = NULL; 1156 1157 error = bus_dma_tag_create(sc->sc_dmat, alignment, 1158 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1159 1, size, flags, &dma->tag); 1160 if (error != 0) { 1161 device_printf(sc->sc_dev, 1162 "%s: bus_dma_tag_create failed, error %d\n", 1163 __func__, error); 1164 goto fail; 1165 } 1166 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1167 flags | BUS_DMA_ZERO, &dma->map); 1168 if (error != 0) { 1169 device_printf(sc->sc_dev, 1170 "%s: bus_dmamem_alloc failed, error %d\n", __func__, error); 1171 goto fail; 1172 } 1173 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, 1174 size, iwn_dma_map_addr, &dma->paddr, flags); 1175 if (error != 0) { 1176 device_printf(sc->sc_dev, 1177 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 1178 goto fail; 1179 } 1180 1181 if (kvap != NULL) 1182 *kvap = dma->vaddr; 1183 return 0; 1184 fail: 1185 iwn_dma_contig_free(dma); 1186 return error; 1187 } 1188 1189 static void 1190 iwn_dma_contig_free(struct iwn_dma_info *dma) 1191 { 1192 if (dma->tag != NULL) { 1193 if (dma->map != NULL) { 1194 if (dma->paddr == 0) { 1195 bus_dmamap_sync(dma->tag, dma->map, 1196 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1197 bus_dmamap_unload(dma->tag, dma->map); 1198 } 1199 bus_dmamap_destroy(dma->tag, dma->map); 1200 } 1201 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1202 bus_dma_tag_destroy(dma->tag); 1203 } 1204 } 1205 1206 static int 1207 iwn_alloc_sched(struct iwn_softc *sc) 1208 { 1209 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1210 return iwn_dma_contig_alloc(sc, &sc->sched_dma, 1211 (void **)&sc->sched, sc->sc_hal->schedsz, 1024, BUS_DMA_NOWAIT); 1212 } 1213 1214 static void 1215 iwn_free_sched(struct iwn_softc *sc) 1216 { 1217 iwn_dma_contig_free(&sc->sched_dma); 1218 } 1219 1220 static int 1221 iwn_alloc_kw(struct iwn_softc *sc) 1222 { 1223 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1224 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096, 1225 BUS_DMA_NOWAIT); 1226 } 1227 1228 static void 1229 iwn_free_kw(struct iwn_softc *sc) 1230 { 1231 iwn_dma_contig_free(&sc->kw_dma); 1232 } 1233 1234 static int 1235 iwn_alloc_ict(struct iwn_softc *sc) 1236 { 1237 /* ICT table must be aligned on a 4KB boundary. */ 1238 return iwn_dma_contig_alloc(sc, &sc->ict_dma, 1239 (void **)&sc->ict, IWN_ICT_SIZE, 4096, BUS_DMA_NOWAIT); 1240 } 1241 1242 static void 1243 iwn_free_ict(struct iwn_softc *sc) 1244 { 1245 iwn_dma_contig_free(&sc->ict_dma); 1246 } 1247 1248 static int 1249 iwn_alloc_fwmem(struct iwn_softc *sc) 1250 { 1251 /* Must be aligned on a 16-byte boundary. */ 1252 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, 1253 sc->sc_hal->fwsz, 16, BUS_DMA_NOWAIT); 1254 } 1255 1256 static void 1257 iwn_free_fwmem(struct iwn_softc *sc) 1258 { 1259 iwn_dma_contig_free(&sc->fw_dma); 1260 } 1261 1262 static int 1263 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1264 { 1265 bus_size_t size; 1266 int i, error; 1267 1268 ring->cur = 0; 1269 1270 /* Allocate RX descriptors (256-byte aligned). */ 1271 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1272 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, 1273 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT); 1274 if (error != 0) { 1275 device_printf(sc->sc_dev, 1276 "%s: could not allocate Rx ring DMA memory, error %d\n", 1277 __func__, error); 1278 goto fail; 1279 } 1280 1281 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 1282 BUS_SPACE_MAXADDR_32BIT, 1283 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1284 MCLBYTES, BUS_DMA_NOWAIT, &ring->data_dmat); 1285 if (error != 0) { 1286 device_printf(sc->sc_dev, 1287 "%s: bus_dma_tag_create_failed, error %d\n", 1288 __func__, error); 1289 goto fail; 1290 } 1291 1292 /* Allocate RX status area (16-byte aligned). */ 1293 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, 1294 (void **)&ring->stat, sizeof (struct iwn_rx_status), 1295 16, BUS_DMA_NOWAIT); 1296 if (error != 0) { 1297 device_printf(sc->sc_dev, 1298 "%s: could not allocate Rx status DMA memory, error %d\n", 1299 __func__, error); 1300 goto fail; 1301 } 1302 1303 /* 1304 * Allocate and map RX buffers. 1305 */ 1306 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1307 struct iwn_rx_data *data = &ring->data[i]; 1308 bus_addr_t paddr; 1309 1310 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1311 if (error != 0) { 1312 device_printf(sc->sc_dev, 1313 "%s: bus_dmamap_create failed, error %d\n", 1314 __func__, error); 1315 goto fail; 1316 } 1317 1318 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1319 if (data->m == NULL) { 1320 device_printf(sc->sc_dev, 1321 "%s: could not allocate rx mbuf\n", __func__); 1322 error = ENOMEM; 1323 goto fail; 1324 } 1325 1326 /* Map page. */ 1327 error = bus_dmamap_load(ring->data_dmat, data->map, 1328 mtod(data->m, caddr_t), MCLBYTES, 1329 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 1330 if (error != 0 && error != EFBIG) { 1331 device_printf(sc->sc_dev, 1332 "%s: bus_dmamap_load failed, error %d\n", 1333 __func__, error); 1334 m_freem(data->m); 1335 error = ENOMEM; /* XXX unique code */ 1336 goto fail; 1337 } 1338 bus_dmamap_sync(ring->data_dmat, data->map, 1339 BUS_DMASYNC_PREWRITE); 1340 1341 /* Set physical address of RX buffer (256-byte aligned). */ 1342 ring->desc[i] = htole32(paddr >> 8); 1343 } 1344 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1345 BUS_DMASYNC_PREWRITE); 1346 return 0; 1347 fail: 1348 iwn_free_rx_ring(sc, ring); 1349 return error; 1350 } 1351 1352 static void 1353 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1354 { 1355 int ntries; 1356 1357 if (iwn_nic_lock(sc) == 0) { 1358 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1359 for (ntries = 0; ntries < 1000; ntries++) { 1360 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1361 IWN_FH_RX_STATUS_IDLE) 1362 break; 1363 DELAY(10); 1364 } 1365 iwn_nic_unlock(sc); 1366 #ifdef IWN_DEBUG 1367 if (ntries == 1000) 1368 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 1369 "timeout resetting Rx ring"); 1370 #endif 1371 } 1372 ring->cur = 0; 1373 sc->last_rx_valid = 0; 1374 } 1375 1376 static void 1377 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1378 { 1379 int i; 1380 1381 iwn_dma_contig_free(&ring->desc_dma); 1382 iwn_dma_contig_free(&ring->stat_dma); 1383 1384 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1385 struct iwn_rx_data *data = &ring->data[i]; 1386 1387 if (data->m != NULL) { 1388 bus_dmamap_sync(ring->data_dmat, data->map, 1389 BUS_DMASYNC_POSTREAD); 1390 bus_dmamap_unload(ring->data_dmat, data->map); 1391 m_freem(data->m); 1392 } 1393 if (data->map != NULL) 1394 bus_dmamap_destroy(ring->data_dmat, data->map); 1395 } 1396 } 1397 1398 static int 1399 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1400 { 1401 bus_size_t size; 1402 bus_addr_t paddr; 1403 int i, error; 1404 1405 ring->qid = qid; 1406 ring->queued = 0; 1407 ring->cur = 0; 1408 1409 /* Allocate TX descriptors (256-byte aligned.) */ 1410 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_desc); 1411 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, 1412 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT); 1413 if (error != 0) { 1414 device_printf(sc->sc_dev, 1415 "%s: could not allocate TX ring DMA memory, error %d\n", 1416 __func__, error); 1417 goto fail; 1418 } 1419 1420 /* 1421 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1422 * to allocate commands space for other rings. 1423 */ 1424 if (qid > 4) 1425 return 0; 1426 1427 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_cmd); 1428 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, 1429 (void **)&ring->cmd, size, 4, BUS_DMA_NOWAIT); 1430 if (error != 0) { 1431 device_printf(sc->sc_dev, 1432 "%s: could not allocate TX cmd DMA memory, error %d\n", 1433 __func__, error); 1434 goto fail; 1435 } 1436 1437 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 1438 BUS_SPACE_MAXADDR_32BIT, 1439 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IWN_MAX_SCATTER - 1, 1440 MCLBYTES, BUS_DMA_NOWAIT, &ring->data_dmat); 1441 if (error != 0) { 1442 device_printf(sc->sc_dev, 1443 "%s: bus_dma_tag_create_failed, error %d\n", 1444 __func__, error); 1445 goto fail; 1446 } 1447 1448 paddr = ring->cmd_dma.paddr; 1449 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1450 struct iwn_tx_data *data = &ring->data[i]; 1451 1452 data->cmd_paddr = paddr; 1453 data->scratch_paddr = paddr + 12; 1454 paddr += sizeof (struct iwn_tx_cmd); 1455 1456 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1457 if (error != 0) { 1458 device_printf(sc->sc_dev, 1459 "%s: bus_dmamap_create failed, error %d\n", 1460 __func__, error); 1461 goto fail; 1462 } 1463 bus_dmamap_sync(ring->data_dmat, data->map, 1464 BUS_DMASYNC_PREWRITE); 1465 } 1466 return 0; 1467 fail: 1468 iwn_free_tx_ring(sc, ring); 1469 return error; 1470 } 1471 1472 static void 1473 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1474 { 1475 int i; 1476 1477 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1478 struct iwn_tx_data *data = &ring->data[i]; 1479 1480 if (data->m != NULL) { 1481 bus_dmamap_unload(ring->data_dmat, data->map); 1482 m_freem(data->m); 1483 data->m = NULL; 1484 } 1485 } 1486 /* Clear TX descriptors. */ 1487 memset(ring->desc, 0, ring->desc_dma.size); 1488 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1489 BUS_DMASYNC_PREWRITE); 1490 sc->qfullmsk &= ~(1 << ring->qid); 1491 ring->queued = 0; 1492 ring->cur = 0; 1493 } 1494 1495 static void 1496 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1497 { 1498 int i; 1499 1500 iwn_dma_contig_free(&ring->desc_dma); 1501 iwn_dma_contig_free(&ring->cmd_dma); 1502 1503 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1504 struct iwn_tx_data *data = &ring->data[i]; 1505 1506 if (data->m != NULL) { 1507 bus_dmamap_sync(ring->data_dmat, data->map, 1508 BUS_DMASYNC_POSTWRITE); 1509 bus_dmamap_unload(ring->data_dmat, data->map); 1510 m_freem(data->m); 1511 } 1512 if (data->map != NULL) 1513 bus_dmamap_destroy(ring->data_dmat, data->map); 1514 } 1515 } 1516 1517 static void 1518 iwn5000_ict_reset(struct iwn_softc *sc) 1519 { 1520 /* Disable interrupts. */ 1521 IWN_WRITE(sc, IWN_INT_MASK, 0); 1522 1523 /* Reset ICT table. */ 1524 memset(sc->ict, 0, IWN_ICT_SIZE); 1525 sc->ict_cur = 0; 1526 1527 /* Set physical address of ICT table (4KB aligned.) */ 1528 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 1529 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1530 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1531 1532 /* Enable periodic RX interrupt. */ 1533 sc->int_mask |= IWN_INT_RX_PERIODIC; 1534 /* Switch to ICT interrupt mode in driver. */ 1535 sc->sc_flags |= IWN_FLAG_USE_ICT; 1536 1537 /* Re-enable interrupts. */ 1538 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1539 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1540 } 1541 1542 static int 1543 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 1544 { 1545 const struct iwn_hal *hal = sc->sc_hal; 1546 int error; 1547 uint16_t val; 1548 1549 /* Check whether adapter has an EEPROM or an OTPROM. */ 1550 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1551 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1552 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1553 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 1554 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 1555 1556 /* Adapter has to be powered on for EEPROM access to work. */ 1557 error = iwn_apm_init(sc); 1558 if (error != 0) { 1559 device_printf(sc->sc_dev, 1560 "%s: could not power ON adapter, error %d\n", 1561 __func__, error); 1562 return error; 1563 } 1564 1565 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1566 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 1567 return EIO; 1568 } 1569 error = iwn_eeprom_lock(sc); 1570 if (error != 0) { 1571 device_printf(sc->sc_dev, 1572 "%s: could not lock ROM, error %d\n", 1573 __func__, error); 1574 return error; 1575 } 1576 1577 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1578 error = iwn_init_otprom(sc); 1579 if (error != 0) { 1580 device_printf(sc->sc_dev, 1581 "%s: could not initialize OTPROM, error %d\n", 1582 __func__, error); 1583 return error; 1584 } 1585 } 1586 1587 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1588 sc->rfcfg = le16toh(val); 1589 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 1590 1591 /* Read MAC address. */ 1592 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 1593 1594 /* Read adapter-specific information from EEPROM. */ 1595 hal->read_eeprom(sc); 1596 1597 iwn_apm_stop(sc); /* Power OFF adapter. */ 1598 1599 iwn_eeprom_unlock(sc); 1600 return 0; 1601 } 1602 1603 static void 1604 iwn4965_read_eeprom(struct iwn_softc *sc) 1605 { 1606 uint32_t addr; 1607 int i; 1608 uint16_t val; 1609 1610 /* Read regulatory domain (4 ASCII characters.) */ 1611 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1612 1613 /* Read the list of authorized channels (20MHz ones only.) */ 1614 for (i = 0; i < 5; i++) { 1615 addr = iwn4965_regulatory_bands[i]; 1616 iwn_read_eeprom_channels(sc, i, addr); 1617 } 1618 1619 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1620 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1621 sc->maxpwr2GHz = val & 0xff; 1622 sc->maxpwr5GHz = val >> 8; 1623 /* Check that EEPROM values are within valid range. */ 1624 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1625 sc->maxpwr5GHz = 38; 1626 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1627 sc->maxpwr2GHz = 38; 1628 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 1629 sc->maxpwr2GHz, sc->maxpwr5GHz); 1630 1631 /* Read samples for each TX power group. */ 1632 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1633 sizeof sc->bands); 1634 1635 /* Read voltage at which samples were taken. */ 1636 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1637 sc->eeprom_voltage = (int16_t)le16toh(val); 1638 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 1639 sc->eeprom_voltage); 1640 1641 #ifdef IWN_DEBUG 1642 /* Print samples. */ 1643 if (sc->sc_debug & IWN_DEBUG_ANY) { 1644 for (i = 0; i < IWN_NBANDS; i++) 1645 iwn4965_print_power_group(sc, i); 1646 } 1647 #endif 1648 } 1649 1650 #ifdef IWN_DEBUG 1651 static void 1652 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1653 { 1654 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1655 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1656 int j, c; 1657 1658 kprintf("===band %d===\n", i); 1659 kprintf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1660 kprintf("chan1 num=%d\n", chans[0].num); 1661 for (c = 0; c < 2; c++) { 1662 for (j = 0; j < IWN_NSAMPLES; j++) { 1663 kprintf("chain %d, sample %d: temp=%d gain=%d " 1664 "power=%d pa_det=%d\n", c, j, 1665 chans[0].samples[c][j].temp, 1666 chans[0].samples[c][j].gain, 1667 chans[0].samples[c][j].power, 1668 chans[0].samples[c][j].pa_det); 1669 } 1670 } 1671 kprintf("chan2 num=%d\n", chans[1].num); 1672 for (c = 0; c < 2; c++) { 1673 for (j = 0; j < IWN_NSAMPLES; j++) { 1674 kprintf("chain %d, sample %d: temp=%d gain=%d " 1675 "power=%d pa_det=%d\n", c, j, 1676 chans[1].samples[c][j].temp, 1677 chans[1].samples[c][j].gain, 1678 chans[1].samples[c][j].power, 1679 chans[1].samples[c][j].pa_det); 1680 } 1681 } 1682 } 1683 #endif 1684 1685 static void 1686 iwn5000_read_eeprom(struct iwn_softc *sc) 1687 { 1688 struct iwn5000_eeprom_calib_hdr hdr; 1689 int32_t temp, volt; 1690 uint32_t addr, base; 1691 int i; 1692 uint16_t val; 1693 1694 /* Read regulatory domain (4 ASCII characters.) */ 1695 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1696 base = le16toh(val); 1697 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1698 sc->eeprom_domain, 4); 1699 1700 /* Read the list of authorized channels (20MHz ones only.) */ 1701 for (i = 0; i < 5; i++) { 1702 addr = base + iwn5000_regulatory_bands[i]; 1703 iwn_read_eeprom_channels(sc, i, addr); 1704 } 1705 1706 /* Read enhanced TX power information for 6000 Series. */ 1707 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1708 iwn_read_eeprom_enhinfo(sc); 1709 1710 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1711 base = le16toh(val); 1712 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1713 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 1714 "%s: calib version=%u pa type=%u voltage=%u\n", 1715 __func__, hdr.version, hdr.pa_type, le16toh(hdr.volt)); 1716 sc->calib_ver = hdr.version; 1717 1718 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1719 /* Compute temperature offset. */ 1720 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1721 temp = le16toh(val); 1722 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1723 volt = le16toh(val); 1724 sc->temp_off = temp - (volt / -5); 1725 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 1726 temp, volt, sc->temp_off); 1727 } else { 1728 /* Read crystal calibration. */ 1729 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1730 &sc->eeprom_crystal, sizeof (uint32_t)); 1731 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 1732 le32toh(sc->eeprom_crystal)); 1733 } 1734 } 1735 1736 /* 1737 * Translate EEPROM flags to net80211. 1738 */ 1739 static uint32_t 1740 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 1741 { 1742 uint32_t nflags; 1743 1744 nflags = 0; 1745 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 1746 nflags |= IEEE80211_CHAN_PASSIVE; 1747 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 1748 nflags |= IEEE80211_CHAN_NOADHOC; 1749 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 1750 nflags |= IEEE80211_CHAN_DFS; 1751 /* XXX apparently IBSS may still be marked */ 1752 nflags |= IEEE80211_CHAN_NOADHOC; 1753 } 1754 1755 return nflags; 1756 } 1757 1758 static void 1759 iwn_read_eeprom_band(struct iwn_softc *sc, int n) 1760 { 1761 struct ifnet *ifp = sc->sc_ifp; 1762 struct ieee80211com *ic = ifp->if_l2com; 1763 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1764 const struct iwn_chan_band *band = &iwn_bands[n]; 1765 struct ieee80211_channel *c; 1766 int i, chan, nflags; 1767 1768 for (i = 0; i < band->nchan; i++) { 1769 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1770 DPRINTF(sc, IWN_DEBUG_RESET, 1771 "skip chan %d flags 0x%x maxpwr %d\n", 1772 band->chan[i], channels[i].flags, 1773 channels[i].maxpwr); 1774 continue; 1775 } 1776 chan = band->chan[i]; 1777 nflags = iwn_eeprom_channel_flags(&channels[i]); 1778 1779 DPRINTF(sc, IWN_DEBUG_RESET, 1780 "add chan %d flags 0x%x maxpwr %d\n", 1781 chan, channels[i].flags, channels[i].maxpwr); 1782 1783 c = &ic->ic_channels[ic->ic_nchans++]; 1784 c->ic_ieee = chan; 1785 c->ic_maxregpower = channels[i].maxpwr; 1786 c->ic_maxpower = 2*c->ic_maxregpower; 1787 1788 /* Save maximum allowed TX power for this channel. */ 1789 sc->maxpwr[chan] = channels[i].maxpwr; 1790 1791 if (n == 0) { /* 2GHz band */ 1792 c->ic_freq = ieee80211_ieee2mhz(chan, 1793 IEEE80211_CHAN_G); 1794 1795 /* G =>'s B is supported */ 1796 c->ic_flags = IEEE80211_CHAN_B | nflags; 1797 1798 c = &ic->ic_channels[ic->ic_nchans++]; 1799 c[0] = c[-1]; 1800 c->ic_flags = IEEE80211_CHAN_G | nflags; 1801 } else { /* 5GHz band */ 1802 c->ic_freq = ieee80211_ieee2mhz(chan, 1803 IEEE80211_CHAN_A); 1804 c->ic_flags = IEEE80211_CHAN_A | nflags; 1805 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1806 } 1807 #if 0 /* HT */ 1808 /* XXX no constraints on using HT20 */ 1809 /* add HT20, HT40 added separately */ 1810 c = &ic->ic_channels[ic->ic_nchans++]; 1811 c[0] = c[-1]; 1812 c->ic_flags |= IEEE80211_CHAN_HT20; 1813 /* XXX NARROW =>'s 1/2 and 1/4 width? */ 1814 #endif 1815 } 1816 } 1817 1818 #if 0 /* HT */ 1819 static void 1820 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 1821 { 1822 struct ifnet *ifp = sc->sc_ifp; 1823 struct ieee80211com *ic = ifp->if_l2com; 1824 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1825 const struct iwn_chan_band *band = &iwn_bands[n]; 1826 struct ieee80211_channel *c, *cent, *extc; 1827 int i; 1828 1829 for (i = 0; i < band->nchan; i++) { 1830 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID) || 1831 !(channels[i].flags & IWN_EEPROM_CHAN_WIDE)) { 1832 DPRINTF(sc, IWN_DEBUG_RESET, 1833 "skip chan %d flags 0x%x maxpwr %d\n", 1834 band->chan[i], channels[i].flags, 1835 channels[i].maxpwr); 1836 continue; 1837 } 1838 /* 1839 * Each entry defines an HT40 channel pair; find the 1840 * center channel, then the extension channel above. 1841 */ 1842 cent = ieee80211_find_channel_byieee(ic, band->chan[i], 1843 band->flags & ~IEEE80211_CHAN_HT); 1844 if (cent == NULL) { /* XXX shouldn't happen */ 1845 device_printf(sc->sc_dev, 1846 "%s: no entry for channel %d\n", 1847 __func__, band->chan[i]); 1848 continue; 1849 } 1850 extc = ieee80211_find_channel(ic, cent->ic_freq+20, 1851 band->flags & ~IEEE80211_CHAN_HT); 1852 if (extc == NULL) { 1853 DPRINTF(sc, IWN_DEBUG_RESET, 1854 "skip chan %d, extension channel not found\n", 1855 band->chan[i]); 1856 continue; 1857 } 1858 1859 DPRINTF(sc, IWN_DEBUG_RESET, 1860 "add ht40 chan %d flags 0x%x maxpwr %d\n", 1861 band->chan[i], channels[i].flags, channels[i].maxpwr); 1862 1863 c = &ic->ic_channels[ic->ic_nchans++]; 1864 c[0] = cent[0]; 1865 c->ic_extieee = extc->ic_ieee; 1866 c->ic_flags &= ~IEEE80211_CHAN_HT; 1867 c->ic_flags |= IEEE80211_CHAN_HT40U; 1868 c = &ic->ic_channels[ic->ic_nchans++]; 1869 c[0] = extc[0]; 1870 c->ic_extieee = cent->ic_ieee; 1871 c->ic_flags &= ~IEEE80211_CHAN_HT; 1872 c->ic_flags |= IEEE80211_CHAN_HT40D; 1873 } 1874 } 1875 #endif 1876 1877 static void 1878 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1879 { 1880 struct ifnet *ifp = sc->sc_ifp; 1881 struct ieee80211com *ic = ifp->if_l2com; 1882 1883 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 1884 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 1885 1886 if (n < 5) 1887 iwn_read_eeprom_band(sc, n); 1888 #if 0 /* HT */ 1889 else 1890 iwn_read_eeprom_ht40(sc, n); 1891 #endif 1892 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 1893 } 1894 1895 #define nitems(_a) (sizeof((_a)) / sizeof((_a)[0])) 1896 1897 static void 1898 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1899 { 1900 struct iwn_eeprom_enhinfo enhinfo[35]; 1901 uint16_t val, base; 1902 int8_t maxpwr; 1903 int i; 1904 1905 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1906 base = le16toh(val); 1907 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1908 enhinfo, sizeof enhinfo); 1909 1910 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1911 for (i = 0; i < nitems(enhinfo); i++) { 1912 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1913 continue; /* Skip invalid entries. */ 1914 1915 maxpwr = 0; 1916 if (sc->txchainmask & IWN_ANT_A) 1917 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1918 if (sc->txchainmask & IWN_ANT_B) 1919 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1920 if (sc->txchainmask & IWN_ANT_C) 1921 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1922 if (sc->ntxchains == 2) 1923 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1924 else if (sc->ntxchains == 3) 1925 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1926 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1927 1928 DPRINTF(sc, IWN_DEBUG_RESET, "enhinfo %d, maxpwr=%d\n", i, 1929 maxpwr); 1930 sc->enh_maxpwr[i] = maxpwr; 1931 } 1932 } 1933 1934 static struct ieee80211_node * 1935 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 1936 { 1937 return kmalloc(sizeof (struct iwn_node), M_80211_NODE,M_INTWAIT | M_ZERO); 1938 } 1939 1940 static void 1941 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1942 { 1943 /* XXX move */ 1944 //if (!isnew) { 1945 ieee80211_ratectl_node_deinit(ni); 1946 //} 1947 1948 ieee80211_ratectl_node_init(ni); 1949 } 1950 1951 static int 1952 iwn_media_change(struct ifnet *ifp) 1953 { 1954 int error = ieee80211_media_change(ifp); 1955 /* NB: only the fixed rate can change and that doesn't need a reset */ 1956 return (error == ENETRESET ? 0 : error); 1957 } 1958 1959 static int 1960 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1961 { 1962 struct iwn_vap *ivp = IWN_VAP(vap); 1963 struct ieee80211com *ic = vap->iv_ic; 1964 struct iwn_softc *sc = ic->ic_ifp->if_softc; 1965 int error; 1966 1967 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1968 ieee80211_state_name[vap->iv_state], 1969 ieee80211_state_name[nstate]); 1970 1971 callout_stop(&sc->sc_timer_to); 1972 1973 if (nstate == IEEE80211_S_AUTH && vap->iv_state != IEEE80211_S_AUTH) { 1974 /* !AUTH -> AUTH requires adapter config */ 1975 /* Reset state to handle reassociations correctly. */ 1976 sc->rxon.associd = 0; 1977 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1978 iwn_calib_reset(sc); 1979 error = iwn_auth(sc, vap); 1980 } 1981 if (nstate == IEEE80211_S_RUN && vap->iv_state != IEEE80211_S_RUN) { 1982 /* 1983 * !RUN -> RUN requires setting the association id 1984 * which is done with a firmware cmd. We also defer 1985 * starting the timers until that work is done. 1986 */ 1987 error = iwn_run(sc, vap); 1988 } 1989 if (nstate == IEEE80211_S_RUN) { 1990 /* 1991 * RUN -> RUN transition; just restart the timers. 1992 */ 1993 iwn_calib_reset(sc); 1994 } 1995 return ivp->iv_newstate(vap, nstate, arg); 1996 } 1997 1998 /* 1999 * Process an RX_PHY firmware notification. This is usually immediately 2000 * followed by an MPDU_RX_DONE notification. 2001 */ 2002 static void 2003 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2004 struct iwn_rx_data *data) 2005 { 2006 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2007 2008 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 2009 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2010 2011 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2012 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2013 sc->last_rx_valid = 1; 2014 } 2015 2016 static void 2017 iwn_timer_callout(void *arg) 2018 { 2019 struct iwn_softc *sc = arg; 2020 uint32_t flags = 0; 2021 2022 wlan_serialize_enter(); 2023 if (sc->calib_cnt && --sc->calib_cnt == 0) { 2024 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2025 "send statistics request"); 2026 (void) iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2027 sizeof flags, 1); 2028 sc->calib_cnt = 60; /* do calibration every 60s */ 2029 } 2030 iwn_watchdog(sc); /* NB: piggyback tx watchdog */ 2031 callout_reset(&sc->sc_timer_to, hz, iwn_timer_callout, sc); 2032 wlan_serialize_exit(); 2033 } 2034 2035 static void 2036 iwn_calib_reset(struct iwn_softc *sc) 2037 { 2038 callout_reset(&sc->sc_timer_to, hz, iwn_timer_callout, sc); 2039 sc->calib_cnt = 60; /* do calibration every 60s */ 2040 } 2041 2042 /* 2043 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2044 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2045 */ 2046 static void 2047 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2048 struct iwn_rx_data *data) 2049 { 2050 const struct iwn_hal *hal = sc->sc_hal; 2051 struct ifnet *ifp = sc->sc_ifp; 2052 struct ieee80211com *ic = ifp->if_l2com; 2053 struct iwn_rx_ring *ring = &sc->rxq; 2054 struct ieee80211_frame *wh; 2055 struct ieee80211_node *ni; 2056 struct mbuf *m, *m1; 2057 struct iwn_rx_stat *stat; 2058 caddr_t head; 2059 bus_addr_t paddr; 2060 uint32_t flags; 2061 int error, len, rssi, nf; 2062 2063 if (desc->type == IWN_MPDU_RX_DONE) { 2064 /* Check for prior RX_PHY notification. */ 2065 if (!sc->last_rx_valid) { 2066 DPRINTF(sc, IWN_DEBUG_ANY, 2067 "%s: missing RX_PHY\n", __func__); 2068 ifp->if_ierrors++; 2069 return; 2070 } 2071 sc->last_rx_valid = 0; 2072 stat = &sc->last_rx_stat; 2073 } else 2074 stat = (struct iwn_rx_stat *)(desc + 1); 2075 2076 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2077 2078 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2079 device_printf(sc->sc_dev, 2080 "%s: invalid rx statistic header, len %d\n", 2081 __func__, stat->cfg_phy_len); 2082 ifp->if_ierrors++; 2083 return; 2084 } 2085 if (desc->type == IWN_MPDU_RX_DONE) { 2086 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2087 head = (caddr_t)(mpdu + 1); 2088 len = le16toh(mpdu->len); 2089 } else { 2090 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2091 len = le16toh(stat->len); 2092 } 2093 2094 flags = le32toh(*(uint32_t *)(head + len)); 2095 2096 /* Discard frames with a bad FCS early. */ 2097 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2098 DPRINTF(sc, IWN_DEBUG_RECV, "%s: rx flags error %x\n", 2099 __func__, flags); 2100 ifp->if_ierrors++; 2101 return; 2102 } 2103 /* Discard frames that are too short. */ 2104 if (len < sizeof (*wh)) { 2105 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 2106 __func__, len); 2107 ifp->if_ierrors++; 2108 return; 2109 } 2110 2111 /* XXX don't need mbuf, just dma buffer */ 2112 m1 = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2113 if (m1 == NULL) { 2114 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 2115 __func__); 2116 ifp->if_ierrors++; 2117 return; 2118 } 2119 bus_dmamap_unload(ring->data_dmat, data->map); 2120 2121 error = bus_dmamap_load(ring->data_dmat, data->map, 2122 mtod(m1, caddr_t), MCLBYTES, 2123 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 2124 if (error != 0 && error != EFBIG) { 2125 device_printf(sc->sc_dev, 2126 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 2127 m_freem(m1); 2128 ifp->if_ierrors++; 2129 return; 2130 } 2131 2132 m = data->m; 2133 data->m = m1; 2134 /* Update RX descriptor. */ 2135 ring->desc[ring->cur] = htole32(paddr >> 8); 2136 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2137 BUS_DMASYNC_PREWRITE); 2138 2139 /* Finalize mbuf. */ 2140 m->m_pkthdr.rcvif = ifp; 2141 m->m_data = head; 2142 m->m_pkthdr.len = m->m_len = len; 2143 2144 rssi = hal->get_rssi(sc, stat); 2145 2146 /* Grab a reference to the source node. */ 2147 wh = mtod(m, struct ieee80211_frame *); 2148 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2149 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 2150 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 2151 2152 if (ieee80211_radiotap_active(ic)) { 2153 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2154 2155 tap->wr_tsft = htole64(stat->tstamp); 2156 tap->wr_flags = 0; 2157 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2158 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2159 switch (stat->rate) { 2160 /* CCK rates. */ 2161 case 10: tap->wr_rate = 2; break; 2162 case 20: tap->wr_rate = 4; break; 2163 case 55: tap->wr_rate = 11; break; 2164 case 110: tap->wr_rate = 22; break; 2165 /* OFDM rates. */ 2166 case 0xd: tap->wr_rate = 12; break; 2167 case 0xf: tap->wr_rate = 18; break; 2168 case 0x5: tap->wr_rate = 24; break; 2169 case 0x7: tap->wr_rate = 36; break; 2170 case 0x9: tap->wr_rate = 48; break; 2171 case 0xb: tap->wr_rate = 72; break; 2172 case 0x1: tap->wr_rate = 96; break; 2173 case 0x3: tap->wr_rate = 108; break; 2174 /* Unknown rate: should not happen. */ 2175 default: tap->wr_rate = 0; 2176 } 2177 tap->wr_dbm_antsignal = rssi; 2178 tap->wr_dbm_antnoise = nf; 2179 } 2180 2181 /* Send the frame to the 802.11 layer. */ 2182 if (ni != NULL) { 2183 (void) ieee80211_input(ni, m, rssi - nf, nf); 2184 /* Node is no longer needed. */ 2185 ieee80211_free_node(ni); 2186 } else { 2187 (void) ieee80211_input_all(ic, m, rssi - nf, nf); 2188 } 2189 } 2190 2191 #if 0 /* HT */ 2192 /* Process an incoming Compressed BlockAck. */ 2193 static void 2194 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2195 struct iwn_rx_data *data) 2196 { 2197 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2198 struct iwn_tx_ring *txq; 2199 2200 txq = &sc->txq[letoh16(ba->qid)]; 2201 /* XXX TBD */ 2202 } 2203 #endif 2204 2205 /* 2206 * Process a CALIBRATION_RESULT notification sent by the initialization 2207 * firmware on response to a CMD_CALIB_CONFIG command (5000 only.) 2208 */ 2209 static void 2210 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2211 struct iwn_rx_data *data) 2212 { 2213 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2214 int len, idx = -1; 2215 2216 /* Runtime firmware should not send such a notification. */ 2217 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2218 return; 2219 2220 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2221 len = (le32toh(desc->len) & 0x3fff) - 4; 2222 2223 switch (calib->code) { 2224 case IWN5000_PHY_CALIB_DC: 2225 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2226 sc->hw_type == IWN_HW_REV_TYPE_6050) 2227 idx = 0; 2228 break; 2229 case IWN5000_PHY_CALIB_LO: 2230 idx = 1; 2231 break; 2232 case IWN5000_PHY_CALIB_TX_IQ: 2233 idx = 2; 2234 break; 2235 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2236 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2237 sc->hw_type != IWN_HW_REV_TYPE_5150) 2238 idx = 3; 2239 break; 2240 case IWN5000_PHY_CALIB_BASE_BAND: 2241 idx = 4; 2242 break; 2243 } 2244 if (idx == -1) /* Ignore other results. */ 2245 return; 2246 2247 /* Save calibration result. */ 2248 if (sc->calibcmd[idx].buf != NULL) 2249 kfree(sc->calibcmd[idx].buf, M_DEVBUF); 2250 sc->calibcmd[idx].buf = kmalloc(len, M_DEVBUF, M_INTWAIT); 2251 if (sc->calibcmd[idx].buf == NULL) { 2252 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2253 "not enough memory for calibration result %d\n", 2254 calib->code); 2255 return; 2256 } 2257 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2258 "saving calibration result code=%d len=%d\n", calib->code, len); 2259 sc->calibcmd[idx].len = len; 2260 memcpy(sc->calibcmd[idx].buf, calib, len); 2261 } 2262 2263 /* 2264 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2265 * The latter is sent by the firmware after each received beacon. 2266 */ 2267 static void 2268 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2269 struct iwn_rx_data *data) 2270 { 2271 const struct iwn_hal *hal = sc->sc_hal; 2272 struct ifnet *ifp = sc->sc_ifp; 2273 struct ieee80211com *ic = ifp->if_l2com; 2274 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2275 struct iwn_calib_state *calib = &sc->calib; 2276 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2277 int temp; 2278 2279 /* Beacon stats are meaningful only when associated and not scanning. */ 2280 if (vap->iv_state != IEEE80211_S_RUN || 2281 (ic->ic_flags & IEEE80211_F_SCAN)) 2282 return; 2283 2284 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2285 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: cmd %d\n", __func__, desc->type); 2286 iwn_calib_reset(sc); /* Reset TX power calibration timeout. */ 2287 2288 /* Test if temperature has changed. */ 2289 if (stats->general.temp != sc->rawtemp) { 2290 /* Convert "raw" temperature to degC. */ 2291 sc->rawtemp = stats->general.temp; 2292 temp = hal->get_temperature(sc); 2293 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 2294 __func__, temp); 2295 2296 /* Update TX power if need be (4965AGN only.) */ 2297 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2298 iwn4965_power_calibration(sc, temp); 2299 } 2300 2301 if (desc->type != IWN_BEACON_STATISTICS) 2302 return; /* Reply to a statistics request. */ 2303 2304 sc->noise = iwn_get_noise(&stats->rx.general); 2305 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 2306 2307 /* Test that RSSI and noise are present in stats report. */ 2308 if (le32toh(stats->rx.general.flags) != 1) { 2309 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 2310 "received statistics without RSSI"); 2311 return; 2312 } 2313 2314 if (calib->state == IWN_CALIB_STATE_ASSOC) 2315 iwn_collect_noise(sc, &stats->rx.general); 2316 else if (calib->state == IWN_CALIB_STATE_RUN) 2317 iwn_tune_sensitivity(sc, &stats->rx); 2318 } 2319 2320 /* 2321 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2322 * and 5000 adapters have different incompatible TX status formats. 2323 */ 2324 static void 2325 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2326 struct iwn_rx_data *data) 2327 { 2328 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2329 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2330 2331 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2332 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2333 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2334 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2335 le32toh(stat->status)); 2336 2337 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2338 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2339 } 2340 2341 static void 2342 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2343 struct iwn_rx_data *data) 2344 { 2345 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2346 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2347 2348 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2349 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2350 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2351 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2352 le32toh(stat->status)); 2353 2354 #ifdef notyet 2355 /* Reset TX scheduler slot. */ 2356 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2357 #endif 2358 2359 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2360 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2361 } 2362 2363 /* 2364 * Adapter-independent backend for TX_DONE firmware notifications. 2365 */ 2366 static void 2367 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2368 uint8_t status) 2369 { 2370 struct ifnet *ifp = sc->sc_ifp; 2371 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2372 struct iwn_tx_data *data = &ring->data[desc->idx]; 2373 struct mbuf *m; 2374 struct ieee80211_node *ni; 2375 struct ieee80211vap *vap; 2376 2377 KASSERT(data->ni != NULL, ("no node")); 2378 2379 /* Unmap and free mbuf. */ 2380 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 2381 bus_dmamap_unload(ring->data_dmat, data->map); 2382 m = data->m, data->m = NULL; 2383 ni = data->ni, data->ni = NULL; 2384 vap = ni->ni_vap; 2385 2386 if (m->m_flags & M_TXCB) { 2387 /* 2388 * Channels marked for "radar" require traffic to be received 2389 * to unlock before we can transmit. Until traffic is seen 2390 * any attempt to transmit is returned immediately with status 2391 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 2392 * happen on first authenticate after scanning. To workaround 2393 * this we ignore a failure of this sort in AUTH state so the 2394 * 802.11 layer will fall back to using a timeout to wait for 2395 * the AUTH reply. This allows the firmware time to see 2396 * traffic so a subsequent retry of AUTH succeeds. It's 2397 * unclear why the firmware does not maintain state for 2398 * channels recently visited as this would allow immediate 2399 * use of the channel after a scan (where we see traffic). 2400 */ 2401 if (status == IWN_TX_FAIL_TX_LOCKED && 2402 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 2403 ieee80211_process_callback(ni, m, 0); 2404 else 2405 ieee80211_process_callback(ni, m, 2406 (status & IWN_TX_FAIL) != 0); 2407 } 2408 2409 /* 2410 * Update rate control statistics for the node. 2411 */ 2412 if (status & 0x80) { 2413 ifp->if_oerrors++; 2414 ieee80211_ratectl_tx_complete(vap, ni, 2415 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 2416 } else { 2417 ieee80211_ratectl_tx_complete(vap, ni, 2418 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 2419 } 2420 m_freem(m); 2421 ieee80211_free_node(ni); 2422 2423 sc->sc_tx_timer = 0; 2424 if (--ring->queued < IWN_TX_RING_LOMARK) { 2425 sc->qfullmsk &= ~(1 << ring->qid); 2426 if (sc->qfullmsk == 0 && 2427 (ifp->if_flags & IFF_OACTIVE)) { 2428 ifp->if_flags &= ~IFF_OACTIVE; 2429 iwn_start_locked(ifp); 2430 } 2431 } 2432 } 2433 2434 /* 2435 * Process a "command done" firmware notification. This is where we wakeup 2436 * processes waiting for a synchronous command completion. 2437 */ 2438 static void 2439 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2440 { 2441 struct iwn_tx_ring *ring = &sc->txq[4]; 2442 struct iwn_tx_data *data; 2443 2444 if ((desc->qid & 0xf) != 4) 2445 return; /* Not a command ack. */ 2446 2447 data = &ring->data[desc->idx]; 2448 2449 /* If the command was mapped in an mbuf, free it. */ 2450 if (data->m != NULL) { 2451 bus_dmamap_unload(ring->data_dmat, data->map); 2452 m_freem(data->m); 2453 data->m = NULL; 2454 } 2455 wakeup(&ring->desc[desc->idx]); 2456 } 2457 2458 /* 2459 * Process an INT_FH_RX or INT_SW_RX interrupt. 2460 */ 2461 static void 2462 iwn_notif_intr(struct iwn_softc *sc) 2463 { 2464 struct ifnet *ifp = sc->sc_ifp; 2465 struct ieee80211com *ic = ifp->if_l2com; 2466 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2467 uint16_t hw; 2468 2469 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 2470 BUS_DMASYNC_POSTREAD); 2471 2472 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2473 while (sc->rxq.cur != hw) { 2474 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2475 struct iwn_rx_desc *desc; 2476 2477 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2478 BUS_DMASYNC_POSTREAD); 2479 desc = mtod(data->m, struct iwn_rx_desc *); 2480 2481 DPRINTF(sc, IWN_DEBUG_RECV, 2482 "%s: qid %x idx %d flags %x type %d(%s) len %d\n", 2483 __func__, desc->qid & 0xf, desc->idx, desc->flags, 2484 desc->type, iwn_intr_str(desc->type), 2485 le16toh(desc->len)); 2486 2487 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2488 iwn_cmd_done(sc, desc); 2489 2490 switch (desc->type) { 2491 case IWN_RX_PHY: 2492 iwn_rx_phy(sc, desc, data); 2493 break; 2494 2495 case IWN_RX_DONE: /* 4965AGN only. */ 2496 case IWN_MPDU_RX_DONE: 2497 /* An 802.11 frame has been received. */ 2498 iwn_rx_done(sc, desc, data); 2499 break; 2500 2501 #if 0 /* HT */ 2502 case IWN_RX_COMPRESSED_BA: 2503 /* A Compressed BlockAck has been received. */ 2504 iwn_rx_compressed_ba(sc, desc, data); 2505 break; 2506 #endif 2507 2508 case IWN_TX_DONE: 2509 /* An 802.11 frame has been transmitted. */ 2510 sc->sc_hal->tx_done(sc, desc, data); 2511 break; 2512 2513 case IWN_RX_STATISTICS: 2514 case IWN_BEACON_STATISTICS: 2515 iwn_rx_statistics(sc, desc, data); 2516 break; 2517 2518 case IWN_BEACON_MISSED: 2519 { 2520 struct iwn_beacon_missed *miss = 2521 (struct iwn_beacon_missed *)(desc + 1); 2522 int misses; 2523 2524 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2525 BUS_DMASYNC_POSTREAD); 2526 misses = le32toh(miss->consecutive); 2527 2528 /* XXX not sure why we're notified w/ zero */ 2529 if (misses == 0) 2530 break; 2531 DPRINTF(sc, IWN_DEBUG_STATE, 2532 "%s: beacons missed %d/%d\n", __func__, 2533 misses, le32toh(miss->total)); 2534 2535 /* 2536 * If more than 5 consecutive beacons are missed, 2537 * reinitialize the sensitivity state machine. 2538 */ 2539 if (vap->iv_state == IEEE80211_S_RUN && misses > 5) 2540 (void) iwn_init_sensitivity(sc); 2541 if (misses >= vap->iv_bmissthreshold) 2542 ieee80211_beacon_miss(ic); 2543 break; 2544 } 2545 case IWN_UC_READY: 2546 { 2547 struct iwn_ucode_info *uc = 2548 (struct iwn_ucode_info *)(desc + 1); 2549 2550 /* The microcontroller is ready. */ 2551 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2552 BUS_DMASYNC_POSTREAD); 2553 DPRINTF(sc, IWN_DEBUG_RESET, 2554 "microcode alive notification version=%d.%d " 2555 "subtype=%x alive=%x\n", uc->major, uc->minor, 2556 uc->subtype, le32toh(uc->valid)); 2557 2558 if (le32toh(uc->valid) != 1) { 2559 device_printf(sc->sc_dev, 2560 "microcontroller initialization failed"); 2561 break; 2562 } 2563 if (uc->subtype == IWN_UCODE_INIT) { 2564 /* Save microcontroller report. */ 2565 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2566 } 2567 /* Save the address of the error log in SRAM. */ 2568 sc->errptr = le32toh(uc->errptr); 2569 break; 2570 } 2571 case IWN_STATE_CHANGED: 2572 { 2573 uint32_t *status = (uint32_t *)(desc + 1); 2574 2575 /* 2576 * State change allows hardware switch change to be 2577 * noted. However, we handle this in iwn_intr as we 2578 * get both the enable/disble intr. 2579 */ 2580 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2581 BUS_DMASYNC_POSTREAD); 2582 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n", 2583 le32toh(*status)); 2584 break; 2585 } 2586 case IWN_START_SCAN: 2587 { 2588 struct iwn_start_scan *scan = 2589 (struct iwn_start_scan *)(desc + 1); 2590 2591 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2592 BUS_DMASYNC_POSTREAD); 2593 DPRINTF(sc, IWN_DEBUG_ANY, 2594 "%s: scanning channel %d status %x\n", 2595 __func__, scan->chan, le32toh(scan->status)); 2596 break; 2597 } 2598 case IWN_STOP_SCAN: 2599 { 2600 struct iwn_stop_scan *scan = 2601 (struct iwn_stop_scan *)(desc + 1); 2602 2603 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2604 BUS_DMASYNC_POSTREAD); 2605 DPRINTF(sc, IWN_DEBUG_STATE, 2606 "scan finished nchan=%d status=%d chan=%d\n", 2607 scan->nchan, scan->status, scan->chan); 2608 2609 ieee80211_scan_next(vap); 2610 break; 2611 } 2612 case IWN5000_CALIBRATION_RESULT: 2613 iwn5000_rx_calib_results(sc, desc, data); 2614 break; 2615 2616 case IWN5000_CALIBRATION_DONE: 2617 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2618 wakeup(sc); 2619 break; 2620 } 2621 2622 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2623 } 2624 2625 /* Tell the firmware what we have processed. */ 2626 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2627 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2628 } 2629 2630 /* 2631 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2632 * from power-down sleep mode. 2633 */ 2634 static void 2635 iwn_wakeup_intr(struct iwn_softc *sc) 2636 { 2637 int qid; 2638 2639 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 2640 __func__); 2641 2642 /* Wakeup RX and TX rings. */ 2643 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2644 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) { 2645 struct iwn_tx_ring *ring = &sc->txq[qid]; 2646 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2647 } 2648 } 2649 2650 static void 2651 iwn_rftoggle_intr(struct iwn_softc *sc) 2652 { 2653 struct ifnet *ifp = sc->sc_ifp; 2654 struct ieee80211com *ic = ifp->if_l2com; 2655 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 2656 2657 device_printf(sc->sc_dev, "RF switch: radio %s\n", 2658 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2659 if (tmp & IWN_GP_CNTRL_RFKILL) 2660 ieee80211_runtask(ic, &sc->sc_radioon_task); 2661 else 2662 ieee80211_runtask(ic, &sc->sc_radiooff_task); 2663 } 2664 2665 /* 2666 * Dump the error log of the firmware when a firmware panic occurs. Although 2667 * we can't debug the firmware because it is neither open source nor free, it 2668 * can help us to identify certain classes of problems. 2669 */ 2670 static void 2671 iwn_fatal_intr(struct iwn_softc *sc) 2672 { 2673 const struct iwn_hal *hal = sc->sc_hal; 2674 struct iwn_fw_dump dump; 2675 int i; 2676 2677 /* Force a complete recalibration on next init. */ 2678 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2679 2680 /* Check that the error log address is valid. */ 2681 if (sc->errptr < IWN_FW_DATA_BASE || 2682 sc->errptr + sizeof (dump) > 2683 IWN_FW_DATA_BASE + hal->fw_data_maxsz) { 2684 kprintf("%s: bad firmware error log address 0x%08x\n", 2685 __func__, sc->errptr); 2686 return; 2687 } 2688 if (iwn_nic_lock(sc) != 0) { 2689 kprintf("%s: could not read firmware error log\n", 2690 __func__); 2691 return; 2692 } 2693 /* Read firmware error log from SRAM. */ 2694 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2695 sizeof (dump) / sizeof (uint32_t)); 2696 iwn_nic_unlock(sc); 2697 2698 if (dump.valid == 0) { 2699 kprintf("%s: firmware error log is empty\n", 2700 __func__); 2701 return; 2702 } 2703 kprintf("firmware error log:\n"); 2704 kprintf(" error type = \"%s\" (0x%08X)\n", 2705 (dump.id < nitems(iwn_fw_errmsg)) ? 2706 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2707 dump.id); 2708 kprintf(" program counter = 0x%08X\n", dump.pc); 2709 kprintf(" source line = 0x%08X\n", dump.src_line); 2710 kprintf(" error data = 0x%08X%08X\n", 2711 dump.error_data[0], dump.error_data[1]); 2712 kprintf(" branch link = 0x%08X%08X\n", 2713 dump.branch_link[0], dump.branch_link[1]); 2714 kprintf(" interrupt link = 0x%08X%08X\n", 2715 dump.interrupt_link[0], dump.interrupt_link[1]); 2716 kprintf(" time = %u\n", dump.time[0]); 2717 2718 /* Dump driver status (TX and RX rings) while we're here. */ 2719 kprintf("driver status:\n"); 2720 for (i = 0; i < hal->ntxqs; i++) { 2721 struct iwn_tx_ring *ring = &sc->txq[i]; 2722 kprintf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2723 i, ring->qid, ring->cur, ring->queued); 2724 } 2725 kprintf(" rx ring: cur=%d\n", sc->rxq.cur); 2726 } 2727 2728 static void 2729 iwn_intr(void *arg) 2730 { 2731 struct iwn_softc *sc = arg; 2732 struct ifnet *ifp = sc->sc_ifp; 2733 uint32_t r1, r2, tmp; 2734 2735 /* Disable interrupts. */ 2736 IWN_WRITE(sc, IWN_INT_MASK, 0); 2737 2738 /* Read interrupts from ICT (fast) or from registers (slow). */ 2739 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2740 tmp = 0; 2741 while (sc->ict[sc->ict_cur] != 0) { 2742 tmp |= sc->ict[sc->ict_cur]; 2743 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2744 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2745 } 2746 tmp = le32toh(tmp); 2747 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2748 tmp = 0; 2749 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2750 tmp |= 0x8000; 2751 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2752 r2 = 0; /* Unused. */ 2753 } else { 2754 r1 = IWN_READ(sc, IWN_INT); 2755 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2756 return; /* Hardware gone! */ 2757 r2 = IWN_READ(sc, IWN_FH_INT); 2758 } 2759 2760 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2); 2761 2762 if (r1 == 0 && r2 == 0) 2763 goto done; /* Interrupt not for us. */ 2764 2765 /* Acknowledge interrupts. */ 2766 IWN_WRITE(sc, IWN_INT, r1); 2767 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2768 IWN_WRITE(sc, IWN_FH_INT, r2); 2769 2770 if (r1 & IWN_INT_RF_TOGGLED) { 2771 iwn_rftoggle_intr(sc); 2772 goto done; 2773 } 2774 if (r1 & IWN_INT_CT_REACHED) { 2775 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 2776 __func__); 2777 } 2778 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2779 iwn_fatal_intr(sc); 2780 ifp->if_flags &= ~IFF_UP; 2781 iwn_stop_locked(sc); 2782 goto done; 2783 } 2784 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2785 (r2 & IWN_FH_INT_RX)) { 2786 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2787 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2788 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2789 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2790 IWN_INT_PERIODIC_DIS); 2791 iwn_notif_intr(sc); 2792 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2793 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2794 IWN_INT_PERIODIC_ENA); 2795 } 2796 } else 2797 iwn_notif_intr(sc); 2798 } 2799 2800 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2801 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2802 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2803 wakeup(sc); /* FH DMA transfer completed. */ 2804 } 2805 2806 if (r1 & IWN_INT_ALIVE) 2807 wakeup(sc); /* Firmware is alive. */ 2808 2809 if (r1 & IWN_INT_WAKEUP) 2810 iwn_wakeup_intr(sc); 2811 2812 done: 2813 /* Re-enable interrupts. */ 2814 if (ifp->if_flags & IFF_UP) 2815 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2816 } 2817 2818 /* 2819 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2820 * 5000 adapters use a slightly different format.) 2821 */ 2822 static void 2823 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2824 uint16_t len) 2825 { 2826 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2827 2828 *w = htole16(len + 8); 2829 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2830 BUS_DMASYNC_PREWRITE); 2831 if (idx < IWN_SCHED_WINSZ) { 2832 *(w + IWN_TX_RING_COUNT) = *w; 2833 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2834 BUS_DMASYNC_PREWRITE); 2835 } 2836 } 2837 2838 static void 2839 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2840 uint16_t len) 2841 { 2842 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2843 2844 *w = htole16(id << 12 | (len + 8)); 2845 2846 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2847 BUS_DMASYNC_PREWRITE); 2848 if (idx < IWN_SCHED_WINSZ) { 2849 *(w + IWN_TX_RING_COUNT) = *w; 2850 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2851 BUS_DMASYNC_PREWRITE); 2852 } 2853 } 2854 2855 #ifdef notyet 2856 static void 2857 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2858 { 2859 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2860 2861 *w = (*w & htole16(0xf000)) | htole16(1); 2862 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2863 BUS_DMASYNC_PREWRITE); 2864 if (idx < IWN_SCHED_WINSZ) { 2865 *(w + IWN_TX_RING_COUNT) = *w; 2866 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2867 BUS_DMASYNC_PREWRITE); 2868 } 2869 } 2870 #endif 2871 2872 static uint8_t 2873 iwn_plcp_signal(int rate) { 2874 int i; 2875 2876 for (i = 0; i < IWN_RIDX_MAX + 1; i++) { 2877 if (rate == iwn_rates[i].rate) 2878 return i; 2879 } 2880 2881 return 0; 2882 } 2883 2884 static int 2885 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2886 struct iwn_tx_ring *ring) 2887 { 2888 const struct iwn_hal *hal = sc->sc_hal; 2889 const struct ieee80211_txparam *tp; 2890 const struct iwn_rate *rinfo; 2891 struct ieee80211vap *vap = ni->ni_vap; 2892 struct ieee80211com *ic = ni->ni_ic; 2893 struct iwn_node *wn = (void *)ni; 2894 struct iwn_tx_desc *desc; 2895 struct iwn_tx_data *data; 2896 struct iwn_tx_cmd *cmd; 2897 struct iwn_cmd_data *tx; 2898 struct ieee80211_frame *wh; 2899 struct ieee80211_key *k = NULL; 2900 struct mbuf *mnew; 2901 bus_dma_segment_t segs[IWN_MAX_SCATTER]; 2902 uint32_t flags; 2903 u_int hdrlen; 2904 int totlen, error, pad, nsegs = 0, i, rate; 2905 uint8_t ridx, type, txant; 2906 2907 wh = mtod(m, struct ieee80211_frame *); 2908 hdrlen = ieee80211_anyhdrsize(wh); 2909 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2910 2911 desc = &ring->desc[ring->cur]; 2912 data = &ring->data[ring->cur]; 2913 2914 /* Choose a TX rate index. */ 2915 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 2916 if (type == IEEE80211_FC0_TYPE_MGT) 2917 rate = tp->mgmtrate; 2918 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2919 rate = tp->mcastrate; 2920 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2921 rate = tp->ucastrate; 2922 else { 2923 /* XXX pass pktlen */ 2924 ieee80211_ratectl_rate(ni, NULL, 0); 2925 2926 rate = ni->ni_txrate; 2927 } 2928 ridx = iwn_plcp_signal(rate); 2929 rinfo = &iwn_rates[ridx]; 2930 2931 /* Encrypt the frame if need be. */ 2932 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2933 k = ieee80211_crypto_encap(ni, m); 2934 if (k == NULL) { 2935 m_freem(m); 2936 return ENOBUFS; 2937 } 2938 /* Packet header may have moved, reset our local pointer. */ 2939 wh = mtod(m, struct ieee80211_frame *); 2940 } 2941 totlen = m->m_pkthdr.len; 2942 2943 if (ieee80211_radiotap_active_vap(vap)) { 2944 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2945 2946 tap->wt_flags = 0; 2947 tap->wt_rate = rinfo->rate; 2948 if (k != NULL) 2949 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2950 2951 ieee80211_radiotap_tx(vap, m); 2952 } 2953 2954 /* Prepare TX firmware command. */ 2955 cmd = &ring->cmd[ring->cur]; 2956 cmd->code = IWN_CMD_TX_DATA; 2957 cmd->flags = 0; 2958 cmd->qid = ring->qid; 2959 cmd->idx = ring->cur; 2960 2961 tx = (struct iwn_cmd_data *)cmd->data; 2962 /* NB: No need to clear tx, all fields are reinitialized here. */ 2963 tx->scratch = 0; /* clear "scratch" area */ 2964 2965 flags = 0; 2966 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) 2967 flags |= IWN_TX_NEED_ACK; 2968 if ((wh->i_fc[0] & 2969 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2970 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2971 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2972 2973 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2974 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2975 2976 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2977 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2978 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2979 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 2980 flags |= IWN_TX_NEED_RTS; 2981 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2982 ridx >= IWN_RIDX_OFDM6) { 2983 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2984 flags |= IWN_TX_NEED_CTS; 2985 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2986 flags |= IWN_TX_NEED_RTS; 2987 } 2988 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2989 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2990 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2991 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2992 flags |= IWN_TX_NEED_PROTECTION; 2993 } else 2994 flags |= IWN_TX_FULL_TXOP; 2995 } 2996 } 2997 2998 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2999 type != IEEE80211_FC0_TYPE_DATA) 3000 tx->id = hal->broadcast_id; 3001 else 3002 tx->id = wn->id; 3003 3004 if (type == IEEE80211_FC0_TYPE_MGT) { 3005 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3006 3007 /* Tell HW to set timestamp in probe responses. */ 3008 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3009 flags |= IWN_TX_INSERT_TSTAMP; 3010 3011 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3012 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3013 tx->timeout = htole16(3); 3014 else 3015 tx->timeout = htole16(2); 3016 } else 3017 tx->timeout = htole16(0); 3018 3019 if (hdrlen & 3) { 3020 /* First segment length must be a multiple of 4. */ 3021 flags |= IWN_TX_NEED_PADDING; 3022 pad = 4 - (hdrlen & 3); 3023 } else 3024 pad = 0; 3025 3026 tx->len = htole16(totlen); 3027 tx->tid = 0; 3028 tx->rts_ntries = 60; 3029 tx->data_ntries = 15; 3030 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3031 tx->plcp = rinfo->plcp; 3032 tx->rflags = rinfo->flags; 3033 if (tx->id == hal->broadcast_id) { 3034 /* Group or management frame. */ 3035 tx->linkq = 0; 3036 /* XXX Alternate between antenna A and B? */ 3037 txant = IWN_LSB(sc->txchainmask); 3038 tx->rflags |= IWN_RFLAG_ANT(txant); 3039 } else { 3040 tx->linkq = IWN_RIDX_OFDM54 - ridx; 3041 flags |= IWN_TX_LINKQ; /* enable MRR */ 3042 } 3043 3044 /* Set physical address of "scratch area". */ 3045 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3046 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3047 3048 /* Copy 802.11 header in TX command. */ 3049 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3050 3051 /* Trim 802.11 header. */ 3052 m_adj(m, hdrlen); 3053 tx->security = 0; 3054 tx->flags = htole32(flags); 3055 3056 if (m->m_len > 0) { 3057 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map, 3058 m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT); 3059 if (error == EFBIG) { 3060 /* too many fragments, linearize */ 3061 mnew = m_defrag(m, MB_DONTWAIT); 3062 if (mnew == NULL) { 3063 device_printf(sc->sc_dev, 3064 "%s: could not defrag mbuf\n", __func__); 3065 m_freem(m); 3066 return ENOBUFS; 3067 } 3068 m = mnew; 3069 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, 3070 data->map, m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT); 3071 } 3072 if (error != 0) { 3073 device_printf(sc->sc_dev, 3074 "%s: bus_dmamap_load_mbuf_segment failed, error %d\n", 3075 __func__, error); 3076 m_freem(m); 3077 return error; 3078 } 3079 } 3080 3081 data->m = m; 3082 data->ni = ni; 3083 3084 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3085 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3086 3087 /* Fill TX descriptor. */ 3088 desc->nsegs = 1 + nsegs; 3089 /* First DMA segment is used by the TX command. */ 3090 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3091 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3092 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3093 /* Other DMA segments are for data payload. */ 3094 for (i = 1; i <= nsegs; i++) { 3095 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr)); 3096 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) | 3097 segs[i - 1].ds_len << 4); 3098 } 3099 3100 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3101 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3102 BUS_DMASYNC_PREWRITE); 3103 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3104 BUS_DMASYNC_PREWRITE); 3105 3106 #ifdef notyet 3107 /* Update TX scheduler. */ 3108 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3109 #endif 3110 3111 /* Kick TX ring. */ 3112 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3113 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3114 3115 /* Mark TX ring as full if we reach a certain threshold. */ 3116 if (++ring->queued > IWN_TX_RING_HIMARK) 3117 sc->qfullmsk |= 1 << ring->qid; 3118 3119 return 0; 3120 } 3121 3122 static int 3123 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3124 struct ieee80211_node *ni, struct iwn_tx_ring *ring, 3125 const struct ieee80211_bpf_params *params) 3126 { 3127 const struct iwn_hal *hal = sc->sc_hal; 3128 const struct iwn_rate *rinfo; 3129 struct ifnet *ifp = sc->sc_ifp; 3130 struct ieee80211vap *vap = ni->ni_vap; 3131 struct ieee80211com *ic = ifp->if_l2com; 3132 struct iwn_tx_cmd *cmd; 3133 struct iwn_cmd_data *tx; 3134 struct ieee80211_frame *wh; 3135 struct iwn_tx_desc *desc; 3136 struct iwn_tx_data *data; 3137 struct mbuf *mnew; 3138 bus_addr_t paddr; 3139 bus_dma_segment_t segs[IWN_MAX_SCATTER]; 3140 uint32_t flags; 3141 u_int hdrlen; 3142 int totlen, error, pad, nsegs = 0, i, rate; 3143 uint8_t ridx, type, txant; 3144 3145 wh = mtod(m, struct ieee80211_frame *); 3146 hdrlen = ieee80211_anyhdrsize(wh); 3147 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3148 3149 desc = &ring->desc[ring->cur]; 3150 data = &ring->data[ring->cur]; 3151 3152 /* Choose a TX rate index. */ 3153 rate = params->ibp_rate0; 3154 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3155 /* XXX fall back to mcast/mgmt rate? */ 3156 m_freem(m); 3157 return EINVAL; 3158 } 3159 ridx = iwn_plcp_signal(rate); 3160 rinfo = &iwn_rates[ridx]; 3161 3162 totlen = m->m_pkthdr.len; 3163 3164 /* Prepare TX firmware command. */ 3165 cmd = &ring->cmd[ring->cur]; 3166 cmd->code = IWN_CMD_TX_DATA; 3167 cmd->flags = 0; 3168 cmd->qid = ring->qid; 3169 cmd->idx = ring->cur; 3170 3171 tx = (struct iwn_cmd_data *)cmd->data; 3172 /* NB: No need to clear tx, all fields are reinitialized here. */ 3173 tx->scratch = 0; /* clear "scratch" area */ 3174 3175 flags = 0; 3176 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 3177 flags |= IWN_TX_NEED_ACK; 3178 if (params->ibp_flags & IEEE80211_BPF_RTS) { 3179 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3180 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3181 flags &= ~IWN_TX_NEED_RTS; 3182 flags |= IWN_TX_NEED_PROTECTION; 3183 } else 3184 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 3185 } 3186 if (params->ibp_flags & IEEE80211_BPF_CTS) { 3187 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3188 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3189 flags &= ~IWN_TX_NEED_CTS; 3190 flags |= IWN_TX_NEED_PROTECTION; 3191 } else 3192 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 3193 } 3194 if (type == IEEE80211_FC0_TYPE_MGT) { 3195 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3196 3197 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3198 flags |= IWN_TX_INSERT_TSTAMP; 3199 3200 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3201 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3202 tx->timeout = htole16(3); 3203 else 3204 tx->timeout = htole16(2); 3205 } else 3206 tx->timeout = htole16(0); 3207 3208 if (hdrlen & 3) { 3209 /* First segment length must be a multiple of 4. */ 3210 flags |= IWN_TX_NEED_PADDING; 3211 pad = 4 - (hdrlen & 3); 3212 } else 3213 pad = 0; 3214 3215 if (ieee80211_radiotap_active_vap(vap)) { 3216 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3217 3218 tap->wt_flags = 0; 3219 tap->wt_rate = rate; 3220 3221 ieee80211_radiotap_tx(vap, m); 3222 } 3223 3224 tx->len = htole16(totlen); 3225 tx->tid = 0; 3226 tx->id = hal->broadcast_id; 3227 tx->rts_ntries = params->ibp_try1; 3228 tx->data_ntries = params->ibp_try0; 3229 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3230 tx->plcp = rinfo->plcp; 3231 tx->rflags = rinfo->flags; 3232 /* Group or management frame. */ 3233 tx->linkq = 0; 3234 txant = IWN_LSB(sc->txchainmask); 3235 tx->rflags |= IWN_RFLAG_ANT(txant); 3236 /* Set physical address of "scratch area". */ 3237 paddr = ring->cmd_dma.paddr + ring->cur * sizeof (struct iwn_tx_cmd); 3238 tx->loaddr = htole32(IWN_LOADDR(paddr)); 3239 tx->hiaddr = IWN_HIADDR(paddr); 3240 3241 /* Copy 802.11 header in TX command. */ 3242 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3243 3244 /* Trim 802.11 header. */ 3245 m_adj(m, hdrlen); 3246 tx->security = 0; 3247 tx->flags = htole32(flags); 3248 3249 if (m->m_len > 0) { 3250 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map, 3251 m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT); 3252 if (error == EFBIG) { 3253 /* Too many fragments, linearize. */ 3254 mnew = m_defrag(m, MB_DONTWAIT); 3255 if (mnew == NULL) { 3256 device_printf(sc->sc_dev, 3257 "%s: could not defrag mbuf\n", __func__); 3258 m_freem(m); 3259 return ENOBUFS; 3260 } 3261 m = mnew; 3262 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, 3263 data->map, m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT); 3264 } 3265 if (error != 0) { 3266 device_printf(sc->sc_dev, 3267 "%s: bus_dmamap_load_mbuf_segment failed, error %d\n", 3268 __func__, error); 3269 m_freem(m); 3270 return error; 3271 } 3272 } 3273 3274 data->m = m; 3275 data->ni = ni; 3276 3277 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3278 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3279 3280 /* Fill TX descriptor. */ 3281 desc->nsegs = 1 + nsegs; 3282 /* First DMA segment is used by the TX command. */ 3283 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3284 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3285 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3286 /* Other DMA segments are for data payload. */ 3287 for (i = 1; i <= nsegs; i++) { 3288 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr)); 3289 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) | 3290 segs[i - 1].ds_len << 4); 3291 } 3292 3293 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3294 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3295 BUS_DMASYNC_PREWRITE); 3296 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3297 BUS_DMASYNC_PREWRITE); 3298 3299 #ifdef notyet 3300 /* Update TX scheduler. */ 3301 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3302 #endif 3303 3304 /* Kick TX ring. */ 3305 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3306 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3307 3308 /* Mark TX ring as full if we reach a certain threshold. */ 3309 if (++ring->queued > IWN_TX_RING_HIMARK) 3310 sc->qfullmsk |= 1 << ring->qid; 3311 3312 return 0; 3313 } 3314 3315 static int 3316 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3317 const struct ieee80211_bpf_params *params) 3318 { 3319 struct ieee80211com *ic = ni->ni_ic; 3320 struct ifnet *ifp = ic->ic_ifp; 3321 struct iwn_softc *sc = ifp->if_softc; 3322 struct iwn_tx_ring *txq; 3323 int error = 0; 3324 3325 if ((ifp->if_flags & IFF_RUNNING) == 0) { 3326 ieee80211_free_node(ni); 3327 m_freem(m); 3328 return ENETDOWN; 3329 } 3330 3331 if (params == NULL) 3332 txq = &sc->txq[M_WME_GETAC(m)]; 3333 else 3334 txq = &sc->txq[params->ibp_pri & 3]; 3335 3336 if (params == NULL) { 3337 /* 3338 * Legacy path; interpret frame contents to decide 3339 * precisely how to send the frame. 3340 */ 3341 error = iwn_tx_data(sc, m, ni, txq); 3342 } else { 3343 /* 3344 * Caller supplied explicit parameters to use in 3345 * sending the frame. 3346 */ 3347 error = iwn_tx_data_raw(sc, m, ni, txq, params); 3348 } 3349 if (error != 0) { 3350 /* NB: m is reclaimed on tx failure */ 3351 ieee80211_free_node(ni); 3352 ifp->if_oerrors++; 3353 } 3354 return error; 3355 } 3356 3357 static void 3358 iwn_start(struct ifnet *ifp) 3359 { 3360 struct iwn_softc *sc; 3361 3362 sc = ifp->if_softc; 3363 3364 iwn_start_locked(ifp); 3365 } 3366 3367 static void 3368 iwn_start_locked(struct ifnet *ifp) 3369 { 3370 struct iwn_softc *sc = ifp->if_softc; 3371 struct ieee80211_node *ni; 3372 struct iwn_tx_ring *txq; 3373 struct mbuf *m; 3374 int pri; 3375 3376 for (;;) { 3377 if (sc->qfullmsk != 0) { 3378 ifp->if_flags |= IFF_OACTIVE; 3379 break; 3380 } 3381 m = ifq_dequeue(&ifp->if_snd, NULL); 3382 if (m == NULL) 3383 break; 3384 KKASSERT(M_TRAILINGSPACE(m) >= 0); 3385 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3386 pri = M_WME_GETAC(m); 3387 txq = &sc->txq[pri]; 3388 if (iwn_tx_data(sc, m, ni, txq) != 0) { 3389 ifp->if_oerrors++; 3390 ieee80211_free_node(ni); 3391 break; 3392 } 3393 sc->sc_tx_timer = 5; 3394 } 3395 } 3396 3397 static void 3398 iwn_watchdog(struct iwn_softc *sc) 3399 { 3400 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 3401 struct ifnet *ifp = sc->sc_ifp; 3402 struct ieee80211com *ic = ifp->if_l2com; 3403 3404 if_printf(ifp, "device timeout\n"); 3405 ieee80211_runtask(ic, &sc->sc_reinit_task); 3406 } 3407 } 3408 3409 static int 3410 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred) 3411 { 3412 struct iwn_softc *sc = ifp->if_softc; 3413 struct ieee80211com *ic = ifp->if_l2com; 3414 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3415 struct ifreq *ifr = (struct ifreq *) data; 3416 int error = 0, startall = 0, stop = 0; 3417 3418 switch (cmd) { 3419 case SIOCSIFFLAGS: 3420 if (ifp->if_flags & IFF_UP) { 3421 if (!(ifp->if_flags & IFF_RUNNING)) { 3422 iwn_init_locked(sc); 3423 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 3424 startall = 1; 3425 else 3426 stop = 1; 3427 } 3428 } else { 3429 if (ifp->if_flags & IFF_RUNNING) 3430 iwn_stop_locked(sc); 3431 } 3432 if (startall) 3433 ieee80211_start_all(ic); 3434 else if (vap != NULL && stop) 3435 ieee80211_stop(vap); 3436 break; 3437 case SIOCGIFMEDIA: 3438 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 3439 break; 3440 case SIOCGIFADDR: 3441 error = ether_ioctl(ifp, cmd, data); 3442 break; 3443 default: 3444 error = EINVAL; 3445 break; 3446 } 3447 return error; 3448 } 3449 3450 /* 3451 * Send a command to the firmware. 3452 */ 3453 static int 3454 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3455 { 3456 struct iwn_tx_ring *ring = &sc->txq[4]; 3457 struct iwn_tx_desc *desc; 3458 struct iwn_tx_data *data; 3459 struct iwn_tx_cmd *cmd; 3460 struct mbuf *m; 3461 bus_addr_t paddr; 3462 int totlen, error; 3463 3464 desc = &ring->desc[ring->cur]; 3465 data = &ring->data[ring->cur]; 3466 totlen = 4 + size; 3467 3468 if (size > sizeof cmd->data) { 3469 /* Command is too large to fit in a descriptor. */ 3470 if (totlen > MCLBYTES) 3471 return EINVAL; 3472 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 3473 if (m == NULL) 3474 return ENOMEM; 3475 cmd = mtod(m, struct iwn_tx_cmd *); 3476 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 3477 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3478 if (error != 0) { 3479 m_freem(m); 3480 return error; 3481 } 3482 data->m = m; 3483 } else { 3484 cmd = &ring->cmd[ring->cur]; 3485 paddr = data->cmd_paddr; 3486 } 3487 3488 cmd->code = code; 3489 cmd->flags = 0; 3490 cmd->qid = ring->qid; 3491 cmd->idx = ring->cur; 3492 memcpy(cmd->data, buf, size); 3493 3494 desc->nsegs = 1; 3495 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3496 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3497 3498 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 3499 __func__, iwn_intr_str(cmd->code), cmd->code, 3500 cmd->flags, cmd->qid, cmd->idx); 3501 3502 if (size > sizeof cmd->data) { 3503 bus_dmamap_sync(ring->data_dmat, data->map, 3504 BUS_DMASYNC_PREWRITE); 3505 } else { 3506 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3507 BUS_DMASYNC_PREWRITE); 3508 } 3509 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3510 BUS_DMASYNC_PREWRITE); 3511 3512 #ifdef notyet 3513 /* Update TX scheduler. */ 3514 sc->sc_hal->update_sched(sc, ring->qid, ring->cur, 0, 0); 3515 #endif 3516 3517 /* Kick command ring. */ 3518 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3519 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3520 3521 if (async) 3522 error = 0; 3523 else 3524 error = zsleep(desc, &wlan_global_serializer, 0, "iwncmd", hz); 3525 return error; 3526 } 3527 3528 static int 3529 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3530 { 3531 struct iwn4965_node_info hnode; 3532 caddr_t src, dst; 3533 3534 /* 3535 * We use the node structure for 5000 Series internally (it is 3536 * a superset of the one for 4965AGN). We thus copy the common 3537 * fields before sending the command. 3538 */ 3539 src = (caddr_t)node; 3540 dst = (caddr_t)&hnode; 3541 memcpy(dst, src, 48); 3542 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3543 memcpy(dst + 48, src + 72, 20); 3544 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3545 } 3546 3547 static int 3548 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3549 { 3550 /* Direct mapping. */ 3551 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3552 } 3553 3554 #if 0 /* HT */ 3555 static const uint8_t iwn_ridx_to_plcp[] = { 3556 10, 20, 55, 110, /* CCK */ 3557 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 0x3 /* OFDM R1-R4 */ 3558 }; 3559 static const uint8_t iwn_siso_mcs_to_plcp[] = { 3560 0, 0, 0, 0, /* CCK */ 3561 0, 0, 1, 2, 3, 4, 5, 6, 7 /* HT */ 3562 }; 3563 static const uint8_t iwn_mimo_mcs_to_plcp[] = { 3564 0, 0, 0, 0, /* CCK */ 3565 8, 8, 9, 10, 11, 12, 13, 14, 15 /* HT */ 3566 }; 3567 #endif 3568 static const uint8_t iwn_prev_ridx[] = { 3569 /* NB: allow fallback from CCK11 to OFDM9 and from OFDM6 to CCK5 */ 3570 0, 0, 1, 5, /* CCK */ 3571 2, 4, 3, 6, 7, 8, 9, 10, 10 /* OFDM */ 3572 }; 3573 3574 /* 3575 * Configure hardware link parameters for the specified 3576 * node operating on the specified channel. 3577 */ 3578 static int 3579 iwn_set_link_quality(struct iwn_softc *sc, uint8_t id, int async) 3580 { 3581 struct ifnet *ifp = sc->sc_ifp; 3582 struct ieee80211com *ic = ifp->if_l2com; 3583 struct iwn_cmd_link_quality linkq; 3584 const struct iwn_rate *rinfo; 3585 int i; 3586 uint8_t txant, ridx; 3587 3588 /* Use the first valid TX antenna. */ 3589 txant = IWN_LSB(sc->txchainmask); 3590 3591 memset(&linkq, 0, sizeof linkq); 3592 linkq.id = id; 3593 linkq.antmsk_1stream = txant; 3594 linkq.antmsk_2stream = IWN_ANT_AB; 3595 linkq.ampdu_max = 31; 3596 linkq.ampdu_threshold = 3; 3597 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3598 3599 #if 0 /* HT */ 3600 if (IEEE80211_IS_CHAN_HT(c)) 3601 linkq.mimo = 1; 3602 #endif 3603 3604 if (id == IWN_ID_BSS) 3605 ridx = IWN_RIDX_OFDM54; 3606 else if (IEEE80211_IS_CHAN_A(ic->ic_curchan)) 3607 ridx = IWN_RIDX_OFDM6; 3608 else 3609 ridx = IWN_RIDX_CCK1; 3610 3611 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3612 rinfo = &iwn_rates[ridx]; 3613 #if 0 /* HT */ 3614 if (IEEE80211_IS_CHAN_HT40(c)) { 3615 linkq.retry[i].plcp = iwn_mimo_mcs_to_plcp[ridx] 3616 | IWN_RIDX_MCS; 3617 linkq.retry[i].rflags = IWN_RFLAG_HT 3618 | IWN_RFLAG_HT40; 3619 /* XXX shortGI */ 3620 } else if (IEEE80211_IS_CHAN_HT(c)) { 3621 linkq.retry[i].plcp = iwn_siso_mcs_to_plcp[ridx] 3622 | IWN_RIDX_MCS; 3623 linkq.retry[i].rflags = IWN_RFLAG_HT; 3624 /* XXX shortGI */ 3625 } else 3626 #endif 3627 { 3628 linkq.retry[i].plcp = rinfo->plcp; 3629 linkq.retry[i].rflags = rinfo->flags; 3630 } 3631 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3632 ridx = iwn_prev_ridx[ridx]; 3633 } 3634 #ifdef IWN_DEBUG 3635 if (sc->sc_debug & IWN_DEBUG_STATE) { 3636 kprintf("%s: set link quality for node %d, mimo %d ssmask %d\n", 3637 __func__, id, linkq.mimo, linkq.antmsk_1stream); 3638 kprintf("%s:", __func__); 3639 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) 3640 kprintf(" %d:%x", linkq.retry[i].plcp, 3641 linkq.retry[i].rflags); 3642 kprintf("\n"); 3643 } 3644 #endif 3645 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3646 } 3647 3648 /* 3649 * Broadcast node is used to send group-addressed and management frames. 3650 */ 3651 static int 3652 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3653 { 3654 const struct iwn_hal *hal = sc->sc_hal; 3655 struct ifnet *ifp = sc->sc_ifp; 3656 struct iwn_node_info node; 3657 int error; 3658 3659 memset(&node, 0, sizeof node); 3660 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr); 3661 node.id = hal->broadcast_id; 3662 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 3663 error = hal->add_node(sc, &node, async); 3664 if (error != 0) 3665 return error; 3666 3667 error = iwn_set_link_quality(sc, hal->broadcast_id, async); 3668 return error; 3669 } 3670 3671 static int 3672 iwn_wme_update(struct ieee80211com *ic) 3673 { 3674 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 3675 #define IWN_TXOP_TO_US(v) (v<<5) 3676 struct iwn_softc *sc = ic->ic_ifp->if_softc; 3677 struct iwn_edca_params cmd; 3678 int i; 3679 3680 memset(&cmd, 0, sizeof cmd); 3681 cmd.flags = htole32(IWN_EDCA_UPDATE); 3682 for (i = 0; i < WME_NUM_AC; i++) { 3683 const struct wmeParams *wmep = 3684 &ic->ic_wme.wme_chanParams.cap_wmeParams[i]; 3685 cmd.ac[i].aifsn = wmep->wmep_aifsn; 3686 cmd.ac[i].cwmin = htole16(IWN_EXP2(wmep->wmep_logcwmin)); 3687 cmd.ac[i].cwmax = htole16(IWN_EXP2(wmep->wmep_logcwmax)); 3688 cmd.ac[i].txoplimit = 3689 htole16(IWN_TXOP_TO_US(wmep->wmep_txopLimit)); 3690 } 3691 (void) iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1 /*async*/); 3692 return 0; 3693 #undef IWN_TXOP_TO_US 3694 #undef IWN_EXP2 3695 } 3696 3697 static void 3698 iwn_update_mcast(struct ifnet *ifp) 3699 { 3700 /* Ignore */ 3701 } 3702 3703 static void 3704 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3705 { 3706 struct iwn_cmd_led led; 3707 3708 /* Clear microcode LED ownership. */ 3709 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3710 3711 led.which = which; 3712 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3713 led.off = off; 3714 led.on = on; 3715 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3716 } 3717 3718 /* 3719 * Set the critical temperature at which the firmware will stop the radio 3720 * and notify us. 3721 */ 3722 static int 3723 iwn_set_critical_temp(struct iwn_softc *sc) 3724 { 3725 struct iwn_critical_temp crit; 3726 int32_t temp; 3727 3728 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3729 3730 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3731 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3732 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3733 temp = IWN_CTOK(110); 3734 else 3735 temp = 110; 3736 memset(&crit, 0, sizeof crit); 3737 crit.tempR = htole32(temp); 3738 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", 3739 temp); 3740 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3741 } 3742 3743 static int 3744 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3745 { 3746 struct iwn_cmd_timing cmd; 3747 uint64_t val, mod; 3748 3749 memset(&cmd, 0, sizeof cmd); 3750 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3751 cmd.bintval = htole16(ni->ni_intval); 3752 cmd.lintval = htole16(10); 3753 3754 /* Compute remaining time until next beacon. */ 3755 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3756 mod = le64toh(cmd.tstamp) % val; 3757 cmd.binitval = htole32((uint32_t)(val - mod)); 3758 3759 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 3760 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 3761 3762 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3763 } 3764 3765 static void 3766 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3767 { 3768 struct ifnet *ifp = sc->sc_ifp; 3769 struct ieee80211com *ic = ifp->if_l2com; 3770 3771 /* Adjust TX power if need be (delta >= 3 degC.) */ 3772 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 3773 __func__, sc->temp, temp); 3774 if (abs(temp - sc->temp) >= 3) { 3775 /* Record temperature of last calibration. */ 3776 sc->temp = temp; 3777 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1); 3778 } 3779 } 3780 3781 /* 3782 * Set TX power for current channel (each rate has its own power settings). 3783 * This function takes into account the regulatory information from EEPROM, 3784 * the current temperature and the current voltage. 3785 */ 3786 static int 3787 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 3788 int async) 3789 { 3790 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3791 #define fdivround(a, b, n) \ 3792 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3793 /* Linear interpolation. */ 3794 #define interpolate(x, x1, y1, x2, y2, n) \ 3795 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3796 3797 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3798 struct ifnet *ifp = sc->sc_ifp; 3799 struct ieee80211com *ic = ifp->if_l2com; 3800 struct iwn_ucode_info *uc = &sc->ucode_info; 3801 struct iwn4965_cmd_txpower cmd; 3802 struct iwn4965_eeprom_chan_samples *chans; 3803 int32_t vdiff, tdiff; 3804 int i, c, grp, maxpwr; 3805 const uint8_t *rf_gain, *dsp_gain; 3806 uint8_t chan; 3807 3808 /* Retrieve channel number. */ 3809 chan = ieee80211_chan2ieee(ic, ch); 3810 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 3811 chan); 3812 3813 memset(&cmd, 0, sizeof cmd); 3814 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3815 cmd.chan = chan; 3816 3817 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3818 maxpwr = sc->maxpwr5GHz; 3819 rf_gain = iwn4965_rf_gain_5ghz; 3820 dsp_gain = iwn4965_dsp_gain_5ghz; 3821 } else { 3822 maxpwr = sc->maxpwr2GHz; 3823 rf_gain = iwn4965_rf_gain_2ghz; 3824 dsp_gain = iwn4965_dsp_gain_2ghz; 3825 } 3826 3827 /* Compute voltage compensation. */ 3828 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3829 if (vdiff > 0) 3830 vdiff *= 2; 3831 if (abs(vdiff) > 2) 3832 vdiff = 0; 3833 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3834 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3835 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 3836 3837 /* Get channel attenuation group. */ 3838 if (chan <= 20) /* 1-20 */ 3839 grp = 4; 3840 else if (chan <= 43) /* 34-43 */ 3841 grp = 0; 3842 else if (chan <= 70) /* 44-70 */ 3843 grp = 1; 3844 else if (chan <= 124) /* 71-124 */ 3845 grp = 2; 3846 else /* 125-200 */ 3847 grp = 3; 3848 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3849 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 3850 3851 /* Get channel sub-band. */ 3852 for (i = 0; i < IWN_NBANDS; i++) 3853 if (sc->bands[i].lo != 0 && 3854 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3855 break; 3856 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3857 return EINVAL; 3858 chans = sc->bands[i].chans; 3859 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3860 "%s: chan %d sub-band=%d\n", __func__, chan, i); 3861 3862 for (c = 0; c < 2; c++) { 3863 uint8_t power, gain, temp; 3864 int maxchpwr, pwr, ridx, idx; 3865 3866 power = interpolate(chan, 3867 chans[0].num, chans[0].samples[c][1].power, 3868 chans[1].num, chans[1].samples[c][1].power, 1); 3869 gain = interpolate(chan, 3870 chans[0].num, chans[0].samples[c][1].gain, 3871 chans[1].num, chans[1].samples[c][1].gain, 1); 3872 temp = interpolate(chan, 3873 chans[0].num, chans[0].samples[c][1].temp, 3874 chans[1].num, chans[1].samples[c][1].temp, 1); 3875 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3876 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 3877 __func__, c, power, gain, temp); 3878 3879 /* Compute temperature compensation. */ 3880 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3881 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3882 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 3883 __func__, tdiff, sc->temp, temp); 3884 3885 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3886 /* Convert dBm to half-dBm. */ 3887 maxchpwr = sc->maxpwr[chan] * 2; 3888 if ((ridx / 8) & 1) 3889 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3890 3891 pwr = maxpwr; 3892 3893 /* Adjust TX power based on rate. */ 3894 if ((ridx % 8) == 5) 3895 pwr -= 15; /* OFDM48: -7.5dB */ 3896 else if ((ridx % 8) == 6) 3897 pwr -= 17; /* OFDM54: -8.5dB */ 3898 else if ((ridx % 8) == 7) 3899 pwr -= 20; /* OFDM60: -10dB */ 3900 else 3901 pwr -= 10; /* Others: -5dB */ 3902 3903 /* Do not exceed channel max TX power. */ 3904 if (pwr > maxchpwr) 3905 pwr = maxchpwr; 3906 3907 idx = gain - (pwr - power) - tdiff - vdiff; 3908 if ((ridx / 8) & 1) /* MIMO */ 3909 idx += (int32_t)le32toh(uc->atten[grp][c]); 3910 3911 if (cmd.band == 0) 3912 idx += 9; /* 5GHz */ 3913 if (ridx == IWN_RIDX_MAX) 3914 idx += 5; /* CCK */ 3915 3916 /* Make sure idx stays in a valid range. */ 3917 if (idx < 0) 3918 idx = 0; 3919 else if (idx > IWN4965_MAX_PWR_INDEX) 3920 idx = IWN4965_MAX_PWR_INDEX; 3921 3922 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3923 "%s: Tx chain %d, rate idx %d: power=%d\n", 3924 __func__, c, ridx, idx); 3925 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3926 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3927 } 3928 } 3929 3930 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3931 "%s: set tx power for chan %d\n", __func__, chan); 3932 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3933 3934 #undef interpolate 3935 #undef fdivround 3936 } 3937 3938 static int 3939 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 3940 int async) 3941 { 3942 struct iwn5000_cmd_txpower cmd; 3943 3944 /* 3945 * TX power calibration is handled automatically by the firmware 3946 * for 5000 Series. 3947 */ 3948 memset(&cmd, 0, sizeof cmd); 3949 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3950 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3951 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3952 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__); 3953 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3954 } 3955 3956 /* 3957 * Retrieve the maximum RSSI (in dBm) among receivers. 3958 */ 3959 static int 3960 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 3961 { 3962 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 3963 uint8_t mask, agc; 3964 int rssi; 3965 3966 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3967 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3968 3969 rssi = 0; 3970 #if 0 3971 if (mask & IWN_ANT_A) /* Ant A */ 3972 rssi = max(rssi, phy->rssi[0]); 3973 if (mask & IWN_ATH_B) /* Ant B */ 3974 rssi = max(rssi, phy->rssi[2]); 3975 if (mask & IWN_ANT_C) /* Ant C */ 3976 rssi = max(rssi, phy->rssi[4]); 3977 #else 3978 rssi = max(rssi, phy->rssi[0]); 3979 rssi = max(rssi, phy->rssi[2]); 3980 rssi = max(rssi, phy->rssi[4]); 3981 #endif 3982 3983 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d mask 0x%x rssi %d %d %d " 3984 "result %d\n", __func__, agc, mask, 3985 phy->rssi[0], phy->rssi[2], phy->rssi[4], 3986 rssi - agc - IWN_RSSI_TO_DBM); 3987 return rssi - agc - IWN_RSSI_TO_DBM; 3988 } 3989 3990 static int 3991 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 3992 { 3993 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 3994 int rssi; 3995 uint8_t agc; 3996 3997 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3998 3999 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 4000 le16toh(phy->rssi[1]) & 0xff); 4001 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 4002 4003 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d rssi %d %d %d " 4004 "result %d\n", __func__, agc, 4005 phy->rssi[0], phy->rssi[1], phy->rssi[2], 4006 rssi - agc - IWN_RSSI_TO_DBM); 4007 return rssi - agc - IWN_RSSI_TO_DBM; 4008 } 4009 4010 /* 4011 * Retrieve the average noise (in dBm) among receivers. 4012 */ 4013 static int 4014 iwn_get_noise(const struct iwn_rx_general_stats *stats) 4015 { 4016 int i, total, nbant, noise; 4017 4018 total = nbant = 0; 4019 for (i = 0; i < 3; i++) { 4020 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 4021 continue; 4022 total += noise; 4023 nbant++; 4024 } 4025 /* There should be at least one antenna but check anyway. */ 4026 return (nbant == 0) ? -127 : (total / nbant) - 107; 4027 } 4028 4029 /* 4030 * Compute temperature (in degC) from last received statistics. 4031 */ 4032 static int 4033 iwn4965_get_temperature(struct iwn_softc *sc) 4034 { 4035 struct iwn_ucode_info *uc = &sc->ucode_info; 4036 int32_t r1, r2, r3, r4, temp; 4037 4038 r1 = le32toh(uc->temp[0].chan20MHz); 4039 r2 = le32toh(uc->temp[1].chan20MHz); 4040 r3 = le32toh(uc->temp[2].chan20MHz); 4041 r4 = le32toh(sc->rawtemp); 4042 4043 if (r1 == r3) /* Prevents division by 0 (should not happen.) */ 4044 return 0; 4045 4046 /* Sign-extend 23-bit R4 value to 32-bit. */ 4047 r4 = (r4 << 8) >> 8; 4048 /* Compute temperature in Kelvin. */ 4049 temp = (259 * (r4 - r2)) / (r3 - r1); 4050 temp = (temp * 97) / 100 + 8; 4051 4052 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 4053 IWN_KTOC(temp)); 4054 return IWN_KTOC(temp); 4055 } 4056 4057 static int 4058 iwn5000_get_temperature(struct iwn_softc *sc) 4059 { 4060 int32_t temp; 4061 4062 /* 4063 * Temperature is not used by the driver for 5000 Series because 4064 * TX power calibration is handled by firmware. We export it to 4065 * users through the sensor framework though. 4066 */ 4067 temp = le32toh(sc->rawtemp); 4068 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 4069 temp = (temp / -5) + sc->temp_off; 4070 temp = IWN_KTOC(temp); 4071 } 4072 return temp; 4073 } 4074 4075 /* 4076 * Initialize sensitivity calibration state machine. 4077 */ 4078 static int 4079 iwn_init_sensitivity(struct iwn_softc *sc) 4080 { 4081 const struct iwn_hal *hal = sc->sc_hal; 4082 struct iwn_calib_state *calib = &sc->calib; 4083 uint32_t flags; 4084 int error; 4085 4086 /* Reset calibration state machine. */ 4087 memset(calib, 0, sizeof (*calib)); 4088 calib->state = IWN_CALIB_STATE_INIT; 4089 calib->cck_state = IWN_CCK_STATE_HIFA; 4090 /* Set initial correlation values. */ 4091 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4092 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4093 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 4094 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4095 calib->cck_x4 = 125; 4096 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4097 calib->energy_cck = sc->limits->energy_cck; 4098 4099 /* Write initial sensitivity. */ 4100 error = iwn_send_sensitivity(sc); 4101 if (error != 0) 4102 return error; 4103 4104 /* Write initial gains. */ 4105 error = hal->init_gains(sc); 4106 if (error != 0) 4107 return error; 4108 4109 /* Request statistics at each beacon interval. */ 4110 flags = 0; 4111 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: calibrate phy\n", __func__); 4112 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4113 } 4114 4115 /* 4116 * Collect noise and RSSI statistics for the first 20 beacons received 4117 * after association and use them to determine connected antennas and 4118 * to set differential gains. 4119 */ 4120 static void 4121 iwn_collect_noise(struct iwn_softc *sc, 4122 const struct iwn_rx_general_stats *stats) 4123 { 4124 const struct iwn_hal *hal = sc->sc_hal; 4125 struct iwn_calib_state *calib = &sc->calib; 4126 uint32_t val; 4127 int i; 4128 4129 /* Accumulate RSSI and noise for all 3 antennas. */ 4130 for (i = 0; i < 3; i++) { 4131 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 4132 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 4133 } 4134 /* NB: We update differential gains only once after 20 beacons. */ 4135 if (++calib->nbeacons < 20) 4136 return; 4137 4138 /* Determine highest average RSSI. */ 4139 val = MAX(calib->rssi[0], calib->rssi[1]); 4140 val = MAX(calib->rssi[2], val); 4141 4142 /* Determine which antennas are connected. */ 4143 sc->chainmask = sc->rxchainmask; 4144 for (i = 0; i < 3; i++) 4145 if (val - calib->rssi[i] > 15 * 20) 4146 sc->chainmask &= ~(1 << i); 4147 4148 /* If none of the TX antennas are connected, keep at least one. */ 4149 if ((sc->chainmask & sc->txchainmask) == 0) 4150 sc->chainmask |= IWN_LSB(sc->txchainmask); 4151 4152 (void)hal->set_gains(sc); 4153 calib->state = IWN_CALIB_STATE_RUN; 4154 4155 #ifdef notyet 4156 /* XXX Disable RX chains with no antennas connected. */ 4157 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4158 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4159 #endif 4160 4161 #if 0 4162 /* XXX: not yet */ 4163 /* Enable power-saving mode if requested by user. */ 4164 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4165 (void)iwn_set_pslevel(sc, 0, 3, 1); 4166 #endif 4167 } 4168 4169 static int 4170 iwn4965_init_gains(struct iwn_softc *sc) 4171 { 4172 struct iwn_phy_calib_gain cmd; 4173 4174 memset(&cmd, 0, sizeof cmd); 4175 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4176 /* Differential gains initially set to 0 for all 3 antennas. */ 4177 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4178 "%s: setting initial differential gains\n", __func__); 4179 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4180 } 4181 4182 static int 4183 iwn5000_init_gains(struct iwn_softc *sc) 4184 { 4185 struct iwn_phy_calib cmd; 4186 4187 memset(&cmd, 0, sizeof cmd); 4188 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 4189 cmd.ngroups = 1; 4190 cmd.isvalid = 1; 4191 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4192 "%s: setting initial differential gains\n", __func__); 4193 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4194 } 4195 4196 static int 4197 iwn4965_set_gains(struct iwn_softc *sc) 4198 { 4199 struct iwn_calib_state *calib = &sc->calib; 4200 struct iwn_phy_calib_gain cmd; 4201 int i, delta, noise; 4202 4203 /* Get minimal noise among connected antennas. */ 4204 noise = INT_MAX; /* NB: There's at least one antenna. */ 4205 for (i = 0; i < 3; i++) 4206 if (sc->chainmask & (1 << i)) 4207 noise = MIN(calib->noise[i], noise); 4208 4209 memset(&cmd, 0, sizeof cmd); 4210 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4211 /* Set differential gains for connected antennas. */ 4212 for (i = 0; i < 3; i++) { 4213 if (sc->chainmask & (1 << i)) { 4214 /* Compute attenuation (in unit of 1.5dB). */ 4215 delta = (noise - (int32_t)calib->noise[i]) / 30; 4216 /* NB: delta <= 0 */ 4217 /* Limit to [-4.5dB,0]. */ 4218 cmd.gain[i] = MIN(abs(delta), 3); 4219 if (delta < 0) 4220 cmd.gain[i] |= 1 << 2; /* sign bit */ 4221 } 4222 } 4223 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4224 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4225 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 4226 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4227 } 4228 4229 static int 4230 iwn5000_set_gains(struct iwn_softc *sc) 4231 { 4232 struct iwn_calib_state *calib = &sc->calib; 4233 struct iwn_phy_calib_gain cmd; 4234 int i, ant, delta, div; 4235 4236 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4237 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4238 4239 memset(&cmd, 0, sizeof cmd); 4240 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 4241 cmd.ngroups = 1; 4242 cmd.isvalid = 1; 4243 /* Get first available RX antenna as referential. */ 4244 ant = IWN_LSB(sc->rxchainmask); 4245 /* Set differential gains for other antennas. */ 4246 for (i = ant + 1; i < 3; i++) { 4247 if (sc->chainmask & (1 << i)) { 4248 /* The delta is relative to antenna "ant". */ 4249 delta = ((int32_t)calib->noise[ant] - 4250 (int32_t)calib->noise[i]) / div; 4251 /* Limit to [-4.5dB,+4.5dB]. */ 4252 cmd.gain[i - 1] = MIN(abs(delta), 3); 4253 if (delta < 0) 4254 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4255 } 4256 } 4257 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4258 "setting differential gains Ant B/C: %x/%x (%x)\n", 4259 cmd.gain[0], cmd.gain[1], sc->chainmask); 4260 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4261 } 4262 4263 /* 4264 * Tune RF RX sensitivity based on the number of false alarms detected 4265 * during the last beacon period. 4266 */ 4267 static void 4268 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4269 { 4270 #define inc(val, inc, max) \ 4271 if ((val) < (max)) { \ 4272 if ((val) < (max) - (inc)) \ 4273 (val) += (inc); \ 4274 else \ 4275 (val) = (max); \ 4276 needs_update = 1; \ 4277 } 4278 #define dec(val, dec, min) \ 4279 if ((val) > (min)) { \ 4280 if ((val) > (min) + (dec)) \ 4281 (val) -= (dec); \ 4282 else \ 4283 (val) = (min); \ 4284 needs_update = 1; \ 4285 } 4286 4287 const struct iwn_sensitivity_limits *limits = sc->limits; 4288 struct iwn_calib_state *calib = &sc->calib; 4289 uint32_t val, rxena, fa; 4290 uint32_t energy[3], energy_min; 4291 uint8_t noise[3], noise_ref; 4292 int i, needs_update = 0; 4293 4294 /* Check that we've been enabled long enough. */ 4295 rxena = le32toh(stats->general.load); 4296 if (rxena == 0) 4297 return; 4298 4299 /* Compute number of false alarms since last call for OFDM. */ 4300 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4301 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 4302 fa *= 200 * 1024; /* 200TU */ 4303 4304 /* Save counters values for next call. */ 4305 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 4306 calib->fa_ofdm = le32toh(stats->ofdm.fa); 4307 4308 if (fa > 50 * rxena) { 4309 /* High false alarm count, decrease sensitivity. */ 4310 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4311 "%s: OFDM high false alarm count: %u\n", __func__, fa); 4312 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4313 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4314 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4315 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4316 4317 } else if (fa < 5 * rxena) { 4318 /* Low false alarm count, increase sensitivity. */ 4319 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4320 "%s: OFDM low false alarm count: %u\n", __func__, fa); 4321 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4322 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4323 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4324 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4325 } 4326 4327 /* Compute maximum noise among 3 receivers. */ 4328 for (i = 0; i < 3; i++) 4329 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4330 val = MAX(noise[0], noise[1]); 4331 val = MAX(noise[2], val); 4332 /* Insert it into our samples table. */ 4333 calib->noise_samples[calib->cur_noise_sample] = val; 4334 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4335 4336 /* Compute maximum noise among last 20 samples. */ 4337 noise_ref = calib->noise_samples[0]; 4338 for (i = 1; i < 20; i++) 4339 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4340 4341 /* Compute maximum energy among 3 receivers. */ 4342 for (i = 0; i < 3; i++) 4343 energy[i] = le32toh(stats->general.energy[i]); 4344 val = MIN(energy[0], energy[1]); 4345 val = MIN(energy[2], val); 4346 /* Insert it into our samples table. */ 4347 calib->energy_samples[calib->cur_energy_sample] = val; 4348 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4349 4350 /* Compute minimum energy among last 10 samples. */ 4351 energy_min = calib->energy_samples[0]; 4352 for (i = 1; i < 10; i++) 4353 energy_min = MAX(energy_min, calib->energy_samples[i]); 4354 energy_min += 6; 4355 4356 /* Compute number of false alarms since last call for CCK. */ 4357 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4358 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4359 fa *= 200 * 1024; /* 200TU */ 4360 4361 /* Save counters values for next call. */ 4362 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4363 calib->fa_cck = le32toh(stats->cck.fa); 4364 4365 if (fa > 50 * rxena) { 4366 /* High false alarm count, decrease sensitivity. */ 4367 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4368 "%s: CCK high false alarm count: %u\n", __func__, fa); 4369 calib->cck_state = IWN_CCK_STATE_HIFA; 4370 calib->low_fa = 0; 4371 4372 if (calib->cck_x4 > 160) { 4373 calib->noise_ref = noise_ref; 4374 if (calib->energy_cck > 2) 4375 dec(calib->energy_cck, 2, energy_min); 4376 } 4377 if (calib->cck_x4 < 160) { 4378 calib->cck_x4 = 161; 4379 needs_update = 1; 4380 } else 4381 inc(calib->cck_x4, 3, limits->max_cck_x4); 4382 4383 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4384 4385 } else if (fa < 5 * rxena) { 4386 /* Low false alarm count, increase sensitivity. */ 4387 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4388 "%s: CCK low false alarm count: %u\n", __func__, fa); 4389 calib->cck_state = IWN_CCK_STATE_LOFA; 4390 calib->low_fa++; 4391 4392 if (calib->cck_state != IWN_CCK_STATE_INIT && 4393 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4394 calib->low_fa > 100)) { 4395 inc(calib->energy_cck, 2, limits->min_energy_cck); 4396 dec(calib->cck_x4, 3, limits->min_cck_x4); 4397 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4398 } 4399 } else { 4400 /* Not worth to increase or decrease sensitivity. */ 4401 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4402 "%s: CCK normal false alarm count: %u\n", __func__, fa); 4403 calib->low_fa = 0; 4404 calib->noise_ref = noise_ref; 4405 4406 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4407 /* Previous interval had many false alarms. */ 4408 dec(calib->energy_cck, 8, energy_min); 4409 } 4410 calib->cck_state = IWN_CCK_STATE_INIT; 4411 } 4412 4413 if (needs_update) 4414 (void)iwn_send_sensitivity(sc); 4415 #undef dec 4416 #undef inc 4417 } 4418 4419 static int 4420 iwn_send_sensitivity(struct iwn_softc *sc) 4421 { 4422 struct iwn_calib_state *calib = &sc->calib; 4423 struct iwn_sensitivity_cmd cmd; 4424 4425 memset(&cmd, 0, sizeof cmd); 4426 cmd.which = IWN_SENSITIVITY_WORKTBL; 4427 /* OFDM modulation. */ 4428 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4429 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4430 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4431 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4432 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4433 cmd.energy_ofdm_th = htole16(62); 4434 /* CCK modulation. */ 4435 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4436 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4437 cmd.energy_cck = htole16(calib->energy_cck); 4438 /* Barker modulation: use default values. */ 4439 cmd.corr_barker = htole16(190); 4440 cmd.corr_barker_mrc = htole16(390); 4441 4442 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4443 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 4444 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4445 calib->ofdm_mrc_x4, calib->cck_x4, 4446 calib->cck_mrc_x4, calib->energy_cck); 4447 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 4448 } 4449 4450 /* 4451 * Set STA mode power saving level (between 0 and 5). 4452 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4453 */ 4454 static int 4455 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4456 { 4457 const struct iwn_pmgt *pmgt; 4458 struct iwn_pmgt_cmd cmd; 4459 uint32_t max, skip_dtim; 4460 uint32_t tmp; 4461 int i; 4462 4463 /* Select which PS parameters to use. */ 4464 if (dtim <= 2) 4465 pmgt = &iwn_pmgt[0][level]; 4466 else if (dtim <= 10) 4467 pmgt = &iwn_pmgt[1][level]; 4468 else 4469 pmgt = &iwn_pmgt[2][level]; 4470 4471 memset(&cmd, 0, sizeof cmd); 4472 if (level != 0) /* not CAM */ 4473 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4474 if (level == 5) 4475 cmd.flags |= htole16(IWN_PS_FAST_PD); 4476 /* Retrieve PCIe Active State Power Management (ASPM). */ 4477 tmp = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 4478 if (!(tmp & 0x1)) /* L0s Entry disabled. */ 4479 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4480 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4481 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4482 4483 if (dtim == 0) { 4484 dtim = 1; 4485 skip_dtim = 0; 4486 } else 4487 skip_dtim = pmgt->skip_dtim; 4488 if (skip_dtim != 0) { 4489 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4490 max = pmgt->intval[4]; 4491 if (max == (uint32_t)-1) 4492 max = dtim * (skip_dtim + 1); 4493 else if (max > dtim) 4494 max = (max / dtim) * dtim; 4495 } else 4496 max = dtim; 4497 for (i = 0; i < 5; i++) 4498 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4499 4500 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 4501 level); 4502 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4503 } 4504 4505 static int 4506 iwn_config(struct iwn_softc *sc) 4507 { 4508 const struct iwn_hal *hal = sc->sc_hal; 4509 struct ifnet *ifp = sc->sc_ifp; 4510 struct ieee80211com *ic = ifp->if_l2com; 4511 struct iwn_bluetooth bluetooth; 4512 uint32_t txmask; 4513 int error; 4514 uint16_t rxchain; 4515 4516 /* Configure valid TX chains for 5000 Series. */ 4517 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4518 txmask = htole32(sc->txchainmask); 4519 DPRINTF(sc, IWN_DEBUG_RESET, 4520 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 4521 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4522 sizeof txmask, 0); 4523 if (error != 0) { 4524 device_printf(sc->sc_dev, 4525 "%s: could not configure valid TX chains, " 4526 "error %d\n", __func__, error); 4527 return error; 4528 } 4529 } 4530 4531 /* Configure bluetooth coexistence. */ 4532 memset(&bluetooth, 0, sizeof bluetooth); 4533 bluetooth.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4534 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4535 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4536 DPRINTF(sc, IWN_DEBUG_RESET, "%s: config bluetooth coexistence\n", 4537 __func__); 4538 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4539 if (error != 0) { 4540 device_printf(sc->sc_dev, 4541 "%s: could not configure bluetooth coexistence, error %d\n", 4542 __func__, error); 4543 return error; 4544 } 4545 4546 /* Set mode, channel, RX filter and enable RX. */ 4547 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4548 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp)); 4549 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp)); 4550 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 4551 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4552 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 4553 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4554 switch (ic->ic_opmode) { 4555 case IEEE80211_M_STA: 4556 sc->rxon.mode = IWN_MODE_STA; 4557 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4558 break; 4559 case IEEE80211_M_MONITOR: 4560 sc->rxon.mode = IWN_MODE_MONITOR; 4561 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4562 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4563 break; 4564 default: 4565 /* Should not get there. */ 4566 break; 4567 } 4568 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4569 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4570 sc->rxon.ht_single_mask = 0xff; 4571 sc->rxon.ht_dual_mask = 0xff; 4572 sc->rxon.ht_triple_mask = 0xff; 4573 rxchain = 4574 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4575 IWN_RXCHAIN_MIMO_COUNT(2) | 4576 IWN_RXCHAIN_IDLE_COUNT(2); 4577 sc->rxon.rxchain = htole16(rxchain); 4578 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__); 4579 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 0); 4580 if (error != 0) { 4581 device_printf(sc->sc_dev, 4582 "%s: RXON command failed\n", __func__); 4583 return error; 4584 } 4585 4586 error = iwn_add_broadcast_node(sc, 0); 4587 if (error != 0) { 4588 device_printf(sc->sc_dev, 4589 "%s: could not add broadcast node\n", __func__); 4590 return error; 4591 } 4592 4593 /* Configuration has changed, set TX power accordingly. */ 4594 error = hal->set_txpower(sc, ic->ic_curchan, 0); 4595 if (error != 0) { 4596 device_printf(sc->sc_dev, 4597 "%s: could not set TX power\n", __func__); 4598 return error; 4599 } 4600 4601 error = iwn_set_critical_temp(sc); 4602 if (error != 0) { 4603 device_printf(sc->sc_dev, 4604 "%s: ccould not set critical temperature\n", __func__); 4605 return error; 4606 } 4607 4608 /* Set power saving level to CAM during initialization. */ 4609 error = iwn_set_pslevel(sc, 0, 0, 0); 4610 if (error != 0) { 4611 device_printf(sc->sc_dev, 4612 "%s: could not set power saving level\n", __func__); 4613 return error; 4614 } 4615 return 0; 4616 } 4617 4618 static int 4619 iwn_scan(struct iwn_softc *sc) 4620 { 4621 struct ifnet *ifp = sc->sc_ifp; 4622 struct ieee80211com *ic = ifp->if_l2com; 4623 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/ 4624 struct iwn_scan_hdr *hdr; 4625 struct iwn_cmd_data *tx; 4626 struct iwn_scan_essid *essid; 4627 struct iwn_scan_chan *chan; 4628 struct ieee80211_frame *wh; 4629 struct ieee80211_rateset *rs; 4630 struct ieee80211_channel *c; 4631 int buflen, error, nrates; 4632 uint16_t rxchain; 4633 uint8_t *buf, *frm, txant; 4634 4635 buf = kmalloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_INTWAIT | M_ZERO); 4636 if (buf == NULL) { 4637 device_printf(sc->sc_dev, 4638 "%s: could not allocate buffer for scan command\n", 4639 __func__); 4640 return ENOMEM; 4641 } 4642 hdr = (struct iwn_scan_hdr *)buf; 4643 4644 /* 4645 * Move to the next channel if no frames are received within 10ms 4646 * after sending the probe request. 4647 */ 4648 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4649 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4650 4651 /* Select antennas for scanning. */ 4652 rxchain = 4653 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4654 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4655 IWN_RXCHAIN_DRIVER_FORCE; 4656 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) && 4657 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4658 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4659 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4660 } else /* Use all available RX antennas. */ 4661 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4662 hdr->rxchain = htole16(rxchain); 4663 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4664 4665 tx = (struct iwn_cmd_data *)(hdr + 1); 4666 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4667 tx->id = sc->sc_hal->broadcast_id; 4668 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4669 4670 if (IEEE80211_IS_CHAN_A(ic->ic_curchan)) { 4671 /* Send probe requests at 6Mbps. */ 4672 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4673 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4674 } else { 4675 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4676 /* Send probe requests at 1Mbps. */ 4677 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4678 tx->rflags = IWN_RFLAG_CCK; 4679 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4680 } 4681 /* Use the first valid TX antenna. */ 4682 txant = IWN_LSB(sc->txchainmask); 4683 tx->rflags |= IWN_RFLAG_ANT(txant); 4684 4685 essid = (struct iwn_scan_essid *)(tx + 1); 4686 if (ss->ss_ssid[0].len != 0) { 4687 essid[0].id = IEEE80211_ELEMID_SSID; 4688 essid[0].len = ss->ss_ssid[0].len; 4689 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 4690 } 4691 4692 /* 4693 * Build a probe request frame. Most of the following code is a 4694 * copy & paste of what is done in net80211. 4695 */ 4696 wh = (struct ieee80211_frame *)(essid + 20); 4697 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4698 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4699 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4700 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr); 4701 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp)); 4702 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr); 4703 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4704 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4705 4706 frm = (uint8_t *)(wh + 1); 4707 4708 /* Add SSID IE. */ 4709 *frm++ = IEEE80211_ELEMID_SSID; 4710 *frm++ = ss->ss_ssid[0].len; 4711 memcpy(frm, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 4712 frm += ss->ss_ssid[0].len; 4713 4714 /* Add supported rates IE. */ 4715 *frm++ = IEEE80211_ELEMID_RATES; 4716 nrates = rs->rs_nrates; 4717 if (nrates > IEEE80211_RATE_SIZE) 4718 nrates = IEEE80211_RATE_SIZE; 4719 *frm++ = nrates; 4720 memcpy(frm, rs->rs_rates, nrates); 4721 frm += nrates; 4722 4723 /* Add supported xrates IE. */ 4724 if (rs->rs_nrates > IEEE80211_RATE_SIZE) { 4725 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 4726 *frm++ = IEEE80211_ELEMID_XRATES; 4727 *frm++ = (uint8_t)nrates; 4728 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 4729 frm += nrates; 4730 } 4731 4732 /* Set length of probe request. */ 4733 tx->len = htole16(frm - (uint8_t *)wh); 4734 4735 c = ic->ic_curchan; 4736 chan = (struct iwn_scan_chan *)frm; 4737 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4738 chan->flags = 0; 4739 if (ss->ss_nssid > 0) 4740 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4741 chan->dsp_gain = 0x6e; 4742 if (IEEE80211_IS_CHAN_5GHZ(c) && 4743 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 4744 chan->rf_gain = 0x3b; 4745 chan->active = htole16(24); 4746 chan->passive = htole16(110); 4747 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4748 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 4749 chan->rf_gain = 0x3b; 4750 chan->active = htole16(24); 4751 if (sc->rxon.associd) 4752 chan->passive = htole16(78); 4753 else 4754 chan->passive = htole16(110); 4755 hdr->crc_threshold = 0xffff; 4756 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 4757 chan->rf_gain = 0x28; 4758 chan->active = htole16(36); 4759 chan->passive = htole16(120); 4760 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4761 } else { 4762 chan->rf_gain = 0x28; 4763 chan->active = htole16(36); 4764 if (sc->rxon.associd) 4765 chan->passive = htole16(88); 4766 else 4767 chan->passive = htole16(120); 4768 hdr->crc_threshold = 0xffff; 4769 } 4770 4771 DPRINTF(sc, IWN_DEBUG_STATE, 4772 "%s: chan %u flags 0x%x rf_gain 0x%x " 4773 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__, 4774 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 4775 chan->active, chan->passive); 4776 4777 hdr->nchan++; 4778 chan++; 4779 buflen = (uint8_t *)chan - buf; 4780 hdr->len = htole16(buflen); 4781 4782 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 4783 hdr->nchan); 4784 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4785 kfree(buf, M_DEVBUF); 4786 return error; 4787 } 4788 4789 static int 4790 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 4791 { 4792 const struct iwn_hal *hal = sc->sc_hal; 4793 struct ifnet *ifp = sc->sc_ifp; 4794 struct ieee80211com *ic = ifp->if_l2com; 4795 struct ieee80211_node *ni = vap->iv_bss; 4796 int error; 4797 4798 sc->calib.state = IWN_CALIB_STATE_INIT; 4799 4800 /* Update adapter configuration. */ 4801 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4802 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan)); 4803 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4804 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4805 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4806 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4807 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4808 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4809 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4810 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 4811 sc->rxon.cck_mask = 0; 4812 sc->rxon.ofdm_mask = 0x15; 4813 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 4814 sc->rxon.cck_mask = 0x03; 4815 sc->rxon.ofdm_mask = 0; 4816 } else { 4817 /* XXX assume 802.11b/g */ 4818 sc->rxon.cck_mask = 0x0f; 4819 sc->rxon.ofdm_mask = 0x15; 4820 } 4821 DPRINTF(sc, IWN_DEBUG_STATE, 4822 "%s: config chan %d mode %d flags 0x%x cck 0x%x ofdm 0x%x " 4823 "ht_single 0x%x ht_dual 0x%x rxchain 0x%x " 4824 "myaddr %6D wlap %6D bssid %6D associd %d filter 0x%x\n", 4825 __func__, 4826 le16toh(sc->rxon.chan), sc->rxon.mode, le32toh(sc->rxon.flags), 4827 sc->rxon.cck_mask, sc->rxon.ofdm_mask, 4828 sc->rxon.ht_single_mask, sc->rxon.ht_dual_mask, 4829 le16toh(sc->rxon.rxchain), 4830 sc->rxon.myaddr, ":", sc->rxon.wlap, ":", sc->rxon.bssid, ":", 4831 le16toh(sc->rxon.associd), le32toh(sc->rxon.filter)); 4832 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4833 if (error != 0) { 4834 device_printf(sc->sc_dev, 4835 "%s: RXON command failed, error %d\n", __func__, error); 4836 return error; 4837 } 4838 4839 /* Configuration has changed, set TX power accordingly. */ 4840 error = hal->set_txpower(sc, ni->ni_chan, 1); 4841 if (error != 0) { 4842 device_printf(sc->sc_dev, 4843 "%s: could not set Tx power, error %d\n", __func__, error); 4844 return error; 4845 } 4846 /* 4847 * Reconfiguring RXON clears the firmware nodes table so we must 4848 * add the broadcast node again. 4849 */ 4850 error = iwn_add_broadcast_node(sc, 1); 4851 if (error != 0) { 4852 device_printf(sc->sc_dev, 4853 "%s: could not add broadcast node, error %d\n", 4854 __func__, error); 4855 return error; 4856 } 4857 return 0; 4858 } 4859 4860 /* 4861 * Configure the adapter for associated state. 4862 */ 4863 static int 4864 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 4865 { 4866 #define MS(v,x) (((v) & x) >> x##_S) 4867 const struct iwn_hal *hal = sc->sc_hal; 4868 struct ifnet *ifp = sc->sc_ifp; 4869 struct ieee80211com *ic = ifp->if_l2com; 4870 struct ieee80211_node *ni = vap->iv_bss; 4871 struct iwn_node_info node; 4872 int error; 4873 4874 sc->calib.state = IWN_CALIB_STATE_INIT; 4875 4876 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4877 /* Link LED blinks while monitoring. */ 4878 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4879 return 0; 4880 } 4881 error = iwn_set_timing(sc, ni); 4882 if (error != 0) { 4883 device_printf(sc->sc_dev, 4884 "%s: could not set timing, error %d\n", __func__, error); 4885 return error; 4886 } 4887 4888 /* Update adapter configuration. */ 4889 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4890 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan)); 4891 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4892 /* Short preamble and slot time are negotiated when associating. */ 4893 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4894 sc->rxon.flags |= htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4895 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4896 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4897 else 4898 sc->rxon.flags &= ~htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4899 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4900 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4901 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4902 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4903 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 4904 sc->rxon.cck_mask = 0; 4905 sc->rxon.ofdm_mask = 0x15; 4906 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 4907 sc->rxon.cck_mask = 0x03; 4908 sc->rxon.ofdm_mask = 0; 4909 } else { 4910 /* XXX assume 802.11b/g */ 4911 sc->rxon.cck_mask = 0x0f; 4912 sc->rxon.ofdm_mask = 0x15; 4913 } 4914 #if 0 /* HT */ 4915 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 4916 sc->rxon.flags &= ~htole32(IWN_RXON_HT); 4917 if (IEEE80211_IS_CHAN_HT40U(ni->ni_chan)) 4918 sc->rxon.flags |= htole32(IWN_RXON_HT40U); 4919 else if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan)) 4920 sc->rxon.flags |= htole32(IWN_RXON_HT40D); 4921 else 4922 sc->rxon.flags |= htole32(IWN_RXON_HT20); 4923 sc->rxon.rxchain = htole16( 4924 IWN_RXCHAIN_VALID(3) 4925 | IWN_RXCHAIN_MIMO_COUNT(3) 4926 | IWN_RXCHAIN_IDLE_COUNT(1) 4927 | IWN_RXCHAIN_MIMO_FORCE); 4928 4929 maxrxampdu = MS(ni->ni_htparam, IEEE80211_HTCAP_MAXRXAMPDU); 4930 ampdudensity = MS(ni->ni_htparam, IEEE80211_HTCAP_MPDUDENSITY); 4931 } else 4932 maxrxampdu = ampdudensity = 0; 4933 #endif 4934 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4935 4936 DPRINTF(sc, IWN_DEBUG_STATE, 4937 "%s: config chan %d mode %d flags 0x%x cck 0x%x ofdm 0x%x " 4938 "ht_single 0x%x ht_dual 0x%x rxchain 0x%x " 4939 "myaddr %6D wlap %6D bssid %6D associd %d filter 0x%x\n", 4940 __func__, 4941 le16toh(sc->rxon.chan), sc->rxon.mode, le32toh(sc->rxon.flags), 4942 sc->rxon.cck_mask, sc->rxon.ofdm_mask, 4943 sc->rxon.ht_single_mask, sc->rxon.ht_dual_mask, 4944 le16toh(sc->rxon.rxchain), 4945 sc->rxon.myaddr, ":", sc->rxon.wlap, ":", sc->rxon.bssid, ":", 4946 le16toh(sc->rxon.associd), le32toh(sc->rxon.filter)); 4947 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4948 if (error != 0) { 4949 device_printf(sc->sc_dev, 4950 "%s: could not update configuration, error %d\n", 4951 __func__, error); 4952 return error; 4953 } 4954 4955 /* Configuration has changed, set TX power accordingly. */ 4956 error = hal->set_txpower(sc, ni->ni_chan, 1); 4957 if (error != 0) { 4958 device_printf(sc->sc_dev, 4959 "%s: could not set Tx power, error %d\n", __func__, error); 4960 return error; 4961 } 4962 4963 /* Add BSS node. */ 4964 memset(&node, 0, sizeof node); 4965 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4966 node.id = IWN_ID_BSS; 4967 #ifdef notyet 4968 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4969 IWN_AMDPU_DENSITY(5)); /* 2us */ 4970 #endif 4971 DPRINTF(sc, IWN_DEBUG_STATE, "%s: add BSS node, id %d htflags 0x%x\n", 4972 __func__, node.id, le32toh(node.htflags)); 4973 error = hal->add_node(sc, &node, 1); 4974 if (error != 0) { 4975 device_printf(sc->sc_dev, "could not add BSS node\n"); 4976 return error; 4977 } 4978 DPRINTF(sc, IWN_DEBUG_STATE, "setting link quality for node %d\n", 4979 node.id); 4980 error = iwn_set_link_quality(sc, node.id, 1); 4981 if (error != 0) { 4982 device_printf(sc->sc_dev, 4983 "%s: could not setup MRR for node %d, error %d\n", 4984 __func__, node.id, error); 4985 return error; 4986 } 4987 4988 error = iwn_init_sensitivity(sc); 4989 if (error != 0) { 4990 device_printf(sc->sc_dev, 4991 "%s: could not set sensitivity, error %d\n", 4992 __func__, error); 4993 return error; 4994 } 4995 4996 /* Start periodic calibration timer. */ 4997 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4998 iwn_calib_reset(sc); 4999 5000 /* Link LED always on while associated. */ 5001 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5002 5003 return 0; 5004 #undef MS 5005 } 5006 5007 #if 0 /* HT */ 5008 /* 5009 * This function is called by upper layer when an ADDBA request is received 5010 * from another STA and before the ADDBA response is sent. 5011 */ 5012 static int 5013 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5014 uint8_t tid) 5015 { 5016 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 5017 struct iwn_softc *sc = ic->ic_softc; 5018 struct iwn_node *wn = (void *)ni; 5019 struct iwn_node_info node; 5020 5021 memset(&node, 0, sizeof node); 5022 node.id = wn->id; 5023 node.control = IWN_NODE_UPDATE; 5024 node.flags = IWN_FLAG_SET_ADDBA; 5025 node.addba_tid = tid; 5026 node.addba_ssn = htole16(ba->ba_winstart); 5027 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 5028 wn->id, tid, ba->ba_winstart)); 5029 return sc->sc_hal->add_node(sc, &node, 1); 5030 } 5031 5032 /* 5033 * This function is called by upper layer on teardown of an HT-immediate 5034 * Block Ack agreement (eg. uppon receipt of a DELBA frame.) 5035 */ 5036 static void 5037 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5038 uint8_t tid) 5039 { 5040 struct iwn_softc *sc = ic->ic_softc; 5041 struct iwn_node *wn = (void *)ni; 5042 struct iwn_node_info node; 5043 5044 memset(&node, 0, sizeof node); 5045 node.id = wn->id; 5046 node.control = IWN_NODE_UPDATE; 5047 node.flags = IWN_FLAG_SET_DELBA; 5048 node.delba_tid = tid; 5049 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 5050 (void)sc->sc_hal->add_node(sc, &node, 1); 5051 } 5052 5053 /* 5054 * This function is called by upper layer when an ADDBA response is received 5055 * from another STA. 5056 */ 5057 static int 5058 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5059 uint8_t tid) 5060 { 5061 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5062 struct iwn_softc *sc = ic->ic_softc; 5063 const struct iwn_hal *hal = sc->sc_hal; 5064 struct iwn_node *wn = (void *)ni; 5065 struct iwn_node_info node; 5066 int error; 5067 5068 /* Enable TX for the specified RA/TID. */ 5069 wn->disable_tid &= ~(1 << tid); 5070 memset(&node, 0, sizeof node); 5071 node.id = wn->id; 5072 node.control = IWN_NODE_UPDATE; 5073 node.flags = IWN_FLAG_SET_DISABLE_TID; 5074 node.disable_tid = htole16(wn->disable_tid); 5075 error = hal->add_node(sc, &node, 1); 5076 if (error != 0) 5077 return error; 5078 5079 if ((error = iwn_nic_lock(sc)) != 0) 5080 return error; 5081 hal->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5082 iwn_nic_unlock(sc); 5083 return 0; 5084 } 5085 5086 static void 5087 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5088 uint8_t tid) 5089 { 5090 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5091 struct iwn_softc *sc = ic->ic_softc; 5092 int error; 5093 5094 error = iwn_nic_lock(sc); 5095 if (error != 0) 5096 return; 5097 sc->sc_hal->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5098 iwn_nic_unlock(sc); 5099 } 5100 5101 static void 5102 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5103 uint8_t tid, uint16_t ssn) 5104 { 5105 struct iwn_node *wn = (void *)ni; 5106 int qid = 7 + tid; 5107 5108 /* Stop TX scheduler while we're changing its configuration. */ 5109 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5110 IWN4965_TXQ_STATUS_CHGACT); 5111 5112 /* Assign RA/TID translation to the queue. */ 5113 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5114 wn->id << 4 | tid); 5115 5116 /* Enable chain-building mode for the queue. */ 5117 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5118 5119 /* Set starting sequence number from the ADDBA request. */ 5120 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5121 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5122 5123 /* Set scheduler window size. */ 5124 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5125 IWN_SCHED_WINSZ); 5126 /* Set scheduler frame limit. */ 5127 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5128 IWN_SCHED_LIMIT << 16); 5129 5130 /* Enable interrupts for the queue. */ 5131 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5132 5133 /* Mark the queue as active. */ 5134 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5135 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5136 iwn_tid2fifo[tid] << 1); 5137 } 5138 5139 static void 5140 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5141 { 5142 int qid = 7 + tid; 5143 5144 /* Stop TX scheduler while we're changing its configuration. */ 5145 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5146 IWN4965_TXQ_STATUS_CHGACT); 5147 5148 /* Set starting sequence number from the ADDBA request. */ 5149 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5150 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5151 5152 /* Disable interrupts for the queue. */ 5153 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5154 5155 /* Mark the queue as inactive. */ 5156 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5157 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5158 } 5159 5160 static void 5161 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5162 uint8_t tid, uint16_t ssn) 5163 { 5164 struct iwn_node *wn = (void *)ni; 5165 int qid = 10 + tid; 5166 5167 /* Stop TX scheduler while we're changing its configuration. */ 5168 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5169 IWN5000_TXQ_STATUS_CHGACT); 5170 5171 /* Assign RA/TID translation to the queue. */ 5172 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5173 wn->id << 4 | tid); 5174 5175 /* Enable chain-building mode for the queue. */ 5176 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5177 5178 /* Enable aggregation for the queue. */ 5179 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5180 5181 /* Set starting sequence number from the ADDBA request. */ 5182 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5183 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5184 5185 /* Set scheduler window size and frame limit. */ 5186 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5187 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5188 5189 /* Enable interrupts for the queue. */ 5190 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5191 5192 /* Mark the queue as active. */ 5193 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5194 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5195 } 5196 5197 static void 5198 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5199 { 5200 int qid = 10 + tid; 5201 5202 /* Stop TX scheduler while we're changing its configuration. */ 5203 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5204 IWN5000_TXQ_STATUS_CHGACT); 5205 5206 /* Disable aggregation for the queue. */ 5207 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5208 5209 /* Set starting sequence number from the ADDBA request. */ 5210 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5211 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5212 5213 /* Disable interrupts for the queue. */ 5214 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5215 5216 /* Mark the queue as inactive. */ 5217 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5218 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5219 } 5220 #endif 5221 5222 /* 5223 * Query calibration tables from the initialization firmware. We do this 5224 * only once at first boot. Called from a process context. 5225 */ 5226 static int 5227 iwn5000_query_calibration(struct iwn_softc *sc) 5228 { 5229 struct iwn5000_calib_config cmd; 5230 int error; 5231 5232 memset(&cmd, 0, sizeof cmd); 5233 cmd.ucode.once.enable = 0xffffffff; 5234 cmd.ucode.once.start = 0xffffffff; 5235 cmd.ucode.once.send = 0xffffffff; 5236 cmd.ucode.flags = 0xffffffff; 5237 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 5238 __func__); 5239 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5240 if (error != 0) 5241 return error; 5242 5243 /* Wait at most two seconds for calibration to complete. */ 5244 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5245 error = zsleep(sc, &wlan_global_serializer, 5246 0, "iwninit", 2 * hz); 5247 } 5248 return error; 5249 } 5250 5251 /* 5252 * Send calibration results to the runtime firmware. These results were 5253 * obtained on first boot from the initialization firmware. 5254 */ 5255 static int 5256 iwn5000_send_calibration(struct iwn_softc *sc) 5257 { 5258 int idx, error; 5259 5260 for (idx = 0; idx < 5; idx++) { 5261 if (sc->calibcmd[idx].buf == NULL) 5262 continue; /* No results available. */ 5263 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5264 "send calibration result idx=%d len=%d\n", 5265 idx, sc->calibcmd[idx].len); 5266 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5267 sc->calibcmd[idx].len, 0); 5268 if (error != 0) { 5269 device_printf(sc->sc_dev, 5270 "%s: could not send calibration result, error %d\n", 5271 __func__, error); 5272 return error; 5273 } 5274 } 5275 return 0; 5276 } 5277 5278 static int 5279 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5280 { 5281 struct iwn5000_wimax_coex wimax; 5282 5283 #ifdef notyet 5284 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5285 /* Enable WiMAX coexistence for combo adapters. */ 5286 wimax.flags = 5287 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5288 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5289 IWN_WIMAX_COEX_STA_TABLE_VALID | 5290 IWN_WIMAX_COEX_ENABLE; 5291 memcpy(wimax.events, iwn6050_wimax_events, 5292 sizeof iwn6050_wimax_events); 5293 } else 5294 #endif 5295 { 5296 /* Disable WiMAX coexistence. */ 5297 wimax.flags = 0; 5298 memset(wimax.events, 0, sizeof wimax.events); 5299 } 5300 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 5301 __func__); 5302 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5303 } 5304 5305 /* 5306 * This function is called after the runtime firmware notifies us of its 5307 * readiness (called in a process context.) 5308 */ 5309 static int 5310 iwn4965_post_alive(struct iwn_softc *sc) 5311 { 5312 int error, qid; 5313 5314 if ((error = iwn_nic_lock(sc)) != 0) 5315 return error; 5316 5317 /* Clear TX scheduler state in SRAM. */ 5318 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5319 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5320 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5321 5322 /* Set physical address of TX scheduler rings (1KB aligned.) */ 5323 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5324 5325 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5326 5327 /* Disable chain mode for all our 16 queues. */ 5328 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5329 5330 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5331 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5332 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5333 5334 /* Set scheduler window size. */ 5335 iwn_mem_write(sc, sc->sched_base + 5336 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5337 /* Set scheduler frame limit. */ 5338 iwn_mem_write(sc, sc->sched_base + 5339 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5340 IWN_SCHED_LIMIT << 16); 5341 } 5342 5343 /* Enable interrupts for all our 16 queues. */ 5344 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5345 /* Identify TX FIFO rings (0-7). */ 5346 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5347 5348 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5349 for (qid = 0; qid < 7; qid++) { 5350 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5351 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5352 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5353 } 5354 iwn_nic_unlock(sc); 5355 return 0; 5356 } 5357 5358 /* 5359 * This function is called after the initialization or runtime firmware 5360 * notifies us of its readiness (called in a process context.) 5361 */ 5362 static int 5363 iwn5000_post_alive(struct iwn_softc *sc) 5364 { 5365 int error, qid; 5366 5367 /* Switch to using ICT interrupt mode. */ 5368 iwn5000_ict_reset(sc); 5369 5370 error = iwn_nic_lock(sc); 5371 if (error != 0) 5372 return error; 5373 5374 /* Clear TX scheduler state in SRAM. */ 5375 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5376 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5377 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5378 5379 /* Set physical address of TX scheduler rings (1KB aligned.) */ 5380 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5381 5382 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5383 5384 /* Enable chain mode for all queues, except command queue. */ 5385 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5386 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5387 5388 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5389 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5390 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5391 5392 iwn_mem_write(sc, sc->sched_base + 5393 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5394 /* Set scheduler window size and frame limit. */ 5395 iwn_mem_write(sc, sc->sched_base + 5396 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5397 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5398 } 5399 5400 /* Enable interrupts for all our 20 queues. */ 5401 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5402 /* Identify TX FIFO rings (0-7). */ 5403 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5404 5405 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5406 for (qid = 0; qid < 7; qid++) { 5407 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5408 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5409 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5410 } 5411 iwn_nic_unlock(sc); 5412 5413 /* Configure WiMAX coexistence for combo adapters. */ 5414 error = iwn5000_send_wimax_coex(sc); 5415 if (error != 0) { 5416 device_printf(sc->sc_dev, 5417 "%s: could not configure WiMAX coexistence, error %d\n", 5418 __func__, error); 5419 return error; 5420 } 5421 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5422 struct iwn5000_phy_calib_crystal cmd; 5423 5424 /* Perform crystal calibration. */ 5425 memset(&cmd, 0, sizeof cmd); 5426 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5427 cmd.ngroups = 1; 5428 cmd.isvalid = 1; 5429 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5430 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5431 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5432 "sending crystal calibration %d, %d\n", 5433 cmd.cap_pin[0], cmd.cap_pin[1]); 5434 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5435 if (error != 0) { 5436 device_printf(sc->sc_dev, 5437 "%s: crystal calibration failed, error %d\n", 5438 __func__, error); 5439 return error; 5440 } 5441 } 5442 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5443 /* Query calibration from the initialization firmware. */ 5444 error = iwn5000_query_calibration(sc); 5445 if (error != 0) { 5446 device_printf(sc->sc_dev, 5447 "%s: could not query calibration, error %d\n", 5448 __func__, error); 5449 return error; 5450 } 5451 /* 5452 * We have the calibration results now, reboot with the 5453 * runtime firmware (call ourselves recursively!) 5454 */ 5455 iwn_hw_stop(sc); 5456 error = iwn_hw_init(sc); 5457 } else { 5458 /* Send calibration results to runtime firmware. */ 5459 error = iwn5000_send_calibration(sc); 5460 } 5461 return error; 5462 } 5463 5464 /* 5465 * The firmware boot code is small and is intended to be copied directly into 5466 * the NIC internal memory (no DMA transfer.) 5467 */ 5468 static int 5469 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5470 { 5471 int error, ntries; 5472 5473 size /= sizeof (uint32_t); 5474 5475 error = iwn_nic_lock(sc); 5476 if (error != 0) 5477 return error; 5478 5479 /* Copy microcode image into NIC memory. */ 5480 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5481 (const uint32_t *)ucode, size); 5482 5483 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5484 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5485 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5486 5487 /* Start boot load now. */ 5488 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5489 5490 /* Wait for transfer to complete. */ 5491 for (ntries = 0; ntries < 1000; ntries++) { 5492 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5493 IWN_BSM_WR_CTRL_START)) 5494 break; 5495 DELAY(10); 5496 } 5497 if (ntries == 1000) { 5498 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 5499 __func__); 5500 iwn_nic_unlock(sc); 5501 return ETIMEDOUT; 5502 } 5503 5504 /* Enable boot after power up. */ 5505 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5506 5507 iwn_nic_unlock(sc); 5508 return 0; 5509 } 5510 5511 static int 5512 iwn4965_load_firmware(struct iwn_softc *sc) 5513 { 5514 struct iwn_fw_info *fw = &sc->fw; 5515 struct iwn_dma_info *dma = &sc->fw_dma; 5516 int error; 5517 5518 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5519 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5520 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5521 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5522 fw->init.text, fw->init.textsz); 5523 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5524 5525 /* Tell adapter where to find initialization sections. */ 5526 error = iwn_nic_lock(sc); 5527 if (error != 0) 5528 return error; 5529 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5530 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5531 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5532 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5533 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5534 iwn_nic_unlock(sc); 5535 5536 /* Load firmware boot code. */ 5537 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5538 if (error != 0) { 5539 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 5540 __func__); 5541 return error; 5542 } 5543 /* Now press "execute". */ 5544 IWN_WRITE(sc, IWN_RESET, 0); 5545 5546 /* Wait at most one second for first alive notification. */ 5547 error = zsleep(sc, &wlan_global_serializer, 0, "iwninit", hz); 5548 if (error) { 5549 device_printf(sc->sc_dev, 5550 "%s: timeout waiting for adapter to initialize, error %d\n", 5551 __func__, error); 5552 return error; 5553 } 5554 5555 /* Retrieve current temperature for initial TX power calibration. */ 5556 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5557 sc->temp = iwn4965_get_temperature(sc); 5558 5559 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5560 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5561 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5562 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5563 fw->main.text, fw->main.textsz); 5564 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5565 5566 /* Tell adapter where to find runtime sections. */ 5567 error = iwn_nic_lock(sc); 5568 if (error != 0) 5569 return error; 5570 5571 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5572 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5573 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5574 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5575 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5576 IWN_FW_UPDATED | fw->main.textsz); 5577 iwn_nic_unlock(sc); 5578 5579 return 0; 5580 } 5581 5582 static int 5583 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5584 const uint8_t *section, int size) 5585 { 5586 struct iwn_dma_info *dma = &sc->fw_dma; 5587 int error; 5588 5589 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5590 memcpy(dma->vaddr, section, size); 5591 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5592 5593 error = iwn_nic_lock(sc); 5594 if (error != 0) 5595 return error; 5596 5597 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5598 IWN_FH_TX_CONFIG_DMA_PAUSE); 5599 5600 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5601 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5602 IWN_LOADDR(dma->paddr)); 5603 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5604 IWN_HIADDR(dma->paddr) << 28 | size); 5605 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5606 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5607 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5608 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5609 5610 /* Kick Flow Handler to start DMA transfer. */ 5611 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5612 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5613 5614 iwn_nic_unlock(sc); 5615 5616 /* 5617 * Wait at most five seconds for FH DMA transfer to complete. 5618 */ 5619 error = zsleep(sc, &wlan_global_serializer, 0, "iwninit", hz); 5620 return (error); 5621 } 5622 5623 static int 5624 iwn5000_load_firmware(struct iwn_softc *sc) 5625 { 5626 struct iwn_fw_part *fw; 5627 int error; 5628 5629 /* Load the initialization firmware on first boot only. */ 5630 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5631 &sc->fw.main : &sc->fw.init; 5632 5633 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5634 fw->text, fw->textsz); 5635 if (error != 0) { 5636 device_printf(sc->sc_dev, 5637 "%s: could not load firmware %s section, error %d\n", 5638 __func__, ".text", error); 5639 return error; 5640 } 5641 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5642 fw->data, fw->datasz); 5643 if (error != 0) { 5644 device_printf(sc->sc_dev, 5645 "%s: could not load firmware %s section, error %d\n", 5646 __func__, ".data", error); 5647 return error; 5648 } 5649 5650 /* Now press "execute". */ 5651 IWN_WRITE(sc, IWN_RESET, 0); 5652 return 0; 5653 } 5654 5655 static int 5656 iwn_read_firmware(struct iwn_softc *sc) 5657 { 5658 const struct iwn_hal *hal = sc->sc_hal; 5659 struct iwn_fw_info *fw = &sc->fw; 5660 const uint32_t *ptr; 5661 uint32_t rev; 5662 size_t size; 5663 5664 /* 5665 * Read firmware image from filesystem. The firmware can block 5666 * in a taskq and deadlock against our serializer so unlock 5667 * while we do tihs. 5668 */ 5669 wlan_assert_serialized(); 5670 wlan_serialize_exit(); 5671 sc->fw_fp = firmware_get(sc->fwname); 5672 wlan_serialize_enter(); 5673 if (sc->fw_fp == NULL) { 5674 device_printf(sc->sc_dev, 5675 "%s: could not load firmare image \"%s\"\n", __func__, 5676 sc->fwname); 5677 return EINVAL; 5678 } 5679 5680 size = sc->fw_fp->datasize; 5681 if (size < 28) { 5682 device_printf(sc->sc_dev, 5683 "%s: truncated firmware header: %zu bytes\n", 5684 __func__, size); 5685 return EINVAL; 5686 } 5687 5688 /* Process firmware header. */ 5689 ptr = (const uint32_t *)sc->fw_fp->data; 5690 rev = le32toh(*ptr++); 5691 /* Check firmware API version. */ 5692 if (IWN_FW_API(rev) <= 1) { 5693 device_printf(sc->sc_dev, 5694 "%s: bad firmware, need API version >=2\n", __func__); 5695 return EINVAL; 5696 } 5697 if (IWN_FW_API(rev) >= 3) { 5698 /* Skip build number (version 2 header). */ 5699 size -= 4; 5700 ptr++; 5701 } 5702 fw->main.textsz = le32toh(*ptr++); 5703 fw->main.datasz = le32toh(*ptr++); 5704 fw->init.textsz = le32toh(*ptr++); 5705 fw->init.datasz = le32toh(*ptr++); 5706 fw->boot.textsz = le32toh(*ptr++); 5707 size -= 24; 5708 5709 /* Sanity-check firmware header. */ 5710 if (fw->main.textsz > hal->fw_text_maxsz || 5711 fw->main.datasz > hal->fw_data_maxsz || 5712 fw->init.textsz > hal->fw_text_maxsz || 5713 fw->init.datasz > hal->fw_data_maxsz || 5714 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5715 (fw->boot.textsz & 3) != 0) { 5716 device_printf(sc->sc_dev, "%s: invalid firmware header\n", 5717 __func__); 5718 return EINVAL; 5719 } 5720 5721 /* Check that all firmware sections fit. */ 5722 if (fw->main.textsz + fw->main.datasz + fw->init.textsz + 5723 fw->init.datasz + fw->boot.textsz > size) { 5724 device_printf(sc->sc_dev, 5725 "%s: firmware file too short: %zu bytes\n", 5726 __func__, size); 5727 return EINVAL; 5728 } 5729 5730 /* Get pointers to firmware sections. */ 5731 fw->main.text = (const uint8_t *)ptr; 5732 fw->main.data = fw->main.text + fw->main.textsz; 5733 fw->init.text = fw->main.data + fw->main.datasz; 5734 fw->init.data = fw->init.text + fw->init.textsz; 5735 fw->boot.text = fw->init.data + fw->init.datasz; 5736 5737 return 0; 5738 } 5739 5740 static int 5741 iwn_clock_wait(struct iwn_softc *sc) 5742 { 5743 int ntries; 5744 5745 /* Set "initialization complete" bit. */ 5746 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5747 5748 /* Wait for clock stabilization. */ 5749 for (ntries = 0; ntries < 2500; ntries++) { 5750 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5751 return 0; 5752 DELAY(10); 5753 } 5754 device_printf(sc->sc_dev, 5755 "%s: timeout waiting for clock stabilization\n", __func__); 5756 return ETIMEDOUT; 5757 } 5758 5759 static int 5760 iwn_apm_init(struct iwn_softc *sc) 5761 { 5762 uint32_t tmp; 5763 int error; 5764 5765 /* Disable L0s exit timer (NMI bug workaround.) */ 5766 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5767 /* Don't wait for ICH L0s (ICH bug workaround.) */ 5768 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5769 5770 /* Set FH wait threshold to max (HW bug under stress workaround.) */ 5771 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5772 5773 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5774 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5775 5776 /* Retrieve PCIe Active State Power Management (ASPM). */ 5777 tmp = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 5778 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5779 if (tmp & 0x02) /* L1 Entry enabled. */ 5780 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5781 else 5782 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5783 5784 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5785 sc->hw_type != IWN_HW_REV_TYPE_6000 && 5786 sc->hw_type != IWN_HW_REV_TYPE_6050) 5787 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5788 5789 /* Wait for clock stabilization before accessing prph. */ 5790 error = iwn_clock_wait(sc); 5791 if (error != 0) 5792 return error; 5793 5794 error = iwn_nic_lock(sc); 5795 if (error != 0) 5796 return error; 5797 5798 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5799 /* Enable DMA and BSM (Bootstrap State Machine.) */ 5800 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5801 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5802 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5803 } else { 5804 /* Enable DMA. */ 5805 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5806 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5807 } 5808 DELAY(20); 5809 5810 /* Disable L1-Active. */ 5811 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5812 iwn_nic_unlock(sc); 5813 5814 return 0; 5815 } 5816 5817 static void 5818 iwn_apm_stop_master(struct iwn_softc *sc) 5819 { 5820 int ntries; 5821 5822 /* Stop busmaster DMA activity. */ 5823 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5824 for (ntries = 0; ntries < 100; ntries++) { 5825 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5826 return; 5827 DELAY(10); 5828 } 5829 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", 5830 __func__); 5831 } 5832 5833 static void 5834 iwn_apm_stop(struct iwn_softc *sc) 5835 { 5836 iwn_apm_stop_master(sc); 5837 5838 /* Reset the entire device. */ 5839 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5840 DELAY(10); 5841 /* Clear "initialization complete" bit. */ 5842 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5843 } 5844 5845 static int 5846 iwn4965_nic_config(struct iwn_softc *sc) 5847 { 5848 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5849 /* 5850 * I don't believe this to be correct but this is what the 5851 * vendor driver is doing. Probably the bits should not be 5852 * shifted in IWN_RFCFG_*. 5853 */ 5854 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5855 IWN_RFCFG_TYPE(sc->rfcfg) | 5856 IWN_RFCFG_STEP(sc->rfcfg) | 5857 IWN_RFCFG_DASH(sc->rfcfg)); 5858 } 5859 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5860 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5861 return 0; 5862 } 5863 5864 static int 5865 iwn5000_nic_config(struct iwn_softc *sc) 5866 { 5867 uint32_t tmp; 5868 int error; 5869 5870 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5871 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5872 IWN_RFCFG_TYPE(sc->rfcfg) | 5873 IWN_RFCFG_STEP(sc->rfcfg) | 5874 IWN_RFCFG_DASH(sc->rfcfg)); 5875 } 5876 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5877 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5878 5879 error = iwn_nic_lock(sc); 5880 if (error != 0) 5881 return error; 5882 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5883 5884 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 5885 /* 5886 * Select first Switching Voltage Regulator (1.32V) to 5887 * solve a stability issue related to noisy DC2DC line 5888 * in the silicon of 1000 Series. 5889 */ 5890 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 5891 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 5892 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 5893 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 5894 } 5895 iwn_nic_unlock(sc); 5896 5897 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 5898 /* Use internal power amplifier only. */ 5899 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 5900 } 5901 if (sc->hw_type == IWN_HW_REV_TYPE_6050 && sc->calib_ver >= 6) { 5902 /* Indicate that ROM calibration version is >=6. */ 5903 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 5904 } 5905 return 0; 5906 } 5907 5908 /* 5909 * Take NIC ownership over Intel Active Management Technology (AMT). 5910 */ 5911 static int 5912 iwn_hw_prepare(struct iwn_softc *sc) 5913 { 5914 int ntries; 5915 5916 /* Check if hardware is ready. */ 5917 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5918 for (ntries = 0; ntries < 5; ntries++) { 5919 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5920 IWN_HW_IF_CONFIG_NIC_READY) 5921 return 0; 5922 DELAY(10); 5923 } 5924 5925 /* Hardware not ready, force into ready state. */ 5926 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 5927 for (ntries = 0; ntries < 15000; ntries++) { 5928 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 5929 IWN_HW_IF_CONFIG_PREPARE_DONE)) 5930 break; 5931 DELAY(10); 5932 } 5933 if (ntries == 15000) 5934 return ETIMEDOUT; 5935 5936 /* Hardware should be ready now. */ 5937 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5938 for (ntries = 0; ntries < 5; ntries++) { 5939 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5940 IWN_HW_IF_CONFIG_NIC_READY) 5941 return 0; 5942 DELAY(10); 5943 } 5944 return ETIMEDOUT; 5945 } 5946 5947 static int 5948 iwn_hw_init(struct iwn_softc *sc) 5949 { 5950 const struct iwn_hal *hal = sc->sc_hal; 5951 int error, chnl, qid; 5952 5953 /* Clear pending interrupts. */ 5954 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5955 5956 error = iwn_apm_init(sc); 5957 if (error != 0) { 5958 device_printf(sc->sc_dev, 5959 "%s: could not power ON adapter, error %d\n", 5960 __func__, error); 5961 return error; 5962 } 5963 5964 /* Select VMAIN power source. */ 5965 error = iwn_nic_lock(sc); 5966 if (error != 0) 5967 return error; 5968 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 5969 iwn_nic_unlock(sc); 5970 5971 /* Perform adapter-specific initialization. */ 5972 error = hal->nic_config(sc); 5973 if (error != 0) 5974 return error; 5975 5976 /* Initialize RX ring. */ 5977 error = iwn_nic_lock(sc); 5978 if (error != 0) 5979 return error; 5980 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 5981 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 5982 /* Set physical address of RX ring (256-byte aligned.) */ 5983 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 5984 /* Set physical address of RX status (16-byte aligned.) */ 5985 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 5986 /* Enable RX. */ 5987 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 5988 IWN_FH_RX_CONFIG_ENA | 5989 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 5990 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 5991 IWN_FH_RX_CONFIG_SINGLE_FRAME | 5992 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 5993 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 5994 iwn_nic_unlock(sc); 5995 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 5996 5997 error = iwn_nic_lock(sc); 5998 if (error != 0) 5999 return error; 6000 6001 /* Initialize TX scheduler. */ 6002 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 6003 6004 /* Set physical address of "keep warm" page (16-byte aligned.) */ 6005 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6006 6007 /* Initialize TX rings. */ 6008 for (qid = 0; qid < hal->ntxqs; qid++) { 6009 struct iwn_tx_ring *txq = &sc->txq[qid]; 6010 6011 /* Set physical address of TX ring (256-byte aligned.) */ 6012 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6013 txq->desc_dma.paddr >> 8); 6014 } 6015 iwn_nic_unlock(sc); 6016 6017 /* Enable DMA channels. */ 6018 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 6019 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6020 IWN_FH_TX_CONFIG_DMA_ENA | 6021 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6022 } 6023 6024 /* Clear "radio off" and "commands blocked" bits. */ 6025 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6026 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6027 6028 /* Clear pending interrupts. */ 6029 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6030 /* Enable interrupt coalescing. */ 6031 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6032 /* Enable interrupts. */ 6033 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6034 6035 /* _Really_ make sure "radio off" bit is cleared! */ 6036 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6037 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6038 6039 error = hal->load_firmware(sc); 6040 if (error != 0) { 6041 device_printf(sc->sc_dev, 6042 "%s: could not load firmware, error %d\n", 6043 __func__, error); 6044 return error; 6045 } 6046 /* Wait at most one second for firmware alive notification. */ 6047 error = zsleep(sc, &wlan_global_serializer, 0, "iwninit", hz); 6048 if (error != 0) { 6049 device_printf(sc->sc_dev, 6050 "%s: timeout waiting for adapter to initialize, error %d\n", 6051 __func__, error); 6052 return error; 6053 } 6054 /* Do post-firmware initialization. */ 6055 return hal->post_alive(sc); 6056 } 6057 6058 static void 6059 iwn_hw_stop(struct iwn_softc *sc) 6060 { 6061 const struct iwn_hal *hal = sc->sc_hal; 6062 uint32_t tmp; 6063 int chnl, qid, ntries; 6064 6065 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6066 6067 /* Disable interrupts. */ 6068 IWN_WRITE(sc, IWN_INT_MASK, 0); 6069 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6070 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6071 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6072 6073 /* Make sure we no longer hold the NIC lock. */ 6074 iwn_nic_unlock(sc); 6075 6076 /* Stop TX scheduler. */ 6077 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 6078 6079 /* Stop all DMA channels. */ 6080 if (iwn_nic_lock(sc) == 0) { 6081 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 6082 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6083 for (ntries = 0; ntries < 200; ntries++) { 6084 tmp = IWN_READ(sc, IWN_FH_TX_STATUS); 6085 if ((tmp & IWN_FH_TX_STATUS_IDLE(chnl)) == 6086 IWN_FH_TX_STATUS_IDLE(chnl)) 6087 break; 6088 DELAY(10); 6089 } 6090 } 6091 iwn_nic_unlock(sc); 6092 } 6093 6094 /* Stop RX ring. */ 6095 iwn_reset_rx_ring(sc, &sc->rxq); 6096 6097 /* Reset all TX rings. */ 6098 for (qid = 0; qid < hal->ntxqs; qid++) 6099 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6100 6101 if (iwn_nic_lock(sc) == 0) { 6102 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6103 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6104 iwn_nic_unlock(sc); 6105 } 6106 DELAY(5); 6107 6108 /* Power OFF adapter. */ 6109 iwn_apm_stop(sc); 6110 } 6111 6112 static void 6113 iwn_init_locked(struct iwn_softc *sc) 6114 { 6115 struct ifnet *ifp = sc->sc_ifp; 6116 int error; 6117 6118 error = iwn_hw_prepare(sc); 6119 if (error != 0) { 6120 device_printf(sc->sc_dev, "%s: hardware not ready, eror %d\n", 6121 __func__, error); 6122 goto fail; 6123 } 6124 6125 /* Initialize interrupt mask to default value. */ 6126 sc->int_mask = IWN_INT_MASK_DEF; 6127 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6128 6129 /* Check that the radio is not disabled by hardware switch. */ 6130 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6131 device_printf(sc->sc_dev, 6132 "radio is disabled by hardware switch\n"); 6133 6134 /* Enable interrupts to get RF toggle notifications. */ 6135 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6136 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6137 return; 6138 } 6139 6140 /* Read firmware images from the filesystem. */ 6141 error = iwn_read_firmware(sc); 6142 if (error != 0) { 6143 device_printf(sc->sc_dev, 6144 "%s: could not read firmware, error %d\n", 6145 __func__, error); 6146 goto fail; 6147 } 6148 6149 /* Initialize hardware and upload firmware. */ 6150 error = iwn_hw_init(sc); 6151 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6152 sc->fw_fp = NULL; 6153 if (error != 0) { 6154 device_printf(sc->sc_dev, 6155 "%s: could not initialize hardware, error %d\n", 6156 __func__, error); 6157 goto fail; 6158 } 6159 6160 /* Configure adapter now that it is ready. */ 6161 error = iwn_config(sc); 6162 if (error != 0) { 6163 device_printf(sc->sc_dev, 6164 "%s: could not configure device, error %d\n", 6165 __func__, error); 6166 goto fail; 6167 } 6168 6169 ifp->if_flags &= ~IFF_OACTIVE; 6170 ifp->if_flags |= IFF_RUNNING; 6171 6172 return; 6173 6174 fail: 6175 iwn_stop_locked(sc); 6176 } 6177 6178 static void 6179 iwn_init(void *arg) 6180 { 6181 struct iwn_softc *sc = arg; 6182 struct ifnet *ifp = sc->sc_ifp; 6183 struct ieee80211com *ic = ifp->if_l2com; 6184 6185 iwn_init_locked(sc); 6186 6187 if (ifp->if_flags & IFF_RUNNING) 6188 ieee80211_start_all(ic); 6189 } 6190 6191 static void 6192 iwn_stop_locked(struct iwn_softc *sc) 6193 { 6194 struct ifnet *ifp = sc->sc_ifp; 6195 6196 sc->sc_tx_timer = 0; 6197 callout_stop(&sc->sc_timer_to); 6198 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6199 6200 /* Power OFF hardware. */ 6201 iwn_hw_stop(sc); 6202 } 6203 6204 static void 6205 iwn_stop(struct iwn_softc *sc) 6206 { 6207 iwn_stop_locked(sc); 6208 } 6209 6210 /* 6211 * Callback from net80211 to start a scan. 6212 */ 6213 static void 6214 iwn_scan_start(struct ieee80211com *ic) 6215 { 6216 struct ifnet *ifp = ic->ic_ifp; 6217 struct iwn_softc *sc = ifp->if_softc; 6218 6219 /* make the link LED blink while we're scanning */ 6220 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 6221 } 6222 6223 /* 6224 * Callback from net80211 to terminate a scan. 6225 */ 6226 static void 6227 iwn_scan_end(struct ieee80211com *ic) 6228 { 6229 struct ifnet *ifp = ic->ic_ifp; 6230 struct iwn_softc *sc = ifp->if_softc; 6231 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6232 6233 if (vap->iv_state == IEEE80211_S_RUN) { 6234 /* Set link LED to ON status if we are associated */ 6235 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 6236 } 6237 } 6238 6239 /* 6240 * Callback from net80211 to force a channel change. 6241 */ 6242 static void 6243 iwn_set_channel(struct ieee80211com *ic) 6244 { 6245 const struct ieee80211_channel *c = ic->ic_curchan; 6246 struct ifnet *ifp = ic->ic_ifp; 6247 struct iwn_softc *sc = ifp->if_softc; 6248 6249 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 6250 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 6251 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 6252 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 6253 } 6254 6255 /* 6256 * Callback from net80211 to start scanning of the current channel. 6257 */ 6258 static void 6259 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 6260 { 6261 struct ieee80211vap *vap = ss->ss_vap; 6262 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc; 6263 int error; 6264 6265 error = iwn_scan(sc); 6266 if (error != 0) 6267 ieee80211_cancel_scan(vap); 6268 } 6269 6270 /* 6271 * Callback from net80211 to handle the minimum dwell time being met. 6272 * The intent is to terminate the scan but we just let the firmware 6273 * notify us when it's finished as we have no safe way to abort it. 6274 */ 6275 static void 6276 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 6277 { 6278 /* NB: don't try to abort scan; wait for firmware to finish */ 6279 } 6280 6281 static struct iwn_eeprom_chan * 6282 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 6283 { 6284 int i, j; 6285 6286 for (j = 0; j < 7; j++) { 6287 for (i = 0; i < iwn_bands[j].nchan; i++) { 6288 if (iwn_bands[j].chan[i] == c->ic_ieee) 6289 return &sc->eeprom_channels[j][i]; 6290 } 6291 } 6292 6293 return NULL; 6294 } 6295 6296 /* 6297 * Enforce flags read from EEPROM. 6298 */ 6299 static int 6300 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 6301 int nchan, struct ieee80211_channel chans[]) 6302 { 6303 struct iwn_softc *sc = ic->ic_ifp->if_softc; 6304 int i; 6305 6306 for (i = 0; i < nchan; i++) { 6307 struct ieee80211_channel *c = &chans[i]; 6308 struct iwn_eeprom_chan *channel; 6309 6310 channel = iwn_find_eeprom_channel(sc, c); 6311 if (channel == NULL) { 6312 if_printf(ic->ic_ifp, 6313 "%s: invalid channel %u freq %u/0x%x\n", 6314 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 6315 return EINVAL; 6316 } 6317 c->ic_flags |= iwn_eeprom_channel_flags(channel); 6318 } 6319 6320 return 0; 6321 } 6322 6323 static void 6324 iwn_hw_reset_task(void *arg0, int pending) 6325 { 6326 struct iwn_softc *sc = arg0; 6327 struct ifnet *ifp; 6328 struct ieee80211com *ic; 6329 6330 wlan_serialize_enter(); 6331 ifp = sc->sc_ifp; 6332 ic = ifp->if_l2com; 6333 iwn_stop(sc); 6334 iwn_init(sc); 6335 ieee80211_notify_radio(ic, 1); 6336 wlan_serialize_exit(); 6337 } 6338 6339 static void 6340 iwn_radio_on_task(void *arg0, int pending) 6341 { 6342 struct iwn_softc *sc = arg0; 6343 struct ifnet *ifp; 6344 struct ieee80211com *ic; 6345 struct ieee80211vap *vap; 6346 6347 wlan_serialize_enter(); 6348 ifp = sc->sc_ifp; 6349 ic = ifp->if_l2com; 6350 vap = TAILQ_FIRST(&ic->ic_vaps); 6351 if (vap != NULL) { 6352 iwn_init(sc); 6353 ieee80211_init(vap); 6354 } 6355 wlan_serialize_exit(); 6356 } 6357 6358 static void 6359 iwn_radio_off_task(void *arg0, int pending) 6360 { 6361 struct iwn_softc *sc = arg0; 6362 struct ifnet *ifp; 6363 struct ieee80211com *ic; 6364 struct ieee80211vap *vap; 6365 6366 wlan_serialize_enter(); 6367 ifp = sc->sc_ifp; 6368 ic = ifp->if_l2com; 6369 vap = TAILQ_FIRST(&ic->ic_vaps); 6370 iwn_stop(sc); 6371 if (vap != NULL) 6372 ieee80211_stop(vap); 6373 6374 /* Enable interrupts to get RF toggle notification. */ 6375 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6376 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6377 wlan_serialize_exit(); 6378 } 6379 6380 static void 6381 iwn_sysctlattach(struct iwn_softc *sc) 6382 { 6383 struct sysctl_ctx_list *ctx; 6384 struct sysctl_oid *tree; 6385 6386 ctx = &sc->sc_sysctl_ctx; 6387 tree = sc->sc_sysctl_tree; 6388 if (tree == NULL) { 6389 device_printf(sc->sc_dev, "can't add sysctl node\n"); 6390 return; 6391 } 6392 6393 #ifdef IWN_DEBUG 6394 sc->sc_debug = 0; 6395 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6396 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 6397 #endif 6398 } 6399 6400 static int 6401 iwn_pci_shutdown(device_t dev) 6402 { 6403 struct iwn_softc *sc = device_get_softc(dev); 6404 6405 wlan_serialize_enter(); 6406 iwn_stop(sc); 6407 wlan_serialize_exit(); 6408 6409 return 0; 6410 } 6411 6412 static int 6413 iwn_pci_suspend(device_t dev) 6414 { 6415 struct iwn_softc *sc = device_get_softc(dev); 6416 struct ifnet *ifp = sc->sc_ifp; 6417 struct ieee80211com *ic = ifp->if_l2com; 6418 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6419 6420 wlan_serialize_enter(); 6421 iwn_stop(sc); 6422 if (vap != NULL) 6423 ieee80211_stop(vap); 6424 wlan_serialize_exit(); 6425 6426 return 0; 6427 } 6428 6429 static int 6430 iwn_pci_resume(device_t dev) 6431 { 6432 struct iwn_softc *sc = device_get_softc(dev); 6433 struct ifnet *ifp; 6434 struct ieee80211com *ic; 6435 struct ieee80211vap *vap; 6436 6437 wlan_serialize_enter(); 6438 ifp = sc->sc_ifp; 6439 ic = ifp->if_l2com; 6440 vap = TAILQ_FIRST(&ic->ic_vaps); 6441 /* Clear device-specific "PCI retry timeout" register (41h). */ 6442 pci_write_config(dev, 0x41, 0, 1); 6443 6444 if (ifp->if_flags & IFF_UP) { 6445 iwn_init(sc); 6446 if (vap != NULL) 6447 ieee80211_init(vap); 6448 if (ifp->if_flags & IFF_RUNNING) 6449 iwn_start(ifp); 6450 } 6451 wlan_serialize_exit(); 6452 6453 return 0; 6454 } 6455 6456 #ifdef IWN_DEBUG 6457 static const char * 6458 iwn_intr_str(uint8_t cmd) 6459 { 6460 switch (cmd) { 6461 /* Notifications */ 6462 case IWN_UC_READY: return "UC_READY"; 6463 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE"; 6464 case IWN_TX_DONE: return "TX_DONE"; 6465 case IWN_START_SCAN: return "START_SCAN"; 6466 case IWN_STOP_SCAN: return "STOP_SCAN"; 6467 case IWN_RX_STATISTICS: return "RX_STATS"; 6468 case IWN_BEACON_STATISTICS: return "BEACON_STATS"; 6469 case IWN_STATE_CHANGED: return "STATE_CHANGED"; 6470 case IWN_BEACON_MISSED: return "BEACON_MISSED"; 6471 case IWN_RX_PHY: return "RX_PHY"; 6472 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE"; 6473 case IWN_RX_DONE: return "RX_DONE"; 6474 6475 /* Command Notifications */ 6476 case IWN_CMD_RXON: return "IWN_CMD_RXON"; 6477 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC"; 6478 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS"; 6479 case IWN_CMD_TIMING: return "IWN_CMD_TIMING"; 6480 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY"; 6481 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED"; 6482 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX"; 6483 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG"; 6484 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT"; 6485 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE"; 6486 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE"; 6487 case IWN_CMD_SCAN: return "IWN_CMD_SCAN"; 6488 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS"; 6489 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER"; 6490 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM"; 6491 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG"; 6492 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX"; 6493 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP"; 6494 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY"; 6495 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB"; 6496 } 6497 return "UNKNOWN INTR NOTIF/CMD"; 6498 } 6499 #endif /* IWN_DEBUG */ 6500 6501 static device_method_t iwn_methods[] = { 6502 /* Device interface */ 6503 DEVMETHOD(device_probe, iwn_pci_probe), 6504 DEVMETHOD(device_attach, iwn_pci_attach), 6505 DEVMETHOD(device_detach, iwn_pci_detach), 6506 DEVMETHOD(device_shutdown, iwn_pci_shutdown), 6507 DEVMETHOD(device_suspend, iwn_pci_suspend), 6508 DEVMETHOD(device_resume, iwn_pci_resume), 6509 { 0, 0 } 6510 }; 6511 6512 static driver_t iwn_driver = { 6513 "iwn", 6514 iwn_methods, 6515 sizeof (struct iwn_softc) 6516 }; 6517 static devclass_t iwn_devclass; 6518 6519 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0); 6520 MODULE_DEPEND(iwn, pci, 1, 1, 1); 6521 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 6522 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 6523 MODULE_DEPEND(iwn, wlan_amrr, 1, 1, 1); 6524