1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_x550.h" 36 #include "ixgbe_x540.h" 37 #include "ixgbe_type.h" 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_phy.h" 41 42 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed); 43 44 /** 45 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type 46 * @hw: pointer to hardware structure 47 * 48 * Initialize the function pointers and assign the MAC type for X550. 49 * Does not touch the hardware. 50 **/ 51 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw) 52 { 53 struct ixgbe_mac_info *mac = &hw->mac; 54 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 55 s32 ret_val; 56 57 DEBUGFUNC("ixgbe_init_ops_X550"); 58 59 ret_val = ixgbe_init_ops_X540(hw); 60 mac->ops.dmac_config = ixgbe_dmac_config_X550; 61 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550; 62 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550; 63 mac->ops.setup_eee = ixgbe_setup_eee_X550; 64 mac->ops.set_source_address_pruning = 65 ixgbe_set_source_address_pruning_X550; 66 mac->ops.set_ethertype_anti_spoofing = 67 ixgbe_set_ethertype_anti_spoofing_X550; 68 69 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 70 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550; 71 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 72 eeprom->ops.read = ixgbe_read_ee_hostif_X550; 73 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 74 eeprom->ops.write = ixgbe_write_ee_hostif_X550; 75 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 76 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 77 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 78 79 mac->ops.disable_mdd = ixgbe_disable_mdd_X550; 80 mac->ops.enable_mdd = ixgbe_enable_mdd_X550; 81 mac->ops.mdd_event = ixgbe_mdd_event_X550; 82 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550; 83 mac->ops.disable_rx = ixgbe_disable_rx_x550; 84 return ret_val; 85 } 86 87 /** 88 * ixgbe_read_cs4227 - Read CS4227 register 89 * @hw: pointer to hardware structure 90 * @reg: register number to write 91 * @value: pointer to receive value read 92 * 93 * Returns status code 94 **/ 95 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 96 { 97 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value); 98 } 99 100 /** 101 * ixgbe_write_cs4227 - Write CS4227 register 102 * @hw: pointer to hardware structure 103 * @reg: register number to write 104 * @value: value to write to register 105 * 106 * Returns status code 107 **/ 108 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 109 { 110 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value); 111 } 112 113 /** 114 * ixgbe_get_cs4227_status - Return CS4227 status 115 * @hw: pointer to hardware structure 116 * 117 * Returns error if CS4227 not successfully initialized 118 **/ 119 static s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw) 120 { 121 s32 status; 122 u16 value = 0; 123 u16 reg_slice, reg_val; 124 u8 retry; 125 126 for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) { 127 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB, 128 &value); 129 if (status != IXGBE_SUCCESS) 130 return status; 131 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE) 132 break; 133 msec_delay(IXGBE_CS4227_CHECK_DELAY); 134 } 135 if (value != IXGBE_CS4227_GLOBAL_ID_VALUE) 136 return IXGBE_ERR_PHY; 137 138 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 139 if (status != IXGBE_SUCCESS) 140 return status; 141 142 /* If this is the first time after power-on, check the ucode. 143 * Otherwise, this will disrupt link on all ports. Because we 144 * can only do this the first time, we must check all ports, 145 * not just our own. 146 */ 147 if (value != IXGBE_CS4227_SCRATCH_VALUE) { 148 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB; 149 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 150 status = ixgbe_write_cs4227(hw, reg_slice, 151 reg_val); 152 if (status != IXGBE_SUCCESS) 153 return status; 154 155 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB; 156 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 157 status = ixgbe_write_cs4227(hw, reg_slice, 158 reg_val); 159 if (status != IXGBE_SUCCESS) 160 return status; 161 162 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12); 163 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 164 status = ixgbe_write_cs4227(hw, reg_slice, 165 reg_val); 166 if (status != IXGBE_SUCCESS) 167 return status; 168 169 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12); 170 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 171 status = ixgbe_write_cs4227(hw, reg_slice, 172 reg_val); 173 if (status != IXGBE_SUCCESS) 174 return status; 175 176 msec_delay(10); 177 } 178 179 /* Verify that the ucode is operational on all ports. */ 180 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB; 181 reg_val = 0xFFFF; 182 status = ixgbe_read_cs4227(hw, reg_slice, ®_val); 183 if (status != IXGBE_SUCCESS) 184 return status; 185 if (reg_val != 0) 186 return IXGBE_ERR_PHY; 187 188 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB; 189 reg_val = 0xFFFF; 190 status = ixgbe_read_cs4227(hw, reg_slice, ®_val); 191 if (status != IXGBE_SUCCESS) 192 return status; 193 if (reg_val != 0) 194 return IXGBE_ERR_PHY; 195 196 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12); 197 reg_val = 0xFFFF; 198 status = ixgbe_read_cs4227(hw, reg_slice, ®_val); 199 if (status != IXGBE_SUCCESS) 200 return status; 201 if (reg_val != 0) 202 return IXGBE_ERR_PHY; 203 204 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12); 205 reg_val = 0xFFFF; 206 status = ixgbe_read_cs4227(hw, reg_slice, ®_val); 207 if (status != IXGBE_SUCCESS) 208 return status; 209 if (reg_val != 0) 210 return IXGBE_ERR_PHY; 211 212 /* Set scratch for next time. */ 213 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 214 IXGBE_CS4227_SCRATCH_VALUE); 215 if (status != IXGBE_SUCCESS) 216 return status; 217 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 218 if (status != IXGBE_SUCCESS) 219 return status; 220 if (value != IXGBE_CS4227_SCRATCH_VALUE) 221 return IXGBE_ERR_PHY; 222 223 return IXGBE_SUCCESS; 224 } 225 226 /** 227 * ixgbe_read_pe - Read register from port expander 228 * @hw: pointer to hardware structure 229 * @reg: register number to read 230 * @value: pointer to receive read value 231 * 232 * Returns status code 233 **/ 234 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 235 { 236 s32 status; 237 238 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 239 if (status != IXGBE_SUCCESS) 240 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 241 "port expander access failed with %d\n", status); 242 return status; 243 } 244 245 /** 246 * ixgbe_write_pe - Write register to port expander 247 * @hw: pointer to hardware structure 248 * @reg: register number to write 249 * @value: value to write 250 * 251 * Returns status code 252 **/ 253 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 254 { 255 s32 status; 256 257 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 258 if (status != IXGBE_SUCCESS) 259 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 260 "port expander access failed with %d\n", status); 261 return status; 262 } 263 264 /** 265 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 266 * @hw: pointer to hardware structure 267 * 268 * Returns error code 269 **/ 270 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 271 { 272 s32 status; 273 u8 reg; 274 275 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 276 if (status != IXGBE_SUCCESS) 277 return status; 278 reg |= IXGBE_PE_BIT1; 279 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 280 if (status != IXGBE_SUCCESS) 281 return status; 282 283 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 284 if (status != IXGBE_SUCCESS) 285 return status; 286 reg &= ~IXGBE_PE_BIT1; 287 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 288 if (status != IXGBE_SUCCESS) 289 return status; 290 291 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 292 if (status != IXGBE_SUCCESS) 293 return status; 294 reg &= ~IXGBE_PE_BIT1; 295 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 296 if (status != IXGBE_SUCCESS) 297 return status; 298 299 usec_delay(IXGBE_CS4227_RESET_HOLD); 300 301 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 302 if (status != IXGBE_SUCCESS) 303 return status; 304 reg |= IXGBE_PE_BIT1; 305 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 306 if (status != IXGBE_SUCCESS) 307 return status; 308 309 msec_delay(IXGBE_CS4227_RESET_DELAY); 310 311 return IXGBE_SUCCESS; 312 } 313 314 /** 315 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 316 * @hw: pointer to hardware structure 317 **/ 318 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 319 { 320 u32 swfw_mask = hw->phy.phy_semaphore_mask; 321 s32 status; 322 u8 retry; 323 324 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 325 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 326 if (status != IXGBE_SUCCESS) { 327 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 328 "semaphore failed with %d\n", status); 329 return; 330 } 331 status = ixgbe_get_cs4227_status(hw); 332 if (status == IXGBE_SUCCESS) { 333 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 334 msec_delay(hw->eeprom.semaphore_delay); 335 return; 336 } 337 ixgbe_reset_cs4227(hw); 338 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 339 msec_delay(hw->eeprom.semaphore_delay); 340 } 341 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 342 "Unable to initialize CS4227, err=%d\n", status); 343 } 344 345 /** 346 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 347 * @hw: pointer to hardware structure 348 **/ 349 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 350 { 351 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 352 353 if (hw->bus.lan_id) { 354 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 355 esdp |= IXGBE_ESDP_SDP1_DIR; 356 } 357 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 358 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 359 IXGBE_WRITE_FLUSH(hw); 360 } 361 362 /** 363 * ixgbe_identify_phy_x550em - Get PHY type based on device id 364 * @hw: pointer to hardware structure 365 * 366 * Returns error code 367 */ 368 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 369 { 370 switch (hw->device_id) { 371 case IXGBE_DEV_ID_X550EM_X_SFP: 372 /* set up for CS4227 usage */ 373 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 374 ixgbe_setup_mux_ctl(hw); 375 ixgbe_check_cs4227(hw); 376 377 return ixgbe_identify_module_generic(hw); 378 break; 379 case IXGBE_DEV_ID_X550EM_X_KX4: 380 hw->phy.type = ixgbe_phy_x550em_kx4; 381 break; 382 case IXGBE_DEV_ID_X550EM_X_KR: 383 hw->phy.type = ixgbe_phy_x550em_kr; 384 break; 385 case IXGBE_DEV_ID_X550EM_X_1G_T: 386 case IXGBE_DEV_ID_X550EM_X_10G_T: 387 return ixgbe_identify_phy_generic(hw); 388 default: 389 break; 390 } 391 return IXGBE_SUCCESS; 392 } 393 394 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 395 u32 device_type, u16 *phy_data) 396 { 397 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data); 398 return IXGBE_NOT_IMPLEMENTED; 399 } 400 401 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 402 u32 device_type, u16 phy_data) 403 { 404 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data); 405 return IXGBE_NOT_IMPLEMENTED; 406 } 407 408 /** 409 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type 410 * @hw: pointer to hardware structure 411 * 412 * Initialize the function pointers and for MAC type X550EM. 413 * Does not touch the hardware. 414 **/ 415 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw) 416 { 417 struct ixgbe_mac_info *mac = &hw->mac; 418 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 419 struct ixgbe_phy_info *phy = &hw->phy; 420 s32 ret_val; 421 422 DEBUGFUNC("ixgbe_init_ops_X550EM"); 423 424 /* Similar to X550 so start there. */ 425 ret_val = ixgbe_init_ops_X550(hw); 426 427 /* Since this function eventually calls 428 * ixgbe_init_ops_540 by design, we are setting 429 * the pointers to NULL explicitly here to overwrite 430 * the values being set in the x540 function. 431 */ 432 433 /* FCOE not supported in x550EM */ 434 mac->ops.get_san_mac_addr = NULL; 435 mac->ops.set_san_mac_addr = NULL; 436 mac->ops.get_wwn_prefix = NULL; 437 mac->ops.get_fcoe_boot_status = NULL; 438 439 /* IPsec not supported in x550EM */ 440 mac->ops.disable_sec_rx_path = NULL; 441 mac->ops.enable_sec_rx_path = NULL; 442 443 /* AUTOC register is not present in x550EM. */ 444 mac->ops.prot_autoc_read = NULL; 445 mac->ops.prot_autoc_write = NULL; 446 447 /* X550EM bus type is internal*/ 448 hw->bus.type = ixgbe_bus_type_internal; 449 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em; 450 451 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 452 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 453 mac->ops.get_media_type = ixgbe_get_media_type_X550em; 454 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em; 455 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em; 456 mac->ops.reset_hw = ixgbe_reset_hw_X550em; 457 mac->ops.get_supported_physical_layer = 458 ixgbe_get_supported_physical_layer_X550em; 459 460 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) 461 mac->ops.setup_fc = ixgbe_setup_fc_generic; 462 else 463 mac->ops.setup_fc = ixgbe_setup_fc_X550em; 464 465 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em; 466 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em; 467 468 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR) 469 mac->ops.setup_eee = NULL; 470 471 /* PHY */ 472 phy->ops.init = ixgbe_init_phy_ops_X550em; 473 phy->ops.identify = ixgbe_identify_phy_x550em; 474 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 475 phy->ops.set_phy_power = NULL; 476 477 478 /* EEPROM */ 479 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 480 eeprom->ops.read = ixgbe_read_ee_hostif_X550; 481 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 482 eeprom->ops.write = ixgbe_write_ee_hostif_X550; 483 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 484 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 485 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 486 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 487 488 return ret_val; 489 } 490 491 /** 492 * ixgbe_dmac_config_X550 493 * @hw: pointer to hardware structure 494 * 495 * Configure DMA coalescing. If enabling dmac, dmac is activated. 496 * When disabling dmac, dmac enable dmac bit is cleared. 497 **/ 498 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw) 499 { 500 u32 reg, high_pri_tc; 501 502 DEBUGFUNC("ixgbe_dmac_config_X550"); 503 504 /* Disable DMA coalescing before configuring */ 505 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 506 reg &= ~IXGBE_DMACR_DMAC_EN; 507 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 508 509 /* Disable DMA Coalescing if the watchdog timer is 0 */ 510 if (!hw->mac.dmac_config.watchdog_timer) 511 goto out; 512 513 ixgbe_dmac_config_tcs_X550(hw); 514 515 /* Configure DMA Coalescing Control Register */ 516 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 517 518 /* Set the watchdog timer in units of 40.96 usec */ 519 reg &= ~IXGBE_DMACR_DMACWT_MASK; 520 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096; 521 522 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK; 523 /* If fcoe is enabled, set high priority traffic class */ 524 if (hw->mac.dmac_config.fcoe_en) { 525 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc; 526 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) & 527 IXGBE_DMACR_HIGH_PRI_TC_MASK); 528 } 529 reg |= IXGBE_DMACR_EN_MNG_IND; 530 531 /* Enable DMA coalescing after configuration */ 532 reg |= IXGBE_DMACR_DMAC_EN; 533 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 534 535 out: 536 return IXGBE_SUCCESS; 537 } 538 539 /** 540 * ixgbe_dmac_config_tcs_X550 541 * @hw: pointer to hardware structure 542 * 543 * Configure DMA coalescing threshold per TC. The dmac enable bit must 544 * be cleared before configuring. 545 **/ 546 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw) 547 { 548 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb; 549 550 DEBUGFUNC("ixgbe_dmac_config_tcs_X550"); 551 552 /* Configure DMA coalescing enabled */ 553 switch (hw->mac.dmac_config.link_speed) { 554 case IXGBE_LINK_SPEED_100_FULL: 555 pb_headroom = IXGBE_DMACRXT_100M; 556 break; 557 case IXGBE_LINK_SPEED_1GB_FULL: 558 pb_headroom = IXGBE_DMACRXT_1G; 559 break; 560 default: 561 pb_headroom = IXGBE_DMACRXT_10G; 562 break; 563 } 564 565 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >> 566 IXGBE_MHADD_MFS_SHIFT) / 1024); 567 568 /* Set the per Rx packet buffer receive threshold */ 569 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) { 570 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc)); 571 reg &= ~IXGBE_DMCTH_DMACRXT_MASK; 572 573 if (tc < hw->mac.dmac_config.num_tcs) { 574 /* Get Rx PB size */ 575 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc)); 576 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >> 577 IXGBE_RXPBSIZE_SHIFT; 578 579 /* Calculate receive buffer threshold in kilobytes */ 580 if (rx_pb_size > pb_headroom) 581 rx_pb_size = rx_pb_size - pb_headroom; 582 else 583 rx_pb_size = 0; 584 585 /* Minimum of MFS shall be set for DMCTH */ 586 reg |= (rx_pb_size > maxframe_size_kb) ? 587 rx_pb_size : maxframe_size_kb; 588 } 589 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg); 590 } 591 return IXGBE_SUCCESS; 592 } 593 594 /** 595 * ixgbe_dmac_update_tcs_X550 596 * @hw: pointer to hardware structure 597 * 598 * Disables dmac, updates per TC settings, and then enables dmac. 599 **/ 600 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw) 601 { 602 u32 reg; 603 604 DEBUGFUNC("ixgbe_dmac_update_tcs_X550"); 605 606 /* Disable DMA coalescing before configuring */ 607 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 608 reg &= ~IXGBE_DMACR_DMAC_EN; 609 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 610 611 ixgbe_dmac_config_tcs_X550(hw); 612 613 /* Enable DMA coalescing after configuration */ 614 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 615 reg |= IXGBE_DMACR_DMAC_EN; 616 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 617 618 return IXGBE_SUCCESS; 619 } 620 621 /** 622 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 623 * @hw: pointer to hardware structure 624 * 625 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 626 * ixgbe_hw struct in order to set up EEPROM access. 627 **/ 628 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 629 { 630 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 631 u32 eec; 632 u16 eeprom_size; 633 634 DEBUGFUNC("ixgbe_init_eeprom_params_X550"); 635 636 if (eeprom->type == ixgbe_eeprom_uninitialized) { 637 eeprom->semaphore_delay = 10; 638 eeprom->type = ixgbe_flash; 639 640 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 641 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 642 IXGBE_EEC_SIZE_SHIFT); 643 eeprom->word_size = 1 << (eeprom_size + 644 IXGBE_EEPROM_WORD_SIZE_SHIFT); 645 646 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 647 eeprom->type, eeprom->word_size); 648 } 649 650 return IXGBE_SUCCESS; 651 } 652 653 /** 654 * ixgbe_setup_eee_X550 - Enable/disable EEE support 655 * @hw: pointer to the HW structure 656 * @enable_eee: boolean flag to enable EEE 657 * 658 * Enable/disable EEE based on enable_eee flag. 659 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 660 * are modified. 661 * 662 **/ 663 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee) 664 { 665 u32 eeer; 666 u16 autoneg_eee_reg; 667 u32 link_reg; 668 s32 status; 669 670 DEBUGFUNC("ixgbe_setup_eee_X550"); 671 672 eeer = IXGBE_READ_REG(hw, IXGBE_EEER); 673 /* Enable or disable EEE per flag */ 674 if (enable_eee) { 675 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); 676 677 if (hw->device_id == IXGBE_DEV_ID_X550T) { 678 /* Advertise EEE capability */ 679 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 680 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); 681 682 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | 683 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | 684 IXGBE_AUTO_NEG_100BASE_EEE_ADVT); 685 686 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 687 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg); 688 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 689 status = ixgbe_read_iosf_sb_reg_x550(hw, 690 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 691 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg); 692 if (status != IXGBE_SUCCESS) 693 return status; 694 695 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR | 696 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX; 697 698 /* Must disable FEC when EEE is enabled. */ 699 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ | 700 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC); 701 702 status = ixgbe_write_iosf_sb_reg_x550(hw, 703 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 704 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); 705 if (status != IXGBE_SUCCESS) 706 return status; 707 } 708 } else { 709 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); 710 711 if (hw->device_id == IXGBE_DEV_ID_X550T) { 712 /* Disable advertised EEE capability */ 713 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 714 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); 715 716 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | 717 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | 718 IXGBE_AUTO_NEG_100BASE_EEE_ADVT); 719 720 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 721 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg); 722 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 723 status = ixgbe_read_iosf_sb_reg_x550(hw, 724 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 725 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg); 726 if (status != IXGBE_SUCCESS) 727 return status; 728 729 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR | 730 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX); 731 732 /* Enable FEC when EEE is disabled. */ 733 link_reg |= (IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ | 734 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC); 735 736 status = ixgbe_write_iosf_sb_reg_x550(hw, 737 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 738 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); 739 if (status != IXGBE_SUCCESS) 740 return status; 741 } 742 } 743 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer); 744 745 return IXGBE_SUCCESS; 746 } 747 748 /** 749 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning 750 * @hw: pointer to hardware structure 751 * @enable: enable or disable source address pruning 752 * @pool: Rx pool to set source address pruning for 753 **/ 754 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable, 755 unsigned int pool) 756 { 757 u64 pfflp; 758 759 /* max rx pool is 63 */ 760 if (pool > 63) 761 return; 762 763 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 764 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 765 766 if (enable) 767 pfflp |= (1ULL << pool); 768 else 769 pfflp &= ~(1ULL << pool); 770 771 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 772 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 773 } 774 775 /** 776 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing 777 * @hw: pointer to hardware structure 778 * @enable: enable or disable switch for Ethertype anti-spoofing 779 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 780 * 781 **/ 782 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 783 bool enable, int vf) 784 { 785 int vf_target_reg = vf >> 3; 786 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 787 u32 pfvfspoof; 788 789 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550"); 790 791 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 792 if (enable) 793 pfvfspoof |= (1 << vf_target_shift); 794 else 795 pfvfspoof &= ~(1 << vf_target_shift); 796 797 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 798 } 799 800 /** 801 * ixgbe_iosf_wait - Wait for IOSF command completion 802 * @hw: pointer to hardware structure 803 * @ctrl: pointer to location to receive final IOSF control value 804 * 805 * Returns failing status on timeout 806 * 807 * Note: ctrl can be NULL if the IOSF control register value is not needed 808 **/ 809 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 810 { 811 u32 i, command; 812 813 /* Check every 10 usec to see if the address cycle completed. 814 * The SB IOSF BUSY bit will clear when the operation is 815 * complete 816 */ 817 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 818 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 819 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) 820 break; 821 usec_delay(10); 822 } 823 if (ctrl) 824 *ctrl = command; 825 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 826 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n"); 827 return IXGBE_ERR_PHY; 828 } 829 830 return IXGBE_SUCCESS; 831 } 832 833 /** 834 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF 835 * device 836 * @hw: pointer to hardware structure 837 * @reg_addr: 32 bit PHY register to write 838 * @device_type: 3 bit device type 839 * @data: Data to write to the register 840 **/ 841 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 842 u32 device_type, u32 data) 843 { 844 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 845 u32 command, error; 846 s32 ret; 847 848 ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 849 if (ret != IXGBE_SUCCESS) 850 return ret; 851 852 ret = ixgbe_iosf_wait(hw, NULL); 853 if (ret != IXGBE_SUCCESS) 854 goto out; 855 856 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 857 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 858 859 /* Write IOSF control register */ 860 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 861 862 /* Write IOSF data register */ 863 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 864 865 ret = ixgbe_iosf_wait(hw, &command); 866 867 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 868 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 869 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 870 ERROR_REPORT2(IXGBE_ERROR_POLLING, 871 "Failed to write, error %x\n", error); 872 ret = IXGBE_ERR_PHY; 873 } 874 875 out: 876 ixgbe_release_swfw_semaphore(hw, gssr); 877 return ret; 878 } 879 880 /** 881 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF 882 * device 883 * @hw: pointer to hardware structure 884 * @reg_addr: 32 bit PHY register to write 885 * @device_type: 3 bit device type 886 * @phy_data: Pointer to read data from the register 887 **/ 888 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 889 u32 device_type, u32 *data) 890 { 891 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 892 u32 command, error; 893 s32 ret; 894 895 ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 896 if (ret != IXGBE_SUCCESS) 897 return ret; 898 899 ret = ixgbe_iosf_wait(hw, NULL); 900 if (ret != IXGBE_SUCCESS) 901 goto out; 902 903 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 904 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 905 906 /* Write IOSF control register */ 907 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 908 909 ret = ixgbe_iosf_wait(hw, &command); 910 911 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 912 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 913 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 914 ERROR_REPORT2(IXGBE_ERROR_POLLING, 915 "Failed to read, error %x\n", error); 916 ret = IXGBE_ERR_PHY; 917 } 918 919 if (ret == IXGBE_SUCCESS) 920 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 921 922 out: 923 ixgbe_release_swfw_semaphore(hw, gssr); 924 return ret; 925 } 926 927 /** 928 * ixgbe_disable_mdd_X550 929 * @hw: pointer to hardware structure 930 * 931 * Disable malicious driver detection 932 **/ 933 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw) 934 { 935 u32 reg; 936 937 DEBUGFUNC("ixgbe_disable_mdd_X550"); 938 939 /* Disable MDD for TX DMA and interrupt */ 940 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 941 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 942 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 943 944 /* Disable MDD for RX and interrupt */ 945 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 946 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 947 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 948 } 949 950 /** 951 * ixgbe_enable_mdd_X550 952 * @hw: pointer to hardware structure 953 * 954 * Enable malicious driver detection 955 **/ 956 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw) 957 { 958 u32 reg; 959 960 DEBUGFUNC("ixgbe_enable_mdd_X550"); 961 962 /* Enable MDD for TX DMA and interrupt */ 963 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 964 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 965 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 966 967 /* Enable MDD for RX and interrupt */ 968 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 969 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 970 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 971 } 972 973 /** 974 * ixgbe_restore_mdd_vf_X550 975 * @hw: pointer to hardware structure 976 * @vf: vf index 977 * 978 * Restore VF that was disabled during malicious driver detection event 979 **/ 980 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf) 981 { 982 u32 idx, reg, num_qs, start_q, bitmask; 983 984 DEBUGFUNC("ixgbe_restore_mdd_vf_X550"); 985 986 /* Map VF to queues */ 987 reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 988 switch (reg & IXGBE_MRQC_MRQE_MASK) { 989 case IXGBE_MRQC_VMDQRT8TCEN: 990 num_qs = 8; /* 16 VFs / pools */ 991 bitmask = 0x000000FF; 992 break; 993 case IXGBE_MRQC_VMDQRSS32EN: 994 case IXGBE_MRQC_VMDQRT4TCEN: 995 num_qs = 4; /* 32 VFs / pools */ 996 bitmask = 0x0000000F; 997 break; 998 default: /* 64 VFs / pools */ 999 num_qs = 2; 1000 bitmask = 0x00000003; 1001 break; 1002 } 1003 start_q = vf * num_qs; 1004 1005 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */ 1006 idx = start_q / 32; 1007 reg = 0; 1008 reg |= (bitmask << (start_q % 32)); 1009 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg); 1010 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg); 1011 } 1012 1013 /** 1014 * ixgbe_mdd_event_X550 1015 * @hw: pointer to hardware structure 1016 * @vf_bitmap: vf bitmap of malicious vfs 1017 * 1018 * Handle malicious driver detection event. 1019 **/ 1020 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap) 1021 { 1022 u32 wqbr; 1023 u32 i, j, reg, q, shift, vf, idx; 1024 1025 DEBUGFUNC("ixgbe_mdd_event_X550"); 1026 1027 /* figure out pool size for mapping to vf's */ 1028 reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 1029 switch (reg & IXGBE_MRQC_MRQE_MASK) { 1030 case IXGBE_MRQC_VMDQRT8TCEN: 1031 shift = 3; /* 16 VFs / pools */ 1032 break; 1033 case IXGBE_MRQC_VMDQRSS32EN: 1034 case IXGBE_MRQC_VMDQRT4TCEN: 1035 shift = 2; /* 32 VFs / pools */ 1036 break; 1037 default: 1038 shift = 1; /* 64 VFs / pools */ 1039 break; 1040 } 1041 1042 /* Read WQBR_TX and WQBR_RX and check for malicious queues */ 1043 for (i = 0; i < 4; i++) { 1044 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i)); 1045 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i)); 1046 1047 if (!wqbr) 1048 continue; 1049 1050 /* Get malicious queue */ 1051 for (j = 0; j < 32 && wqbr; j++) { 1052 1053 if (!(wqbr & (1 << j))) 1054 continue; 1055 1056 /* Get queue from bitmask */ 1057 q = j + (i * 32); 1058 1059 /* Map queue to vf */ 1060 vf = (q >> shift); 1061 1062 /* Set vf bit in vf_bitmap */ 1063 idx = vf / 32; 1064 vf_bitmap[idx] |= (1 << (vf % 32)); 1065 wqbr &= ~(1 << j); 1066 } 1067 } 1068 } 1069 1070 /** 1071 * ixgbe_get_media_type_X550em - Get media type 1072 * @hw: pointer to hardware structure 1073 * 1074 * Returns the media type (fiber, copper, backplane) 1075 */ 1076 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 1077 { 1078 enum ixgbe_media_type media_type; 1079 1080 DEBUGFUNC("ixgbe_get_media_type_X550em"); 1081 1082 /* Detect if there is a copper PHY attached. */ 1083 switch (hw->device_id) { 1084 case IXGBE_DEV_ID_X550EM_X_KR: 1085 case IXGBE_DEV_ID_X550EM_X_KX4: 1086 media_type = ixgbe_media_type_backplane; 1087 break; 1088 case IXGBE_DEV_ID_X550EM_X_SFP: 1089 media_type = ixgbe_media_type_fiber; 1090 break; 1091 case IXGBE_DEV_ID_X550EM_X_1G_T: 1092 case IXGBE_DEV_ID_X550EM_X_10G_T: 1093 media_type = ixgbe_media_type_copper; 1094 break; 1095 default: 1096 media_type = ixgbe_media_type_unknown; 1097 break; 1098 } 1099 return media_type; 1100 } 1101 1102 /** 1103 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1104 * @hw: pointer to hardware structure 1105 * @linear: TRUE if SFP module is linear 1106 */ 1107 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1108 { 1109 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em"); 1110 1111 switch (hw->phy.sfp_type) { 1112 case ixgbe_sfp_type_not_present: 1113 return IXGBE_ERR_SFP_NOT_PRESENT; 1114 case ixgbe_sfp_type_da_cu_core0: 1115 case ixgbe_sfp_type_da_cu_core1: 1116 *linear = TRUE; 1117 break; 1118 case ixgbe_sfp_type_srlr_core0: 1119 case ixgbe_sfp_type_srlr_core1: 1120 case ixgbe_sfp_type_da_act_lmt_core0: 1121 case ixgbe_sfp_type_da_act_lmt_core1: 1122 case ixgbe_sfp_type_1g_sx_core0: 1123 case ixgbe_sfp_type_1g_sx_core1: 1124 case ixgbe_sfp_type_1g_lx_core0: 1125 case ixgbe_sfp_type_1g_lx_core1: 1126 *linear = FALSE; 1127 break; 1128 case ixgbe_sfp_type_unknown: 1129 case ixgbe_sfp_type_1g_cu_core0: 1130 case ixgbe_sfp_type_1g_cu_core1: 1131 default: 1132 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1133 } 1134 1135 return IXGBE_SUCCESS; 1136 } 1137 1138 /** 1139 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules 1140 * @hw: pointer to hardware structure 1141 * 1142 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1143 **/ 1144 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw) 1145 { 1146 s32 status; 1147 bool linear; 1148 1149 DEBUGFUNC("ixgbe_identify_sfp_module_X550em"); 1150 1151 status = ixgbe_identify_module_generic(hw); 1152 1153 if (status != IXGBE_SUCCESS) 1154 return status; 1155 1156 /* Check if SFP module is supported */ 1157 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1158 1159 return status; 1160 } 1161 1162 /** 1163 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops 1164 * @hw: pointer to hardware structure 1165 */ 1166 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 1167 { 1168 s32 status; 1169 bool linear; 1170 1171 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); 1172 1173 /* Check if SFP module is supported */ 1174 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1175 1176 if (status != IXGBE_SUCCESS) 1177 return status; 1178 1179 ixgbe_init_mac_link_ops_X550em(hw); 1180 hw->phy.ops.reset = NULL; 1181 1182 return IXGBE_SUCCESS; 1183 } 1184 1185 /** 1186 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers 1187 * @hw: pointer to hardware structure 1188 */ 1189 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 1190 { 1191 struct ixgbe_mac_info *mac = &hw->mac; 1192 1193 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em"); 1194 1195 switch (hw->mac.ops.get_media_type(hw)) { 1196 case ixgbe_media_type_fiber: 1197 /* CS4227 does not support autoneg, so disable the laser control 1198 * functions for SFP+ fiber 1199 */ 1200 mac->ops.disable_tx_laser = NULL; 1201 mac->ops.enable_tx_laser = NULL; 1202 mac->ops.flap_tx_laser = NULL; 1203 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 1204 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em; 1205 mac->ops.set_rate_select_speed = 1206 ixgbe_set_soft_rate_select_speed; 1207 break; 1208 case ixgbe_media_type_copper: 1209 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 1210 mac->ops.check_link = ixgbe_check_link_t_X550em; 1211 break; 1212 default: 1213 break; 1214 } 1215 } 1216 1217 /** 1218 * ixgbe_get_link_capabilities_x550em - Determines link capabilities 1219 * @hw: pointer to hardware structure 1220 * @speed: pointer to link speed 1221 * @autoneg: TRUE when autoneg or autotry is enabled 1222 */ 1223 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 1224 ixgbe_link_speed *speed, 1225 bool *autoneg) 1226 { 1227 DEBUGFUNC("ixgbe_get_link_capabilities_X550em"); 1228 1229 /* SFP */ 1230 if (hw->phy.media_type == ixgbe_media_type_fiber) { 1231 1232 /* CS4227 SFP must not enable auto-negotiation */ 1233 *autoneg = FALSE; 1234 1235 /* Check if 1G SFP module. */ 1236 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1237 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 1238 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1239 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { 1240 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1241 return IXGBE_SUCCESS; 1242 } 1243 1244 /* Link capabilities are based on SFP */ 1245 if (hw->phy.multispeed_fiber) 1246 *speed = IXGBE_LINK_SPEED_10GB_FULL | 1247 IXGBE_LINK_SPEED_1GB_FULL; 1248 else 1249 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1250 } else { 1251 *speed = IXGBE_LINK_SPEED_10GB_FULL | 1252 IXGBE_LINK_SPEED_1GB_FULL; 1253 *autoneg = TRUE; 1254 } 1255 1256 return IXGBE_SUCCESS; 1257 } 1258 1259 /** 1260 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 1261 * @hw: pointer to hardware structure 1262 * @lsc: pointer to boolean flag which indicates whether external Base T 1263 * PHY interrupt is lsc 1264 * 1265 * Determime if external Base T PHY interrupt cause is high temperature 1266 * failure alarm or link status change. 1267 * 1268 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1269 * failure alarm, else return PHY access status. 1270 */ 1271 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 1272 { 1273 u32 status; 1274 u16 reg; 1275 1276 *lsc = FALSE; 1277 1278 /* Vendor alarm triggered */ 1279 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1280 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1281 ®); 1282 1283 if (status != IXGBE_SUCCESS || 1284 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 1285 return status; 1286 1287 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 1288 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 1289 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1290 ®); 1291 1292 if (status != IXGBE_SUCCESS || 1293 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1294 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 1295 return status; 1296 1297 /* High temperature failure alarm triggered */ 1298 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 1299 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1300 ®); 1301 1302 if (status != IXGBE_SUCCESS) 1303 return status; 1304 1305 /* If high temperature failure, then return over temp error and exit */ 1306 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 1307 /* power down the PHY in case the PHY FW didn't already */ 1308 ixgbe_set_copper_phy_power(hw, FALSE); 1309 return IXGBE_ERR_OVERTEMP; 1310 } 1311 1312 /* Vendor alarm 2 triggered */ 1313 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1314 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1315 1316 if (status != IXGBE_SUCCESS || 1317 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 1318 return status; 1319 1320 /* link connect/disconnect event occurred */ 1321 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 1322 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1323 1324 if (status != IXGBE_SUCCESS) 1325 return status; 1326 1327 /* Indicate LSC */ 1328 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 1329 *lsc = TRUE; 1330 1331 return IXGBE_SUCCESS; 1332 } 1333 1334 /** 1335 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 1336 * @hw: pointer to hardware structure 1337 * 1338 * Enable link status change and temperature failure alarm for the external 1339 * Base T PHY 1340 * 1341 * Returns PHY access status 1342 */ 1343 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 1344 { 1345 u32 status; 1346 u16 reg; 1347 bool lsc; 1348 1349 /* Clear interrupt flags */ 1350 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 1351 1352 /* Enable link status change alarm */ 1353 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1354 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1355 1356 if (status != IXGBE_SUCCESS) 1357 return status; 1358 1359 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 1360 1361 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1362 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); 1363 1364 if (status != IXGBE_SUCCESS) 1365 return status; 1366 1367 /* Enables high temperature failure alarm */ 1368 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1369 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1370 ®); 1371 1372 if (status != IXGBE_SUCCESS) 1373 return status; 1374 1375 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN; 1376 1377 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1378 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1379 reg); 1380 1381 if (status != IXGBE_SUCCESS) 1382 return status; 1383 1384 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 1385 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1386 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1387 ®); 1388 1389 if (status != IXGBE_SUCCESS) 1390 return status; 1391 1392 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1393 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 1394 1395 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1396 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1397 reg); 1398 1399 if (status != IXGBE_SUCCESS) 1400 return status; 1401 1402 /* Enable chip-wide vendor alarm */ 1403 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1404 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1405 ®); 1406 1407 if (status != IXGBE_SUCCESS) 1408 return status; 1409 1410 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 1411 1412 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1413 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1414 reg); 1415 1416 return status; 1417 } 1418 1419 /** 1420 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 1421 * @hw: pointer to hardware structure 1422 * @speed: link speed 1423 * 1424 * Configures the integrated KR PHY. 1425 **/ 1426 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 1427 ixgbe_link_speed speed) 1428 { 1429 s32 status; 1430 u32 reg_val; 1431 1432 status = ixgbe_read_iosf_sb_reg_x550(hw, 1433 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1434 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1435 if (status) 1436 return status; 1437 1438 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1439 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ | 1440 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC); 1441 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 1442 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 1443 1444 /* Advertise 10G support. */ 1445 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1446 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 1447 1448 /* Advertise 1G support. */ 1449 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 1450 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 1451 1452 /* Restart auto-negotiation. */ 1453 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1454 status = ixgbe_write_iosf_sb_reg_x550(hw, 1455 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1456 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1457 1458 return status; 1459 } 1460 1461 /** 1462 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init 1463 * @hw: pointer to hardware structure 1464 * 1465 * Initialize any function pointers that were not able to be 1466 * set during init_shared_code because the PHY/SFP type was 1467 * not known. Perform the SFP init if necessary. 1468 */ 1469 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 1470 { 1471 struct ixgbe_phy_info *phy = &hw->phy; 1472 ixgbe_link_speed speed; 1473 s32 ret_val; 1474 1475 DEBUGFUNC("ixgbe_init_phy_ops_X550em"); 1476 1477 hw->mac.ops.set_lan_id(hw); 1478 1479 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 1480 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 1481 ixgbe_setup_mux_ctl(hw); 1482 1483 /* Save NW management interface connected on board. This is used 1484 * to determine internal PHY mode. 1485 */ 1486 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1487 1488 /* If internal PHY mode is KR, then initialize KR link */ 1489 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) { 1490 speed = IXGBE_LINK_SPEED_10GB_FULL | 1491 IXGBE_LINK_SPEED_1GB_FULL; 1492 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); 1493 } 1494 1495 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; 1496 } 1497 1498 /* Identify the PHY or SFP module */ 1499 ret_val = phy->ops.identify(hw); 1500 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 1501 return ret_val; 1502 1503 /* Setup function pointers based on detected hardware */ 1504 ixgbe_init_mac_link_ops_X550em(hw); 1505 if (phy->sfp_type != ixgbe_sfp_type_unknown) 1506 phy->ops.reset = NULL; 1507 1508 /* Set functions pointers based on phy type */ 1509 switch (hw->phy.type) { 1510 case ixgbe_phy_x550em_kx4: 1511 phy->ops.setup_link = ixgbe_setup_kx4_x550em; 1512 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1513 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1514 break; 1515 case ixgbe_phy_x550em_kr: 1516 phy->ops.setup_link = ixgbe_setup_kr_x550em; 1517 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1518 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1519 break; 1520 case ixgbe_phy_x550em_ext_t: 1521 /* Save NW management interface connected on board. This is used 1522 * to determine internal PHY mode 1523 */ 1524 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1525 1526 /* If internal link mode is XFI, then setup iXFI internal link, 1527 * else setup KR now. 1528 */ 1529 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1530 phy->ops.setup_internal_link = 1531 ixgbe_setup_internal_phy_t_x550em; 1532 } else { 1533 speed = IXGBE_LINK_SPEED_10GB_FULL | 1534 IXGBE_LINK_SPEED_1GB_FULL; 1535 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); 1536 } 1537 1538 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 1539 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 1540 phy->ops.reset = ixgbe_reset_phy_t_X550em; 1541 break; 1542 default: 1543 break; 1544 } 1545 return ret_val; 1546 } 1547 1548 /** 1549 * ixgbe_reset_hw_X550em - Perform hardware reset 1550 * @hw: pointer to hardware structure 1551 * 1552 * Resets the hardware by resetting the transmit and receive units, masks 1553 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1554 * reset. 1555 */ 1556 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 1557 { 1558 ixgbe_link_speed link_speed; 1559 s32 status; 1560 u32 ctrl = 0; 1561 u32 i; 1562 u32 hlreg0; 1563 bool link_up = FALSE; 1564 1565 DEBUGFUNC("ixgbe_reset_hw_X550em"); 1566 1567 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 1568 status = hw->mac.ops.stop_adapter(hw); 1569 if (status != IXGBE_SUCCESS) 1570 return status; 1571 1572 /* flush pending Tx transactions */ 1573 ixgbe_clear_tx_pending(hw); 1574 1575 /* PHY ops must be identified and initialized prior to reset */ 1576 1577 /* Identify PHY and related function pointers */ 1578 status = hw->phy.ops.init(hw); 1579 1580 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1581 return status; 1582 1583 /* start the external PHY */ 1584 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 1585 status = ixgbe_init_ext_t_x550em(hw); 1586 if (status) 1587 return status; 1588 } 1589 1590 /* Setup SFP module if there is one present. */ 1591 if (hw->phy.sfp_setup_needed) { 1592 status = hw->mac.ops.setup_sfp(hw); 1593 hw->phy.sfp_setup_needed = FALSE; 1594 } 1595 1596 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1597 return status; 1598 1599 /* Reset PHY */ 1600 if (!hw->phy.reset_disable && hw->phy.ops.reset) 1601 hw->phy.ops.reset(hw); 1602 1603 mac_reset_top: 1604 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 1605 * If link reset is used when link is up, it might reset the PHY when 1606 * mng is using it. If link is down or the flag to force full link 1607 * reset is set, then perform link reset. 1608 */ 1609 ctrl = IXGBE_CTRL_LNK_RST; 1610 if (!hw->force_full_reset) { 1611 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 1612 if (link_up) 1613 ctrl = IXGBE_CTRL_RST; 1614 } 1615 1616 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1617 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1618 IXGBE_WRITE_FLUSH(hw); 1619 1620 /* Poll for reset bit to self-clear meaning reset is complete */ 1621 for (i = 0; i < 10; i++) { 1622 usec_delay(1); 1623 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1624 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1625 break; 1626 } 1627 1628 if (ctrl & IXGBE_CTRL_RST_MASK) { 1629 status = IXGBE_ERR_RESET_FAILED; 1630 DEBUGOUT("Reset polling failed to complete.\n"); 1631 } 1632 1633 msec_delay(50); 1634 1635 /* Double resets are required for recovery from certain error 1636 * conditions. Between resets, it is necessary to stall to 1637 * allow time for any pending HW events to complete. 1638 */ 1639 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1640 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1641 goto mac_reset_top; 1642 } 1643 1644 /* Store the permanent mac address */ 1645 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1646 1647 /* Store MAC address from RAR0, clear receive address registers, and 1648 * clear the multicast table. Also reset num_rar_entries to 128, 1649 * since we modify this value when programming the SAN MAC address. 1650 */ 1651 hw->mac.num_rar_entries = 128; 1652 hw->mac.ops.init_rx_addrs(hw); 1653 1654 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 1655 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1656 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 1657 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 1658 } 1659 1660 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 1661 ixgbe_setup_mux_ctl(hw); 1662 1663 return status; 1664 } 1665 1666 /** 1667 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 1668 * @hw: pointer to hardware structure 1669 */ 1670 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 1671 { 1672 u32 status; 1673 u16 reg; 1674 1675 status = hw->phy.ops.read_reg(hw, 1676 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 1677 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1678 ®); 1679 1680 if (status != IXGBE_SUCCESS) 1681 return status; 1682 1683 /* If PHY FW reset completed bit is set then this is the first 1684 * SW instance after a power on so the PHY FW must be un-stalled. 1685 */ 1686 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 1687 status = hw->phy.ops.read_reg(hw, 1688 IXGBE_MDIO_GLOBAL_RES_PR_10, 1689 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1690 ®); 1691 1692 if (status != IXGBE_SUCCESS) 1693 return status; 1694 1695 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 1696 1697 status = hw->phy.ops.write_reg(hw, 1698 IXGBE_MDIO_GLOBAL_RES_PR_10, 1699 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1700 reg); 1701 1702 if (status != IXGBE_SUCCESS) 1703 return status; 1704 } 1705 1706 return status; 1707 } 1708 1709 /** 1710 * ixgbe_setup_kr_x550em - Configure the KR PHY. 1711 * @hw: pointer to hardware structure 1712 * 1713 * Configures the integrated KR PHY. 1714 **/ 1715 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 1716 { 1717 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 1718 } 1719 1720 /** 1721 * ixgbe_setup_kx4_x550em - Configure the KX4 PHY. 1722 * @hw: pointer to hardware structure 1723 * 1724 * Configures the integrated KX4 PHY. 1725 **/ 1726 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw) 1727 { 1728 s32 status; 1729 u32 reg_val; 1730 1731 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, 1732 IXGBE_SB_IOSF_TARGET_KX4_PCS, ®_val); 1733 if (status) 1734 return status; 1735 1736 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 | 1737 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX); 1738 1739 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE; 1740 1741 /* Advertise 10G support. */ 1742 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1743 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4; 1744 1745 /* Advertise 1G support. */ 1746 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1747 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX; 1748 1749 /* Restart auto-negotiation. */ 1750 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART; 1751 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, 1752 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val); 1753 1754 return status; 1755 } 1756 1757 /** 1758 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP 1759 * @hw: pointer to hardware structure 1760 * 1761 * Configure the external PHY and the integrated KR PHY for SFP support. 1762 **/ 1763 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1764 ixgbe_link_speed speed, 1765 bool autoneg_wait_to_complete) 1766 { 1767 s32 ret_val; 1768 u16 reg_slice, reg_val; 1769 bool setup_linear = FALSE; 1770 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 1771 1772 /* Check if SFP module is supported and linear */ 1773 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1774 1775 /* If no SFP module present, then return success. Return success since 1776 * there is no reason to configure CS4227 and SFP not present error is 1777 * not excepted in the setup MAC link flow. 1778 */ 1779 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1780 return IXGBE_SUCCESS; 1781 1782 if (ret_val != IXGBE_SUCCESS) 1783 return ret_val; 1784 1785 /* Configure CS4227 for LINE connection rate then type. */ 1786 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12); 1787 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000; 1788 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1789 reg_val); 1790 1791 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); 1792 if (setup_linear) 1793 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1794 else 1795 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1796 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1797 reg_val); 1798 1799 /* Configure CS4227 for HOST connection rate then type. */ 1800 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12); 1801 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000; 1802 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1803 reg_val); 1804 1805 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12); 1806 if (setup_linear) 1807 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1808 else 1809 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1810 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1811 reg_val); 1812 1813 /* If internal link mode is XFI, then setup XFI internal link. */ 1814 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) 1815 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed); 1816 1817 return ret_val; 1818 } 1819 1820 /** 1821 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1822 * @hw: pointer to hardware structure 1823 * @speed: the link speed to force 1824 * 1825 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1826 * internal and external PHY at a specific speed, without autonegotiation. 1827 **/ 1828 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1829 { 1830 s32 status; 1831 u32 reg_val; 1832 1833 /* Disable AN and force speed to 10G Serial. */ 1834 status = ixgbe_read_iosf_sb_reg_x550(hw, 1835 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1836 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1837 if (status != IXGBE_SUCCESS) 1838 return status; 1839 1840 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1841 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1842 1843 /* Select forced link speed for internal PHY. */ 1844 switch (*speed) { 1845 case IXGBE_LINK_SPEED_10GB_FULL: 1846 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1847 break; 1848 case IXGBE_LINK_SPEED_1GB_FULL: 1849 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1850 break; 1851 default: 1852 /* Other link speeds are not supported by internal KR PHY. */ 1853 return IXGBE_ERR_LINK_SETUP; 1854 } 1855 1856 status = ixgbe_write_iosf_sb_reg_x550(hw, 1857 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1858 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1859 if (status != IXGBE_SUCCESS) 1860 return status; 1861 1862 /* Disable training protocol FSM. */ 1863 status = ixgbe_read_iosf_sb_reg_x550(hw, 1864 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1865 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1866 if (status != IXGBE_SUCCESS) 1867 return status; 1868 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1869 status = ixgbe_write_iosf_sb_reg_x550(hw, 1870 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1871 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1872 if (status != IXGBE_SUCCESS) 1873 return status; 1874 1875 /* Disable Flex from training TXFFE. */ 1876 status = ixgbe_read_iosf_sb_reg_x550(hw, 1877 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1878 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1879 if (status != IXGBE_SUCCESS) 1880 return status; 1881 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1882 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1883 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1884 status = ixgbe_write_iosf_sb_reg_x550(hw, 1885 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1886 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1887 if (status != IXGBE_SUCCESS) 1888 return status; 1889 status = ixgbe_read_iosf_sb_reg_x550(hw, 1890 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1891 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1892 if (status != IXGBE_SUCCESS) 1893 return status; 1894 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1895 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1896 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1897 status = ixgbe_write_iosf_sb_reg_x550(hw, 1898 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1899 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1900 if (status != IXGBE_SUCCESS) 1901 return status; 1902 1903 /* Enable override for coefficients. */ 1904 status = ixgbe_read_iosf_sb_reg_x550(hw, 1905 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1906 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1907 if (status != IXGBE_SUCCESS) 1908 return status; 1909 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1910 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1911 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1912 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1913 status = ixgbe_write_iosf_sb_reg_x550(hw, 1914 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1915 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1916 if (status != IXGBE_SUCCESS) 1917 return status; 1918 1919 /* Toggle port SW reset by AN reset. */ 1920 status = ixgbe_read_iosf_sb_reg_x550(hw, 1921 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1922 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1923 if (status != IXGBE_SUCCESS) 1924 return status; 1925 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1926 status = ixgbe_write_iosf_sb_reg_x550(hw, 1927 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1928 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1929 1930 return status; 1931 } 1932 1933 /** 1934 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 1935 * @hw: point to hardware structure 1936 * 1937 * Configures the link between the integrated KR PHY and the external X557 PHY 1938 * The driver will call this function when it gets a link status change 1939 * interrupt from the X557 PHY. This function configures the link speed 1940 * between the PHYs to match the link speed of the BASE-T link. 1941 * 1942 * A return of a non-zero value indicates an error, and the base driver should 1943 * not report link up. 1944 */ 1945 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 1946 { 1947 u32 status; 1948 u16 autoneg_status, speed; 1949 ixgbe_link_speed force_speed; 1950 1951 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1952 return IXGBE_ERR_CONFIG; 1953 1954 /* read this twice back to back to indicate current status */ 1955 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1956 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1957 &autoneg_status); 1958 if (status != IXGBE_SUCCESS) 1959 return status; 1960 1961 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1962 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1963 &autoneg_status); 1964 if (status != IXGBE_SUCCESS) 1965 return status; 1966 1967 /* If link is not up, then there is no setup necessary so return */ 1968 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 1969 return IXGBE_SUCCESS; 1970 1971 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 1972 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1973 &speed); 1974 1975 /* clear everything but the speed and duplex bits */ 1976 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 1977 1978 switch (speed) { 1979 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 1980 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1981 break; 1982 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 1983 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1984 break; 1985 default: 1986 /* Internal PHY does not support anything else */ 1987 return IXGBE_ERR_INVALID_LINK_SETTINGS; 1988 } 1989 1990 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 1991 } 1992 1993 /** 1994 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback. 1995 * @hw: pointer to hardware structure 1996 * 1997 * Configures the integrated KR PHY to use internal loopback mode. 1998 **/ 1999 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw) 2000 { 2001 s32 status; 2002 u32 reg_val; 2003 2004 /* Disable AN and force speed to 10G Serial. */ 2005 status = ixgbe_read_iosf_sb_reg_x550(hw, 2006 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2007 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2008 if (status != IXGBE_SUCCESS) 2009 return status; 2010 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2011 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2012 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 2013 status = ixgbe_write_iosf_sb_reg_x550(hw, 2014 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2015 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2016 if (status != IXGBE_SUCCESS) 2017 return status; 2018 2019 /* Set near-end loopback clocks. */ 2020 status = ixgbe_read_iosf_sb_reg_x550(hw, 2021 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 2022 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2023 if (status != IXGBE_SUCCESS) 2024 return status; 2025 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B; 2026 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS; 2027 status = ixgbe_write_iosf_sb_reg_x550(hw, 2028 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 2029 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2030 if (status != IXGBE_SUCCESS) 2031 return status; 2032 2033 /* Set loopback enable. */ 2034 status = ixgbe_read_iosf_sb_reg_x550(hw, 2035 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 2036 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2037 if (status != IXGBE_SUCCESS) 2038 return status; 2039 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK; 2040 status = ixgbe_write_iosf_sb_reg_x550(hw, 2041 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 2042 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2043 if (status != IXGBE_SUCCESS) 2044 return status; 2045 2046 /* Training bypass. */ 2047 status = ixgbe_read_iosf_sb_reg_x550(hw, 2048 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2049 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2050 if (status != IXGBE_SUCCESS) 2051 return status; 2052 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS; 2053 status = ixgbe_write_iosf_sb_reg_x550(hw, 2054 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2055 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2056 2057 return status; 2058 } 2059 2060 /** 2061 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 2062 * assuming that the semaphore is already obtained. 2063 * @hw: pointer to hardware structure 2064 * @offset: offset of word in the EEPROM to read 2065 * @data: word read from the EEPROM 2066 * 2067 * Reads a 16 bit word from the EEPROM using the hostif. 2068 **/ 2069 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 2070 u16 *data) 2071 { 2072 s32 status; 2073 struct ixgbe_hic_read_shadow_ram buffer; 2074 2075 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550"); 2076 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 2077 buffer.hdr.req.buf_lenh = 0; 2078 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 2079 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2080 2081 /* convert offset from words to bytes */ 2082 buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 2083 /* one word */ 2084 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 2085 2086 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2087 sizeof(buffer), 2088 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2089 2090 if (status) 2091 return status; 2092 2093 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 2094 FW_NVM_DATA_OFFSET); 2095 2096 return 0; 2097 } 2098 2099 /** 2100 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 2101 * @hw: pointer to hardware structure 2102 * @offset: offset of word in the EEPROM to read 2103 * @data: word read from the EEPROM 2104 * 2105 * Reads a 16 bit word from the EEPROM using the hostif. 2106 **/ 2107 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 2108 u16 *data) 2109 { 2110 s32 status = IXGBE_SUCCESS; 2111 2112 DEBUGFUNC("ixgbe_read_ee_hostif_X550"); 2113 2114 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 2115 IXGBE_SUCCESS) { 2116 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data); 2117 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2118 } else { 2119 status = IXGBE_ERR_SWFW_SYNC; 2120 } 2121 2122 return status; 2123 } 2124 2125 /** 2126 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 2127 * @hw: pointer to hardware structure 2128 * @offset: offset of word in the EEPROM to read 2129 * @words: number of words 2130 * @data: word(s) read from the EEPROM 2131 * 2132 * Reads a 16 bit word(s) from the EEPROM using the hostif. 2133 **/ 2134 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 2135 u16 offset, u16 words, u16 *data) 2136 { 2137 struct ixgbe_hic_read_shadow_ram buffer; 2138 u32 current_word = 0; 2139 u16 words_to_read; 2140 s32 status; 2141 u32 i; 2142 2143 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550"); 2144 2145 /* Take semaphore for the entire operation. */ 2146 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2147 if (status) { 2148 DEBUGOUT("EEPROM read buffer - semaphore failed\n"); 2149 return status; 2150 } 2151 while (words) { 2152 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 2153 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 2154 else 2155 words_to_read = words; 2156 2157 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 2158 buffer.hdr.req.buf_lenh = 0; 2159 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 2160 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2161 2162 /* convert offset from words to bytes */ 2163 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); 2164 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2); 2165 2166 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2167 sizeof(buffer), 2168 IXGBE_HI_COMMAND_TIMEOUT, 2169 FALSE); 2170 2171 if (status) { 2172 DEBUGOUT("Host interface command failed\n"); 2173 goto out; 2174 } 2175 2176 for (i = 0; i < words_to_read; i++) { 2177 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 2178 2 * i; 2179 u32 value = IXGBE_READ_REG(hw, reg); 2180 2181 data[current_word] = (u16)(value & 0xffff); 2182 current_word++; 2183 i++; 2184 if (i < words_to_read) { 2185 value >>= 16; 2186 data[current_word] = (u16)(value & 0xffff); 2187 current_word++; 2188 } 2189 } 2190 words -= words_to_read; 2191 } 2192 2193 out: 2194 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2195 return status; 2196 } 2197 2198 /** 2199 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 2200 * @hw: pointer to hardware structure 2201 * @offset: offset of word in the EEPROM to write 2202 * @data: word write to the EEPROM 2203 * 2204 * Write a 16 bit word to the EEPROM using the hostif. 2205 **/ 2206 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 2207 u16 data) 2208 { 2209 s32 status; 2210 struct ixgbe_hic_write_shadow_ram buffer; 2211 2212 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550"); 2213 2214 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 2215 buffer.hdr.req.buf_lenh = 0; 2216 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 2217 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2218 2219 /* one word */ 2220 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 2221 buffer.data = data; 2222 buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 2223 2224 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2225 sizeof(buffer), 2226 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2227 2228 return status; 2229 } 2230 2231 /** 2232 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 2233 * @hw: pointer to hardware structure 2234 * @offset: offset of word in the EEPROM to write 2235 * @data: word write to the EEPROM 2236 * 2237 * Write a 16 bit word to the EEPROM using the hostif. 2238 **/ 2239 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 2240 u16 data) 2241 { 2242 s32 status = IXGBE_SUCCESS; 2243 2244 DEBUGFUNC("ixgbe_write_ee_hostif_X550"); 2245 2246 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 2247 IXGBE_SUCCESS) { 2248 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 2249 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2250 } else { 2251 DEBUGOUT("write ee hostif failed to get semaphore"); 2252 status = IXGBE_ERR_SWFW_SYNC; 2253 } 2254 2255 return status; 2256 } 2257 2258 /** 2259 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 2260 * @hw: pointer to hardware structure 2261 * @offset: offset of word in the EEPROM to write 2262 * @words: number of words 2263 * @data: word(s) write to the EEPROM 2264 * 2265 * Write a 16 bit word(s) to the EEPROM using the hostif. 2266 **/ 2267 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 2268 u16 offset, u16 words, u16 *data) 2269 { 2270 s32 status = IXGBE_SUCCESS; 2271 u32 i = 0; 2272 2273 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550"); 2274 2275 /* Take semaphore for the entire operation. */ 2276 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2277 if (status != IXGBE_SUCCESS) { 2278 DEBUGOUT("EEPROM write buffer - semaphore failed\n"); 2279 goto out; 2280 } 2281 2282 for (i = 0; i < words; i++) { 2283 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 2284 data[i]); 2285 2286 if (status != IXGBE_SUCCESS) { 2287 DEBUGOUT("Eeprom buffered write failed\n"); 2288 break; 2289 } 2290 } 2291 2292 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2293 out: 2294 2295 return status; 2296 } 2297 2298 /** 2299 * ixgbe_checksum_ptr_x550 - Checksum one pointer region 2300 * @hw: pointer to hardware structure 2301 * @ptr: pointer offset in eeprom 2302 * @size: size of section pointed by ptr, if 0 first word will be used as size 2303 * @csum: address of checksum to update 2304 * 2305 * Returns error status for any failure 2306 */ 2307 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 2308 u16 size, u16 *csum, u16 *buffer, 2309 u32 buffer_size) 2310 { 2311 u16 buf[256]; 2312 s32 status; 2313 u16 length, bufsz, i, start; 2314 u16 *local_buffer; 2315 2316 bufsz = sizeof(buf) / sizeof(buf[0]); 2317 2318 /* Read a chunk at the pointer location */ 2319 if (!buffer) { 2320 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 2321 if (status) { 2322 DEBUGOUT("Failed to read EEPROM image\n"); 2323 return status; 2324 } 2325 local_buffer = buf; 2326 } else { 2327 if (buffer_size < ptr) 2328 return IXGBE_ERR_PARAM; 2329 local_buffer = &buffer[ptr]; 2330 } 2331 2332 if (size) { 2333 start = 0; 2334 length = size; 2335 } else { 2336 start = 1; 2337 length = local_buffer[0]; 2338 2339 /* Skip pointer section if length is invalid. */ 2340 if (length == 0xFFFF || length == 0 || 2341 (ptr + length) >= hw->eeprom.word_size) 2342 return IXGBE_SUCCESS; 2343 } 2344 2345 if (buffer && ((u32)start + (u32)length > buffer_size)) 2346 return IXGBE_ERR_PARAM; 2347 2348 for (i = start; length; i++, length--) { 2349 if (i == bufsz && !buffer) { 2350 ptr += bufsz; 2351 i = 0; 2352 if (length < bufsz) 2353 bufsz = length; 2354 2355 /* Read a chunk at the pointer location */ 2356 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 2357 bufsz, buf); 2358 if (status) { 2359 DEBUGOUT("Failed to read EEPROM image\n"); 2360 return status; 2361 } 2362 } 2363 *csum += local_buffer[i]; 2364 } 2365 return IXGBE_SUCCESS; 2366 } 2367 2368 /** 2369 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum 2370 * @hw: pointer to hardware structure 2371 * @buffer: pointer to buffer containing calculated checksum 2372 * @buffer_size: size of buffer 2373 * 2374 * Returns a negative error code on error, or the 16-bit checksum 2375 **/ 2376 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size) 2377 { 2378 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 2379 u16 *local_buffer; 2380 s32 status; 2381 u16 checksum = 0; 2382 u16 pointer, i, size; 2383 2384 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550"); 2385 2386 hw->eeprom.ops.init_params(hw); 2387 2388 if (!buffer) { 2389 /* Read pointer area */ 2390 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 2391 IXGBE_EEPROM_LAST_WORD + 1, 2392 eeprom_ptrs); 2393 if (status) { 2394 DEBUGOUT("Failed to read EEPROM image\n"); 2395 return status; 2396 } 2397 local_buffer = eeprom_ptrs; 2398 } else { 2399 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 2400 return IXGBE_ERR_PARAM; 2401 local_buffer = buffer; 2402 } 2403 2404 /* 2405 * For X550 hardware include 0x0-0x41 in the checksum, skip the 2406 * checksum word itself 2407 */ 2408 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 2409 if (i != IXGBE_EEPROM_CHECKSUM) 2410 checksum += local_buffer[i]; 2411 2412 /* 2413 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 2414 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 2415 */ 2416 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 2417 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 2418 continue; 2419 2420 pointer = local_buffer[i]; 2421 2422 /* Skip pointer section if the pointer is invalid. */ 2423 if (pointer == 0xFFFF || pointer == 0 || 2424 pointer >= hw->eeprom.word_size) 2425 continue; 2426 2427 switch (i) { 2428 case IXGBE_PCIE_GENERAL_PTR: 2429 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 2430 break; 2431 case IXGBE_PCIE_CONFIG0_PTR: 2432 case IXGBE_PCIE_CONFIG1_PTR: 2433 size = IXGBE_PCIE_CONFIG_SIZE; 2434 break; 2435 default: 2436 size = 0; 2437 break; 2438 } 2439 2440 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 2441 buffer, buffer_size); 2442 if (status) 2443 return status; 2444 } 2445 2446 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2447 2448 return (s32)checksum; 2449 } 2450 2451 /** 2452 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 2453 * @hw: pointer to hardware structure 2454 * 2455 * Returns a negative error code on error, or the 16-bit checksum 2456 **/ 2457 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 2458 { 2459 return ixgbe_calc_checksum_X550(hw, NULL, 0); 2460 } 2461 2462 /** 2463 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 2464 * @hw: pointer to hardware structure 2465 * @checksum_val: calculated checksum 2466 * 2467 * Performs checksum calculation and validates the EEPROM checksum. If the 2468 * caller does not need checksum_val, the value can be NULL. 2469 **/ 2470 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val) 2471 { 2472 s32 status; 2473 u16 checksum; 2474 u16 read_checksum = 0; 2475 2476 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550"); 2477 2478 /* Read the first word from the EEPROM. If this times out or fails, do 2479 * not continue or we could be in for a very long wait while every 2480 * EEPROM read fails 2481 */ 2482 status = hw->eeprom.ops.read(hw, 0, &checksum); 2483 if (status) { 2484 DEBUGOUT("EEPROM read failed\n"); 2485 return status; 2486 } 2487 2488 status = hw->eeprom.ops.calc_checksum(hw); 2489 if (status < 0) 2490 return status; 2491 2492 checksum = (u16)(status & 0xffff); 2493 2494 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 2495 &read_checksum); 2496 if (status) 2497 return status; 2498 2499 /* Verify read checksum from EEPROM is the same as 2500 * calculated checksum 2501 */ 2502 if (read_checksum != checksum) { 2503 status = IXGBE_ERR_EEPROM_CHECKSUM; 2504 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 2505 "Invalid EEPROM checksum"); 2506 } 2507 2508 /* If the user cares, return the calculated checksum */ 2509 if (checksum_val) 2510 *checksum_val = checksum; 2511 2512 return status; 2513 } 2514 2515 /** 2516 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 2517 * @hw: pointer to hardware structure 2518 * 2519 * After writing EEPROM to shadow RAM using EEWR register, software calculates 2520 * checksum and updates the EEPROM and instructs the hardware to update 2521 * the flash. 2522 **/ 2523 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 2524 { 2525 s32 status; 2526 u16 checksum = 0; 2527 2528 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550"); 2529 2530 /* Read the first word from the EEPROM. If this times out or fails, do 2531 * not continue or we could be in for a very long wait while every 2532 * EEPROM read fails 2533 */ 2534 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 2535 if (status) { 2536 DEBUGOUT("EEPROM read failed\n"); 2537 return status; 2538 } 2539 2540 status = ixgbe_calc_eeprom_checksum_X550(hw); 2541 if (status < 0) 2542 return status; 2543 2544 checksum = (u16)(status & 0xffff); 2545 2546 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 2547 checksum); 2548 if (status) 2549 return status; 2550 2551 status = ixgbe_update_flash_X550(hw); 2552 2553 return status; 2554 } 2555 2556 /** 2557 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 2558 * @hw: pointer to hardware structure 2559 * 2560 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 2561 **/ 2562 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 2563 { 2564 s32 status = IXGBE_SUCCESS; 2565 union ixgbe_hic_hdr2 buffer; 2566 2567 DEBUGFUNC("ixgbe_update_flash_X550"); 2568 2569 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 2570 buffer.req.buf_lenh = 0; 2571 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 2572 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 2573 2574 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2575 sizeof(buffer), 2576 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2577 2578 return status; 2579 } 2580 2581 /** 2582 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type 2583 * @hw: pointer to hardware structure 2584 * 2585 * Determines physical layer capabilities of the current configuration. 2586 **/ 2587 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw) 2588 { 2589 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 2590 u16 ext_ability = 0; 2591 2592 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em"); 2593 2594 hw->phy.ops.identify(hw); 2595 2596 switch (hw->phy.type) { 2597 case ixgbe_phy_x550em_kr: 2598 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR | 2599 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2600 break; 2601 case ixgbe_phy_x550em_kx4: 2602 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 2603 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2604 break; 2605 case ixgbe_phy_x550em_ext_t: 2606 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 2607 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 2608 &ext_ability); 2609 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 2610 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 2611 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 2612 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 2613 break; 2614 default: 2615 break; 2616 } 2617 2618 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 2619 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 2620 2621 return physical_layer; 2622 } 2623 2624 /** 2625 * ixgbe_get_bus_info_x550em - Set PCI bus info 2626 * @hw: pointer to hardware structure 2627 * 2628 * Sets bus link width and speed to unknown because X550em is 2629 * not a PCI device. 2630 **/ 2631 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 2632 { 2633 2634 DEBUGFUNC("ixgbe_get_bus_info_x550em"); 2635 2636 hw->bus.width = ixgbe_bus_width_unknown; 2637 hw->bus.speed = ixgbe_bus_speed_unknown; 2638 2639 hw->mac.ops.set_lan_id(hw); 2640 2641 return IXGBE_SUCCESS; 2642 } 2643 2644 /** 2645 * ixgbe_disable_rx_x550 - Disable RX unit 2646 * 2647 * Enables the Rx DMA unit for x550 2648 **/ 2649 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 2650 { 2651 u32 rxctrl, pfdtxgswc; 2652 s32 status; 2653 struct ixgbe_hic_disable_rxen fw_cmd; 2654 2655 DEBUGFUNC("ixgbe_enable_rx_dma_x550"); 2656 2657 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 2658 if (rxctrl & IXGBE_RXCTRL_RXEN) { 2659 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 2660 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 2661 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 2662 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 2663 hw->mac.set_lben = TRUE; 2664 } else { 2665 hw->mac.set_lben = FALSE; 2666 } 2667 2668 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 2669 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 2670 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 2671 fw_cmd.port_number = (u8)hw->bus.lan_id; 2672 2673 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2674 sizeof(struct ixgbe_hic_disable_rxen), 2675 IXGBE_HI_COMMAND_TIMEOUT, TRUE); 2676 2677 /* If we fail - disable RX using register write */ 2678 if (status) { 2679 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 2680 if (rxctrl & IXGBE_RXCTRL_RXEN) { 2681 rxctrl &= ~IXGBE_RXCTRL_RXEN; 2682 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 2683 } 2684 } 2685 } 2686 } 2687 2688 /** 2689 * ixgbe_enter_lplu_x550em - Transition to low power states 2690 * @hw: pointer to hardware structure 2691 * 2692 * Configures Low Power Link Up on transition to low power states 2693 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the 2694 * X557 PHY immediately prior to entering LPLU. 2695 **/ 2696 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 2697 { 2698 u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed; 2699 s32 status; 2700 ixgbe_link_speed lcd_speed; 2701 u32 save_autoneg; 2702 2703 /* If blocked by MNG FW, then don't restart AN */ 2704 if (ixgbe_check_reset_blocked(hw)) 2705 return IXGBE_SUCCESS; 2706 2707 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 2708 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2709 &autoneg_status); 2710 2711 if (status != IXGBE_SUCCESS) 2712 return status; 2713 2714 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3); 2715 2716 if (status != IXGBE_SUCCESS) 2717 return status; 2718 2719 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability 2720 * disabled, then force link down by entering low power mode. 2721 */ 2722 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) || 2723 !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 2724 !(hw->wol_enabled || ixgbe_mng_present(hw))) 2725 return ixgbe_set_copper_phy_power(hw, FALSE); 2726 2727 /* Determine LCD */ 2728 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 2729 2730 if (status != IXGBE_SUCCESS) 2731 return status; 2732 2733 /* If no valid LCD link speed, then force link down and exit. */ 2734 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 2735 return ixgbe_set_copper_phy_power(hw, FALSE); 2736 2737 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2738 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2739 &speed); 2740 2741 if (status != IXGBE_SUCCESS) 2742 return status; 2743 2744 /* clear everything but the speed bits */ 2745 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 2746 2747 /* If current speed is already LCD, then exit. */ 2748 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 2749 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 2750 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 2751 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 2752 return status; 2753 2754 /* Clear AN completed indication */ 2755 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 2756 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2757 &autoneg_status); 2758 2759 if (status != IXGBE_SUCCESS) 2760 return status; 2761 2762 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 2763 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2764 &an_10g_cntl_reg); 2765 2766 if (status != IXGBE_SUCCESS) 2767 return status; 2768 2769 status = hw->phy.ops.read_reg(hw, 2770 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 2771 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2772 &autoneg_reg); 2773 2774 if (status != IXGBE_SUCCESS) 2775 return status; 2776 2777 save_autoneg = hw->phy.autoneg_advertised; 2778 2779 /* Setup link at least common link speed */ 2780 status = hw->mac.ops.setup_link(hw, lcd_speed, FALSE); 2781 2782 /* restore autoneg from before setting lplu speed */ 2783 hw->phy.autoneg_advertised = save_autoneg; 2784 2785 return status; 2786 } 2787 2788 /** 2789 * ixgbe_get_lcd_x550em - Determine lowest common denominator 2790 * @hw: pointer to hardware structure 2791 * @lcd_speed: pointer to lowest common link speed 2792 * 2793 * Determine lowest common link speed with link partner. 2794 **/ 2795 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed) 2796 { 2797 u16 an_lp_status; 2798 s32 status; 2799 u16 word = hw->eeprom.ctrl_word_3; 2800 2801 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2802 2803 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2804 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2805 &an_lp_status); 2806 2807 if (status != IXGBE_SUCCESS) 2808 return status; 2809 2810 /* If link partner advertised 1G, return 1G */ 2811 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2812 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2813 return status; 2814 } 2815 2816 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2817 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2818 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2819 return status; 2820 2821 /* Link partner not capable of lower speeds, return 10G */ 2822 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2823 return status; 2824 } 2825 2826 /** 2827 * ixgbe_setup_fc_X550em - Set up flow control 2828 * @hw: pointer to hardware structure 2829 * 2830 * Called at init time to set up flow control. 2831 **/ 2832 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw) 2833 { 2834 s32 ret_val = IXGBE_SUCCESS; 2835 u32 pause, asm_dir, reg_val; 2836 2837 DEBUGFUNC("ixgbe_setup_fc_X550em"); 2838 2839 /* Validate the requested mode */ 2840 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2841 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 2842 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2843 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2844 goto out; 2845 } 2846 2847 /* 10gig parts do not have a word in the EEPROM to determine the 2848 * default flow control setting, so we explicitly set it to full. 2849 */ 2850 if (hw->fc.requested_mode == ixgbe_fc_default) 2851 hw->fc.requested_mode = ixgbe_fc_full; 2852 2853 /* Determine PAUSE and ASM_DIR bits. */ 2854 switch (hw->fc.requested_mode) { 2855 case ixgbe_fc_none: 2856 pause = 0; 2857 asm_dir = 0; 2858 break; 2859 case ixgbe_fc_tx_pause: 2860 pause = 0; 2861 asm_dir = 1; 2862 break; 2863 case ixgbe_fc_rx_pause: 2864 /* Rx Flow control is enabled and Tx Flow control is 2865 * disabled by software override. Since there really 2866 * isn't a way to advertise that we are capable of RX 2867 * Pause ONLY, we will advertise that we support both 2868 * symmetric and asymmetric Rx PAUSE, as such we fall 2869 * through to the fc_full statement. Later, we will 2870 * disable the adapter's ability to send PAUSE frames. 2871 */ 2872 case ixgbe_fc_full: 2873 pause = 1; 2874 asm_dir = 1; 2875 break; 2876 default: 2877 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2878 "Flow control param set incorrectly\n"); 2879 ret_val = IXGBE_ERR_CONFIG; 2880 goto out; 2881 } 2882 2883 if (hw->phy.media_type == ixgbe_media_type_backplane) { 2884 ret_val = ixgbe_read_iosf_sb_reg_x550(hw, 2885 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2886 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2887 if (ret_val != IXGBE_SUCCESS) 2888 goto out; 2889 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2890 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2891 if (pause) 2892 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2893 if (asm_dir) 2894 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2895 ret_val = ixgbe_write_iosf_sb_reg_x550(hw, 2896 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2897 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2898 2899 /* Not all devices fully support AN. */ 2900 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) 2901 hw->fc.disable_fc_autoneg = TRUE; 2902 } 2903 2904 out: 2905 return ret_val; 2906 } 2907 2908 /** 2909 * ixgbe_set_mux - Set mux for port 1 access with CS4227 2910 * @hw: pointer to hardware structure 2911 * @state: set mux if 1, clear if 0 2912 */ 2913 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 2914 { 2915 u32 esdp; 2916 2917 if (!hw->bus.lan_id) 2918 return; 2919 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2920 if (state) 2921 esdp |= IXGBE_ESDP_SDP1; 2922 else 2923 esdp &= ~IXGBE_ESDP_SDP1; 2924 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2925 IXGBE_WRITE_FLUSH(hw); 2926 } 2927 2928 /** 2929 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 2930 * @hw: pointer to hardware structure 2931 * @mask: Mask to specify which semaphore to acquire 2932 * 2933 * Acquires the SWFW semaphore and sets the I2C MUX 2934 **/ 2935 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 2936 { 2937 s32 status; 2938 2939 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em"); 2940 2941 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 2942 if (status) 2943 return status; 2944 2945 if (mask & IXGBE_GSSR_I2C_MASK) 2946 ixgbe_set_mux(hw, 1); 2947 2948 return IXGBE_SUCCESS; 2949 } 2950 2951 /** 2952 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 2953 * @hw: pointer to hardware structure 2954 * @mask: Mask to specify which semaphore to release 2955 * 2956 * Releases the SWFW semaphore and sets the I2C MUX 2957 **/ 2958 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 2959 { 2960 DEBUGFUNC("ixgbe_release_swfw_sync_X550em"); 2961 2962 if (mask & IXGBE_GSSR_I2C_MASK) 2963 ixgbe_set_mux(hw, 0); 2964 2965 ixgbe_release_swfw_sync_X540(hw, mask); 2966 } 2967 2968 /** 2969 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2970 * @hw: pointer to hardware structure 2971 * 2972 * Handle external Base T PHY interrupt. If high temperature 2973 * failure alarm then return error, else if link status change 2974 * then setup internal/external PHY link 2975 * 2976 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2977 * failure alarm, else return PHY access status. 2978 */ 2979 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2980 { 2981 bool lsc; 2982 u32 status; 2983 2984 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2985 2986 if (status != IXGBE_SUCCESS) 2987 return status; 2988 2989 if (lsc) 2990 return ixgbe_setup_internal_phy(hw); 2991 2992 return IXGBE_SUCCESS; 2993 } 2994 2995 /** 2996 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 2997 * @hw: pointer to hardware structure 2998 * @speed: new link speed 2999 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 3000 * 3001 * Setup internal/external PHY link speed based on link speed, then set 3002 * external PHY auto advertised link speed. 3003 * 3004 * Returns error status for any failure 3005 **/ 3006 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 3007 ixgbe_link_speed speed, 3008 bool autoneg_wait_to_complete) 3009 { 3010 s32 status; 3011 ixgbe_link_speed force_speed; 3012 3013 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em"); 3014 3015 /* Setup internal/external PHY link speed to iXFI (10G), unless 3016 * only 1G is auto advertised then setup KX link. 3017 */ 3018 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 3019 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 3020 else 3021 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 3022 3023 /* If internal link mode is XFI, then setup XFI internal link. */ 3024 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 3025 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 3026 3027 if (status != IXGBE_SUCCESS) 3028 return status; 3029 } 3030 3031 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 3032 } 3033 3034 /** 3035 * ixgbe_check_link_t_X550em - Determine link and speed status 3036 * @hw: pointer to hardware structure 3037 * @speed: pointer to link speed 3038 * @link_up: TRUE when link is up 3039 * @link_up_wait_to_complete: bool used to wait for link up or not 3040 * 3041 * Check that both the MAC and X557 external PHY have link. 3042 **/ 3043 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3044 bool *link_up, bool link_up_wait_to_complete) 3045 { 3046 u32 status; 3047 u16 autoneg_status; 3048 3049 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 3050 return IXGBE_ERR_CONFIG; 3051 3052 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 3053 link_up_wait_to_complete); 3054 3055 /* If check link fails or MAC link is not up, then return */ 3056 if (status != IXGBE_SUCCESS || !(*link_up)) 3057 return status; 3058 3059 /* MAC link is up, so check external PHY link. 3060 * Read this twice back to back to indicate current status. 3061 */ 3062 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3063 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3064 &autoneg_status); 3065 3066 if (status != IXGBE_SUCCESS) 3067 return status; 3068 3069 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3070 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3071 &autoneg_status); 3072 3073 if (status != IXGBE_SUCCESS) 3074 return status; 3075 3076 /* If external PHY link is not up, then indicate link not up */ 3077 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 3078 *link_up = FALSE; 3079 3080 return IXGBE_SUCCESS; 3081 } 3082 3083 /** 3084 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 3085 * @hw: pointer to hardware structure 3086 **/ 3087 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 3088 { 3089 s32 status; 3090 3091 status = ixgbe_reset_phy_generic(hw); 3092 3093 if (status != IXGBE_SUCCESS) 3094 return status; 3095 3096 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 3097 return ixgbe_enable_lasi_ext_t_x550em(hw); 3098 } 3099