1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $ 28 */ 29 30 #include "opt_polling.h" 31 #include "opt_jme.h" 32 33 #include <sys/param.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/interrupt.h> 38 #include <sys/malloc.h> 39 #include <sys/proc.h> 40 #include <sys/rman.h> 41 #include <sys/serialize.h> 42 #include <sys/serialize2.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 47 #include <net/ethernet.h> 48 #include <net/if.h> 49 #include <net/bpf.h> 50 #include <net/if_arp.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/ifq_var.h> 54 #include <net/toeplitz.h> 55 #include <net/toeplitz2.h> 56 #include <net/vlan/if_vlan_var.h> 57 #include <net/vlan/if_vlan_ether.h> 58 59 #include <netinet/in.h> 60 61 #include <dev/netif/mii_layer/miivar.h> 62 #include <dev/netif/mii_layer/jmphyreg.h> 63 64 #include <bus/pci/pcireg.h> 65 #include <bus/pci/pcivar.h> 66 #include <bus/pci/pcidevs.h> 67 68 #include <dev/netif/jme/if_jmereg.h> 69 #include <dev/netif/jme/if_jmevar.h> 70 71 #include "miibus_if.h" 72 73 #define JME_TX_SERIALIZE 1 74 #define JME_RX_SERIALIZE 2 75 76 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 77 78 #ifdef JME_RSS_DEBUG 79 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \ 80 do { \ 81 if ((sc)->jme_rss_debug >= (lvl)) \ 82 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \ 83 } while (0) 84 #else /* !JME_RSS_DEBUG */ 85 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 86 #endif /* JME_RSS_DEBUG */ 87 88 static int jme_probe(device_t); 89 static int jme_attach(device_t); 90 static int jme_detach(device_t); 91 static int jme_shutdown(device_t); 92 static int jme_suspend(device_t); 93 static int jme_resume(device_t); 94 95 static int jme_miibus_readreg(device_t, int, int); 96 static int jme_miibus_writereg(device_t, int, int, int); 97 static void jme_miibus_statchg(device_t); 98 99 static void jme_init(void *); 100 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 101 static void jme_start(struct ifnet *); 102 static void jme_watchdog(struct ifnet *); 103 static void jme_mediastatus(struct ifnet *, struct ifmediareq *); 104 static int jme_mediachange(struct ifnet *); 105 #ifdef DEVICE_POLLING 106 static void jme_poll(struct ifnet *, enum poll_cmd, int); 107 #endif 108 static void jme_serialize(struct ifnet *, enum ifnet_serialize); 109 static void jme_deserialize(struct ifnet *, enum ifnet_serialize); 110 static int jme_tryserialize(struct ifnet *, enum ifnet_serialize); 111 #ifdef INVARIANTS 112 static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize, 113 boolean_t); 114 #endif 115 116 static void jme_intr(void *); 117 static void jme_msix_tx(void *); 118 static void jme_msix_rx(void *); 119 static void jme_txeof(struct jme_softc *); 120 static void jme_rxeof(struct jme_rxdata *, int); 121 static void jme_rx_intr(struct jme_softc *, uint32_t); 122 123 static int jme_msix_setup(device_t); 124 static void jme_msix_teardown(device_t, int); 125 static int jme_intr_setup(device_t); 126 static void jme_intr_teardown(device_t); 127 static void jme_msix_try_alloc(device_t); 128 static void jme_msix_free(device_t); 129 static int jme_intr_alloc(device_t); 130 static void jme_intr_free(device_t); 131 static int jme_dma_alloc(struct jme_softc *); 132 static void jme_dma_free(struct jme_softc *); 133 static int jme_init_rx_ring(struct jme_rxdata *); 134 static void jme_init_tx_ring(struct jme_softc *); 135 static void jme_init_ssb(struct jme_softc *); 136 static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int); 137 static int jme_encap(struct jme_softc *, struct mbuf **); 138 static void jme_rxpkt(struct jme_rxdata *); 139 static int jme_rxring_dma_alloc(struct jme_rxdata *); 140 static int jme_rxbuf_dma_alloc(struct jme_rxdata *); 141 static int jme_rxbuf_dma_filter(void *, bus_addr_t); 142 143 static void jme_tick(void *); 144 static void jme_stop(struct jme_softc *); 145 static void jme_reset(struct jme_softc *); 146 static void jme_set_msinum(struct jme_softc *); 147 static void jme_set_vlan(struct jme_softc *); 148 static void jme_set_filter(struct jme_softc *); 149 static void jme_stop_tx(struct jme_softc *); 150 static void jme_stop_rx(struct jme_softc *); 151 static void jme_mac_config(struct jme_softc *); 152 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]); 153 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]); 154 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 155 #ifdef notyet 156 static void jme_setwol(struct jme_softc *); 157 static void jme_setlinkspeed(struct jme_softc *); 158 #endif 159 static void jme_set_tx_coal(struct jme_softc *); 160 static void jme_set_rx_coal(struct jme_softc *); 161 static void jme_enable_rss(struct jme_softc *); 162 static void jme_disable_rss(struct jme_softc *); 163 164 static void jme_sysctl_node(struct jme_softc *); 165 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS); 166 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 167 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS); 168 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 169 170 /* 171 * Devices supported by this driver. 172 */ 173 static const struct jme_dev { 174 uint16_t jme_vendorid; 175 uint16_t jme_deviceid; 176 uint32_t jme_caps; 177 const char *jme_name; 178 } jme_devs[] = { 179 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250, 180 JME_CAP_JUMBO, 181 "JMicron Inc, JMC250 Gigabit Ethernet" }, 182 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260, 183 JME_CAP_FASTETH, 184 "JMicron Inc, JMC260 Fast Ethernet" }, 185 { 0, 0, 0, NULL } 186 }; 187 188 static device_method_t jme_methods[] = { 189 /* Device interface. */ 190 DEVMETHOD(device_probe, jme_probe), 191 DEVMETHOD(device_attach, jme_attach), 192 DEVMETHOD(device_detach, jme_detach), 193 DEVMETHOD(device_shutdown, jme_shutdown), 194 DEVMETHOD(device_suspend, jme_suspend), 195 DEVMETHOD(device_resume, jme_resume), 196 197 /* Bus interface. */ 198 DEVMETHOD(bus_print_child, bus_generic_print_child), 199 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 200 201 /* MII interface. */ 202 DEVMETHOD(miibus_readreg, jme_miibus_readreg), 203 DEVMETHOD(miibus_writereg, jme_miibus_writereg), 204 DEVMETHOD(miibus_statchg, jme_miibus_statchg), 205 206 { NULL, NULL } 207 }; 208 209 static driver_t jme_driver = { 210 "jme", 211 jme_methods, 212 sizeof(struct jme_softc) 213 }; 214 215 static devclass_t jme_devclass; 216 217 DECLARE_DUMMY_MODULE(if_jme); 218 MODULE_DEPEND(if_jme, miibus, 1, 1, 1); 219 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL); 220 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL); 221 222 static const struct { 223 uint32_t jme_coal; 224 uint32_t jme_comp; 225 uint32_t jme_empty; 226 } jme_rx_status[JME_NRXRING_MAX] = { 227 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP, 228 INTR_RXQ0_DESC_EMPTY }, 229 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP, 230 INTR_RXQ1_DESC_EMPTY }, 231 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP, 232 INTR_RXQ2_DESC_EMPTY }, 233 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP, 234 INTR_RXQ3_DESC_EMPTY } 235 }; 236 237 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF; 238 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF; 239 static int jme_rx_ring_count = 0; 240 static int jme_msi_enable = 1; 241 static int jme_msix_enable = 1; 242 243 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count); 244 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count); 245 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count); 246 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable); 247 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable); 248 249 static __inline void 250 jme_setup_rxdesc(struct jme_rxdesc *rxd) 251 { 252 struct jme_desc *desc; 253 254 desc = rxd->rx_desc; 255 desc->buflen = htole32(MCLBYTES); 256 desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr)); 257 desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr)); 258 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 259 } 260 261 /* 262 * Read a PHY register on the MII of the JMC250. 263 */ 264 static int 265 jme_miibus_readreg(device_t dev, int phy, int reg) 266 { 267 struct jme_softc *sc = device_get_softc(dev); 268 uint32_t val; 269 int i; 270 271 /* For FPGA version, PHY address 0 should be ignored. */ 272 if (sc->jme_caps & JME_CAP_FPGA) { 273 if (phy == 0) 274 return (0); 275 } else { 276 if (sc->jme_phyaddr != phy) 277 return (0); 278 } 279 280 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 281 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 282 283 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 284 DELAY(1); 285 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 286 break; 287 } 288 if (i == 0) { 289 device_printf(sc->jme_dev, "phy read timeout: " 290 "phy %d, reg %d\n", phy, reg); 291 return (0); 292 } 293 294 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 295 } 296 297 /* 298 * Write a PHY register on the MII of the JMC250. 299 */ 300 static int 301 jme_miibus_writereg(device_t dev, int phy, int reg, int val) 302 { 303 struct jme_softc *sc = device_get_softc(dev); 304 int i; 305 306 /* For FPGA version, PHY address 0 should be ignored. */ 307 if (sc->jme_caps & JME_CAP_FPGA) { 308 if (phy == 0) 309 return (0); 310 } else { 311 if (sc->jme_phyaddr != phy) 312 return (0); 313 } 314 315 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 316 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 317 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 318 319 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 320 DELAY(1); 321 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 322 break; 323 } 324 if (i == 0) { 325 device_printf(sc->jme_dev, "phy write timeout: " 326 "phy %d, reg %d\n", phy, reg); 327 } 328 329 return (0); 330 } 331 332 /* 333 * Callback from MII layer when media changes. 334 */ 335 static void 336 jme_miibus_statchg(device_t dev) 337 { 338 struct jme_softc *sc = device_get_softc(dev); 339 struct ifnet *ifp = &sc->arpcom.ac_if; 340 struct mii_data *mii; 341 struct jme_txdesc *txd; 342 bus_addr_t paddr; 343 int i, r; 344 345 ASSERT_IFNET_SERIALIZED_ALL(ifp); 346 347 if ((ifp->if_flags & IFF_RUNNING) == 0) 348 return; 349 350 mii = device_get_softc(sc->jme_miibus); 351 352 sc->jme_flags &= ~JME_FLAG_LINK; 353 if ((mii->mii_media_status & IFM_AVALID) != 0) { 354 switch (IFM_SUBTYPE(mii->mii_media_active)) { 355 case IFM_10_T: 356 case IFM_100_TX: 357 sc->jme_flags |= JME_FLAG_LINK; 358 break; 359 case IFM_1000_T: 360 if (sc->jme_caps & JME_CAP_FASTETH) 361 break; 362 sc->jme_flags |= JME_FLAG_LINK; 363 break; 364 default: 365 break; 366 } 367 } 368 369 /* 370 * Disabling Rx/Tx MACs have a side-effect of resetting 371 * JME_TXNDA/JME_RXNDA register to the first address of 372 * Tx/Rx descriptor address. So driver should reset its 373 * internal procucer/consumer pointer and reclaim any 374 * allocated resources. Note, just saving the value of 375 * JME_TXNDA and JME_RXNDA registers before stopping MAC 376 * and restoring JME_TXNDA/JME_RXNDA register is not 377 * sufficient to make sure correct MAC state because 378 * stopping MAC operation can take a while and hardware 379 * might have updated JME_TXNDA/JME_RXNDA registers 380 * during the stop operation. 381 */ 382 383 /* Disable interrupts */ 384 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 385 386 /* Stop driver */ 387 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 388 ifp->if_timer = 0; 389 callout_stop(&sc->jme_tick_ch); 390 391 /* Stop receiver/transmitter. */ 392 jme_stop_rx(sc); 393 jme_stop_tx(sc); 394 395 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 396 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 397 398 jme_rxeof(rdata, -1); 399 if (rdata->jme_rxhead != NULL) 400 m_freem(rdata->jme_rxhead); 401 JME_RXCHAIN_RESET(rdata); 402 403 /* 404 * Reuse configured Rx descriptors and reset 405 * procuder/consumer index. 406 */ 407 rdata->jme_rx_cons = 0; 408 } 409 if (JME_ENABLE_HWRSS(sc)) 410 jme_enable_rss(sc); 411 else 412 jme_disable_rss(sc); 413 414 jme_txeof(sc); 415 if (sc->jme_cdata.jme_tx_cnt != 0) { 416 /* Remove queued packets for transmit. */ 417 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) { 418 txd = &sc->jme_cdata.jme_txdesc[i]; 419 if (txd->tx_m != NULL) { 420 bus_dmamap_unload( 421 sc->jme_cdata.jme_tx_tag, 422 txd->tx_dmamap); 423 m_freem(txd->tx_m); 424 txd->tx_m = NULL; 425 txd->tx_ndesc = 0; 426 ifp->if_oerrors++; 427 } 428 } 429 } 430 jme_init_tx_ring(sc); 431 432 /* Initialize shadow status block. */ 433 jme_init_ssb(sc); 434 435 /* Program MAC with resolved speed/duplex/flow-control. */ 436 if (sc->jme_flags & JME_FLAG_LINK) { 437 jme_mac_config(sc); 438 439 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 440 441 /* Set Tx ring address to the hardware. */ 442 paddr = sc->jme_cdata.jme_tx_ring_paddr; 443 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 444 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 445 446 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 447 CSR_WRITE_4(sc, JME_RXCSR, 448 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r)); 449 450 /* Set Rx ring address to the hardware. */ 451 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr; 452 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 453 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 454 } 455 456 /* Restart receiver/transmitter. */ 457 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 458 RXCSR_RXQ_START); 459 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 460 } 461 462 ifp->if_flags |= IFF_RUNNING; 463 ifp->if_flags &= ~IFF_OACTIVE; 464 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 465 466 #ifdef DEVICE_POLLING 467 if (!(ifp->if_flags & IFF_POLLING)) 468 #endif 469 /* Reenable interrupts. */ 470 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 471 } 472 473 /* 474 * Get the current interface media status. 475 */ 476 static void 477 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 478 { 479 struct jme_softc *sc = ifp->if_softc; 480 struct mii_data *mii = device_get_softc(sc->jme_miibus); 481 482 ASSERT_IFNET_SERIALIZED_ALL(ifp); 483 484 mii_pollstat(mii); 485 ifmr->ifm_status = mii->mii_media_status; 486 ifmr->ifm_active = mii->mii_media_active; 487 } 488 489 /* 490 * Set hardware to newly-selected media. 491 */ 492 static int 493 jme_mediachange(struct ifnet *ifp) 494 { 495 struct jme_softc *sc = ifp->if_softc; 496 struct mii_data *mii = device_get_softc(sc->jme_miibus); 497 int error; 498 499 ASSERT_IFNET_SERIALIZED_ALL(ifp); 500 501 if (mii->mii_instance != 0) { 502 struct mii_softc *miisc; 503 504 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 505 mii_phy_reset(miisc); 506 } 507 error = mii_mediachg(mii); 508 509 return (error); 510 } 511 512 static int 513 jme_probe(device_t dev) 514 { 515 const struct jme_dev *sp; 516 uint16_t vid, did; 517 518 vid = pci_get_vendor(dev); 519 did = pci_get_device(dev); 520 for (sp = jme_devs; sp->jme_name != NULL; ++sp) { 521 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) { 522 struct jme_softc *sc = device_get_softc(dev); 523 524 sc->jme_caps = sp->jme_caps; 525 device_set_desc(dev, sp->jme_name); 526 return (0); 527 } 528 } 529 return (ENXIO); 530 } 531 532 static int 533 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 534 { 535 uint32_t reg; 536 int i; 537 538 *val = 0; 539 for (i = JME_TIMEOUT; i > 0; i--) { 540 reg = CSR_READ_4(sc, JME_SMBCSR); 541 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 542 break; 543 DELAY(1); 544 } 545 546 if (i == 0) { 547 device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 548 return (ETIMEDOUT); 549 } 550 551 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 552 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 553 for (i = JME_TIMEOUT; i > 0; i--) { 554 DELAY(1); 555 reg = CSR_READ_4(sc, JME_SMBINTF); 556 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 557 break; 558 } 559 560 if (i == 0) { 561 device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 562 return (ETIMEDOUT); 563 } 564 565 reg = CSR_READ_4(sc, JME_SMBINTF); 566 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 567 568 return (0); 569 } 570 571 static int 572 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[]) 573 { 574 uint8_t fup, reg, val; 575 uint32_t offset; 576 int match; 577 578 offset = 0; 579 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 580 fup != JME_EEPROM_SIG0) 581 return (ENOENT); 582 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 583 fup != JME_EEPROM_SIG1) 584 return (ENOENT); 585 match = 0; 586 do { 587 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 588 break; 589 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 590 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 591 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 592 break; 593 if (reg >= JME_PAR0 && 594 reg < JME_PAR0 + ETHER_ADDR_LEN) { 595 if (jme_eeprom_read_byte(sc, offset + 2, 596 &val) != 0) 597 break; 598 eaddr[reg - JME_PAR0] = val; 599 match++; 600 } 601 } 602 /* Check for the end of EEPROM descriptor. */ 603 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 604 break; 605 /* Try next eeprom descriptor. */ 606 offset += JME_EEPROM_DESC_BYTES; 607 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 608 609 if (match == ETHER_ADDR_LEN) 610 return (0); 611 612 return (ENOENT); 613 } 614 615 static void 616 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[]) 617 { 618 uint32_t par0, par1; 619 620 /* Read station address. */ 621 par0 = CSR_READ_4(sc, JME_PAR0); 622 par1 = CSR_READ_4(sc, JME_PAR1); 623 par1 &= 0xFFFF; 624 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) { 625 device_printf(sc->jme_dev, 626 "generating fake ethernet address.\n"); 627 par0 = karc4random(); 628 /* Set OUI to JMicron. */ 629 eaddr[0] = 0x00; 630 eaddr[1] = 0x1B; 631 eaddr[2] = 0x8C; 632 eaddr[3] = (par0 >> 16) & 0xff; 633 eaddr[4] = (par0 >> 8) & 0xff; 634 eaddr[5] = par0 & 0xff; 635 } else { 636 eaddr[0] = (par0 >> 0) & 0xFF; 637 eaddr[1] = (par0 >> 8) & 0xFF; 638 eaddr[2] = (par0 >> 16) & 0xFF; 639 eaddr[3] = (par0 >> 24) & 0xFF; 640 eaddr[4] = (par1 >> 0) & 0xFF; 641 eaddr[5] = (par1 >> 8) & 0xFF; 642 } 643 } 644 645 static int 646 jme_attach(device_t dev) 647 { 648 struct jme_softc *sc = device_get_softc(dev); 649 struct ifnet *ifp = &sc->arpcom.ac_if; 650 uint32_t reg; 651 uint16_t did; 652 uint8_t pcie_ptr, rev; 653 int error = 0, i, j, rx_desc_cnt; 654 uint8_t eaddr[ETHER_ADDR_LEN]; 655 656 lwkt_serialize_init(&sc->jme_serialize); 657 lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize); 658 for (i = 0; i < JME_NRXRING_MAX; ++i) { 659 lwkt_serialize_init( 660 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize); 661 } 662 663 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count", 664 jme_rx_desc_count); 665 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN); 666 if (rx_desc_cnt > JME_NDESC_MAX) 667 rx_desc_cnt = JME_NDESC_MAX; 668 669 sc->jme_cdata.jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count", 670 jme_tx_desc_count); 671 sc->jme_cdata.jme_tx_desc_cnt = roundup(sc->jme_cdata.jme_tx_desc_cnt, 672 JME_NDESC_ALIGN); 673 if (sc->jme_cdata.jme_tx_desc_cnt > JME_NDESC_MAX) 674 sc->jme_cdata.jme_tx_desc_cnt = JME_NDESC_MAX; 675 676 /* 677 * Calculate rx rings 678 */ 679 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count", 680 jme_rx_ring_count); 681 sc->jme_cdata.jme_rx_ring_cnt = 682 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX); 683 684 i = 0; 685 sc->jme_serialize_arr[i++] = &sc->jme_serialize; 686 687 KKASSERT(i == JME_TX_SERIALIZE); 688 sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize; 689 690 KKASSERT(i == JME_RX_SERIALIZE); 691 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) { 692 sc->jme_serialize_arr[i++] = 693 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize; 694 } 695 KKASSERT(i <= JME_NSERIALIZE); 696 sc->jme_serialize_cnt = i; 697 698 sc->jme_cdata.jme_sc = sc; 699 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 700 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i]; 701 702 rdata->jme_sc = sc; 703 rdata->jme_rx_coal = jme_rx_status[i].jme_coal; 704 rdata->jme_rx_comp = jme_rx_status[i].jme_comp; 705 rdata->jme_rx_empty = jme_rx_status[i].jme_empty; 706 rdata->jme_rx_idx = i; 707 rdata->jme_rx_desc_cnt = rx_desc_cnt; 708 } 709 710 sc->jme_dev = dev; 711 sc->jme_lowaddr = BUS_SPACE_MAXADDR; 712 713 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 714 715 callout_init(&sc->jme_tick_ch); 716 717 #ifndef BURN_BRIDGES 718 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 719 uint32_t irq, mem; 720 721 irq = pci_read_config(dev, PCIR_INTLINE, 4); 722 mem = pci_read_config(dev, JME_PCIR_BAR, 4); 723 724 device_printf(dev, "chip is in D%d power mode " 725 "-- setting to D0\n", pci_get_powerstate(dev)); 726 727 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 728 729 pci_write_config(dev, PCIR_INTLINE, irq, 4); 730 pci_write_config(dev, JME_PCIR_BAR, mem, 4); 731 } 732 #endif /* !BURN_BRIDGE */ 733 734 /* Enable bus mastering */ 735 pci_enable_busmaster(dev); 736 737 /* 738 * Allocate IO memory 739 * 740 * JMC250 supports both memory mapped and I/O register space 741 * access. Because I/O register access should use different 742 * BARs to access registers it's waste of time to use I/O 743 * register spce access. JMC250 uses 16K to map entire memory 744 * space. 745 */ 746 sc->jme_mem_rid = JME_PCIR_BAR; 747 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 748 &sc->jme_mem_rid, RF_ACTIVE); 749 if (sc->jme_mem_res == NULL) { 750 device_printf(dev, "can't allocate IO memory\n"); 751 return ENXIO; 752 } 753 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res); 754 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res); 755 756 /* 757 * Allocate IRQ 758 */ 759 error = jme_intr_alloc(dev); 760 if (error) 761 goto fail; 762 763 /* 764 * Extract revisions 765 */ 766 reg = CSR_READ_4(sc, JME_CHIPMODE); 767 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 768 CHIPMODE_NOT_FPGA) { 769 sc->jme_caps |= JME_CAP_FPGA; 770 if (bootverbose) { 771 device_printf(dev, "FPGA revision: 0x%04x\n", 772 (reg & CHIPMODE_FPGA_REV_MASK) >> 773 CHIPMODE_FPGA_REV_SHIFT); 774 } 775 } 776 777 /* NOTE: FM revision is put in the upper 4 bits */ 778 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4; 779 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT; 780 if (bootverbose) 781 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev); 782 783 did = pci_get_device(dev); 784 switch (did) { 785 case PCI_PRODUCT_JMICRON_JMC250: 786 if (rev == JME_REV1_A2) 787 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX; 788 break; 789 790 case PCI_PRODUCT_JMICRON_JMC260: 791 if (rev == JME_REV2) 792 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT; 793 break; 794 795 default: 796 panic("unknown device id 0x%04x", did); 797 } 798 if (rev >= JME_REV2) { 799 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC; 800 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 | 801 GHC_TXMAC_CLKSRC_1000; 802 } 803 804 /* Reset the ethernet controller. */ 805 jme_reset(sc); 806 807 /* Map MSI/MSI-X vectors */ 808 jme_set_msinum(sc); 809 810 /* Get station address. */ 811 reg = CSR_READ_4(sc, JME_SMBCSR); 812 if (reg & SMBCSR_EEPROM_PRESENT) 813 error = jme_eeprom_macaddr(sc, eaddr); 814 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) { 815 if (error != 0 && (bootverbose)) { 816 device_printf(dev, "ethernet hardware address " 817 "not found in EEPROM.\n"); 818 } 819 jme_reg_macaddr(sc, eaddr); 820 } 821 822 /* 823 * Save PHY address. 824 * Integrated JR0211 has fixed PHY address whereas FPGA version 825 * requires PHY probing to get correct PHY address. 826 */ 827 if ((sc->jme_caps & JME_CAP_FPGA) == 0) { 828 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 829 GPREG0_PHY_ADDR_MASK; 830 if (bootverbose) { 831 device_printf(dev, "PHY is at address %d.\n", 832 sc->jme_phyaddr); 833 } 834 } else { 835 sc->jme_phyaddr = 0; 836 } 837 838 /* Set max allowable DMA size. */ 839 pcie_ptr = pci_get_pciecap_ptr(dev); 840 if (pcie_ptr != 0) { 841 uint16_t ctrl; 842 843 sc->jme_caps |= JME_CAP_PCIE; 844 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2); 845 if (bootverbose) { 846 device_printf(dev, "Read request size : %d bytes.\n", 847 128 << ((ctrl >> 12) & 0x07)); 848 device_printf(dev, "TLP payload size : %d bytes.\n", 849 128 << ((ctrl >> 5) & 0x07)); 850 } 851 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) { 852 case PCIEM_DEVCTL_MAX_READRQ_128: 853 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 854 break; 855 case PCIEM_DEVCTL_MAX_READRQ_256: 856 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 857 break; 858 default: 859 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 860 break; 861 } 862 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 863 } else { 864 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 865 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 866 } 867 868 #ifdef notyet 869 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) 870 sc->jme_caps |= JME_CAP_PMCAP; 871 #endif 872 873 /* 874 * Create sysctl tree 875 */ 876 jme_sysctl_node(sc); 877 878 /* Allocate DMA stuffs */ 879 error = jme_dma_alloc(sc); 880 if (error) 881 goto fail; 882 883 ifp->if_softc = sc; 884 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 885 ifp->if_init = jme_init; 886 ifp->if_ioctl = jme_ioctl; 887 ifp->if_start = jme_start; 888 #ifdef DEVICE_POLLING 889 ifp->if_poll = jme_poll; 890 #endif 891 ifp->if_watchdog = jme_watchdog; 892 ifp->if_serialize = jme_serialize; 893 ifp->if_deserialize = jme_deserialize; 894 ifp->if_tryserialize = jme_tryserialize; 895 #ifdef INVARIANTS 896 ifp->if_serialize_assert = jme_serialize_assert; 897 #endif 898 ifq_set_maxlen(&ifp->if_snd, 899 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD); 900 ifq_set_ready(&ifp->if_snd); 901 902 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */ 903 ifp->if_capabilities = IFCAP_HWCSUM | 904 IFCAP_VLAN_MTU | 905 IFCAP_VLAN_HWTAGGING; 906 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN) 907 ifp->if_capabilities |= IFCAP_RSS; 908 ifp->if_capenable = ifp->if_capabilities; 909 910 /* 911 * Disable TXCSUM by default to improve bulk data 912 * transmit performance (+20Mbps improvement). 913 */ 914 ifp->if_capenable &= ~IFCAP_TXCSUM; 915 916 if (ifp->if_capenable & IFCAP_TXCSUM) 917 ifp->if_hwassist = JME_CSUM_FEATURES; 918 919 /* Set up MII bus. */ 920 error = mii_phy_probe(dev, &sc->jme_miibus, 921 jme_mediachange, jme_mediastatus); 922 if (error) { 923 device_printf(dev, "no PHY found!\n"); 924 goto fail; 925 } 926 927 /* 928 * Save PHYADDR for FPGA mode PHY. 929 */ 930 if (sc->jme_caps & JME_CAP_FPGA) { 931 struct mii_data *mii = device_get_softc(sc->jme_miibus); 932 933 if (mii->mii_instance != 0) { 934 struct mii_softc *miisc; 935 936 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 937 if (miisc->mii_phy != 0) { 938 sc->jme_phyaddr = miisc->mii_phy; 939 break; 940 } 941 } 942 if (sc->jme_phyaddr != 0) { 943 device_printf(sc->jme_dev, 944 "FPGA PHY is at %d\n", sc->jme_phyaddr); 945 /* vendor magic. */ 946 jme_miibus_writereg(dev, sc->jme_phyaddr, 947 JMPHY_CONF, JMPHY_CONF_DEFFIFO); 948 949 /* XXX should we clear JME_WA_EXTFIFO */ 950 } 951 } 952 } 953 954 ether_ifattach(ifp, eaddr, NULL); 955 956 /* Tell the upper layer(s) we support long frames. */ 957 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 958 959 error = jme_intr_setup(dev); 960 if (error) { 961 ether_ifdetach(ifp); 962 goto fail; 963 } 964 965 return 0; 966 fail: 967 jme_detach(dev); 968 return (error); 969 } 970 971 static int 972 jme_detach(device_t dev) 973 { 974 struct jme_softc *sc = device_get_softc(dev); 975 976 if (device_is_attached(dev)) { 977 struct ifnet *ifp = &sc->arpcom.ac_if; 978 979 ifnet_serialize_all(ifp); 980 jme_stop(sc); 981 jme_intr_teardown(dev); 982 ifnet_deserialize_all(ifp); 983 984 ether_ifdetach(ifp); 985 } 986 987 if (sc->jme_sysctl_tree != NULL) 988 sysctl_ctx_free(&sc->jme_sysctl_ctx); 989 990 if (sc->jme_miibus != NULL) 991 device_delete_child(dev, sc->jme_miibus); 992 bus_generic_detach(dev); 993 994 jme_intr_free(dev); 995 996 if (sc->jme_mem_res != NULL) { 997 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid, 998 sc->jme_mem_res); 999 } 1000 1001 jme_dma_free(sc); 1002 1003 return (0); 1004 } 1005 1006 static void 1007 jme_sysctl_node(struct jme_softc *sc) 1008 { 1009 int coal_max; 1010 #ifdef JME_RSS_DEBUG 1011 int r; 1012 #endif 1013 1014 sysctl_ctx_init(&sc->jme_sysctl_ctx); 1015 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx, 1016 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 1017 device_get_nameunit(sc->jme_dev), 1018 CTLFLAG_RD, 0, ""); 1019 if (sc->jme_sysctl_tree == NULL) { 1020 device_printf(sc->jme_dev, "can't add sysctl node\n"); 1021 return; 1022 } 1023 1024 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1025 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1026 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW, 1027 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout"); 1028 1029 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1030 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1031 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, 1032 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet"); 1033 1034 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1035 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1036 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW, 1037 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout"); 1038 1039 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx, 1040 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1041 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, 1042 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet"); 1043 1044 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1045 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1046 "rx_desc_count", CTLFLAG_RD, 1047 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt, 1048 0, "RX desc count"); 1049 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1050 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1051 "tx_desc_count", CTLFLAG_RD, 1052 &sc->jme_cdata.jme_tx_desc_cnt, 1053 0, "TX desc count"); 1054 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1055 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1056 "rx_ring_count", CTLFLAG_RD, 1057 &sc->jme_cdata.jme_rx_ring_cnt, 1058 0, "RX ring count"); 1059 #ifdef JME_RSS_DEBUG 1060 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx, 1061 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1062 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug, 1063 0, "RSS debug level"); 1064 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1065 char rx_ring_pkt[32]; 1066 1067 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r); 1068 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx, 1069 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO, 1070 rx_ring_pkt, CTLFLAG_RW, 1071 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets"); 1072 } 1073 #endif 1074 1075 /* 1076 * Set default coalesce valves 1077 */ 1078 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 1079 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 1080 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 1081 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 1082 1083 /* 1084 * Adjust coalesce valves, in case that the number of TX/RX 1085 * descs are set to small values by users. 1086 * 1087 * NOTE: coal_max will not be zero, since number of descs 1088 * must aligned by JME_NDESC_ALIGN (16 currently) 1089 */ 1090 coal_max = sc->jme_cdata.jme_tx_desc_cnt / 6; 1091 if (coal_max < sc->jme_tx_coal_pkt) 1092 sc->jme_tx_coal_pkt = coal_max; 1093 1094 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4; 1095 if (coal_max < sc->jme_rx_coal_pkt) 1096 sc->jme_rx_coal_pkt = coal_max; 1097 } 1098 1099 static int 1100 jme_dma_alloc(struct jme_softc *sc) 1101 { 1102 struct jme_txdesc *txd; 1103 bus_dmamem_t dmem; 1104 int error, i, asize; 1105 1106 sc->jme_cdata.jme_txdesc = 1107 kmalloc(sc->jme_cdata.jme_tx_desc_cnt * sizeof(struct jme_txdesc), 1108 M_DEVBUF, M_WAITOK | M_ZERO); 1109 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 1110 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i]; 1111 1112 rdata->jme_rxdesc = 1113 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc), 1114 M_DEVBUF, M_WAITOK | M_ZERO); 1115 } 1116 1117 /* Create parent ring tag. */ 1118 error = bus_dma_tag_create(NULL,/* parent */ 1119 1, JME_RING_BOUNDARY, /* algnmnt, boundary */ 1120 sc->jme_lowaddr, /* lowaddr */ 1121 BUS_SPACE_MAXADDR, /* highaddr */ 1122 NULL, NULL, /* filter, filterarg */ 1123 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1124 0, /* nsegments */ 1125 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1126 0, /* flags */ 1127 &sc->jme_cdata.jme_ring_tag); 1128 if (error) { 1129 device_printf(sc->jme_dev, 1130 "could not create parent ring DMA tag.\n"); 1131 return error; 1132 } 1133 1134 /* 1135 * Create DMA stuffs for TX ring 1136 */ 1137 asize = roundup2(JME_TX_RING_SIZE(sc), JME_TX_RING_ALIGN); 1138 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag, 1139 JME_TX_RING_ALIGN, 0, 1140 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1141 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 1142 if (error) { 1143 device_printf(sc->jme_dev, "could not allocate Tx ring.\n"); 1144 return error; 1145 } 1146 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag; 1147 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map; 1148 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr; 1149 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr; 1150 1151 /* 1152 * Create DMA stuffs for RX rings 1153 */ 1154 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 1155 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]); 1156 if (error) 1157 return error; 1158 } 1159 1160 /* Create parent buffer tag. */ 1161 error = bus_dma_tag_create(NULL,/* parent */ 1162 1, 0, /* algnmnt, boundary */ 1163 sc->jme_lowaddr, /* lowaddr */ 1164 BUS_SPACE_MAXADDR, /* highaddr */ 1165 NULL, NULL, /* filter, filterarg */ 1166 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1167 0, /* nsegments */ 1168 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1169 0, /* flags */ 1170 &sc->jme_cdata.jme_buffer_tag); 1171 if (error) { 1172 device_printf(sc->jme_dev, 1173 "could not create parent buffer DMA tag.\n"); 1174 return error; 1175 } 1176 1177 /* 1178 * Create DMA stuffs for shadow status block 1179 */ 1180 asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN); 1181 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag, 1182 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1183 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 1184 if (error) { 1185 device_printf(sc->jme_dev, 1186 "could not create shadow status block.\n"); 1187 return error; 1188 } 1189 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag; 1190 sc->jme_cdata.jme_ssb_map = dmem.dmem_map; 1191 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr; 1192 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr; 1193 1194 /* 1195 * Create DMA stuffs for TX buffers 1196 */ 1197 1198 /* Create tag for Tx buffers. */ 1199 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1200 1, 0, /* algnmnt, boundary */ 1201 BUS_SPACE_MAXADDR, /* lowaddr */ 1202 BUS_SPACE_MAXADDR, /* highaddr */ 1203 NULL, NULL, /* filter, filterarg */ 1204 JME_JUMBO_FRAMELEN, /* maxsize */ 1205 JME_MAXTXSEGS, /* nsegments */ 1206 JME_MAXSEGSIZE, /* maxsegsize */ 1207 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */ 1208 &sc->jme_cdata.jme_tx_tag); 1209 if (error != 0) { 1210 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1211 return error; 1212 } 1213 1214 /* Create DMA maps for Tx buffers. */ 1215 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) { 1216 txd = &sc->jme_cdata.jme_txdesc[i]; 1217 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 1218 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1219 &txd->tx_dmamap); 1220 if (error) { 1221 int j; 1222 1223 device_printf(sc->jme_dev, 1224 "could not create %dth Tx dmamap.\n", i); 1225 1226 for (j = 0; j < i; ++j) { 1227 txd = &sc->jme_cdata.jme_txdesc[j]; 1228 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag, 1229 txd->tx_dmamap); 1230 } 1231 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag); 1232 sc->jme_cdata.jme_tx_tag = NULL; 1233 return error; 1234 } 1235 } 1236 1237 /* 1238 * Create DMA stuffs for RX buffers 1239 */ 1240 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 1241 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]); 1242 if (error) 1243 return error; 1244 } 1245 return 0; 1246 } 1247 1248 static void 1249 jme_dma_free(struct jme_softc *sc) 1250 { 1251 struct jme_txdesc *txd; 1252 struct jme_rxdesc *rxd; 1253 struct jme_rxdata *rdata; 1254 int i, r; 1255 1256 /* Tx ring */ 1257 if (sc->jme_cdata.jme_tx_ring_tag != NULL) { 1258 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag, 1259 sc->jme_cdata.jme_tx_ring_map); 1260 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag, 1261 sc->jme_cdata.jme_tx_ring, 1262 sc->jme_cdata.jme_tx_ring_map); 1263 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag); 1264 sc->jme_cdata.jme_tx_ring_tag = NULL; 1265 } 1266 1267 /* Rx ring */ 1268 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1269 rdata = &sc->jme_cdata.jme_rx_data[r]; 1270 if (rdata->jme_rx_ring_tag != NULL) { 1271 bus_dmamap_unload(rdata->jme_rx_ring_tag, 1272 rdata->jme_rx_ring_map); 1273 bus_dmamem_free(rdata->jme_rx_ring_tag, 1274 rdata->jme_rx_ring, 1275 rdata->jme_rx_ring_map); 1276 bus_dma_tag_destroy(rdata->jme_rx_ring_tag); 1277 rdata->jme_rx_ring_tag = NULL; 1278 } 1279 } 1280 1281 /* Tx buffers */ 1282 if (sc->jme_cdata.jme_tx_tag != NULL) { 1283 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) { 1284 txd = &sc->jme_cdata.jme_txdesc[i]; 1285 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag, 1286 txd->tx_dmamap); 1287 } 1288 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag); 1289 sc->jme_cdata.jme_tx_tag = NULL; 1290 } 1291 1292 /* Rx buffers */ 1293 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1294 rdata = &sc->jme_cdata.jme_rx_data[r]; 1295 if (rdata->jme_rx_tag != NULL) { 1296 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 1297 rxd = &rdata->jme_rxdesc[i]; 1298 bus_dmamap_destroy(rdata->jme_rx_tag, 1299 rxd->rx_dmamap); 1300 } 1301 bus_dmamap_destroy(rdata->jme_rx_tag, 1302 rdata->jme_rx_sparemap); 1303 bus_dma_tag_destroy(rdata->jme_rx_tag); 1304 rdata->jme_rx_tag = NULL; 1305 } 1306 } 1307 1308 /* Shadow status block. */ 1309 if (sc->jme_cdata.jme_ssb_tag != NULL) { 1310 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1311 sc->jme_cdata.jme_ssb_map); 1312 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1313 sc->jme_cdata.jme_ssb_block, 1314 sc->jme_cdata.jme_ssb_map); 1315 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1316 sc->jme_cdata.jme_ssb_tag = NULL; 1317 } 1318 1319 if (sc->jme_cdata.jme_buffer_tag != NULL) { 1320 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1321 sc->jme_cdata.jme_buffer_tag = NULL; 1322 } 1323 if (sc->jme_cdata.jme_ring_tag != NULL) { 1324 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1325 sc->jme_cdata.jme_ring_tag = NULL; 1326 } 1327 1328 if (sc->jme_cdata.jme_txdesc != NULL) { 1329 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF); 1330 sc->jme_cdata.jme_txdesc = NULL; 1331 } 1332 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1333 rdata = &sc->jme_cdata.jme_rx_data[r]; 1334 if (rdata->jme_rxdesc != NULL) { 1335 kfree(rdata->jme_rxdesc, M_DEVBUF); 1336 rdata->jme_rxdesc = NULL; 1337 } 1338 } 1339 } 1340 1341 /* 1342 * Make sure the interface is stopped at reboot time. 1343 */ 1344 static int 1345 jme_shutdown(device_t dev) 1346 { 1347 return jme_suspend(dev); 1348 } 1349 1350 #ifdef notyet 1351 /* 1352 * Unlike other ethernet controllers, JMC250 requires 1353 * explicit resetting link speed to 10/100Mbps as gigabit 1354 * link will cunsume more power than 375mA. 1355 * Note, we reset the link speed to 10/100Mbps with 1356 * auto-negotiation but we don't know whether that operation 1357 * would succeed or not as we have no control after powering 1358 * off. If the renegotiation fail WOL may not work. Running 1359 * at 1Gbps draws more power than 375mA at 3.3V which is 1360 * specified in PCI specification and that would result in 1361 * complete shutdowning power to ethernet controller. 1362 * 1363 * TODO 1364 * Save current negotiated media speed/duplex/flow-control 1365 * to softc and restore the same link again after resuming. 1366 * PHY handling such as power down/resetting to 100Mbps 1367 * may be better handled in suspend method in phy driver. 1368 */ 1369 static void 1370 jme_setlinkspeed(struct jme_softc *sc) 1371 { 1372 struct mii_data *mii; 1373 int aneg, i; 1374 1375 JME_LOCK_ASSERT(sc); 1376 1377 mii = device_get_softc(sc->jme_miibus); 1378 mii_pollstat(mii); 1379 aneg = 0; 1380 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1381 switch IFM_SUBTYPE(mii->mii_media_active) { 1382 case IFM_10_T: 1383 case IFM_100_TX: 1384 return; 1385 case IFM_1000_T: 1386 aneg++; 1387 default: 1388 break; 1389 } 1390 } 1391 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1392 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1393 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1394 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1395 BMCR_AUTOEN | BMCR_STARTNEG); 1396 DELAY(1000); 1397 if (aneg != 0) { 1398 /* Poll link state until jme(4) get a 10/100 link. */ 1399 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1400 mii_pollstat(mii); 1401 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1402 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1403 case IFM_10_T: 1404 case IFM_100_TX: 1405 jme_mac_config(sc); 1406 return; 1407 default: 1408 break; 1409 } 1410 } 1411 JME_UNLOCK(sc); 1412 pause("jmelnk", hz); 1413 JME_LOCK(sc); 1414 } 1415 if (i == MII_ANEGTICKS_GIGE) 1416 device_printf(sc->jme_dev, "establishing link failed, " 1417 "WOL may not work!"); 1418 } 1419 /* 1420 * No link, force MAC to have 100Mbps, full-duplex link. 1421 * This is the last resort and may/may not work. 1422 */ 1423 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1424 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1425 jme_mac_config(sc); 1426 } 1427 1428 static void 1429 jme_setwol(struct jme_softc *sc) 1430 { 1431 struct ifnet *ifp = &sc->arpcom.ac_if; 1432 uint32_t gpr, pmcs; 1433 uint16_t pmstat; 1434 int pmc; 1435 1436 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1437 /* No PME capability, PHY power down. */ 1438 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1439 MII_BMCR, BMCR_PDOWN); 1440 return; 1441 } 1442 1443 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1444 pmcs = CSR_READ_4(sc, JME_PMCS); 1445 pmcs &= ~PMCS_WOL_ENB_MASK; 1446 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1447 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1448 /* Enable PME message. */ 1449 gpr |= GPREG0_PME_ENB; 1450 /* For gigabit controllers, reset link speed to 10/100. */ 1451 if ((sc->jme_caps & JME_CAP_FASTETH) == 0) 1452 jme_setlinkspeed(sc); 1453 } 1454 1455 CSR_WRITE_4(sc, JME_PMCS, pmcs); 1456 CSR_WRITE_4(sc, JME_GPREG0, gpr); 1457 1458 /* Request PME. */ 1459 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1460 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1461 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1462 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1463 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1464 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1465 /* No WOL, PHY power down. */ 1466 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1467 MII_BMCR, BMCR_PDOWN); 1468 } 1469 } 1470 #endif 1471 1472 static int 1473 jme_suspend(device_t dev) 1474 { 1475 struct jme_softc *sc = device_get_softc(dev); 1476 struct ifnet *ifp = &sc->arpcom.ac_if; 1477 1478 ifnet_serialize_all(ifp); 1479 jme_stop(sc); 1480 #ifdef notyet 1481 jme_setwol(sc); 1482 #endif 1483 ifnet_deserialize_all(ifp); 1484 1485 return (0); 1486 } 1487 1488 static int 1489 jme_resume(device_t dev) 1490 { 1491 struct jme_softc *sc = device_get_softc(dev); 1492 struct ifnet *ifp = &sc->arpcom.ac_if; 1493 #ifdef notyet 1494 int pmc; 1495 #endif 1496 1497 ifnet_serialize_all(ifp); 1498 1499 #ifdef notyet 1500 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1501 uint16_t pmstat; 1502 1503 pmstat = pci_read_config(sc->jme_dev, 1504 pmc + PCIR_POWER_STATUS, 2); 1505 /* Disable PME clear PME status. */ 1506 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1507 pci_write_config(sc->jme_dev, 1508 pmc + PCIR_POWER_STATUS, pmstat, 2); 1509 } 1510 #endif 1511 1512 if (ifp->if_flags & IFF_UP) 1513 jme_init(sc); 1514 1515 ifnet_deserialize_all(ifp); 1516 1517 return (0); 1518 } 1519 1520 static int 1521 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1522 { 1523 struct jme_txdesc *txd; 1524 struct jme_desc *desc; 1525 struct mbuf *m; 1526 bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1527 int maxsegs, nsegs; 1528 int error, i, prod, symbol_desc; 1529 uint32_t cflags, flag64; 1530 1531 M_ASSERTPKTHDR((*m_head)); 1532 1533 prod = sc->jme_cdata.jme_tx_prod; 1534 txd = &sc->jme_cdata.jme_txdesc[prod]; 1535 1536 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) 1537 symbol_desc = 1; 1538 else 1539 symbol_desc = 0; 1540 1541 maxsegs = (sc->jme_cdata.jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) - 1542 (JME_TXD_RSVD + symbol_desc); 1543 if (maxsegs > JME_MAXTXSEGS) 1544 maxsegs = JME_MAXTXSEGS; 1545 KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc), 1546 ("not enough segments %d", maxsegs)); 1547 1548 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag, 1549 txd->tx_dmamap, m_head, 1550 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1551 if (error) 1552 goto fail; 1553 1554 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 1555 BUS_DMASYNC_PREWRITE); 1556 1557 m = *m_head; 1558 cflags = 0; 1559 1560 /* Configure checksum offload. */ 1561 if (m->m_pkthdr.csum_flags & CSUM_IP) 1562 cflags |= JME_TD_IPCSUM; 1563 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1564 cflags |= JME_TD_TCPCSUM; 1565 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1566 cflags |= JME_TD_UDPCSUM; 1567 1568 /* Configure VLAN. */ 1569 if (m->m_flags & M_VLANTAG) { 1570 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK); 1571 cflags |= JME_TD_VLAN_TAG; 1572 } 1573 1574 desc = &sc->jme_cdata.jme_tx_ring[prod]; 1575 desc->flags = htole32(cflags); 1576 desc->addr_hi = htole32(m->m_pkthdr.len); 1577 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1578 /* 1579 * Use 64bits TX desc chain format. 1580 * 1581 * The first TX desc of the chain, which is setup here, 1582 * is just a symbol TX desc carrying no payload. 1583 */ 1584 flag64 = JME_TD_64BIT; 1585 desc->buflen = 0; 1586 desc->addr_lo = 0; 1587 1588 /* No effective TX desc is consumed */ 1589 i = 0; 1590 } else { 1591 /* 1592 * Use 32bits TX desc chain format. 1593 * 1594 * The first TX desc of the chain, which is setup here, 1595 * is an effective TX desc carrying the first segment of 1596 * the mbuf chain. 1597 */ 1598 flag64 = 0; 1599 desc->buflen = htole32(txsegs[0].ds_len); 1600 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr)); 1601 1602 /* One effective TX desc is consumed */ 1603 i = 1; 1604 } 1605 sc->jme_cdata.jme_tx_cnt++; 1606 KKASSERT(sc->jme_cdata.jme_tx_cnt - i < 1607 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD); 1608 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt); 1609 1610 txd->tx_ndesc = 1 - i; 1611 for (; i < nsegs; i++) { 1612 desc = &sc->jme_cdata.jme_tx_ring[prod]; 1613 desc->buflen = htole32(txsegs[i].ds_len); 1614 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1615 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1616 desc->flags = htole32(JME_TD_OWN | flag64); 1617 1618 sc->jme_cdata.jme_tx_cnt++; 1619 KKASSERT(sc->jme_cdata.jme_tx_cnt <= 1620 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD); 1621 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt); 1622 } 1623 1624 /* Update producer index. */ 1625 sc->jme_cdata.jme_tx_prod = prod; 1626 /* 1627 * Finally request interrupt and give the first descriptor 1628 * owenership to hardware. 1629 */ 1630 desc = txd->tx_desc; 1631 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1632 1633 txd->tx_m = m; 1634 txd->tx_ndesc += nsegs; 1635 1636 return 0; 1637 fail: 1638 m_freem(*m_head); 1639 *m_head = NULL; 1640 return error; 1641 } 1642 1643 static void 1644 jme_start(struct ifnet *ifp) 1645 { 1646 struct jme_softc *sc = ifp->if_softc; 1647 struct mbuf *m_head; 1648 int enq = 0; 1649 1650 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize); 1651 1652 if ((sc->jme_flags & JME_FLAG_LINK) == 0) { 1653 ifq_purge(&ifp->if_snd); 1654 return; 1655 } 1656 1657 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1658 return; 1659 1660 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc)) 1661 jme_txeof(sc); 1662 1663 while (!ifq_is_empty(&ifp->if_snd)) { 1664 /* 1665 * Check number of available TX descs, always 1666 * leave JME_TXD_RSVD free TX descs. 1667 */ 1668 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare > 1669 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) { 1670 ifp->if_flags |= IFF_OACTIVE; 1671 break; 1672 } 1673 1674 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1675 if (m_head == NULL) 1676 break; 1677 1678 /* 1679 * Pack the data into the transmit ring. If we 1680 * don't have room, set the OACTIVE flag and wait 1681 * for the NIC to drain the ring. 1682 */ 1683 if (jme_encap(sc, &m_head)) { 1684 KKASSERT(m_head == NULL); 1685 ifp->if_oerrors++; 1686 ifp->if_flags |= IFF_OACTIVE; 1687 break; 1688 } 1689 enq++; 1690 1691 /* 1692 * If there's a BPF listener, bounce a copy of this frame 1693 * to him. 1694 */ 1695 ETHER_BPF_MTAP(ifp, m_head); 1696 } 1697 1698 if (enq > 0) { 1699 /* 1700 * Reading TXCSR takes very long time under heavy load 1701 * so cache TXCSR value and writes the ORed value with 1702 * the kick command to the TXCSR. This saves one register 1703 * access cycle. 1704 */ 1705 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1706 TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1707 /* Set a timeout in case the chip goes out to lunch. */ 1708 ifp->if_timer = JME_TX_TIMEOUT; 1709 } 1710 } 1711 1712 static void 1713 jme_watchdog(struct ifnet *ifp) 1714 { 1715 struct jme_softc *sc = ifp->if_softc; 1716 1717 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1718 1719 if ((sc->jme_flags & JME_FLAG_LINK) == 0) { 1720 if_printf(ifp, "watchdog timeout (missed link)\n"); 1721 ifp->if_oerrors++; 1722 jme_init(sc); 1723 return; 1724 } 1725 1726 jme_txeof(sc); 1727 if (sc->jme_cdata.jme_tx_cnt == 0) { 1728 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 1729 "-- recovering\n"); 1730 if (!ifq_is_empty(&ifp->if_snd)) 1731 if_devstart(ifp); 1732 return; 1733 } 1734 1735 if_printf(ifp, "watchdog timeout\n"); 1736 ifp->if_oerrors++; 1737 jme_init(sc); 1738 if (!ifq_is_empty(&ifp->if_snd)) 1739 if_devstart(ifp); 1740 } 1741 1742 static int 1743 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1744 { 1745 struct jme_softc *sc = ifp->if_softc; 1746 struct mii_data *mii = device_get_softc(sc->jme_miibus); 1747 struct ifreq *ifr = (struct ifreq *)data; 1748 int error = 0, mask; 1749 1750 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1751 1752 switch (cmd) { 1753 case SIOCSIFMTU: 1754 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1755 (!(sc->jme_caps & JME_CAP_JUMBO) && 1756 ifr->ifr_mtu > JME_MAX_MTU)) { 1757 error = EINVAL; 1758 break; 1759 } 1760 1761 if (ifp->if_mtu != ifr->ifr_mtu) { 1762 /* 1763 * No special configuration is required when interface 1764 * MTU is changed but availability of Tx checksum 1765 * offload should be chcked against new MTU size as 1766 * FIFO size is just 2K. 1767 */ 1768 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 1769 ifp->if_capenable &= ~IFCAP_TXCSUM; 1770 ifp->if_hwassist &= ~JME_CSUM_FEATURES; 1771 } 1772 ifp->if_mtu = ifr->ifr_mtu; 1773 if (ifp->if_flags & IFF_RUNNING) 1774 jme_init(sc); 1775 } 1776 break; 1777 1778 case SIOCSIFFLAGS: 1779 if (ifp->if_flags & IFF_UP) { 1780 if (ifp->if_flags & IFF_RUNNING) { 1781 if ((ifp->if_flags ^ sc->jme_if_flags) & 1782 (IFF_PROMISC | IFF_ALLMULTI)) 1783 jme_set_filter(sc); 1784 } else { 1785 jme_init(sc); 1786 } 1787 } else { 1788 if (ifp->if_flags & IFF_RUNNING) 1789 jme_stop(sc); 1790 } 1791 sc->jme_if_flags = ifp->if_flags; 1792 break; 1793 1794 case SIOCADDMULTI: 1795 case SIOCDELMULTI: 1796 if (ifp->if_flags & IFF_RUNNING) 1797 jme_set_filter(sc); 1798 break; 1799 1800 case SIOCSIFMEDIA: 1801 case SIOCGIFMEDIA: 1802 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1803 break; 1804 1805 case SIOCSIFCAP: 1806 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1807 1808 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) { 1809 ifp->if_capenable ^= IFCAP_TXCSUM; 1810 if (IFCAP_TXCSUM & ifp->if_capenable) 1811 ifp->if_hwassist |= JME_CSUM_FEATURES; 1812 else 1813 ifp->if_hwassist &= ~JME_CSUM_FEATURES; 1814 } 1815 if (mask & IFCAP_RXCSUM) { 1816 uint32_t reg; 1817 1818 ifp->if_capenable ^= IFCAP_RXCSUM; 1819 reg = CSR_READ_4(sc, JME_RXMAC); 1820 reg &= ~RXMAC_CSUM_ENB; 1821 if (ifp->if_capenable & IFCAP_RXCSUM) 1822 reg |= RXMAC_CSUM_ENB; 1823 CSR_WRITE_4(sc, JME_RXMAC, reg); 1824 } 1825 1826 if (mask & IFCAP_VLAN_HWTAGGING) { 1827 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1828 jme_set_vlan(sc); 1829 } 1830 1831 if (mask & IFCAP_RSS) 1832 ifp->if_capenable ^= IFCAP_RSS; 1833 break; 1834 1835 default: 1836 error = ether_ioctl(ifp, cmd, data); 1837 break; 1838 } 1839 return (error); 1840 } 1841 1842 static void 1843 jme_mac_config(struct jme_softc *sc) 1844 { 1845 struct mii_data *mii; 1846 uint32_t ghc, rxmac, txmac, txpause, gp1; 1847 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0; 1848 1849 mii = device_get_softc(sc->jme_miibus); 1850 1851 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 1852 DELAY(10); 1853 CSR_WRITE_4(sc, JME_GHC, 0); 1854 ghc = 0; 1855 rxmac = CSR_READ_4(sc, JME_RXMAC); 1856 rxmac &= ~RXMAC_FC_ENB; 1857 txmac = CSR_READ_4(sc, JME_TXMAC); 1858 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1859 txpause = CSR_READ_4(sc, JME_TXPFC); 1860 txpause &= ~TXPFC_PAUSE_ENB; 1861 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1862 ghc |= GHC_FULL_DUPLEX; 1863 rxmac &= ~RXMAC_COLL_DET_ENB; 1864 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1865 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1866 TXMAC_FRAME_BURST); 1867 #ifdef notyet 1868 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1869 txpause |= TXPFC_PAUSE_ENB; 1870 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1871 rxmac |= RXMAC_FC_ENB; 1872 #endif 1873 /* Disable retry transmit timer/retry limit. */ 1874 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 1875 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 1876 } else { 1877 rxmac |= RXMAC_COLL_DET_ENB; 1878 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 1879 /* Enable retry transmit timer/retry limit. */ 1880 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 1881 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 1882 } 1883 1884 /* 1885 * Reprogram Tx/Rx MACs with resolved speed/duplex. 1886 */ 1887 gp1 = CSR_READ_4(sc, JME_GPREG1); 1888 gp1 &= ~GPREG1_WA_HDX; 1889 1890 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 1891 hdx = 1; 1892 1893 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1894 case IFM_10_T: 1895 ghc |= GHC_SPEED_10 | sc->jme_clksrc; 1896 if (hdx) 1897 gp1 |= GPREG1_WA_HDX; 1898 break; 1899 1900 case IFM_100_TX: 1901 ghc |= GHC_SPEED_100 | sc->jme_clksrc; 1902 if (hdx) 1903 gp1 |= GPREG1_WA_HDX; 1904 1905 /* 1906 * Use extended FIFO depth to workaround CRC errors 1907 * emitted by chips before JMC250B 1908 */ 1909 phyconf = JMPHY_CONF_EXTFIFO; 1910 break; 1911 1912 case IFM_1000_T: 1913 if (sc->jme_caps & JME_CAP_FASTETH) 1914 break; 1915 1916 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000; 1917 if (hdx) 1918 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 1919 break; 1920 1921 default: 1922 break; 1923 } 1924 CSR_WRITE_4(sc, JME_GHC, ghc); 1925 CSR_WRITE_4(sc, JME_RXMAC, rxmac); 1926 CSR_WRITE_4(sc, JME_TXMAC, txmac); 1927 CSR_WRITE_4(sc, JME_TXPFC, txpause); 1928 1929 if (sc->jme_workaround & JME_WA_EXTFIFO) { 1930 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1931 JMPHY_CONF, phyconf); 1932 } 1933 if (sc->jme_workaround & JME_WA_HDX) 1934 CSR_WRITE_4(sc, JME_GPREG1, gp1); 1935 } 1936 1937 static void 1938 jme_intr(void *xsc) 1939 { 1940 struct jme_softc *sc = xsc; 1941 struct ifnet *ifp = &sc->arpcom.ac_if; 1942 uint32_t status; 1943 int r; 1944 1945 ASSERT_SERIALIZED(&sc->jme_serialize); 1946 1947 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 1948 if (status == 0 || status == 0xFFFFFFFF) 1949 return; 1950 1951 /* Disable interrupts. */ 1952 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 1953 1954 status = CSR_READ_4(sc, JME_INTR_STATUS); 1955 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 1956 goto back; 1957 1958 /* Reset PCC counter/timer and Ack interrupts. */ 1959 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 1960 1961 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) 1962 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 1963 1964 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1965 if (status & jme_rx_status[r].jme_coal) { 1966 status |= jme_rx_status[r].jme_coal | 1967 jme_rx_status[r].jme_comp; 1968 } 1969 } 1970 1971 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 1972 1973 if (ifp->if_flags & IFF_RUNNING) { 1974 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) 1975 jme_rx_intr(sc, status); 1976 1977 if (status & INTR_RXQ_DESC_EMPTY) { 1978 /* 1979 * Notify hardware availability of new Rx buffers. 1980 * Reading RXCSR takes very long time under heavy 1981 * load so cache RXCSR value and writes the ORed 1982 * value with the kick command to the RXCSR. This 1983 * saves one register access cycle. 1984 */ 1985 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 1986 RXCSR_RX_ENB | RXCSR_RXQ_START); 1987 } 1988 1989 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) { 1990 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize); 1991 jme_txeof(sc); 1992 if (!ifq_is_empty(&ifp->if_snd)) 1993 if_devstart(ifp); 1994 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize); 1995 } 1996 } 1997 back: 1998 /* Reenable interrupts. */ 1999 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2000 } 2001 2002 static void 2003 jme_txeof(struct jme_softc *sc) 2004 { 2005 struct ifnet *ifp = &sc->arpcom.ac_if; 2006 struct jme_txdesc *txd; 2007 uint32_t status; 2008 int cons, nsegs; 2009 2010 cons = sc->jme_cdata.jme_tx_cons; 2011 if (cons == sc->jme_cdata.jme_tx_prod) 2012 return; 2013 2014 /* 2015 * Go through our Tx list and free mbufs for those 2016 * frames which have been transmitted. 2017 */ 2018 while (cons != sc->jme_cdata.jme_tx_prod) { 2019 txd = &sc->jme_cdata.jme_txdesc[cons]; 2020 KASSERT(txd->tx_m != NULL, 2021 ("%s: freeing NULL mbuf!", __func__)); 2022 2023 status = le32toh(txd->tx_desc->flags); 2024 if ((status & JME_TD_OWN) == JME_TD_OWN) 2025 break; 2026 2027 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) { 2028 ifp->if_oerrors++; 2029 } else { 2030 ifp->if_opackets++; 2031 if (status & JME_TD_COLLISION) { 2032 ifp->if_collisions += 2033 le32toh(txd->tx_desc->buflen) & 2034 JME_TD_BUF_LEN_MASK; 2035 } 2036 } 2037 2038 /* 2039 * Only the first descriptor of multi-descriptor 2040 * transmission is updated so driver have to skip entire 2041 * chained buffers for the transmiited frame. In other 2042 * words, JME_TD_OWN bit is valid only at the first 2043 * descriptor of a multi-descriptor transmission. 2044 */ 2045 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2046 sc->jme_cdata.jme_tx_ring[cons].flags = 0; 2047 JME_DESC_INC(cons, sc->jme_cdata.jme_tx_desc_cnt); 2048 } 2049 2050 /* Reclaim transferred mbufs. */ 2051 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 2052 m_freem(txd->tx_m); 2053 txd->tx_m = NULL; 2054 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc; 2055 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0, 2056 ("%s: Active Tx desc counter was garbled", __func__)); 2057 txd->tx_ndesc = 0; 2058 } 2059 sc->jme_cdata.jme_tx_cons = cons; 2060 2061 if (sc->jme_cdata.jme_tx_cnt == 0) 2062 ifp->if_timer = 0; 2063 2064 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <= 2065 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) 2066 ifp->if_flags &= ~IFF_OACTIVE; 2067 } 2068 2069 static __inline void 2070 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count) 2071 { 2072 int i; 2073 2074 for (i = 0; i < count; ++i) { 2075 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]); 2076 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt); 2077 } 2078 } 2079 2080 static __inline struct pktinfo * 2081 jme_pktinfo(struct pktinfo *pi, uint32_t flags) 2082 { 2083 if (flags & JME_RD_IPV4) 2084 pi->pi_netisr = NETISR_IP; 2085 else if (flags & JME_RD_IPV6) 2086 pi->pi_netisr = NETISR_IPV6; 2087 else 2088 return NULL; 2089 2090 pi->pi_flags = 0; 2091 pi->pi_l3proto = IPPROTO_UNKNOWN; 2092 2093 if (flags & JME_RD_MORE_FRAG) 2094 pi->pi_flags |= PKTINFO_FLAG_FRAG; 2095 else if (flags & JME_RD_TCP) 2096 pi->pi_l3proto = IPPROTO_TCP; 2097 else if (flags & JME_RD_UDP) 2098 pi->pi_l3proto = IPPROTO_UDP; 2099 else 2100 pi = NULL; 2101 return pi; 2102 } 2103 2104 /* Receive a frame. */ 2105 static void 2106 jme_rxpkt(struct jme_rxdata *rdata) 2107 { 2108 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if; 2109 struct jme_desc *desc; 2110 struct jme_rxdesc *rxd; 2111 struct mbuf *mp, *m; 2112 uint32_t flags, status, hash, hashinfo; 2113 int cons, count, nsegs; 2114 2115 cons = rdata->jme_rx_cons; 2116 desc = &rdata->jme_rx_ring[cons]; 2117 2118 flags = le32toh(desc->flags); 2119 status = le32toh(desc->buflen); 2120 hash = le32toh(desc->addr_hi); 2121 hashinfo = le32toh(desc->addr_lo); 2122 nsegs = JME_RX_NSEGS(status); 2123 2124 if (nsegs > 1) { 2125 /* Skip the first descriptor. */ 2126 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt); 2127 2128 /* 2129 * Clear the OWN bit of the following RX descriptors; 2130 * hardware will not clear the OWN bit except the first 2131 * RX descriptor. 2132 * 2133 * Since the first RX descriptor is setup, i.e. OWN bit 2134 * on, before its followins RX descriptors, leaving the 2135 * OWN bit on the following RX descriptors will trick 2136 * the hardware into thinking that the following RX 2137 * descriptors are ready to be used too. 2138 */ 2139 for (count = 1; count < nsegs; count++, 2140 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) 2141 rdata->jme_rx_ring[cons].flags = 0; 2142 2143 cons = rdata->jme_rx_cons; 2144 } 2145 2146 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, " 2147 "hash 0x%08x, hash info 0x%08x\n", 2148 rdata->jme_rx_idx, flags, hash, hashinfo); 2149 2150 if (status & JME_RX_ERR_STAT) { 2151 ifp->if_ierrors++; 2152 jme_discard_rxbufs(rdata, cons, nsegs); 2153 #ifdef JME_SHOW_ERRORS 2154 if_printf(ifp, "%s : receive error = 0x%b\n", 2155 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2156 #endif 2157 rdata->jme_rx_cons += nsegs; 2158 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt; 2159 return; 2160 } 2161 2162 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2163 for (count = 0; count < nsegs; count++, 2164 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) { 2165 rxd = &rdata->jme_rxdesc[cons]; 2166 mp = rxd->rx_m; 2167 2168 /* Add a new receive buffer to the ring. */ 2169 if (jme_newbuf(rdata, rxd, 0) != 0) { 2170 ifp->if_iqdrops++; 2171 /* Reuse buffer. */ 2172 jme_discard_rxbufs(rdata, cons, nsegs - count); 2173 if (rdata->jme_rxhead != NULL) { 2174 m_freem(rdata->jme_rxhead); 2175 JME_RXCHAIN_RESET(rdata); 2176 } 2177 break; 2178 } 2179 2180 /* 2181 * Assume we've received a full sized frame. 2182 * Actual size is fixed when we encounter the end of 2183 * multi-segmented frame. 2184 */ 2185 mp->m_len = MCLBYTES; 2186 2187 /* Chain received mbufs. */ 2188 if (rdata->jme_rxhead == NULL) { 2189 rdata->jme_rxhead = mp; 2190 rdata->jme_rxtail = mp; 2191 } else { 2192 /* 2193 * Receive processor can receive a maximum frame 2194 * size of 65535 bytes. 2195 */ 2196 rdata->jme_rxtail->m_next = mp; 2197 rdata->jme_rxtail = mp; 2198 } 2199 2200 if (count == nsegs - 1) { 2201 struct pktinfo pi0, *pi; 2202 2203 /* Last desc. for this frame. */ 2204 m = rdata->jme_rxhead; 2205 m->m_pkthdr.len = rdata->jme_rxlen; 2206 if (nsegs > 1) { 2207 /* Set first mbuf size. */ 2208 m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2209 /* Set last mbuf size. */ 2210 mp->m_len = rdata->jme_rxlen - 2211 ((MCLBYTES - JME_RX_PAD_BYTES) + 2212 (MCLBYTES * (nsegs - 2))); 2213 } else { 2214 m->m_len = rdata->jme_rxlen; 2215 } 2216 m->m_pkthdr.rcvif = ifp; 2217 2218 /* 2219 * Account for 10bytes auto padding which is used 2220 * to align IP header on 32bit boundary. Also note, 2221 * CRC bytes is automatically removed by the 2222 * hardware. 2223 */ 2224 m->m_data += JME_RX_PAD_BYTES; 2225 2226 /* Set checksum information. */ 2227 if ((ifp->if_capenable & IFCAP_RXCSUM) && 2228 (flags & JME_RD_IPV4)) { 2229 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2230 if (flags & JME_RD_IPCSUM) 2231 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2232 if ((flags & JME_RD_MORE_FRAG) == 0 && 2233 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2234 (JME_RD_TCP | JME_RD_TCPCSUM) || 2235 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2236 (JME_RD_UDP | JME_RD_UDPCSUM))) { 2237 m->m_pkthdr.csum_flags |= 2238 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2239 m->m_pkthdr.csum_data = 0xffff; 2240 } 2241 } 2242 2243 /* Check for VLAN tagged packets. */ 2244 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) && 2245 (flags & JME_RD_VLAN_TAG)) { 2246 m->m_pkthdr.ether_vlantag = 2247 flags & JME_RD_VLAN_MASK; 2248 m->m_flags |= M_VLANTAG; 2249 } 2250 2251 ifp->if_ipackets++; 2252 2253 if (ifp->if_capenable & IFCAP_RSS) 2254 pi = jme_pktinfo(&pi0, flags); 2255 else 2256 pi = NULL; 2257 2258 if (pi != NULL && 2259 (hashinfo & JME_RD_HASH_FN_MASK) != 0) { 2260 m->m_flags |= M_HASH; 2261 m->m_pkthdr.hash = toeplitz_hash(hash); 2262 } 2263 2264 #ifdef JME_RSS_DEBUG 2265 if (pi != NULL) { 2266 JME_RSS_DPRINTF(rdata->jme_sc, 10, 2267 "isr %d flags %08x, l3 %d %s\n", 2268 pi->pi_netisr, pi->pi_flags, 2269 pi->pi_l3proto, 2270 (m->m_flags & M_HASH) ? "hash" : ""); 2271 } 2272 #endif 2273 2274 /* Pass it on. */ 2275 ether_input_pkt(ifp, m, pi); 2276 2277 /* Reset mbuf chains. */ 2278 JME_RXCHAIN_RESET(rdata); 2279 #ifdef JME_RSS_DEBUG 2280 rdata->jme_rx_pkt++; 2281 #endif 2282 } 2283 } 2284 2285 rdata->jme_rx_cons += nsegs; 2286 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt; 2287 } 2288 2289 static void 2290 jme_rxeof(struct jme_rxdata *rdata, int count) 2291 { 2292 struct jme_desc *desc; 2293 int nsegs, pktlen; 2294 2295 for (;;) { 2296 #ifdef DEVICE_POLLING 2297 if (count >= 0 && count-- == 0) 2298 break; 2299 #endif 2300 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons]; 2301 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2302 break; 2303 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2304 break; 2305 2306 /* 2307 * Check number of segments against received bytes. 2308 * Non-matching value would indicate that hardware 2309 * is still trying to update Rx descriptors. I'm not 2310 * sure whether this check is needed. 2311 */ 2312 nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2313 pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2314 if (nsegs != howmany(pktlen, MCLBYTES)) { 2315 if_printf(&rdata->jme_sc->arpcom.ac_if, 2316 "RX fragment count(%d) and " 2317 "packet size(%d) mismach\n", nsegs, pktlen); 2318 break; 2319 } 2320 2321 /* 2322 * NOTE: 2323 * RSS hash and hash information may _not_ be set by the 2324 * hardware even if the OWN bit is cleared and VALID bit 2325 * is set. 2326 * 2327 * If the RSS information is not delivered by the hardware 2328 * yet, we MUST NOT accept this packet, let alone reusing 2329 * its RX descriptor. If this packet was accepted and its 2330 * RX descriptor was reused before hardware delivering the 2331 * RSS information, the RX buffer's address would be trashed 2332 * by the RSS information delivered by the hardware. 2333 */ 2334 if (JME_ENABLE_HWRSS(rdata->jme_sc)) { 2335 struct jme_rxdesc *rxd; 2336 uint32_t hashinfo; 2337 2338 hashinfo = le32toh(desc->addr_lo); 2339 rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons]; 2340 2341 /* 2342 * This test should be enough to detect the pending 2343 * RSS information delivery, given: 2344 * - If RSS hash is not calculated, the hashinfo 2345 * will be 0. Howvever, the lower 32bits of RX 2346 * buffers' physical address will never be 0. 2347 * (see jme_rxbuf_dma_filter) 2348 * - If RSS hash is calculated, the lowest 4 bits 2349 * of hashinfo will be set, while the RX buffers 2350 * are at least 2K aligned. 2351 */ 2352 if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) { 2353 #ifdef JME_SHOW_RSSWB 2354 if_printf(&rdata->jme_sc->arpcom.ac_if, 2355 "RSS is not written back yet\n"); 2356 #endif 2357 break; 2358 } 2359 } 2360 2361 /* Received a frame. */ 2362 jme_rxpkt(rdata); 2363 } 2364 } 2365 2366 static void 2367 jme_tick(void *xsc) 2368 { 2369 struct jme_softc *sc = xsc; 2370 struct ifnet *ifp = &sc->arpcom.ac_if; 2371 struct mii_data *mii = device_get_softc(sc->jme_miibus); 2372 2373 ifnet_serialize_all(ifp); 2374 2375 mii_tick(mii); 2376 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2377 2378 ifnet_deserialize_all(ifp); 2379 } 2380 2381 static void 2382 jme_reset(struct jme_softc *sc) 2383 { 2384 uint32_t val; 2385 2386 /* Make sure that TX and RX are stopped */ 2387 jme_stop_tx(sc); 2388 jme_stop_rx(sc); 2389 2390 /* Start reset */ 2391 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2392 DELAY(20); 2393 2394 /* 2395 * Hold reset bit before stop reset 2396 */ 2397 2398 /* Disable TXMAC and TXOFL clock sources */ 2399 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2400 /* Disable RXMAC clock source */ 2401 val = CSR_READ_4(sc, JME_GPREG1); 2402 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC); 2403 /* Flush */ 2404 CSR_READ_4(sc, JME_GHC); 2405 2406 /* Stop reset */ 2407 CSR_WRITE_4(sc, JME_GHC, 0); 2408 /* Flush */ 2409 CSR_READ_4(sc, JME_GHC); 2410 2411 /* 2412 * Clear reset bit after stop reset 2413 */ 2414 2415 /* Enable TXMAC and TXOFL clock sources */ 2416 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC); 2417 /* Enable RXMAC clock source */ 2418 val = CSR_READ_4(sc, JME_GPREG1); 2419 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC); 2420 /* Flush */ 2421 CSR_READ_4(sc, JME_GHC); 2422 2423 /* Disable TXMAC and TXOFL clock sources */ 2424 CSR_WRITE_4(sc, JME_GHC, 0); 2425 /* Disable RXMAC clock source */ 2426 val = CSR_READ_4(sc, JME_GPREG1); 2427 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC); 2428 /* Flush */ 2429 CSR_READ_4(sc, JME_GHC); 2430 2431 /* Enable TX and RX */ 2432 val = CSR_READ_4(sc, JME_TXCSR); 2433 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB); 2434 val = CSR_READ_4(sc, JME_RXCSR); 2435 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB); 2436 /* Flush */ 2437 CSR_READ_4(sc, JME_TXCSR); 2438 CSR_READ_4(sc, JME_RXCSR); 2439 2440 /* Enable TXMAC and TXOFL clock sources */ 2441 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC); 2442 /* Eisable RXMAC clock source */ 2443 val = CSR_READ_4(sc, JME_GPREG1); 2444 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC); 2445 /* Flush */ 2446 CSR_READ_4(sc, JME_GHC); 2447 2448 /* Stop TX and RX */ 2449 jme_stop_tx(sc); 2450 jme_stop_rx(sc); 2451 } 2452 2453 static void 2454 jme_init(void *xsc) 2455 { 2456 struct jme_softc *sc = xsc; 2457 struct ifnet *ifp = &sc->arpcom.ac_if; 2458 struct mii_data *mii; 2459 uint8_t eaddr[ETHER_ADDR_LEN]; 2460 bus_addr_t paddr; 2461 uint32_t reg; 2462 int error, r; 2463 2464 ASSERT_IFNET_SERIALIZED_ALL(ifp); 2465 2466 /* 2467 * Cancel any pending I/O. 2468 */ 2469 jme_stop(sc); 2470 2471 /* 2472 * Reset the chip to a known state. 2473 */ 2474 jme_reset(sc); 2475 2476 /* 2477 * Setup MSI/MSI-X vectors to interrupts mapping 2478 */ 2479 jme_set_msinum(sc); 2480 2481 sc->jme_txd_spare = 2482 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES); 2483 KKASSERT(sc->jme_txd_spare >= 1); 2484 2485 /* 2486 * If we use 64bit address mode for transmitting, each Tx request 2487 * needs one more symbol descriptor. 2488 */ 2489 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) 2490 sc->jme_txd_spare += 1; 2491 2492 if (JME_ENABLE_HWRSS(sc)) 2493 jme_enable_rss(sc); 2494 else 2495 jme_disable_rss(sc); 2496 2497 /* Init RX descriptors */ 2498 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2499 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]); 2500 if (error) { 2501 if_printf(ifp, "initialization failed: " 2502 "no memory for %dth RX ring.\n", r); 2503 jme_stop(sc); 2504 return; 2505 } 2506 } 2507 2508 /* Init TX descriptors */ 2509 jme_init_tx_ring(sc); 2510 2511 /* Initialize shadow status block. */ 2512 jme_init_ssb(sc); 2513 2514 /* Reprogram the station address. */ 2515 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2516 CSR_WRITE_4(sc, JME_PAR0, 2517 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 2518 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 2519 2520 /* 2521 * Configure Tx queue. 2522 * Tx priority queue weight value : 0 2523 * Tx FIFO threshold for processing next packet : 16QW 2524 * Maximum Tx DMA length : 512 2525 * Allow Tx DMA burst. 2526 */ 2527 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2528 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2529 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2530 sc->jme_txcsr |= sc->jme_tx_dma_size; 2531 sc->jme_txcsr |= TXCSR_DMA_BURST; 2532 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2533 2534 /* Set Tx descriptor counter. */ 2535 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_desc_cnt); 2536 2537 /* Set Tx ring address to the hardware. */ 2538 paddr = sc->jme_cdata.jme_tx_ring_paddr; 2539 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2540 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2541 2542 /* Configure TxMAC parameters. */ 2543 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2544 reg |= TXMAC_THRESH_1_PKT; 2545 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2546 CSR_WRITE_4(sc, JME_TXMAC, reg); 2547 2548 /* 2549 * Configure Rx queue. 2550 * FIFO full threshold for transmitting Tx pause packet : 128T 2551 * FIFO threshold for processing next packet : 128QW 2552 * Rx queue 0 select 2553 * Max Rx DMA length : 128 2554 * Rx descriptor retry : 32 2555 * Rx descriptor retry time gap : 256ns 2556 * Don't receive runt/bad frame. 2557 */ 2558 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2559 #if 0 2560 /* 2561 * Since Rx FIFO size is 4K bytes, receiving frames larger 2562 * than 4K bytes will suffer from Rx FIFO overruns. So 2563 * decrease FIFO threshold to reduce the FIFO overruns for 2564 * frames larger than 4000 bytes. 2565 * For best performance of standard MTU sized frames use 2566 * maximum allowable FIFO threshold, 128QW. 2567 */ 2568 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) > 2569 JME_RX_FIFO_SIZE) 2570 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2571 else 2572 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2573 #else 2574 /* Improve PCI Express compatibility */ 2575 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2576 #endif 2577 sc->jme_rxcsr |= sc->jme_rx_dma_size; 2578 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2579 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2580 /* XXX TODO DROP_BAD */ 2581 2582 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2583 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 2584 2585 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r)); 2586 2587 /* Set Rx descriptor counter. */ 2588 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt); 2589 2590 /* Set Rx ring address to the hardware. */ 2591 paddr = rdata->jme_rx_ring_paddr; 2592 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2593 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2594 } 2595 2596 /* Clear receive filter. */ 2597 CSR_WRITE_4(sc, JME_RXMAC, 0); 2598 2599 /* Set up the receive filter. */ 2600 jme_set_filter(sc); 2601 jme_set_vlan(sc); 2602 2603 /* 2604 * Disable all WOL bits as WOL can interfere normal Rx 2605 * operation. Also clear WOL detection status bits. 2606 */ 2607 reg = CSR_READ_4(sc, JME_PMCS); 2608 reg &= ~PMCS_WOL_ENB_MASK; 2609 CSR_WRITE_4(sc, JME_PMCS, reg); 2610 2611 /* 2612 * Pad 10bytes right before received frame. This will greatly 2613 * help Rx performance on strict-alignment architectures as 2614 * it does not need to copy the frame to align the payload. 2615 */ 2616 reg = CSR_READ_4(sc, JME_RXMAC); 2617 reg |= RXMAC_PAD_10BYTES; 2618 2619 if (ifp->if_capenable & IFCAP_RXCSUM) 2620 reg |= RXMAC_CSUM_ENB; 2621 CSR_WRITE_4(sc, JME_RXMAC, reg); 2622 2623 /* Configure general purpose reg0 */ 2624 reg = CSR_READ_4(sc, JME_GPREG0); 2625 reg &= ~GPREG0_PCC_UNIT_MASK; 2626 /* Set PCC timer resolution to micro-seconds unit. */ 2627 reg |= GPREG0_PCC_UNIT_US; 2628 /* 2629 * Disable all shadow register posting as we have to read 2630 * JME_INTR_STATUS register in jme_intr. Also it seems 2631 * that it's hard to synchronize interrupt status between 2632 * hardware and software with shadow posting due to 2633 * requirements of bus_dmamap_sync(9). 2634 */ 2635 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2636 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2637 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2638 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2639 /* Disable posting of DW0. */ 2640 reg &= ~GPREG0_POST_DW0_ENB; 2641 /* Clear PME message. */ 2642 reg &= ~GPREG0_PME_ENB; 2643 /* Set PHY address. */ 2644 reg &= ~GPREG0_PHY_ADDR_MASK; 2645 reg |= sc->jme_phyaddr; 2646 CSR_WRITE_4(sc, JME_GPREG0, reg); 2647 2648 /* Configure Tx queue 0 packet completion coalescing. */ 2649 jme_set_tx_coal(sc); 2650 2651 /* Configure Rx queues packet completion coalescing. */ 2652 jme_set_rx_coal(sc); 2653 2654 /* Configure shadow status block but don't enable posting. */ 2655 paddr = sc->jme_cdata.jme_ssb_block_paddr; 2656 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2657 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2658 2659 /* Disable Timer 1 and Timer 2. */ 2660 CSR_WRITE_4(sc, JME_TIMER1, 0); 2661 CSR_WRITE_4(sc, JME_TIMER2, 0); 2662 2663 /* Configure retry transmit period, retry limit value. */ 2664 CSR_WRITE_4(sc, JME_TXTRHD, 2665 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2666 TXTRHD_RT_PERIOD_MASK) | 2667 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2668 TXTRHD_RT_LIMIT_SHIFT)); 2669 2670 #ifdef DEVICE_POLLING 2671 if (!(ifp->if_flags & IFF_POLLING)) 2672 #endif 2673 /* Initialize the interrupt mask. */ 2674 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2675 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2676 2677 /* 2678 * Enabling Tx/Rx DMA engines and Rx queue processing is 2679 * done after detection of valid link in jme_miibus_statchg. 2680 */ 2681 sc->jme_flags &= ~JME_FLAG_LINK; 2682 2683 /* Set the current media. */ 2684 mii = device_get_softc(sc->jme_miibus); 2685 mii_mediachg(mii); 2686 2687 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2688 2689 ifp->if_flags |= IFF_RUNNING; 2690 ifp->if_flags &= ~IFF_OACTIVE; 2691 } 2692 2693 static void 2694 jme_stop(struct jme_softc *sc) 2695 { 2696 struct ifnet *ifp = &sc->arpcom.ac_if; 2697 struct jme_txdesc *txd; 2698 struct jme_rxdesc *rxd; 2699 struct jme_rxdata *rdata; 2700 int i, r; 2701 2702 ASSERT_IFNET_SERIALIZED_ALL(ifp); 2703 2704 /* 2705 * Mark the interface down and cancel the watchdog timer. 2706 */ 2707 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2708 ifp->if_timer = 0; 2709 2710 callout_stop(&sc->jme_tick_ch); 2711 sc->jme_flags &= ~JME_FLAG_LINK; 2712 2713 /* 2714 * Disable interrupts. 2715 */ 2716 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2717 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2718 2719 /* Disable updating shadow status block. */ 2720 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 2721 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 2722 2723 /* Stop receiver, transmitter. */ 2724 jme_stop_rx(sc); 2725 jme_stop_tx(sc); 2726 2727 /* 2728 * Free partial finished RX segments 2729 */ 2730 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2731 rdata = &sc->jme_cdata.jme_rx_data[r]; 2732 if (rdata->jme_rxhead != NULL) 2733 m_freem(rdata->jme_rxhead); 2734 JME_RXCHAIN_RESET(rdata); 2735 } 2736 2737 /* 2738 * Free RX and TX mbufs still in the queues. 2739 */ 2740 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2741 rdata = &sc->jme_cdata.jme_rx_data[r]; 2742 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 2743 rxd = &rdata->jme_rxdesc[i]; 2744 if (rxd->rx_m != NULL) { 2745 bus_dmamap_unload(rdata->jme_rx_tag, 2746 rxd->rx_dmamap); 2747 m_freem(rxd->rx_m); 2748 rxd->rx_m = NULL; 2749 } 2750 } 2751 } 2752 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) { 2753 txd = &sc->jme_cdata.jme_txdesc[i]; 2754 if (txd->tx_m != NULL) { 2755 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, 2756 txd->tx_dmamap); 2757 m_freem(txd->tx_m); 2758 txd->tx_m = NULL; 2759 txd->tx_ndesc = 0; 2760 } 2761 } 2762 } 2763 2764 static void 2765 jme_stop_tx(struct jme_softc *sc) 2766 { 2767 uint32_t reg; 2768 int i; 2769 2770 reg = CSR_READ_4(sc, JME_TXCSR); 2771 if ((reg & TXCSR_TX_ENB) == 0) 2772 return; 2773 reg &= ~TXCSR_TX_ENB; 2774 CSR_WRITE_4(sc, JME_TXCSR, reg); 2775 for (i = JME_TIMEOUT; i > 0; i--) { 2776 DELAY(1); 2777 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 2778 break; 2779 } 2780 if (i == 0) 2781 device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 2782 } 2783 2784 static void 2785 jme_stop_rx(struct jme_softc *sc) 2786 { 2787 uint32_t reg; 2788 int i; 2789 2790 reg = CSR_READ_4(sc, JME_RXCSR); 2791 if ((reg & RXCSR_RX_ENB) == 0) 2792 return; 2793 reg &= ~RXCSR_RX_ENB; 2794 CSR_WRITE_4(sc, JME_RXCSR, reg); 2795 for (i = JME_TIMEOUT; i > 0; i--) { 2796 DELAY(1); 2797 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 2798 break; 2799 } 2800 if (i == 0) 2801 device_printf(sc->jme_dev, "stopping recevier timeout!\n"); 2802 } 2803 2804 static void 2805 jme_init_tx_ring(struct jme_softc *sc) 2806 { 2807 struct jme_chain_data *cd; 2808 struct jme_txdesc *txd; 2809 int i; 2810 2811 sc->jme_cdata.jme_tx_prod = 0; 2812 sc->jme_cdata.jme_tx_cons = 0; 2813 sc->jme_cdata.jme_tx_cnt = 0; 2814 2815 cd = &sc->jme_cdata; 2816 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc)); 2817 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) { 2818 txd = &sc->jme_cdata.jme_txdesc[i]; 2819 txd->tx_m = NULL; 2820 txd->tx_desc = &cd->jme_tx_ring[i]; 2821 txd->tx_ndesc = 0; 2822 } 2823 } 2824 2825 static void 2826 jme_init_ssb(struct jme_softc *sc) 2827 { 2828 struct jme_chain_data *cd; 2829 2830 cd = &sc->jme_cdata; 2831 bzero(cd->jme_ssb_block, JME_SSB_SIZE); 2832 } 2833 2834 static int 2835 jme_init_rx_ring(struct jme_rxdata *rdata) 2836 { 2837 struct jme_rxdesc *rxd; 2838 int i; 2839 2840 KKASSERT(rdata->jme_rxhead == NULL && 2841 rdata->jme_rxtail == NULL && 2842 rdata->jme_rxlen == 0); 2843 rdata->jme_rx_cons = 0; 2844 2845 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata)); 2846 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 2847 int error; 2848 2849 rxd = &rdata->jme_rxdesc[i]; 2850 rxd->rx_m = NULL; 2851 rxd->rx_desc = &rdata->jme_rx_ring[i]; 2852 error = jme_newbuf(rdata, rxd, 1); 2853 if (error) 2854 return error; 2855 } 2856 return 0; 2857 } 2858 2859 static int 2860 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init) 2861 { 2862 struct mbuf *m; 2863 bus_dma_segment_t segs; 2864 bus_dmamap_t map; 2865 int error, nsegs; 2866 2867 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 2868 if (m == NULL) 2869 return ENOBUFS; 2870 /* 2871 * JMC250 has 64bit boundary alignment limitation so jme(4) 2872 * takes advantage of 10 bytes padding feature of hardware 2873 * in order not to copy entire frame to align IP header on 2874 * 32bit boundary. 2875 */ 2876 m->m_len = m->m_pkthdr.len = MCLBYTES; 2877 2878 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag, 2879 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs, 2880 BUS_DMA_NOWAIT); 2881 if (error) { 2882 m_freem(m); 2883 if (init) { 2884 if_printf(&rdata->jme_sc->arpcom.ac_if, 2885 "can't load RX mbuf\n"); 2886 } 2887 return error; 2888 } 2889 2890 if (rxd->rx_m != NULL) { 2891 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap, 2892 BUS_DMASYNC_POSTREAD); 2893 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap); 2894 } 2895 map = rxd->rx_dmamap; 2896 rxd->rx_dmamap = rdata->jme_rx_sparemap; 2897 rdata->jme_rx_sparemap = map; 2898 rxd->rx_m = m; 2899 rxd->rx_paddr = segs.ds_addr; 2900 2901 jme_setup_rxdesc(rxd); 2902 return 0; 2903 } 2904 2905 static void 2906 jme_set_vlan(struct jme_softc *sc) 2907 { 2908 struct ifnet *ifp = &sc->arpcom.ac_if; 2909 uint32_t reg; 2910 2911 ASSERT_IFNET_SERIALIZED_ALL(ifp); 2912 2913 reg = CSR_READ_4(sc, JME_RXMAC); 2914 reg &= ~RXMAC_VLAN_ENB; 2915 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2916 reg |= RXMAC_VLAN_ENB; 2917 CSR_WRITE_4(sc, JME_RXMAC, reg); 2918 } 2919 2920 static void 2921 jme_set_filter(struct jme_softc *sc) 2922 { 2923 struct ifnet *ifp = &sc->arpcom.ac_if; 2924 struct ifmultiaddr *ifma; 2925 uint32_t crc; 2926 uint32_t mchash[2]; 2927 uint32_t rxcfg; 2928 2929 ASSERT_IFNET_SERIALIZED_ALL(ifp); 2930 2931 rxcfg = CSR_READ_4(sc, JME_RXMAC); 2932 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 2933 RXMAC_ALLMULTI); 2934 2935 /* 2936 * Always accept frames destined to our station address. 2937 * Always accept broadcast frames. 2938 */ 2939 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST; 2940 2941 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 2942 if (ifp->if_flags & IFF_PROMISC) 2943 rxcfg |= RXMAC_PROMISC; 2944 if (ifp->if_flags & IFF_ALLMULTI) 2945 rxcfg |= RXMAC_ALLMULTI; 2946 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 2947 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 2948 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 2949 return; 2950 } 2951 2952 /* 2953 * Set up the multicast address filter by passing all multicast 2954 * addresses through a CRC generator, and then using the low-order 2955 * 6 bits as an index into the 64 bit multicast hash table. The 2956 * high order bits select the register, while the rest of the bits 2957 * select the bit within the register. 2958 */ 2959 rxcfg |= RXMAC_MULTICAST; 2960 bzero(mchash, sizeof(mchash)); 2961 2962 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2963 if (ifma->ifma_addr->sa_family != AF_LINK) 2964 continue; 2965 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2966 ifma->ifma_addr), ETHER_ADDR_LEN); 2967 2968 /* Just want the 6 least significant bits. */ 2969 crc &= 0x3f; 2970 2971 /* Set the corresponding bit in the hash table. */ 2972 mchash[crc >> 5] |= 1 << (crc & 0x1f); 2973 } 2974 2975 CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 2976 CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 2977 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 2978 } 2979 2980 static int 2981 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS) 2982 { 2983 struct jme_softc *sc = arg1; 2984 struct ifnet *ifp = &sc->arpcom.ac_if; 2985 int error, v; 2986 2987 ifnet_serialize_all(ifp); 2988 2989 v = sc->jme_tx_coal_to; 2990 error = sysctl_handle_int(oidp, &v, 0, req); 2991 if (error || req->newptr == NULL) 2992 goto back; 2993 2994 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) { 2995 error = EINVAL; 2996 goto back; 2997 } 2998 2999 if (v != sc->jme_tx_coal_to) { 3000 sc->jme_tx_coal_to = v; 3001 if (ifp->if_flags & IFF_RUNNING) 3002 jme_set_tx_coal(sc); 3003 } 3004 back: 3005 ifnet_deserialize_all(ifp); 3006 return error; 3007 } 3008 3009 static int 3010 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3011 { 3012 struct jme_softc *sc = arg1; 3013 struct ifnet *ifp = &sc->arpcom.ac_if; 3014 int error, v; 3015 3016 ifnet_serialize_all(ifp); 3017 3018 v = sc->jme_tx_coal_pkt; 3019 error = sysctl_handle_int(oidp, &v, 0, req); 3020 if (error || req->newptr == NULL) 3021 goto back; 3022 3023 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) { 3024 error = EINVAL; 3025 goto back; 3026 } 3027 3028 if (v != sc->jme_tx_coal_pkt) { 3029 sc->jme_tx_coal_pkt = v; 3030 if (ifp->if_flags & IFF_RUNNING) 3031 jme_set_tx_coal(sc); 3032 } 3033 back: 3034 ifnet_deserialize_all(ifp); 3035 return error; 3036 } 3037 3038 static int 3039 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS) 3040 { 3041 struct jme_softc *sc = arg1; 3042 struct ifnet *ifp = &sc->arpcom.ac_if; 3043 int error, v; 3044 3045 ifnet_serialize_all(ifp); 3046 3047 v = sc->jme_rx_coal_to; 3048 error = sysctl_handle_int(oidp, &v, 0, req); 3049 if (error || req->newptr == NULL) 3050 goto back; 3051 3052 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) { 3053 error = EINVAL; 3054 goto back; 3055 } 3056 3057 if (v != sc->jme_rx_coal_to) { 3058 sc->jme_rx_coal_to = v; 3059 if (ifp->if_flags & IFF_RUNNING) 3060 jme_set_rx_coal(sc); 3061 } 3062 back: 3063 ifnet_deserialize_all(ifp); 3064 return error; 3065 } 3066 3067 static int 3068 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3069 { 3070 struct jme_softc *sc = arg1; 3071 struct ifnet *ifp = &sc->arpcom.ac_if; 3072 int error, v; 3073 3074 ifnet_serialize_all(ifp); 3075 3076 v = sc->jme_rx_coal_pkt; 3077 error = sysctl_handle_int(oidp, &v, 0, req); 3078 if (error || req->newptr == NULL) 3079 goto back; 3080 3081 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) { 3082 error = EINVAL; 3083 goto back; 3084 } 3085 3086 if (v != sc->jme_rx_coal_pkt) { 3087 sc->jme_rx_coal_pkt = v; 3088 if (ifp->if_flags & IFF_RUNNING) 3089 jme_set_rx_coal(sc); 3090 } 3091 back: 3092 ifnet_deserialize_all(ifp); 3093 return error; 3094 } 3095 3096 static void 3097 jme_set_tx_coal(struct jme_softc *sc) 3098 { 3099 uint32_t reg; 3100 3101 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 3102 PCCTX_COAL_TO_MASK; 3103 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 3104 PCCTX_COAL_PKT_MASK; 3105 reg |= PCCTX_COAL_TXQ0; 3106 CSR_WRITE_4(sc, JME_PCCTX, reg); 3107 } 3108 3109 static void 3110 jme_set_rx_coal(struct jme_softc *sc) 3111 { 3112 uint32_t reg; 3113 int r; 3114 3115 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 3116 PCCRX_COAL_TO_MASK; 3117 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 3118 PCCRX_COAL_PKT_MASK; 3119 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) 3120 CSR_WRITE_4(sc, JME_PCCRX(r), reg); 3121 } 3122 3123 #ifdef DEVICE_POLLING 3124 3125 static void 3126 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3127 { 3128 struct jme_softc *sc = ifp->if_softc; 3129 uint32_t status; 3130 int r; 3131 3132 ASSERT_SERIALIZED(&sc->jme_serialize); 3133 3134 switch (cmd) { 3135 case POLL_REGISTER: 3136 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 3137 break; 3138 3139 case POLL_DEREGISTER: 3140 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 3141 break; 3142 3143 case POLL_AND_CHECK_STATUS: 3144 case POLL_ONLY: 3145 status = CSR_READ_4(sc, JME_INTR_STATUS); 3146 3147 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 3148 struct jme_rxdata *rdata = 3149 &sc->jme_cdata.jme_rx_data[r]; 3150 3151 lwkt_serialize_enter(&rdata->jme_rx_serialize); 3152 jme_rxeof(rdata, count); 3153 lwkt_serialize_exit(&rdata->jme_rx_serialize); 3154 } 3155 3156 if (status & INTR_RXQ_DESC_EMPTY) { 3157 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 3158 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 3159 RXCSR_RX_ENB | RXCSR_RXQ_START); 3160 } 3161 3162 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize); 3163 jme_txeof(sc); 3164 if (!ifq_is_empty(&ifp->if_snd)) 3165 if_devstart(ifp); 3166 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize); 3167 break; 3168 } 3169 } 3170 3171 #endif /* DEVICE_POLLING */ 3172 3173 static int 3174 jme_rxring_dma_alloc(struct jme_rxdata *rdata) 3175 { 3176 bus_dmamem_t dmem; 3177 int error, asize; 3178 3179 asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN); 3180 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag, 3181 JME_RX_RING_ALIGN, 0, 3182 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3183 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 3184 if (error) { 3185 device_printf(rdata->jme_sc->jme_dev, 3186 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx); 3187 return error; 3188 } 3189 rdata->jme_rx_ring_tag = dmem.dmem_tag; 3190 rdata->jme_rx_ring_map = dmem.dmem_map; 3191 rdata->jme_rx_ring = dmem.dmem_addr; 3192 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr; 3193 3194 return 0; 3195 } 3196 3197 static int 3198 jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr) 3199 { 3200 if ((paddr & 0xffffffff) == 0) { 3201 /* 3202 * Don't allow lower 32bits of the RX buffer's 3203 * physical address to be 0, else it will break 3204 * hardware pending RSS information delivery 3205 * detection on RX path. 3206 */ 3207 return 1; 3208 } 3209 return 0; 3210 } 3211 3212 static int 3213 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata) 3214 { 3215 bus_addr_t lowaddr; 3216 int i, error; 3217 3218 lowaddr = BUS_SPACE_MAXADDR; 3219 if (JME_ENABLE_HWRSS(rdata->jme_sc)) { 3220 /* jme_rxbuf_dma_filter will be called */ 3221 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3222 } 3223 3224 /* Create tag for Rx buffers. */ 3225 error = bus_dma_tag_create( 3226 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */ 3227 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 3228 lowaddr, /* lowaddr */ 3229 BUS_SPACE_MAXADDR, /* highaddr */ 3230 jme_rxbuf_dma_filter, NULL, /* filter, filterarg */ 3231 MCLBYTES, /* maxsize */ 3232 1, /* nsegments */ 3233 MCLBYTES, /* maxsegsize */ 3234 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */ 3235 &rdata->jme_rx_tag); 3236 if (error) { 3237 device_printf(rdata->jme_sc->jme_dev, 3238 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx); 3239 return error; 3240 } 3241 3242 /* Create DMA maps for Rx buffers. */ 3243 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK, 3244 &rdata->jme_rx_sparemap); 3245 if (error) { 3246 device_printf(rdata->jme_sc->jme_dev, 3247 "could not create %dth spare Rx dmamap.\n", 3248 rdata->jme_rx_idx); 3249 bus_dma_tag_destroy(rdata->jme_rx_tag); 3250 rdata->jme_rx_tag = NULL; 3251 return error; 3252 } 3253 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 3254 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i]; 3255 3256 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK, 3257 &rxd->rx_dmamap); 3258 if (error) { 3259 int j; 3260 3261 device_printf(rdata->jme_sc->jme_dev, 3262 "could not create %dth Rx dmamap " 3263 "for %dth RX ring.\n", i, rdata->jme_rx_idx); 3264 3265 for (j = 0; j < i; ++j) { 3266 rxd = &rdata->jme_rxdesc[j]; 3267 bus_dmamap_destroy(rdata->jme_rx_tag, 3268 rxd->rx_dmamap); 3269 } 3270 bus_dmamap_destroy(rdata->jme_rx_tag, 3271 rdata->jme_rx_sparemap); 3272 bus_dma_tag_destroy(rdata->jme_rx_tag); 3273 rdata->jme_rx_tag = NULL; 3274 return error; 3275 } 3276 } 3277 return 0; 3278 } 3279 3280 static void 3281 jme_rx_intr(struct jme_softc *sc, uint32_t status) 3282 { 3283 int r; 3284 3285 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 3286 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 3287 3288 if (status & rdata->jme_rx_coal) { 3289 lwkt_serialize_enter(&rdata->jme_rx_serialize); 3290 jme_rxeof(rdata, -1); 3291 lwkt_serialize_exit(&rdata->jme_rx_serialize); 3292 } 3293 } 3294 } 3295 3296 static void 3297 jme_enable_rss(struct jme_softc *sc) 3298 { 3299 uint32_t rssc, ind; 3300 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE]; 3301 int i; 3302 3303 KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 || 3304 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4, 3305 ("%s: invalid # of RX rings (%d)", 3306 sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt)); 3307 3308 rssc = RSSC_HASH_64_ENTRY; 3309 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP; 3310 rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1; 3311 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc); 3312 CSR_WRITE_4(sc, JME_RSSC, rssc); 3313 3314 toeplitz_get_key(key, sizeof(key)); 3315 for (i = 0; i < RSSKEY_NREGS; ++i) { 3316 uint32_t keyreg; 3317 3318 keyreg = RSSKEY_REGVAL(key, i); 3319 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg); 3320 3321 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg); 3322 } 3323 3324 /* 3325 * Create redirect table in following fashion: 3326 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3327 */ 3328 ind = 0; 3329 for (i = 0; i < RSSTBL_REGSIZE; ++i) { 3330 int q; 3331 3332 q = i % sc->jme_cdata.jme_rx_ring_cnt; 3333 ind |= q << (i * 8); 3334 } 3335 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind); 3336 3337 for (i = 0; i < RSSTBL_NREGS; ++i) 3338 CSR_WRITE_4(sc, RSSTBL_REG(i), ind); 3339 } 3340 3341 static void 3342 jme_disable_rss(struct jme_softc *sc) 3343 { 3344 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 3345 } 3346 3347 static void 3348 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 3349 { 3350 struct jme_softc *sc = ifp->if_softc; 3351 3352 ifnet_serialize_array_enter(sc->jme_serialize_arr, 3353 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz); 3354 } 3355 3356 static void 3357 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3358 { 3359 struct jme_softc *sc = ifp->if_softc; 3360 3361 ifnet_serialize_array_exit(sc->jme_serialize_arr, 3362 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz); 3363 } 3364 3365 static int 3366 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3367 { 3368 struct jme_softc *sc = ifp->if_softc; 3369 3370 return ifnet_serialize_array_try(sc->jme_serialize_arr, 3371 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz); 3372 } 3373 3374 #ifdef INVARIANTS 3375 3376 static void 3377 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 3378 boolean_t serialized) 3379 { 3380 struct jme_softc *sc = ifp->if_softc; 3381 3382 ifnet_serialize_array_assert(sc->jme_serialize_arr, 3383 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, 3384 slz, serialized); 3385 } 3386 3387 #endif /* INVARIANTS */ 3388 3389 static void 3390 jme_msix_try_alloc(device_t dev) 3391 { 3392 struct jme_softc *sc = device_get_softc(dev); 3393 struct jme_msix_data *msix; 3394 int error, i, r, msix_enable, msix_count; 3395 3396 msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt; 3397 KKASSERT(msix_count <= JME_NMSIX); 3398 3399 msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable); 3400 3401 /* 3402 * We leave the 1st MSI-X vector unused, so we 3403 * actually need msix_count + 1 MSI-X vectors. 3404 */ 3405 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1)) 3406 return; 3407 3408 for (i = 0; i < msix_count; ++i) 3409 sc->jme_msix[i].jme_msix_rid = -1; 3410 3411 i = 0; 3412 3413 msix = &sc->jme_msix[i++]; 3414 msix->jme_msix_cpuid = 0; /* XXX Put TX to cpu0 */ 3415 msix->jme_msix_arg = &sc->jme_cdata; 3416 msix->jme_msix_func = jme_msix_tx; 3417 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO; 3418 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize; 3419 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx", 3420 device_get_nameunit(dev)); 3421 3422 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 3423 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 3424 3425 msix = &sc->jme_msix[i++]; 3426 msix->jme_msix_cpuid = r; /* XXX Put RX to cpuX */ 3427 msix->jme_msix_arg = rdata; 3428 msix->jme_msix_func = jme_msix_rx; 3429 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty; 3430 msix->jme_msix_serialize = &rdata->jme_rx_serialize; 3431 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), 3432 "%s rx%d", device_get_nameunit(dev), r); 3433 } 3434 3435 KKASSERT(i == msix_count); 3436 3437 error = pci_setup_msix(dev); 3438 if (error) 3439 return; 3440 3441 /* Setup jme_msix_cnt early, so we could cleanup */ 3442 sc->jme_msix_cnt = msix_count; 3443 3444 for (i = 0; i < msix_count; ++i) { 3445 msix = &sc->jme_msix[i]; 3446 3447 msix->jme_msix_vector = i + 1; 3448 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector, 3449 &msix->jme_msix_rid, msix->jme_msix_cpuid); 3450 if (error) 3451 goto back; 3452 3453 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 3454 &msix->jme_msix_rid, RF_ACTIVE); 3455 if (msix->jme_msix_res == NULL) { 3456 error = ENOMEM; 3457 goto back; 3458 } 3459 } 3460 3461 for (i = 0; i < JME_INTR_CNT; ++i) { 3462 uint32_t intr_mask = (1 << i); 3463 int x; 3464 3465 if ((JME_INTRS & intr_mask) == 0) 3466 continue; 3467 3468 for (x = 0; x < msix_count; ++x) { 3469 msix = &sc->jme_msix[x]; 3470 if (msix->jme_msix_intrs & intr_mask) { 3471 int reg, shift; 3472 3473 reg = i / JME_MSINUM_FACTOR; 3474 KKASSERT(reg < JME_MSINUM_CNT); 3475 3476 shift = (i % JME_MSINUM_FACTOR) * 4; 3477 3478 sc->jme_msinum[reg] |= 3479 (msix->jme_msix_vector << shift); 3480 3481 break; 3482 } 3483 } 3484 } 3485 3486 if (bootverbose) { 3487 for (i = 0; i < JME_MSINUM_CNT; ++i) { 3488 device_printf(dev, "MSINUM%d: %#x\n", i, 3489 sc->jme_msinum[i]); 3490 } 3491 } 3492 3493 pci_enable_msix(dev); 3494 sc->jme_irq_type = PCI_INTR_TYPE_MSIX; 3495 3496 back: 3497 if (error) 3498 jme_msix_free(dev); 3499 } 3500 3501 static int 3502 jme_intr_alloc(device_t dev) 3503 { 3504 struct jme_softc *sc = device_get_softc(dev); 3505 u_int irq_flags; 3506 3507 jme_msix_try_alloc(dev); 3508 3509 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) { 3510 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable, 3511 &sc->jme_irq_rid, &irq_flags); 3512 3513 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 3514 &sc->jme_irq_rid, irq_flags); 3515 if (sc->jme_irq_res == NULL) { 3516 device_printf(dev, "can't allocate irq\n"); 3517 return ENXIO; 3518 } 3519 } 3520 return 0; 3521 } 3522 3523 static void 3524 jme_msix_free(device_t dev) 3525 { 3526 struct jme_softc *sc = device_get_softc(dev); 3527 int i; 3528 3529 KKASSERT(sc->jme_msix_cnt > 1); 3530 3531 for (i = 0; i < sc->jme_msix_cnt; ++i) { 3532 struct jme_msix_data *msix = &sc->jme_msix[i]; 3533 3534 if (msix->jme_msix_res != NULL) { 3535 bus_release_resource(dev, SYS_RES_IRQ, 3536 msix->jme_msix_rid, msix->jme_msix_res); 3537 msix->jme_msix_res = NULL; 3538 } 3539 if (msix->jme_msix_rid >= 0) { 3540 pci_release_msix_vector(dev, msix->jme_msix_rid); 3541 msix->jme_msix_rid = -1; 3542 } 3543 } 3544 pci_teardown_msix(dev); 3545 } 3546 3547 static void 3548 jme_intr_free(device_t dev) 3549 { 3550 struct jme_softc *sc = device_get_softc(dev); 3551 3552 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) { 3553 if (sc->jme_irq_res != NULL) { 3554 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid, 3555 sc->jme_irq_res); 3556 } 3557 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI) 3558 pci_release_msi(dev); 3559 } else { 3560 jme_msix_free(dev); 3561 } 3562 } 3563 3564 static void 3565 jme_msix_tx(void *xcd) 3566 { 3567 struct jme_chain_data *cd = xcd; 3568 struct jme_softc *sc = cd->jme_sc; 3569 struct ifnet *ifp = &sc->arpcom.ac_if; 3570 3571 ASSERT_SERIALIZED(&cd->jme_tx_serialize); 3572 3573 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO); 3574 3575 CSR_WRITE_4(sc, JME_INTR_STATUS, 3576 INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP); 3577 3578 if (ifp->if_flags & IFF_RUNNING) { 3579 jme_txeof(sc); 3580 if (!ifq_is_empty(&ifp->if_snd)) 3581 if_devstart(ifp); 3582 } 3583 3584 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO); 3585 } 3586 3587 static void 3588 jme_msix_rx(void *xrdata) 3589 { 3590 struct jme_rxdata *rdata = xrdata; 3591 struct jme_softc *sc = rdata->jme_sc; 3592 struct ifnet *ifp = &sc->arpcom.ac_if; 3593 uint32_t status; 3594 3595 ASSERT_SERIALIZED(&rdata->jme_rx_serialize); 3596 3597 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, 3598 (rdata->jme_rx_coal | rdata->jme_rx_empty)); 3599 3600 status = CSR_READ_4(sc, JME_INTR_STATUS); 3601 status &= (rdata->jme_rx_coal | rdata->jme_rx_empty); 3602 3603 if (status & rdata->jme_rx_coal) 3604 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp); 3605 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 3606 3607 if (ifp->if_flags & IFF_RUNNING) { 3608 if (status & rdata->jme_rx_coal) 3609 jme_rxeof(rdata, -1); 3610 3611 if (status & rdata->jme_rx_empty) { 3612 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 3613 RXCSR_RX_ENB | RXCSR_RXQ_START); 3614 } 3615 } 3616 3617 CSR_WRITE_4(sc, JME_INTR_MASK_SET, 3618 (rdata->jme_rx_coal | rdata->jme_rx_empty)); 3619 } 3620 3621 static void 3622 jme_set_msinum(struct jme_softc *sc) 3623 { 3624 int i; 3625 3626 for (i = 0; i < JME_MSINUM_CNT; ++i) 3627 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]); 3628 } 3629 3630 static int 3631 jme_intr_setup(device_t dev) 3632 { 3633 struct jme_softc *sc = device_get_softc(dev); 3634 struct ifnet *ifp = &sc->arpcom.ac_if; 3635 int error; 3636 3637 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX) 3638 return jme_msix_setup(dev); 3639 3640 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE, 3641 jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize); 3642 if (error) { 3643 device_printf(dev, "could not set up interrupt handler.\n"); 3644 return error; 3645 } 3646 3647 ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res); 3648 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 3649 return 0; 3650 } 3651 3652 static void 3653 jme_intr_teardown(device_t dev) 3654 { 3655 struct jme_softc *sc = device_get_softc(dev); 3656 3657 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX) 3658 jme_msix_teardown(dev, sc->jme_msix_cnt); 3659 else 3660 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle); 3661 } 3662 3663 static int 3664 jme_msix_setup(device_t dev) 3665 { 3666 struct jme_softc *sc = device_get_softc(dev); 3667 struct ifnet *ifp = &sc->arpcom.ac_if; 3668 int x; 3669 3670 for (x = 0; x < sc->jme_msix_cnt; ++x) { 3671 struct jme_msix_data *msix = &sc->jme_msix[x]; 3672 int error; 3673 3674 error = bus_setup_intr_descr(dev, msix->jme_msix_res, 3675 INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg, 3676 &msix->jme_msix_handle, msix->jme_msix_serialize, 3677 msix->jme_msix_desc); 3678 if (error) { 3679 device_printf(dev, "could not set up %s " 3680 "interrupt handler.\n", msix->jme_msix_desc); 3681 jme_msix_teardown(dev, x); 3682 return error; 3683 } 3684 } 3685 ifp->if_cpuid = 0; /* XXX */ 3686 return 0; 3687 } 3688 3689 static void 3690 jme_msix_teardown(device_t dev, int msix_count) 3691 { 3692 struct jme_softc *sc = device_get_softc(dev); 3693 int x; 3694 3695 for (x = 0; x < msix_count; ++x) { 3696 struct jme_msix_data *msix = &sc->jme_msix[x]; 3697 3698 bus_teardown_intr(dev, msix->jme_msix_res, 3699 msix->jme_msix_handle); 3700 } 3701 } 3702