1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/jme/if_jmereg.h,v 1.1 2008/05/27 01:42:01 yongari Exp $ 28 * $DragonFly: src/sys/dev/netif/jme/if_jmereg.h,v 1.6 2008/11/26 11:55:18 sephe Exp $ 29 */ 30 31 #ifndef _IF_JMEREG_H 32 #define _IF_JMEREG_H 33 34 /* FM/ECO revision. FM revision is in the upper 4bits. */ 35 #define JME_REV1_A1 0x10 36 #define JME_REV1_A2 0x11 /* JMC250A2 */ 37 #define JME_REV2 0x20 38 #define JME_REV5 0x50 39 40 /* JMC250 PCI configuration register. */ 41 #define JME_PCIR_BAR PCIR_BAR(0) 42 43 #define JME_PCI_EROM 0x30 44 45 #define JME_PCI_DBG 0x9C 46 47 #define JME_PCI_SPI 0xB0 48 49 #define SPI_ENB 0x00000010 50 #define SPI_SO_STATUS 0x00000008 51 #define SPI_SI_CTRL 0x00000004 52 #define SPI_SCK_CTRL 0x00000002 53 #define SPI_CS_N_CTRL 0x00000001 54 55 #define JME_PCI_PHYCFG0 0xC0 56 57 #define JME_PCI_PHYCFG1 0xC4 58 59 #define JME_PCI_PHYCFG2 0xC8 60 61 #define JME_PCI_PHYCFG3 0xCC 62 63 #define JME_PCI_PIPECTL1 0xD0 64 65 #define JME_PCI_PIPECTL2 0xD4 66 67 /* PCIe link error/status. */ 68 #define JME_PCI_LES 0xD8 69 70 /* propeietary register 0. */ 71 #define JME_PCI_PE0 0xE0 72 #define PE0_SPI_EXIST 0x00200000 73 #define PE0_PME_D0 0x00100000 74 #define PE0_PME_D3H 0x00080000 75 #define PE0_PME_SPI_PAD 0x00040000 76 #define PE0_MASK_ASPM 0x00020000 77 #define PE0_EEPROM_RW_DIS 0x00008000 78 #define PE0_PCI_INTA 0x00001000 79 #define PE0_PCI_INTB 0x00002000 80 #define PE0_PCI_INTC 0x00003000 81 #define PE0_PCI_INTD 0x00004000 82 #define PE0_PCI_SVSSID_WR_ENB 0x00000800 83 #define PE0_MSIX_SIZE_8 0x00000700 84 #define PE0_MSIX_SIZE_7 0x00000600 85 #define PE0_MSIX_SIZE_6 0x00000500 86 #define PE0_MSIX_SIZE_5 0x00000400 87 #define PE0_MSIX_SIZE_4 0x00000300 88 #define PE0_MSIX_SIZE_3 0x00000200 89 #define PE0_MSIX_SIZE_2 0x00000100 90 #define PE0_MSIX_SIZE_1 0x00000000 91 #define PE0_MSIX_SIZE_DEF 0x00000700 92 #define PE0_MSIX_CAP_DIS 0x00000080 93 #define PE0_MSI_PVMC_ENB 0x00000040 94 #define PE0_LCAP_EXIT_LAT_MASK 0x00000038 95 #define PE0_LCAP_EXIT_LAT_DEF 0x00000038 96 #define PE0_PM_AUXC_MASK 0x00000007 97 #define PE0_PM_AUXC_DEF 0x00000007 98 99 #define JME_PCI_PE1 0xE4 100 101 #define JME_PCI_PHYTEST 0xF8 102 103 #define JME_PCI_GPR 0xFC 104 105 /* 106 * JMC Register Map. 107 * ----------------------------------------------------------------------- 108 * Register Size IO space Memory space 109 * ----------------------------------------------------------------------- 110 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 111 * BAR1 + 0x7F BAR0 + 0x7F 112 * ----------------------------------------------------------------------- 113 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 114 * BAR2 + 0x7F BAR0 + 0x47F 115 * ----------------------------------------------------------------------- 116 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 117 * BAR2 + 0x7F BAR0 + 0x87F 118 * ----------------------------------------------------------------------- 119 * To simplify register access fuctions and to get better performance 120 * this driver doesn't support IO space access. It could be implemented 121 * as a function which selects appropriate BARs to access requested 122 * register. 123 */ 124 125 /* Tx control and status. */ 126 #define JME_TXCSR 0x0000 127 #define TXCSR_QWEIGHT_MASK 0x0F000000 128 #define TXCSR_QWEIGHT_SHIFT 24 129 #define TXCSR_TXQ_SEL_MASK 0x00070000 130 #define TXCSR_TXQ_SEL_SHIFT 16 131 #define TXCSR_TXQ_START 0x00000001 132 #define TXCSR_TXQ_START_SHIFT 8 133 #define TXCSR_FIFO_THRESH_4QW 0x00000000 134 #define TXCSR_FIFO_THRESH_8QW 0x00000040 135 #define TXCSR_FIFO_THRESH_12QW 0x00000080 136 #define TXCSR_FIFO_THRESH_16QW 0x000000C0 137 #define TXCSR_DMA_SIZE_64 0x00000000 138 #define TXCSR_DMA_SIZE_128 0x00000010 139 #define TXCSR_DMA_SIZE_256 0x00000020 140 #define TXCSR_DMA_SIZE_512 0x00000030 141 #define TXCSR_DMA_BURST 0x00000004 142 #define TXCSR_TX_SUSPEND 0x00000002 143 #define TXCSR_TX_ENB 0x00000001 144 #define TXCSR_TXQ0 0 145 #define TXCSR_TXQ1 1 146 #define TXCSR_TXQ2 2 147 #define TXCSR_TXQ3 3 148 #define TXCSR_TXQ4 4 149 #define TXCSR_TXQ5 5 150 #define TXCSR_TXQ6 6 151 #define TXCSR_TXQ7 7 152 #define TXCSR_TXQ_WEIGHT(x) \ 153 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 154 #define TXCSR_TXQ_WEIGHT_MIN 0 155 #define TXCSR_TXQ_WEIGHT_MAX 15 156 #define TXCSR_TXQ_N_SEL(x) \ 157 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 158 #define TXCSR_TXQ_N_START(x) \ 159 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 160 161 /* Tx queue descriptor base address. 16bytes alignment required. */ 162 #define JME_TXDBA_LO 0x0004 163 #define JME_TXDBA_HI 0x0008 164 165 /* Tx queue descriptor count. multiple of 16(max = 1024). */ 166 #define JME_TXQDC 0x000C 167 #define TXQDC_MASK 0x0000007F0 168 169 /* Tx queue next descriptor address. */ 170 #define JME_TXNDA 0x0010 171 #define TXNDA_ADDR_MASK 0xFFFFFFF0 172 #define TXNDA_DESC_EMPTY 0x00000008 173 #define TXNDA_DESC_VALID 0x00000004 174 #define TXNDA_DESC_WAIT 0x00000002 175 #define TXNDA_DESC_FETCH 0x00000001 176 177 /* Tx MAC control ans status. */ 178 #define JME_TXMAC 0x0014 179 #define TXMAC_IFG2_MASK 0xC0000000 180 #define TXMAC_IFG2_DEFAULT 0x40000000 181 #define TXMAC_IFG1_MASK 0x30000000 182 #define TXMAC_IFG1_DEFAULT 0x20000000 183 #define TXMAC_THRESH_1_PKT 0x00000300 184 #define TXMAC_THRESH_1_2_PKT 0x00000200 185 #define TXMAC_THRESH_1_4_PKT 0x00000100 186 #define TXMAC_THRESH_1_8_PKT 0x00000000 187 #define TXMAC_FRAME_BURST 0x00000080 188 #define TXMAC_CARRIER_EXT 0x00000040 189 #define TXMAC_IFG_ENB 0x00000020 190 #define TXMAC_BACKOFF 0x00000010 191 #define TXMAC_CARRIER_SENSE 0x00000008 192 #define TXMAC_COLL_ENB 0x00000004 193 #define TXMAC_CRC_ENB 0x00000002 194 #define TXMAC_PAD_ENB 0x00000001 195 196 /* Tx pause frame control. */ 197 #define JME_TXPFC 0x0018 198 #define TXPFC_VLAN_TAG_MASK 0xFFFF0000 199 #define TXPFC_VLAN_TAG_SHIFT 16 200 #define TXPFC_VLAN_ENB 0x00008000 201 #define TXPFC_PAUSE_ENB 0x00000001 202 203 /* Tx timer/retry at half duplex. */ 204 #define JME_TXTRHD 0x001C 205 #define TXTRHD_RT_PERIOD_ENB 0x80000000 206 #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 207 #define TXTRHD_RT_PERIOD_SHIFT 8 208 #define TXTRHD_RT_LIMIT_ENB 0x00000080 209 #define TXTRHD_RT_LIMIT_MASK 0x0000007F 210 #define TXTRHD_RT_LIMIT_SHIFT 0 211 #define TXTRHD_RT_PERIOD_DEFAULT 8192 212 #define TXTRHD_RT_LIMIT_DEFAULT 8 213 214 /* Rx control & status. */ 215 #define JME_RXCSR 0x0020 216 #define RXCSR_FIFO_FTHRESH_16T 0x00000000 217 #define RXCSR_FIFO_FTHRESH_32T 0x10000000 218 #define RXCSR_FIFO_FTHRESH_64T 0x20000000 219 #define RXCSR_FIFO_FTHRESH_128T 0x30000000 220 #define RXCSR_FIFO_FTHRESH_MASK 0x30000000 221 #define RXCSR_FIFO_THRESH_16QW 0x00000000 222 #define RXCSR_FIFO_THRESH_32QW 0x04000000 223 #define RXCSR_FIFO_THRESH_64QW 0x08000000 224 #define RXCSR_FIFO_THRESH_128QW 0x0C000000 225 #define RXCSR_FIFO_THRESH_MASK 0x0C000000 226 #define RXCSR_DMA_SIZE_16 0x00000000 227 #define RXCSR_DMA_SIZE_32 0x01000000 228 #define RXCSR_DMA_SIZE_64 0x02000000 229 #define RXCSR_DMA_SIZE_128 0x03000000 230 #define RXCSR_RXQ_SEL_MASK 0x00030000 231 #define RXCSR_RXQ_SEL_SHIFT 16 232 #define RXCSR_DESC_RT_GAP_MASK 0x0000F000 233 #define RXCSR_DESC_RT_GAP_SHIFT 12 234 #define RXCSR_DESC_RT_GAP_256 0x00000000 235 #define RXCSR_DESC_RT_GAP_512 0x00001000 236 #define RXCSR_DESC_RT_GAP_1024 0x00002000 237 #define RXCSR_DESC_RT_GAP_2048 0x00003000 238 #define RXCSR_DESC_RT_GAP_4096 0x00004000 239 #define RXCSR_DESC_RT_GAP_8192 0x00005000 240 #define RXCSR_DESC_RT_GAP_16384 0x00006000 241 #define RXCSR_DESC_RT_GAP_32768 0x00007000 242 #define RXCSR_DESC_RT_CNT_MASK 0x00000F00 243 #define RXCSR_DESC_RT_CNT_SHIFT 8 244 #define RXCSR_PASS_WAKEUP_PKT 0x00000040 245 #define RXCSR_PASS_MAGIC_PKT 0x00000020 246 #define RXCSR_PASS_RUNT_PKT 0x00000010 247 #define RXCSR_PASS_BAD_PKT 0x00000008 248 #define RXCSR_RXQ_START 0x00000004 249 #define RXCSR_RX_SUSPEND 0x00000002 250 #define RXCSR_RX_ENB 0x00000001 251 252 #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 253 #define RXCSR_RXQ0 0 254 #define RXCSR_RXQ1 1 255 #define RXCSR_RXQ2 2 256 #define RXCSR_RXQ3 3 257 #define RXCSR_DESC_RT_CNT(x) \ 258 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 259 #define RXCSR_DESC_RT_CNT_DEFAULT 32 260 261 /* Rx queue descriptor base address. 16bytes alignment needed. */ 262 #define JME_RXDBA_LO 0x0024 263 #define JME_RXDBA_HI 0x0028 264 265 /* Rx queue descriptor count. multiple of 16(max = 1024). */ 266 #define JME_RXQDC 0x002C 267 #define RXQDC_MASK 0x0000007F0 268 269 /* Rx queue next descriptor address. */ 270 #define JME_RXNDA 0x0030 271 #define RXNDA_ADDR_MASK 0xFFFFFFF0 272 #define RXNDA_DESC_EMPTY 0x00000008 273 #define RXNDA_DESC_VALID 0x00000004 274 #define RXNDA_DESC_WAIT 0x00000002 275 #define RXNDA_DESC_FETCH 0x00000001 276 277 /* Rx MAC control and status. */ 278 #define JME_RXMAC 0x0034 279 #define RXMAC_RSS_UNICAST 0x00000000 280 #define RXMAC_RSS_UNI_MULTICAST 0x00010000 281 #define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 282 #define RXMAC_RSS_ALLFRAME 0x00030000 283 #define RXMAC_PROMISC 0x00000800 284 #define RXMAC_BROADCAST 0x00000400 285 #define RXMAC_MULTICAST 0x00000200 286 #define RXMAC_UNICAST 0x00000100 287 #define RXMAC_ALLMULTI 0x00000080 288 #define RXMAC_MULTICAST_FILTER 0x00000040 289 #define RXMAC_COLL_DET_ENB 0x00000020 290 #define RXMAC_FC_ENB 0x00000008 291 #define RXMAC_VLAN_ENB 0x00000004 292 #define RXMAC_PAD_10BYTES 0x00000002 293 #define RXMAC_CSUM_ENB 0x00000001 294 295 /* Rx unicast MAC address. */ 296 #define JME_PAR0 0x0038 297 #define JME_PAR1 0x003C 298 299 /* Rx multicast address hash table. */ 300 #define JME_MAR0 0x0040 301 #define JME_MAR1 0x0044 302 303 /* Wakeup frame output data port. */ 304 #define JME_WFODP 0x0048 305 306 /* Wakeup frame output interface. */ 307 #define JME_WFOI 0x004C 308 #define WFOI_MASK_0_31 0x00000000 309 #define WFOI_MASK_31_63 0x00000010 310 #define WFOI_MASK_64_95 0x00000020 311 #define WFOI_MASK_96_127 0x00000030 312 #define WFOI_MASK_SEL 0x00000008 313 #define WFOI_CRC_SEL 0x00000000 314 #define WFOI_WAKEUP_FRAME_MASK 0x00000007 315 #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 316 317 /* Station management interface. */ 318 #define JME_SMI 0x0050 319 #define SMI_DATA_MASK 0xFFFF0000 320 #define SMI_DATA_SHIFT 16 321 #define SMI_REG_ADDR_MASK 0x0000F800 322 #define SMI_REG_ADDR_SHIFT 11 323 #define SMI_PHY_ADDR_MASK 0x000007C0 324 #define SMI_PHY_ADDR_SHIFT 6 325 #define SMI_OP_WRITE 0x00000020 326 #define SMI_OP_READ 0x00000000 327 #define SMI_OP_EXECUTE 0x00000010 328 #define SMI_MDIO 0x00000008 329 #define SMI_MDOE 0x00000004 330 #define SMI_MDC 0x00000002 331 #define SMI_MDEN 0x00000001 332 #define SMI_REG_ADDR(x) \ 333 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 334 #define SMI_PHY_ADDR(x) \ 335 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 336 337 /* Global host control. */ 338 #define JME_GHC 0x0054 339 #define GHC_LOOPBACK 0x80000000 340 #define GHC_RESET 0x40000000 341 #define GHC_TXOFL_CLKSRC 0x00800000 342 #define GHC_TXOFL_CLKSRC_1000 0x00400000 343 #define GHC_TXMAC_CLKSRC 0x00200000 344 #define GHC_TXMAC_CLKSRC_1000 0x00100000 345 #define GHC_FULL_DUPLEX 0x00000040 346 #define GHC_SPEED_UNKNOWN 0x00000000 347 #define GHC_SPEED_10 0x00000010 348 #define GHC_SPEED_100 0x00000020 349 #define GHC_SPEED_1000 0x00000030 350 #define GHC_SPEED_MASK 0x00000030 351 #define GHC_LINK_OFF 0x00000004 352 #define GHC_LINK_ON 0x00000002 353 #define GHC_LINK_STAT_POLLING 0x00000001 354 355 /* Power management control and status. */ 356 #define JME_PMCS 0x0060 357 #define PMCS_WAKEUP_FRAME_7 0x80000000 358 #define PMCS_WAKEUP_FRAME_6 0x40000000 359 #define PMCS_WAKEUP_FRAME_5 0x20000000 360 #define PMCS_WAKEUP_FRAME_4 0x10000000 361 #define PMCS_WAKEUP_FRAME_3 0x08000000 362 #define PMCS_WAKEUP_FRAME_2 0x04000000 363 #define PMCS_WAKEUP_FRAME_1 0x02000000 364 #define PMCS_WAKEUP_FRAME_0 0x01000000 365 #define PMCS_LINK_FAIL 0x00040000 366 #define PMCS_LINK_RISING 0x00020000 367 #define PMCS_MAGIC_FRAME 0x00010000 368 #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 369 #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 370 #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 371 #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 372 #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 373 #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 374 #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 375 #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 376 #define PMCS_LINK_FAIL_ENB 0x00000004 377 #define PMCS_LINK_RISING_ENB 0x00000002 378 #define PMCS_MAGIC_FRAME_ENB 0x00000001 379 #define PMCS_WOL_ENB_MASK 0x0000FFFF 380 381 /* Giga PHY & EEPROM registers. */ 382 #define JME_PHY_EEPROM_BASE_ADDR 0x0400 383 384 #define JME_GIGAR0LO 0x0400 385 #define JME_GIGAR0HI 0x0404 386 #define JME_GIGARALO 0x0408 387 #define JME_GIGARAHI 0x040C 388 #define JME_GIGARBLO 0x0410 389 #define JME_GIGARBHI 0x0414 390 #define JME_GIGARCLO 0x0418 391 #define JME_GIGARCHI 0x041C 392 #define JME_GIGARDLO 0x0420 393 #define JME_GIGARDHI 0x0424 394 395 /* BIST status and control. */ 396 #define JME_GIGACSR 0x0428 397 #define GIGACSR_STATUS 0x40000000 398 #define GIGACSR_CTRL_MASK 0x30000000 399 #define GIGACSR_CTRL_DEFAULT 0x30000000 400 #define GIGACSR_TX_CLK_MASK 0x0F000000 401 #define GIGACSR_RX_CLK_MASK 0x00F00000 402 #define GIGACSR_TX_CLK_INV 0x00080000 403 #define GIGACSR_RX_CLK_INV 0x00040000 404 #define GIGACSR_PHY_RST 0x00010000 405 #define GIGACSR_IRQ_N_O 0x00001000 406 #define GIGACSR_BIST_OK 0x00000200 407 #define GIGACSR_BIST_DONE 0x00000100 408 #define GIGACSR_BIST_LED_ENB 0x00000010 409 #define GIGACSR_BIST_MASK 0x00000003 410 411 /* PHY Link Status. */ 412 #define JME_LNKSTS 0x0430 413 #define LINKSTS_SPEED_10 0x00000000 414 #define LINKSTS_SPEED_100 0x00004000 415 #define LINKSTS_SPEED_1000 0x00008000 416 #define LINKSTS_FULL_DUPLEX 0x00002000 417 #define LINKSTS_PAGE_RCVD 0x00001000 418 #define LINKSTS_SPDDPX_RESOLVED 0x00000800 419 #define LINKSTS_UP 0x00000400 420 #define LINKSTS_ANEG_COMP 0x00000200 421 #define LINKSTS_MDI_CROSSOVR 0x00000040 422 #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 423 #define LINKSTS_LPAR_PAUSE 0x00000001 424 425 /* SMB control and status. */ 426 #define JME_SMBCSR 0x0440 427 #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 428 #define SMBCSR_WR_DATA_NACK 0x00040000 429 #define SMBCSR_CMD_NACK 0x00020000 430 #define SMBCSR_RELOAD 0x00010000 431 #define SMBCSR_CMD_ADDR_MASK 0x0000FF00 432 #define SMBCSR_SCL_STAT 0x00000080 433 #define SMBCSR_SDA_STAT 0x00000040 434 #define SMBCSR_EEPROM_PRESENT 0x00000020 435 #define SMBCSR_INIT_LD_DONE 0x00000010 436 #define SMBCSR_HW_BUSY_MASK 0x0000000F 437 #define SMBCSR_HW_IDLE 0x00000000 438 439 /* SMB interface. */ 440 #define JME_SMBINTF 0x0444 441 #define SMBINTF_RD_DATA_MASK 0xFF000000 442 #define SMBINTF_RD_DATA_SHIFT 24 443 #define SMBINTF_WR_DATA_MASK 0x00FF0000 444 #define SMBINTF_WR_DATA_SHIFT 16 445 #define SMBINTF_ADDR_MASK 0x0000FF00 446 #define SMBINTF_ADDR_SHIFT 8 447 #define SMBINTF_RD 0x00000020 448 #define SMBINTF_WR 0x00000000 449 #define SMBINTF_CMD_TRIGGER 0x00000010 450 #define SMBINTF_BUSY 0x00000010 451 #define SMBINTF_FAST_MODE 0x00000008 452 #define SMBINTF_GPIO_SCL 0x00000004 453 #define SMBINTF_GPIO_SDA 0x00000002 454 #define SMBINTF_GPIO_ENB 0x00000001 455 456 #define JME_EEPROM_SIG0 0x55 457 #define JME_EEPROM_SIG1 0xAA 458 #define JME_EEPROM_DESC_BYTES 3 459 #define JME_EEPROM_DESC_END 0x80 460 #define JME_EEPROM_FUNC_MASK 0x70 461 #define JME_EEPROM_FUNC_SHIFT 4 462 #define JME_EEPROM_PAGE_MASK 0x0F 463 #define JME_EEPROM_PAGE_SHIFT 0 464 465 #define JME_EEPROM_FUNC0 0 466 /* PCI configuration space. */ 467 #define JME_EEPROM_PAGE_BAR0 0 468 /* 128 bytes I/O window. */ 469 #define JME_EEPROM_PAGE_BAR1 1 470 /* 256 bytes I/O window. */ 471 #define JME_EEPROM_PAGE_BAR2 2 472 473 #define JME_EEPROM_END 0xFF 474 475 #define JME_EEPROM_MKDESC(f, p) \ 476 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 477 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 478 479 /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 480 #define JME_EEPINTF 0x0448 481 #define EEPINTF_DATA_MASK 0xFFFF0000 482 #define EEPINTF_DATA_SHIFT 16 483 #define EEPINTF_ADDR_MASK 0x0000FC00 484 #define EEPINTF_ADDR_SHIFT 10 485 #define EEPRINTF_OP_MASK 0x00000300 486 #define EEPINTF_OP_EXECUTE 0x00000080 487 #define EEPINTF_DATA_OUT 0x00000008 488 #define EEPINTF_DATA_IN 0x00000004 489 #define EEPINTF_CLK 0x00000002 490 #define EEPINTF_SEL 0x00000001 491 492 /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 493 #define JME_EEPCSR 0x044C 494 #define EEPCSR_EEPROM_RELOAD 0x00000002 495 #define EEPCSR_EEPROM_PRESENT 0x00000001 496 497 /* Misc registers. */ 498 #define JME_MISC_BASE_ADDR 0x800 499 500 /* Timer control and status. */ 501 #define JME_TMCSR 0x0800 502 #define TMCSR_SW_INTR 0x80000000 503 #define TMCSR_TIMER_INTR 0x10000000 504 #define TMCSR_TIMER_ENB 0x01000000 505 #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 506 507 /* GPIO control and status. */ 508 #define JME_GPIO 0x0804 509 #define GPIO_4_SPI_IN 0x80000000 510 #define GPIO_3_SPI_IN 0x40000000 511 #define GPIO_4_SPI_OUT 0x20000000 512 #define GPIO_4_SPI_OUT_ENB 0x10000000 513 #define GPIO_3_SPI_OUT 0x08000000 514 #define GPIO_3_SPI_OUT_ENB 0x04000000 515 #define GPIO_3_4_LED 0x00000000 516 #define GPIO_3_4_GPIO 0x02000000 517 #define GPIO_2_CLKREQN_IN 0x00100000 518 #define GPIO_2_CLKREQN_OUT 0x00040000 519 #define GPIO_2_CLKREQN_OUT_ENB 0x00020000 520 #define GPIO_1_LED42_IN 0x00001000 521 #define GPIO_1_LED42_OUT 0x00000400 522 #define GPIO_1_LED42_OUT_ENB 0x00000200 523 #define GPIO_1_LED42_ENB 0x00000100 524 #define GPIO_0_SDA_IN 0x00000010 525 #define GPIO_0_SDA_OUT 0x00000004 526 #define GPIO_0_SDA_OUT_ENB 0x00000002 527 #define GPIO_0_SDA_ENB 0x00000001 528 529 /* General purpose register 0. */ 530 #define JME_GPREG0 0x0808 531 #define GPREG0_SH_POST_DW7_DIS 0x80000000 532 #define GPREG0_SH_POST_DW6_DIS 0x40000000 533 #define GPREG0_SH_POST_DW5_DIS 0x20000000 534 #define GPREG0_SH_POST_DW4_DIS 0x10000000 535 #define GPREG0_SH_POST_DW3_DIS 0x08000000 536 #define GPREG0_SH_POST_DW2_DIS 0x04000000 537 #define GPREG0_SH_POST_DW1_DIS 0x02000000 538 #define GPREG0_SH_POST_DW0_DIS 0x01000000 539 #define GPREG0_DMA_RD_REQ_8 0x00000000 540 #define GPREG0_DMA_RD_REQ_6 0x00100000 541 #define GPREG0_DMA_RD_REQ_5 0x00200000 542 #define GPREG0_DMA_RD_REQ_4 0x00300000 543 #define GPREG0_POST_DW0_ENB 0x00040000 544 #define GPREG0_PCC_CLR_DIS 0x00020000 545 #define GPREG0_FORCE_SCL_OUT 0x00010000 546 #define GPREG0_DL_RSTB_DIS 0x00008000 547 #define GPREG0_STICKY_RESET 0x00004000 548 #define GPREG0_DL_RSTB_CFG_DIS 0x00002000 549 #define GPREG0_LINK_CHG_POLL 0x00001000 550 #define GPREG0_LINK_CHG_DIRECT 0x00000000 551 #define GPREG0_MSI_GEN_SEL 0x00000800 552 #define GPREG0_SMB_PAD_PU_DIS 0x00000400 553 #define GPREG0_PCC_UNIT_16US 0x00000000 554 #define GPREG0_PCC_UNIT_256US 0x00000100 555 #define GPREG0_PCC_UNIT_US 0x00000200 556 #define GPREG0_PCC_UNIT_MS 0x00000300 557 #define GPREG0_PCC_UNIT_MASK 0x00000300 558 #define GPREG0_INTR_EVENT_ENB 0x00000080 559 #define GPREG0_PME_ENB 0x00000020 560 #define GPREG0_PHY_ADDR_MASK 0x0000001F 561 #define GPREG0_PHY_ADDR_SHIFT 0 562 #define GPREG0_PHY_ADDR 1 563 564 /* General purpose register 1. */ 565 #define JME_GPREG1 0x080C 566 #define GPREG1_WA_HDX 0x00000020 /* 250A2 only, for 10/100 mode */ 567 #define GPREG1_WA_IP6RSS 0x00000040 /* 250A2 only, for 10/100 mode */ 568 #define GPREG1_DIS_RXMAC_CLKSRC 0x04000000 569 570 /* MSIX entry number of interrupt source. */ 571 #define JME_MSINUM_BASE 0x0810 572 #define JME_MSINUM(x) (JME_MSINUM_BASE + (4 * (x))) 573 #define JME_MSINUM_CNT 4 574 #define JME_MSINUM_FACTOR 8 575 576 /* Interrupt event status. */ 577 #define JME_INTR_STATUS 0x0820 578 #define INTR_SW 0x80000000 579 #define INTR_TIMER 0x40000000 580 #define INTR_LINKCHG 0x20000000 581 #define INTR_PAUSE 0x10000000 582 #define INTR_MAGIC_PKT 0x08000000 583 #define INTR_WAKEUP_PKT 0x04000000 584 #define INTR_RXQ0_COAL_TO 0x02000000 585 #define INTR_RXQ1_COAL_TO 0x01000000 586 #define INTR_RXQ2_COAL_TO 0x00800000 587 #define INTR_RXQ3_COAL_TO 0x00400000 588 #define INTR_TXQ_COAL_TO 0x00200000 589 #define INTR_RXQ0_COAL 0x00100000 590 #define INTR_RXQ1_COAL 0x00080000 591 #define INTR_RXQ2_COAL 0x00040000 592 #define INTR_RXQ3_COAL 0x00020000 593 #define INTR_TXQ_COAL 0x00010000 594 #define INTR_RXQ3_DESC_EMPTY 0x00008000 595 #define INTR_RXQ2_DESC_EMPTY 0x00004000 596 #define INTR_RXQ1_DESC_EMPTY 0x00002000 597 #define INTR_RXQ0_DESC_EMPTY 0x00001000 598 #define INTR_RXQ3_COMP 0x00000800 599 #define INTR_RXQ2_COMP 0x00000400 600 #define INTR_RXQ1_COMP 0x00000200 601 #define INTR_RXQ0_COMP 0x00000100 602 #define INTR_TXQ7_COMP 0x00000080 603 #define INTR_TXQ6_COMP 0x00000040 604 #define INTR_TXQ5_COMP 0x00000020 605 #define INTR_TXQ4_COMP 0x00000010 606 #define INTR_TXQ3_COMP 0x00000008 607 #define INTR_TXQ2_COMP 0x00000004 608 #define INTR_TXQ1_COMP 0x00000002 609 #define INTR_TXQ0_COMP 0x00000001 610 611 #define JME_INTR_CNT 32 612 613 #define INTR_RXQ_COAL_TO \ 614 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 615 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 616 617 #define INTR_RXQ_COAL \ 618 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 619 INTR_RXQ3_COAL) 620 621 #define INTR_RXQ_COMP \ 622 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 623 INTR_RXQ3_COMP) 624 625 #define INTR_RXQ_DESC_EMPTY \ 626 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 627 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 628 629 #define INTR_RXQ_COMP \ 630 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 631 INTR_RXQ3_COMP) 632 633 #define INTR_TXQ_COMP \ 634 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 635 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 636 INTR_TXQ6_COMP | INTR_TXQ7_COMP) 637 638 #define JME_INTRS \ 639 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 640 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 641 642 #define N_INTR_SW 31 643 #define N_INTR_TIMER 30 644 #define N_INTR_LINKCHG 29 645 #define N_INTR_PAUSE 28 646 #define N_INTR_MAGIC_PKT 27 647 #define N_INTR_WAKEUP_PKT 26 648 #define N_INTR_RXQ0_COAL_TO 25 649 #define N_INTR_RXQ1_COAL_TO 24 650 #define N_INTR_RXQ2_COAL_TO 23 651 #define N_INTR_RXQ3_COAL_TO 22 652 #define N_INTR_TXQ_COAL_TO 21 653 #define N_INTR_RXQ0_COAL 20 654 #define N_INTR_RXQ1_COAL 19 655 #define N_INTR_RXQ2_COAL 18 656 #define N_INTR_RXQ3_COAL 17 657 #define N_INTR_TXQ_COAL 16 658 #define N_INTR_RXQ3_DESC_EMPTY 15 659 #define N_INTR_RXQ2_DESC_EMPTY 14 660 #define N_INTR_RXQ1_DESC_EMPTY 13 661 #define N_INTR_RXQ0_DESC_EMPTY 12 662 #define N_INTR_RXQ3_COMP 11 663 #define N_INTR_RXQ2_COMP 10 664 #define N_INTR_RXQ1_COMP 9 665 #define N_INTR_RXQ0_COMP 8 666 #define N_INTR_TXQ7_COMP 7 667 #define N_INTR_TXQ6_COMP 6 668 #define N_INTR_TXQ5_COMP 5 669 #define N_INTR_TXQ4_COMP 4 670 #define N_INTR_TXQ3_COMP 3 671 #define N_INTR_TXQ2_COMP 2 672 #define N_INTR_TXQ1_COMP 1 673 #define N_INTR_TXQ0_COMP 0 674 675 /* Interrupt request status. */ 676 #define JME_INTR_REQ_STATUS 0x0824 677 678 /* Interrupt enable - setting port. */ 679 #define JME_INTR_MASK_SET 0x0828 680 681 /* Interrupt enable - clearing port. */ 682 #define JME_INTR_MASK_CLR 0x082C 683 684 /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 685 #define JME_PCCRX(r) (0x0830 + ((r) * 4)) 686 #define PCCRX_COAL_TO_MASK 0xFFFF0000 687 #define PCCRX_COAL_TO_SHIFT 16 688 #define PCCRX_COAL_PKT_MASK 0x0000FF00 689 #define PCCRX_COAL_PKT_SHIFT 8 690 691 #define PCCRX_COAL_TO_MIN 1 692 #define PCCRX_COAL_TO_DEFAULT 100 693 #define PCCRX_COAL_TO_MAX 65535 694 695 #define PCCRX_COAL_PKT_MIN 0 696 #define PCCRX_COAL_PKT_DEFAULT 64 697 #define PCCRX_COAL_PKT_MAX 255 698 699 /* Packet completion coalescing control of Tx queue. */ 700 #define JME_PCCTX 0x0840 701 #define PCCTX_COAL_TO_MASK 0xFFFF0000 702 #define PCCTX_COAL_TO_SHIFT 16 703 #define PCCTX_COAL_PKT_MASK 0x0000FF00 704 #define PCCTX_COAL_PKT_SHIFT 8 705 #define PCCTX_COAL_TXQ7 0x00000080 706 #define PCCTX_COAL_TXQ6 0x00000040 707 #define PCCTX_COAL_TXQ5 0x00000020 708 #define PCCTX_COAL_TXQ4 0x00000010 709 #define PCCTX_COAL_TXQ3 0x00000008 710 #define PCCTX_COAL_TXQ2 0x00000004 711 #define PCCTX_COAL_TXQ1 0x00000002 712 #define PCCTX_COAL_TXQ0 0x00000001 713 714 #define PCCTX_COAL_TO_MIN 1 715 #define PCCTX_COAL_TO_DEFAULT 65535 716 #define PCCTX_COAL_TO_MAX 65535 717 718 #define PCCTX_COAL_PKT_MIN 0 719 #define PCCTX_COAL_PKT_DEFAULT 64 720 #define PCCTX_COAL_PKT_MAX 255 721 722 /* Chip mode and FPGA version. */ 723 #define JME_CHIPMODE 0x0844 724 #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 725 #define CHIPMODE_FPGA_REV_SHIFT 16 726 #define CHIPMODE_NOT_FPGA 0 727 #define CHIPMODE_REVECO_MASK 0x0000F000 728 #define CHIPMODE_REVECO_SHIFT 12 729 #define CHIPMODE_REVFM_MASK 0x00000F00 730 #define CHIPMODE_REVFM_SHIFT 8 731 #define CHIPMODE_MODE_48P 0x0000000C 732 #define CHIPMODE_MODE_64P 0x00000004 733 #define CHIPMODE_MODE_128P_MAC 0x00000003 734 #define CHIPMODE_MODE_128P_DBG 0x00000002 735 #define CHIPMODE_MODE_128P_PHY 0x00000000 736 737 /* Shadow status base address high/low. */ 738 #define JME_SHBASE_ADDR_HI 0x0848 739 #define JME_SHBASE_ADDR_LO 0x084C 740 #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 741 #define SHBASE_POST_FORCE 0x00000002 742 #define SHBASE_POST_ENB 0x00000001 743 744 /* Timer 1 and 2. */ 745 #define JME_TIMER1 0x0870 746 #define JME_TIMER2 0x0874 747 #define TIMER_ENB 0x01000000 748 #define TIMER_CNT_MASK 0x00FFFFFF 749 #define TIMER_CNT_SHIFT 0 750 #define TIMER_UNIT 1024 /* 1024us */ 751 752 /* Aggresive power mode control. */ 753 #define JME_APMC 0x087C 754 #define APMC_PCIE_SDOWN_STAT 0x80000000 755 #define APMC_PCIE_SDOWN_ENB 0x40000000 756 #define APMC_PSEUDO_HOT_PLUG 0x20000000 757 #define APMC_EXT_PLUGIN_ENB 0x04000000 758 #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 759 #define APMC_DIS_SRAM 0x00000004 760 #define APMC_DIS_CLKPM 0x00000002 761 #define APMC_DIS_CLKTX 0x00000001 762 763 /* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ 764 #define JME_PCCSRX_BASE 0x0880 765 #define JME_PCCSRX_END 0x088F 766 #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 767 #define PCCSRX_TO_MASK 0xFFFF0000 768 #define PCCSRX_TO_SHIFT 16 769 #define PCCSRX_PKT_CNT_MASK 0x0000FF00 770 #define PCCSRX_PKT_CNT_SHIFT 8 771 772 /* Packet completion coalesing status of Tx queue. */ 773 #define JME_PCCSTX 0x0890 774 #define PCCSTX_TO_MASK 0xFFFF0000 775 #define PCCSTX_TO_SHIFT 16 776 #define PCCSTX_PKT_CNT_MASK 0x0000FF00 777 #define PCCSTX_PKT_CNT_SHIFT 8 778 779 /* Tx queues empty indicator. */ 780 #define JME_TXQEMPTY 0x0894 781 #define TXQEMPTY_TXQ7 0x00000080 782 #define TXQEMPTY_TXQ6 0x00000040 783 #define TXQEMPTY_TXQ5 0x00000020 784 #define TXQEMPTY_TXQ4 0x00000010 785 #define TXQEMPTY_TXQ3 0x00000008 786 #define TXQEMPTY_TXQ2 0x00000004 787 #define TXQEMPTY_TXQ1 0x00000002 788 #define TXQEMPTY_TXQ0 0x00000001 789 #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 790 791 /* RSS control registers. */ 792 #define JME_RSS_BASE 0x0C00 793 794 #define JME_RSSC 0x0C00 795 #define RSSC_HASH_LEN_MASK 0x0000E000 796 #define RSSC_HASH_64_ENTRY 0x0000A000 797 #define RSSC_HASH_128_ENTRY 0x0000E000 798 #define RSSC_HASH_NONE 0x00001000 799 #define RSSC_HASH_IPV6 0x00000800 800 #define RSSC_HASH_IPV4 0x00000400 801 #define RSSC_HASH_IPV6_TCP 0x00000200 802 #define RSSC_HASH_IPV4_TCP 0x00000100 803 #define RSSC_NCPU_MASK 0x000000F8 804 #define RSSC_NCPU_SHIFT 3 805 #define RSSC_DIS_RSS 0x00000000 806 #define RSSC_2RXQ_ENB 0x00000001 807 #define RSSS_4RXQ_ENB 0x00000002 808 809 /* CPU vector. */ 810 #define JME_RSSCPU 0x0C04 811 #define RSSCPU_N_SEL(x) ((1 << (x)) 812 813 /* RSS Hash value. */ 814 #define JME_RSSHASH 0x0C10 815 816 #define JME_RSSHASH_STAT 0x0C14 817 818 #define JME_RSS_RDATA0 0x0C18 819 820 #define JME_RSS_RDATA1 0x0C1C 821 822 /* RSS secret key. */ 823 #define JME_RSSKEY_BASE 0x0C40 824 #define RSSKEY_NREGS 10 825 #define RSSKEY_REGSIZE 4 826 #define RSSKEY_REGVAL(k, x) (k[(x) * RSSKEY_REGSIZE] << 24 | \ 827 k[(x) * RSSKEY_REGSIZE + 1] << 16 | \ 828 k[(x) * RSSKEY_REGSIZE + 2] << 8 | \ 829 k[(x) * RSSKEY_REGSIZE + 3]) 830 #define RSSKEY_REG(x) (JME_RSSKEY_BASE + (RSSKEY_REGSIZE * (x))) 831 832 /* RSS indirection table entries. */ 833 #define JME_RSSTBL_BASE 0x0C80 834 #define RSSTBL_NREGS 32 835 #define RSSTBL_REGSIZE 4 836 #define RSSTBL_REG(x) (JME_RSSTBL_BASE + (RSSTBL_REGSIZE * (x))) 837 838 /* MSI-X table. */ 839 #define JME_MSIX_BASE_ADDR 0x2000 840 841 #define JME_MSIX_BASE 0x2000 842 #define JME_MSIX_END 0x207F 843 #define JME_MSIX_NENTRY 8 844 #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 845 #define MSIX_ADDR_HI_OFF 0x00 846 #define MSIX_ADDR_LO_OFF 0x04 847 #define MSIX_ADDR_LO_MASK 0xFFFFFFFC 848 #define MSIX_DATA_OFF 0x08 849 #define MSIX_VECTOR_OFF 0x0C 850 #define MSIX_VECTOR_RSVD 0x80000000 851 #define MSIX_VECTOR_DIS 0x00000001 852 853 /* MSI-X PBA. */ 854 #define JME_MSIX_PBA_BASE_ADDR 0x3000 855 856 #define JME_MSIX_PBA 0x3000 857 #define MSIX_PBA_RSVD_MASK 0xFFFFFF00 858 #define MSIX_PBA_RSVD_SHIFT 8 859 #define MSIX_PBA_PEND_MASK 0x000000FF 860 #define MSIX_PBA_PEND_SHIFT 0 861 #define MSIX_PBA_PEND_ENTRY7 0x00000080 862 #define MSIX_PBA_PEND_ENTRY6 0x00000040 863 #define MSIX_PBA_PEND_ENTRY5 0x00000020 864 #define MSIX_PBA_PEND_ENTRY4 0x00000010 865 #define MSIX_PBA_PEND_ENTRY3 0x00000008 866 #define MSIX_PBA_PEND_ENTRY2 0x00000004 867 #define MSIX_PBA_PEND_ENTRY1 0x00000002 868 #define MSIX_PBA_PEND_ENTRY0 0x00000001 869 870 #define JME_PHY_OUI 0x001B8C 871 #define JME_PHY_MODEL 0x21 872 #define JME_PHY_REV 0x01 873 #define JME_PHY_ADDR 1 874 875 /* JMC250 shadow status block. */ 876 struct jme_ssb { 877 uint32_t dw0; 878 uint32_t dw1; 879 uint32_t dw2; 880 uint32_t dw3; 881 uint32_t dw4; 882 uint32_t dw5; 883 uint32_t dw6; 884 uint32_t dw7; 885 }; 886 887 /* JMC250 descriptor structures. */ 888 struct jme_desc { 889 uint32_t flags; 890 uint32_t buflen; 891 uint32_t addr_hi; 892 uint32_t addr_lo; 893 }; 894 895 #define JME_TD_OWN 0x80000000 896 #define JME_TD_INTR 0x40000000 897 #define JME_TD_64BIT 0x20000000 898 #define JME_TD_TCPCSUM 0x10000000 899 #define JME_TD_UDPCSUM 0x08000000 900 #define JME_TD_IPCSUM 0x04000000 901 #define JME_TD_TSO 0x02000000 902 #define JME_TD_VLAN_TAG 0x01000000 903 #define JME_TD_VLAN_MASK 0x0000FFFF 904 905 #define JME_TD_MSS_MASK 0xFFFC0000 906 #define JME_TD_MSS_SHIFT 18 907 #define JME_TD_BUF_LEN_MASK 0x0000FFFF 908 #define JME_TD_BUF_LEN_SHIFT 0 909 910 #define JME_TD_FRAME_LEN_MASK 0x0000FFFF 911 #define JME_TD_FRAME_LEN_SHIFT 0 912 913 /* 914 * Only the first Tx descriptor of a packet is updated 915 * after packet transmission. 916 */ 917 #define JME_TD_TMOUT 0x20000000 918 #define JME_TD_RETRY_EXP 0x10000000 919 #define JME_TD_COLLISION 0x08000000 920 #define JME_TD_UNDERRUN 0x04000000 921 #define JME_TD_EHDR_SIZE_MASK 0x000000FF 922 #define JME_TD_EHDR_SIZE_SHIFT 0 923 924 #define JME_TD_SEG_CNT_MASK 0xFFFF0000 925 #define JME_TD_SEG_CNT_SHIFT 16 926 #define JME_TD_RETRY_CNT_MASK 0x0000FFFF 927 #define JME_TD_RETRY_CNT_SHIFT 0 928 929 #define JME_RD_OWN 0x80000000 930 #define JME_RD_INTR 0x40000000 931 #define JME_RD_64BIT 0x20000000 932 933 #define JME_RD_BUF_LEN_MASK 0x0000FFFF 934 #define JME_RD_BUF_LEN_SHIFT 0 935 936 /* 937 * Only the first Rx descriptor of a packet is updated 938 * after packet reception. 939 */ 940 #define JME_RD_MORE_FRAG 0x20000000 941 #define JME_RD_TCP 0x10000000 942 #define JME_RD_UDP 0x08000000 943 #define JME_RD_IPCSUM 0x04000000 944 #define JME_RD_TCPCSUM 0x02000000 945 #define JME_RD_UDPCSUM 0x01000000 946 #define JME_RD_VLAN_TAG 0x00800000 947 #define JME_RD_IPV4 0x00400000 948 #define JME_RD_IPV6 0x00200000 949 #define JME_RD_PAUSE 0x00100000 950 #define JME_RD_MAGIC 0x00080000 951 #define JME_RD_WAKEUP 0x00040000 952 #define JME_RD_BCAST 0x00030000 953 #define JME_RD_MCAST 0x00020000 954 #define JME_RD_UCAST 0x00010000 955 #define JME_RD_VLAN_MASK 0x0000FFFF 956 #define JME_RD_VLAN_SHIFT 0 957 958 #define JME_RD_VALID 0x80000000 959 #define JME_RD_CNT_MASK 0x7F000000 960 #define JME_RD_CNT_SHIFT 24 961 #define JME_RD_GIANT 0x00800000 962 #define JME_RD_GMII_ERR 0x00400000 963 #define JME_RD_NBL_RCVD 0x00200000 964 #define JME_RD_COLL 0x00100000 965 #define JME_RD_ABORT 0x00080000 966 #define JME_RD_RUNT 0x00040000 967 #define JME_RD_FIFO_OVRN 0x00020000 968 #define JME_RD_CRC_ERR 0x00010000 969 #define JME_RD_FRAME_LEN_MASK 0x0000FFFF 970 971 #define JME_RX_ERR_STAT \ 972 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 973 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 974 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 975 976 #define JME_RD_ERR_MASK 0x00FF0000 977 #define JME_RD_ERR_SHIFT 16 978 #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 979 #define JME_RX_ERR_BITS "\20" \ 980 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 981 "\5COLL\6NBLRCVD\7GMIIERR\10" 982 983 #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 984 #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 985 #define JME_RX_PAD_BYTES 10 986 987 #define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 988 989 #define JME_RD_RSS_HASH_MASK 0x00003F00 990 #define JME_RD_RSS_HASH_SHIFT 8 991 #define JME_RD_RSS_HASH_NONE 0x00000000 992 #define JME_RD_RSS_HASH_IPV4 0x00000100 993 #define JME_RD_RSS_HASH_IPV4TCP 0x00000200 994 #define JME_RD_RSS_HASH_IPV6 0x00000400 995 #define JME_RD_RSS_HASH_IPV6TCP 0x00001000 996 #define JME_RD_HASH_FN_MASK 0x0000000f 997 #define JME_RD_HASH_FN_NONE 0x00000000 998 #define JME_RD_HASH_FN_TOEPLITZ 0x00000001 999 1000 #endif 1001