1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $ 34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.7 2004/01/06 01:40:48 dillon Exp $ 35 * 36 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $ 37 */ 38 39 /* 40 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 41 * documentation not available, but ask me nicely. 42 * 43 * Written by Bill Paul <william.paul@windriver.com> 44 * Wind River Systems 45 */ 46 47 /* 48 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 49 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 50 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 51 * are three supported methods for data transfer between host and 52 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 53 * Propulsion Technology (tm) DMA. The latter mechanism is a form 54 * of double buffer DMA where the packet data is copied to a 55 * pre-allocated DMA buffer who's physical address has been loaded 56 * into a table at device initialization time. The rationale is that 57 * the virtual to physical address translation needed for normal 58 * scatter/gather DMA is more expensive than the data copy needed 59 * for double buffering. This may be true in Windows NT and the like, 60 * but it isn't true for us, at least on the x86 arch. This driver 61 * uses the scatter/gather I/O method for both TX and RX. 62 * 63 * The LXT1001 only supports TCP/IP checksum offload on receive. 64 * Also, the VLAN tagging is done using a 16-entry table which allows 65 * the chip to perform hardware filtering based on VLAN tags. Sadly, 66 * our vlan support doesn't currently play well with this kind of 67 * hardware support. 68 * 69 * Special thanks to: 70 * - Jeff James at Intel, for arranging to have the LXT1001 manual 71 * released (at long last) 72 * - Beny Chen at D-Link, for actually sending it to me 73 * - Brad Short and Keith Alexis at SMC, for sending me sample 74 * SMC9462SX and SMC9462TX adapters for testing 75 * - Paul Saab at Y!, for not killing me (though it remains to be seen 76 * if in fact he did me much of a favor) 77 */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/sockio.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/socket.h> 86 87 #include <net/if.h> 88 #include <net/if_arp.h> 89 #include <net/ethernet.h> 90 #include <net/if_dl.h> 91 #include <net/if_media.h> 92 93 #include <net/bpf.h> 94 95 #include <vm/vm.h> /* for vtophys */ 96 #include <vm/pmap.h> /* for vtophys */ 97 #include <machine/clock.h> /* for DELAY */ 98 #include <machine/bus_pio.h> 99 #include <machine/bus_memio.h> 100 #include <machine/bus.h> 101 #include <machine/resource.h> 102 #include <sys/bus.h> 103 #include <sys/rman.h> 104 105 #include "../mii_layer/mii.h" 106 #include "../mii_layer/miivar.h" 107 108 #include <bus/pci/pcireg.h> 109 #include <bus/pci/pcivar.h> 110 111 #define LGE_USEIOSPACE 112 113 #include "if_lgereg.h" 114 115 /* "controller miibus0" required. See GENERIC if you get errors here. */ 116 #include "miibus_if.h" 117 118 /* 119 * Various supported device vendors/types and their names. 120 */ 121 static struct lge_type lge_devs[] = { 122 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 123 { 0, 0, NULL } 124 }; 125 126 static int lge_probe (device_t); 127 static int lge_attach (device_t); 128 static int lge_detach (device_t); 129 130 static int lge_alloc_jumbo_mem (struct lge_softc *); 131 static void lge_free_jumbo_mem (struct lge_softc *); 132 static void *lge_jalloc (struct lge_softc *); 133 static void lge_jfree (caddr_t, u_int); 134 static void lge_jref (caddr_t, u_int); 135 136 static int lge_newbuf (struct lge_softc *, 137 struct lge_rx_desc *, 138 struct mbuf *); 139 static int lge_encap (struct lge_softc *, 140 struct mbuf *, u_int32_t *); 141 static void lge_rxeof (struct lge_softc *, int); 142 static void lge_rxeoc (struct lge_softc *); 143 static void lge_txeof (struct lge_softc *); 144 static void lge_intr (void *); 145 static void lge_tick (void *); 146 static void lge_start (struct ifnet *); 147 static int lge_ioctl (struct ifnet *, u_long, caddr_t); 148 static void lge_init (void *); 149 static void lge_stop (struct lge_softc *); 150 static void lge_watchdog (struct ifnet *); 151 static void lge_shutdown (device_t); 152 static int lge_ifmedia_upd (struct ifnet *); 153 static void lge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 154 155 static void lge_eeprom_getword (struct lge_softc *, int, u_int16_t *); 156 static void lge_read_eeprom (struct lge_softc *, caddr_t, int, 157 int, int); 158 159 static int lge_miibus_readreg (device_t, int, int); 160 static int lge_miibus_writereg (device_t, int, int, int); 161 static void lge_miibus_statchg (device_t); 162 163 static void lge_setmulti (struct lge_softc *); 164 static u_int32_t lge_crc (struct lge_softc *, caddr_t); 165 static void lge_reset (struct lge_softc *); 166 static int lge_list_rx_init (struct lge_softc *); 167 static int lge_list_tx_init (struct lge_softc *); 168 169 #ifdef LGE_USEIOSPACE 170 #define LGE_RES SYS_RES_IOPORT 171 #define LGE_RID LGE_PCI_LOIO 172 #else 173 #define LGE_RES SYS_RES_MEMORY 174 #define LGE_RID LGE_PCI_LOMEM 175 #endif 176 177 static device_method_t lge_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, lge_probe), 180 DEVMETHOD(device_attach, lge_attach), 181 DEVMETHOD(device_detach, lge_detach), 182 DEVMETHOD(device_shutdown, lge_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 190 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 191 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 192 193 { 0, 0 } 194 }; 195 196 static driver_t lge_driver = { 197 "lge", 198 lge_methods, 199 sizeof(struct lge_softc) 200 }; 201 202 static devclass_t lge_devclass; 203 204 DECLARE_DUMMY_MODULE(if_lge); 205 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0); 206 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 207 208 #define LGE_SETBIT(sc, reg, x) \ 209 CSR_WRITE_4(sc, reg, \ 210 CSR_READ_4(sc, reg) | (x)) 211 212 #define LGE_CLRBIT(sc, reg, x) \ 213 CSR_WRITE_4(sc, reg, \ 214 CSR_READ_4(sc, reg) & ~(x)) 215 216 #define SIO_SET(x) \ 217 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 218 219 #define SIO_CLR(x) \ 220 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 221 222 /* 223 * Read a word of data stored in the EEPROM at address 'addr.' 224 */ 225 static void lge_eeprom_getword(sc, addr, dest) 226 struct lge_softc *sc; 227 int addr; 228 u_int16_t *dest; 229 { 230 int i; 231 u_int32_t val; 232 233 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 234 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 235 236 for (i = 0; i < LGE_TIMEOUT; i++) 237 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 238 break; 239 240 if (i == LGE_TIMEOUT) { 241 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 242 return; 243 } 244 245 val = CSR_READ_4(sc, LGE_EEDATA); 246 247 if (addr & 1) 248 *dest = (val >> 16) & 0xFFFF; 249 else 250 *dest = val & 0xFFFF; 251 252 return; 253 } 254 255 /* 256 * Read a sequence of words from the EEPROM. 257 */ 258 static void lge_read_eeprom(sc, dest, off, cnt, swap) 259 struct lge_softc *sc; 260 caddr_t dest; 261 int off; 262 int cnt; 263 int swap; 264 { 265 int i; 266 u_int16_t word = 0, *ptr; 267 268 for (i = 0; i < cnt; i++) { 269 lge_eeprom_getword(sc, off + i, &word); 270 ptr = (u_int16_t *)(dest + (i * 2)); 271 if (swap) 272 *ptr = ntohs(word); 273 else 274 *ptr = word; 275 } 276 277 return; 278 } 279 280 static int lge_miibus_readreg(dev, phy, reg) 281 device_t dev; 282 int phy, reg; 283 { 284 struct lge_softc *sc; 285 int i; 286 287 sc = device_get_softc(dev); 288 289 /* 290 * If we have a non-PCS PHY, pretend that the internal 291 * autoneg stuff at PHY address 0 isn't there so that 292 * the miibus code will find only the GMII PHY. 293 */ 294 if (sc->lge_pcs == 0 && phy == 0) 295 return(0); 296 297 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 298 299 for (i = 0; i < LGE_TIMEOUT; i++) 300 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 301 break; 302 303 if (i == LGE_TIMEOUT) { 304 printf("lge%d: PHY read timed out\n", sc->lge_unit); 305 return(0); 306 } 307 308 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 309 } 310 311 static int lge_miibus_writereg(dev, phy, reg, data) 312 device_t dev; 313 int phy, reg, data; 314 { 315 struct lge_softc *sc; 316 int i; 317 318 sc = device_get_softc(dev); 319 320 CSR_WRITE_4(sc, LGE_GMIICTL, 321 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 322 323 for (i = 0; i < LGE_TIMEOUT; i++) 324 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 325 break; 326 327 if (i == LGE_TIMEOUT) { 328 printf("lge%d: PHY write timed out\n", sc->lge_unit); 329 return(0); 330 } 331 332 return(0); 333 } 334 335 static void lge_miibus_statchg(dev) 336 device_t dev; 337 { 338 struct lge_softc *sc; 339 struct mii_data *mii; 340 341 sc = device_get_softc(dev); 342 mii = device_get_softc(sc->lge_miibus); 343 344 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 345 switch (IFM_SUBTYPE(mii->mii_media_active)) { 346 case IFM_1000_TX: 347 case IFM_1000_SX: 348 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 349 break; 350 case IFM_100_TX: 351 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 352 break; 353 case IFM_10_T: 354 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 355 break; 356 default: 357 /* 358 * Choose something, even if it's wrong. Clearing 359 * all the bits will hose autoneg on the internal 360 * PHY. 361 */ 362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 363 break; 364 } 365 366 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 367 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 368 } else { 369 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 370 } 371 372 return; 373 } 374 375 static u_int32_t lge_crc(sc, addr) 376 struct lge_softc *sc; 377 caddr_t addr; 378 { 379 u_int32_t crc, carry; 380 int i, j; 381 u_int8_t c; 382 383 /* Compute CRC for the address value. */ 384 crc = 0xFFFFFFFF; /* initial value */ 385 386 for (i = 0; i < 6; i++) { 387 c = *(addr + i); 388 for (j = 0; j < 8; j++) { 389 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 390 crc <<= 1; 391 c >>= 1; 392 if (carry) 393 crc = (crc ^ 0x04c11db6) | carry; 394 } 395 } 396 397 /* 398 * return the filter bit position 399 */ 400 return((crc >> 26) & 0x0000003F); 401 } 402 403 static void lge_setmulti(sc) 404 struct lge_softc *sc; 405 { 406 struct ifnet *ifp; 407 struct ifmultiaddr *ifma; 408 u_int32_t h = 0, hashes[2] = { 0, 0 }; 409 410 ifp = &sc->arpcom.ac_if; 411 412 /* Make sure multicast hash table is enabled. */ 413 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 414 415 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 416 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 417 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 418 return; 419 } 420 421 /* first, zot all the existing hash bits */ 422 CSR_WRITE_4(sc, LGE_MAR0, 0); 423 CSR_WRITE_4(sc, LGE_MAR1, 0); 424 425 /* now program new ones */ 426 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 427 ifma = ifma->ifma_link.le_next) { 428 if (ifma->ifma_addr->sa_family != AF_LINK) 429 continue; 430 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 431 if (h < 32) 432 hashes[0] |= (1 << h); 433 else 434 hashes[1] |= (1 << (h - 32)); 435 } 436 437 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 438 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 439 440 return; 441 } 442 443 static void lge_reset(sc) 444 struct lge_softc *sc; 445 { 446 int i; 447 448 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 449 450 for (i = 0; i < LGE_TIMEOUT; i++) { 451 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 452 break; 453 } 454 455 if (i == LGE_TIMEOUT) 456 printf("lge%d: reset never completed\n", sc->lge_unit); 457 458 /* Wait a little while for the chip to get its brains in order. */ 459 DELAY(1000); 460 461 return; 462 } 463 464 /* 465 * Probe for a Level 1 chip. Check the PCI vendor and device 466 * IDs against our list and return a device name if we find a match. 467 */ 468 static int lge_probe(dev) 469 device_t dev; 470 { 471 struct lge_type *t; 472 473 t = lge_devs; 474 475 while(t->lge_name != NULL) { 476 if ((pci_get_vendor(dev) == t->lge_vid) && 477 (pci_get_device(dev) == t->lge_did)) { 478 device_set_desc(dev, t->lge_name); 479 return(0); 480 } 481 t++; 482 } 483 484 return(ENXIO); 485 } 486 487 /* 488 * Attach the interface. Allocate softc structures, do ifmedia 489 * setup and ethernet/BPF attach. 490 */ 491 static int lge_attach(dev) 492 device_t dev; 493 { 494 int s; 495 u_char eaddr[ETHER_ADDR_LEN]; 496 u_int32_t command; 497 struct lge_softc *sc; 498 struct ifnet *ifp; 499 int unit, error = 0, rid; 500 501 s = splimp(); 502 503 sc = device_get_softc(dev); 504 unit = device_get_unit(dev); 505 bzero(sc, sizeof(struct lge_softc)); 506 507 /* 508 * Handle power management nonsense. 509 */ 510 command = pci_read_config(dev, LGE_PCI_CAPID, 4) & 0x000000FF; 511 if (command == 0x01) { 512 513 command = pci_read_config(dev, LGE_PCI_PWRMGMTCTRL, 4); 514 if (command & LGE_PSTATE_MASK) { 515 u_int32_t iobase, membase, irq; 516 517 /* Save important PCI config data. */ 518 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 519 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 520 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 521 522 /* Reset the power state. */ 523 printf("lge%d: chip is in D%d power mode " 524 "-- setting to D0\n", unit, command & LGE_PSTATE_MASK); 525 command &= 0xFFFFFFFC; 526 pci_write_config(dev, LGE_PCI_PWRMGMTCTRL, command, 4); 527 528 /* Restore PCI config data. */ 529 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 530 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 531 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 532 } 533 } 534 535 /* 536 * Map control/status registers. 537 */ 538 command = pci_read_config(dev, PCIR_COMMAND, 4); 539 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 540 pci_write_config(dev, PCIR_COMMAND, command, 4); 541 command = pci_read_config(dev, PCIR_COMMAND, 4); 542 543 #ifdef LGE_USEIOSPACE 544 if (!(command & PCIM_CMD_PORTEN)) { 545 printf("lge%d: failed to enable I/O ports!\n", unit); 546 error = ENXIO;; 547 goto fail; 548 } 549 #else 550 if (!(command & PCIM_CMD_MEMEN)) { 551 printf("lge%d: failed to enable memory mapping!\n", unit); 552 error = ENXIO;; 553 goto fail; 554 } 555 #endif 556 557 rid = LGE_RID; 558 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid, 559 0, ~0, 1, RF_ACTIVE); 560 561 if (sc->lge_res == NULL) { 562 printf("lge%d: couldn't map ports/memory\n", unit); 563 error = ENXIO; 564 goto fail; 565 } 566 567 sc->lge_btag = rman_get_bustag(sc->lge_res); 568 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 569 570 /* Allocate interrupt */ 571 rid = 0; 572 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 573 RF_SHAREABLE | RF_ACTIVE); 574 575 if (sc->lge_irq == NULL) { 576 printf("lge%d: couldn't map interrupt\n", unit); 577 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 578 error = ENXIO; 579 goto fail; 580 } 581 582 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 583 lge_intr, sc, &sc->lge_intrhand); 584 585 if (error) { 586 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 587 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 588 printf("lge%d: couldn't set up irq\n", unit); 589 goto fail; 590 } 591 592 /* Reset the adapter. */ 593 lge_reset(sc); 594 595 /* 596 * Get station address from the EEPROM. 597 */ 598 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 599 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 600 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 601 602 /* 603 * A Level 1 chip was detected. Inform the world. 604 */ 605 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 606 607 sc->lge_unit = unit; 608 callout_handle_init(&sc->lge_stat_ch); 609 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 610 611 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 612 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 613 614 if (sc->lge_ldata == NULL) { 615 printf("lge%d: no memory for list buffers!\n", unit); 616 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 617 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 618 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 619 error = ENXIO; 620 goto fail; 621 } 622 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 623 624 /* Try to allocate memory for jumbo buffers. */ 625 if (lge_alloc_jumbo_mem(sc)) { 626 printf("lge%d: jumbo buffer allocation failed\n", 627 sc->lge_unit); 628 contigfree(sc->lge_ldata, 629 sizeof(struct lge_list_data), M_DEVBUF); 630 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 631 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 632 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 633 error = ENXIO; 634 goto fail; 635 } 636 637 ifp = &sc->arpcom.ac_if; 638 ifp->if_softc = sc; 639 if_initname(ifp, "lge", unit); 640 ifp->if_mtu = ETHERMTU; 641 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 642 ifp->if_ioctl = lge_ioctl; 643 ifp->if_output = ether_output; 644 ifp->if_start = lge_start; 645 ifp->if_watchdog = lge_watchdog; 646 ifp->if_init = lge_init; 647 ifp->if_baudrate = 1000000000; 648 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 649 ifp->if_capabilities = IFCAP_RXCSUM; 650 ifp->if_capenable = ifp->if_capabilities; 651 652 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 653 sc->lge_pcs = 1; 654 else 655 sc->lge_pcs = 0; 656 657 /* 658 * Do MII setup. 659 */ 660 if (mii_phy_probe(dev, &sc->lge_miibus, 661 lge_ifmedia_upd, lge_ifmedia_sts)) { 662 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 663 contigfree(sc->lge_ldata, 664 sizeof(struct lge_list_data), M_DEVBUF); 665 lge_free_jumbo_mem(sc); 666 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 667 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 668 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 669 error = ENXIO; 670 goto fail; 671 } 672 673 /* 674 * Call MI attach routine. 675 */ 676 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 677 callout_handle_init(&sc->lge_stat_ch); 678 679 fail: 680 splx(s); 681 return(error); 682 } 683 684 static int lge_detach(dev) 685 device_t dev; 686 { 687 struct lge_softc *sc; 688 struct ifnet *ifp; 689 int s; 690 691 s = splimp(); 692 693 sc = device_get_softc(dev); 694 ifp = &sc->arpcom.ac_if; 695 696 lge_reset(sc); 697 lge_stop(sc); 698 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 699 700 bus_generic_detach(dev); 701 device_delete_child(dev, sc->lge_miibus); 702 703 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 704 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 705 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 706 707 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 708 lge_free_jumbo_mem(sc); 709 710 splx(s); 711 712 return(0); 713 } 714 715 /* 716 * Initialize the transmit descriptors. 717 */ 718 static int lge_list_tx_init(sc) 719 struct lge_softc *sc; 720 { 721 struct lge_list_data *ld; 722 struct lge_ring_data *cd; 723 int i; 724 725 cd = &sc->lge_cdata; 726 ld = sc->lge_ldata; 727 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 728 ld->lge_tx_list[i].lge_mbuf = NULL; 729 ld->lge_tx_list[i].lge_ctl = 0; 730 } 731 732 cd->lge_tx_prod = cd->lge_tx_cons = 0; 733 734 return(0); 735 } 736 737 738 /* 739 * Initialize the RX descriptors and allocate mbufs for them. Note that 740 * we arralge the descriptors in a closed ring, so that the last descriptor 741 * points back to the first. 742 */ 743 static int lge_list_rx_init(sc) 744 struct lge_softc *sc; 745 { 746 struct lge_list_data *ld; 747 struct lge_ring_data *cd; 748 int i; 749 750 ld = sc->lge_ldata; 751 cd = &sc->lge_cdata; 752 753 cd->lge_rx_prod = cd->lge_rx_cons = 0; 754 755 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 756 757 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 758 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 759 break; 760 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 761 return(ENOBUFS); 762 } 763 764 /* Clear possible 'rx command queue empty' interrupt. */ 765 CSR_READ_4(sc, LGE_ISR); 766 767 return(0); 768 } 769 770 /* 771 * Initialize an RX descriptor and attach an MBUF cluster. 772 */ 773 static int lge_newbuf(sc, c, m) 774 struct lge_softc *sc; 775 struct lge_rx_desc *c; 776 struct mbuf *m; 777 { 778 struct mbuf *m_new = NULL; 779 caddr_t *buf = NULL; 780 781 if (m == NULL) { 782 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 783 if (m_new == NULL) { 784 printf("lge%d: no memory for rx list " 785 "-- packet dropped!\n", sc->lge_unit); 786 return(ENOBUFS); 787 } 788 789 /* Allocate the jumbo buffer */ 790 buf = lge_jalloc(sc); 791 if (buf == NULL) { 792 #ifdef LGE_VERBOSE 793 printf("lge%d: jumbo allocation failed " 794 "-- packet dropped!\n", sc->lge_unit); 795 #endif 796 m_freem(m_new); 797 return(ENOBUFS); 798 } 799 /* Attach the buffer to the mbuf */ 800 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 801 m_new->m_flags |= M_EXT; 802 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 803 m_new->m_len = LGE_MCLBYTES; 804 m_new->m_ext.ext_free = lge_jfree; 805 m_new->m_ext.ext_ref = lge_jref; 806 } else { 807 m_new = m; 808 m_new->m_len = m_new->m_pkthdr.len = LGE_MCLBYTES; 809 m_new->m_data = m_new->m_ext.ext_buf; 810 } 811 812 /* 813 * Adjust alignment so packet payload begins on a 814 * longword boundary. Mandatory for Alpha, useful on 815 * x86 too. 816 */ 817 m_adj(m_new, ETHER_ALIGN); 818 819 c->lge_mbuf = m_new; 820 c->lge_fragptr_hi = 0; 821 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 822 c->lge_fraglen = m_new->m_len; 823 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 824 c->lge_sts = 0; 825 826 /* 827 * Put this buffer in the RX command FIFO. To do this, 828 * we just write the physical address of the descriptor 829 * into the RX descriptor address registers. Note that 830 * there are two registers, one high DWORD and one low 831 * DWORD, which lets us specify a 64-bit address if 832 * desired. We only use a 32-bit address for now. 833 * Writing to the low DWORD register is what actually 834 * causes the command to be issued, so we do that 835 * last. 836 */ 837 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 838 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 839 840 return(0); 841 } 842 843 static int lge_alloc_jumbo_mem(sc) 844 struct lge_softc *sc; 845 { 846 caddr_t ptr; 847 int i; 848 struct lge_jpool_entry *entry; 849 850 /* Grab a big chunk o' storage. */ 851 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 852 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 853 854 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 855 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 856 return(ENOBUFS); 857 } 858 859 SLIST_INIT(&sc->lge_jfree_listhead); 860 SLIST_INIT(&sc->lge_jinuse_listhead); 861 862 /* 863 * Now divide it up into 9K pieces and save the addresses 864 * in an array. 865 */ 866 ptr = sc->lge_cdata.lge_jumbo_buf; 867 for (i = 0; i < LGE_JSLOTS; i++) { 868 u_int64_t **aptr; 869 aptr = (u_int64_t **)ptr; 870 aptr[0] = (u_int64_t *)sc; 871 ptr += sizeof(u_int64_t); 872 sc->lge_cdata.lge_jslots[i].lge_buf = ptr; 873 sc->lge_cdata.lge_jslots[i].lge_inuse = 0; 874 ptr += LGE_MCLBYTES; 875 entry = malloc(sizeof(struct lge_jpool_entry), 876 M_DEVBUF, M_NOWAIT); 877 if (entry == NULL) { 878 printf("lge%d: no memory for jumbo " 879 "buffer queue!\n", sc->lge_unit); 880 return(ENOBUFS); 881 } 882 entry->slot = i; 883 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 884 entry, jpool_entries); 885 } 886 887 return(0); 888 } 889 890 static void lge_free_jumbo_mem(sc) 891 struct lge_softc *sc; 892 { 893 int i; 894 struct lge_jpool_entry *entry; 895 896 for (i = 0; i < LGE_JSLOTS; i++) { 897 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 898 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 899 free(entry, M_DEVBUF); 900 } 901 902 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 903 904 return; 905 } 906 907 /* 908 * Allocate a jumbo buffer. 909 */ 910 static void *lge_jalloc(sc) 911 struct lge_softc *sc; 912 { 913 struct lge_jpool_entry *entry; 914 915 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 916 917 if (entry == NULL) { 918 #ifdef LGE_VERBOSE 919 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 920 #endif 921 return(NULL); 922 } 923 924 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 925 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 926 sc->lge_cdata.lge_jslots[entry->slot].lge_inuse = 1; 927 return(sc->lge_cdata.lge_jslots[entry->slot].lge_buf); 928 } 929 930 /* 931 * Adjust usage count on a jumbo buffer. In general this doesn't 932 * get used much because our jumbo buffers don't get passed around 933 * a lot, but it's implemented for correctness. 934 */ 935 static void lge_jref(buf, size) 936 caddr_t buf; 937 u_int size; 938 { 939 struct lge_softc *sc; 940 u_int64_t **aptr; 941 int i; 942 943 /* Extract the softc struct pointer. */ 944 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 945 sc = (struct lge_softc *)(aptr[0]); 946 947 if (sc == NULL) 948 panic("lge_jref: can't find softc pointer!"); 949 950 if (size != LGE_MCLBYTES) 951 panic("lge_jref: adjusting refcount of buf of wrong size!"); 952 953 /* calculate the slot this buffer belongs to */ 954 955 i = ((vm_offset_t)aptr 956 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 957 958 if ((i < 0) || (i >= LGE_JSLOTS)) 959 panic("lge_jref: asked to reference buffer " 960 "that we don't manage!"); 961 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0) 962 panic("lge_jref: buffer already free!"); 963 else 964 sc->lge_cdata.lge_jslots[i].lge_inuse++; 965 966 return; 967 } 968 969 /* 970 * Release a jumbo buffer. 971 */ 972 static void lge_jfree(buf, size) 973 caddr_t buf; 974 u_int size; 975 { 976 struct lge_softc *sc; 977 u_int64_t **aptr; 978 int i; 979 struct lge_jpool_entry *entry; 980 981 /* Extract the softc struct pointer. */ 982 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 983 sc = (struct lge_softc *)(aptr[0]); 984 985 if (sc == NULL) 986 panic("lge_jfree: can't find softc pointer!"); 987 988 if (size != LGE_MCLBYTES) 989 panic("lge_jfree: freeing buffer of wrong size!"); 990 991 /* calculate the slot this buffer belongs to */ 992 i = ((vm_offset_t)aptr 993 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 994 995 if ((i < 0) || (i >= LGE_JSLOTS)) 996 panic("lge_jfree: asked to free buffer that we don't manage!"); 997 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0) 998 panic("lge_jfree: buffer already free!"); 999 else { 1000 sc->lge_cdata.lge_jslots[i].lge_inuse--; 1001 if(sc->lge_cdata.lge_jslots[i].lge_inuse == 0) { 1002 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 1003 if (entry == NULL) 1004 panic("lge_jfree: buffer not in use!"); 1005 entry->slot = i; 1006 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, 1007 jpool_entries); 1008 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 1009 entry, jpool_entries); 1010 } 1011 } 1012 1013 return; 1014 } 1015 1016 /* 1017 * A frame has been uploaded: pass the resulting mbuf chain up to 1018 * the higher level protocols. 1019 */ 1020 static void lge_rxeof(sc, cnt) 1021 struct lge_softc *sc; 1022 int cnt; 1023 { 1024 struct ether_header *eh; 1025 struct mbuf *m; 1026 struct ifnet *ifp; 1027 struct lge_rx_desc *cur_rx; 1028 int c, i, total_len = 0; 1029 u_int32_t rxsts, rxctl; 1030 1031 ifp = &sc->arpcom.ac_if; 1032 1033 /* Find out how many frames were processed. */ 1034 c = cnt; 1035 i = sc->lge_cdata.lge_rx_cons; 1036 1037 /* Suck them in. */ 1038 while(c) { 1039 struct mbuf *m0 = NULL; 1040 1041 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 1042 rxctl = cur_rx->lge_ctl; 1043 rxsts = cur_rx->lge_sts; 1044 m = cur_rx->lge_mbuf; 1045 cur_rx->lge_mbuf = NULL; 1046 total_len = LGE_RXBYTES(cur_rx); 1047 LGE_INC(i, LGE_RX_LIST_CNT); 1048 c--; 1049 1050 /* 1051 * If an error occurs, update stats, clear the 1052 * status word and leave the mbuf cluster in place: 1053 * it should simply get re-used next time this descriptor 1054 * comes up in the ring. 1055 */ 1056 if (rxctl & LGE_RXCTL_ERRMASK) { 1057 ifp->if_ierrors++; 1058 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 1059 continue; 1060 } 1061 1062 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 1063 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1064 total_len + ETHER_ALIGN, 0, ifp, NULL); 1065 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 1066 if (m0 == NULL) { 1067 printf("lge%d: no receive buffers " 1068 "available -- packet dropped!\n", 1069 sc->lge_unit); 1070 ifp->if_ierrors++; 1071 continue; 1072 } 1073 m_adj(m0, ETHER_ALIGN); 1074 m = m0; 1075 } else { 1076 m->m_pkthdr.rcvif = ifp; 1077 m->m_pkthdr.len = m->m_len = total_len; 1078 } 1079 1080 ifp->if_ipackets++; 1081 eh = mtod(m, struct ether_header *); 1082 1083 /* Remove header from mbuf and pass it on. */ 1084 m_adj(m, sizeof(struct ether_header)); 1085 1086 /* Do IP checksum checking. */ 1087 if (rxsts & LGE_RXSTS_ISIP) 1088 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1089 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 1090 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1091 if ((rxsts & LGE_RXSTS_ISTCP && 1092 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1093 (rxsts & LGE_RXSTS_ISUDP && 1094 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1095 m->m_pkthdr.csum_flags |= 1096 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1097 m->m_pkthdr.csum_data = 0xffff; 1098 } 1099 1100 ether_input(ifp, eh, m); 1101 } 1102 1103 sc->lge_cdata.lge_rx_cons = i; 1104 1105 return; 1106 } 1107 1108 void lge_rxeoc(sc) 1109 struct lge_softc *sc; 1110 { 1111 struct ifnet *ifp; 1112 1113 ifp = &sc->arpcom.ac_if; 1114 ifp->if_flags &= ~IFF_RUNNING; 1115 lge_init(sc); 1116 return; 1117 } 1118 1119 /* 1120 * A frame was downloaded to the chip. It's safe for us to clean up 1121 * the list buffers. 1122 */ 1123 1124 static void lge_txeof(sc) 1125 struct lge_softc *sc; 1126 { 1127 struct lge_tx_desc *cur_tx = NULL; 1128 struct ifnet *ifp; 1129 u_int32_t idx, txdone; 1130 1131 ifp = &sc->arpcom.ac_if; 1132 1133 /* Clear the timeout timer. */ 1134 ifp->if_timer = 0; 1135 1136 /* 1137 * Go through our tx list and free mbufs for those 1138 * frames that have been transmitted. 1139 */ 1140 idx = sc->lge_cdata.lge_tx_cons; 1141 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1142 1143 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1144 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1145 1146 ifp->if_opackets++; 1147 if (cur_tx->lge_mbuf != NULL) { 1148 m_freem(cur_tx->lge_mbuf); 1149 cur_tx->lge_mbuf = NULL; 1150 } 1151 cur_tx->lge_ctl = 0; 1152 1153 txdone--; 1154 LGE_INC(idx, LGE_TX_LIST_CNT); 1155 ifp->if_timer = 0; 1156 } 1157 1158 sc->lge_cdata.lge_tx_cons = idx; 1159 1160 if (cur_tx != NULL) 1161 ifp->if_flags &= ~IFF_OACTIVE; 1162 1163 return; 1164 } 1165 1166 static void lge_tick(xsc) 1167 void *xsc; 1168 { 1169 struct lge_softc *sc; 1170 struct mii_data *mii; 1171 struct ifnet *ifp; 1172 int s; 1173 1174 s = splimp(); 1175 1176 sc = xsc; 1177 ifp = &sc->arpcom.ac_if; 1178 1179 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1180 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1181 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1182 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1183 1184 if (!sc->lge_link) { 1185 mii = device_get_softc(sc->lge_miibus); 1186 mii_tick(mii); 1187 mii_pollstat(mii); 1188 if (mii->mii_media_status & IFM_ACTIVE && 1189 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1190 sc->lge_link++; 1191 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1192 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) 1193 printf("lge%d: gigabit link up\n", 1194 sc->lge_unit); 1195 if (ifp->if_snd.ifq_head != NULL) 1196 lge_start(ifp); 1197 } 1198 } 1199 1200 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1201 1202 splx(s); 1203 1204 return; 1205 } 1206 1207 static void lge_intr(arg) 1208 void *arg; 1209 { 1210 struct lge_softc *sc; 1211 struct ifnet *ifp; 1212 u_int32_t status; 1213 1214 sc = arg; 1215 ifp = &sc->arpcom.ac_if; 1216 1217 /* Supress unwanted interrupts */ 1218 if (!(ifp->if_flags & IFF_UP)) { 1219 lge_stop(sc); 1220 return; 1221 } 1222 1223 for (;;) { 1224 /* 1225 * Reading the ISR register clears all interrupts, and 1226 * clears the 'interrupts enabled' bit in the IMR 1227 * register. 1228 */ 1229 status = CSR_READ_4(sc, LGE_ISR); 1230 1231 if ((status & LGE_INTRS) == 0) 1232 break; 1233 1234 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1235 lge_txeof(sc); 1236 1237 if (status & LGE_ISR_RXDMA_DONE) 1238 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1239 1240 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1241 lge_rxeoc(sc); 1242 1243 if (status & LGE_ISR_PHY_INTR) { 1244 sc->lge_link = 0; 1245 untimeout(lge_tick, sc, sc->lge_stat_ch); 1246 lge_tick(sc); 1247 } 1248 } 1249 1250 /* Re-enable interrupts. */ 1251 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1252 1253 if (ifp->if_snd.ifq_head != NULL) 1254 lge_start(ifp); 1255 1256 return; 1257 } 1258 1259 /* 1260 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1261 * pointers to the fragment pointers. 1262 */ 1263 static int lge_encap(sc, m_head, txidx) 1264 struct lge_softc *sc; 1265 struct mbuf *m_head; 1266 u_int32_t *txidx; 1267 { 1268 struct lge_frag *f = NULL; 1269 struct lge_tx_desc *cur_tx; 1270 struct mbuf *m; 1271 int frag = 0, tot_len = 0; 1272 1273 /* 1274 * Start packing the mbufs in this chain into 1275 * the fragment pointers. Stop when we run out 1276 * of fragments or hit the end of the mbuf chain. 1277 */ 1278 m = m_head; 1279 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1280 frag = 0; 1281 1282 for (m = m_head; m != NULL; m = m->m_next) { 1283 if (m->m_len != 0) { 1284 tot_len += m->m_len; 1285 f = &cur_tx->lge_frags[frag]; 1286 f->lge_fraglen = m->m_len; 1287 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1288 f->lge_fragptr_hi = 0; 1289 frag++; 1290 } 1291 } 1292 1293 if (m != NULL) 1294 return(ENOBUFS); 1295 1296 cur_tx->lge_mbuf = m_head; 1297 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1298 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1299 1300 /* Queue for transmit */ 1301 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1302 1303 return(0); 1304 } 1305 1306 /* 1307 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1308 * to the mbuf data regions directly in the transmit lists. We also save a 1309 * copy of the pointers since the transmit list fragment pointers are 1310 * physical addresses. 1311 */ 1312 1313 static void lge_start(ifp) 1314 struct ifnet *ifp; 1315 { 1316 struct lge_softc *sc; 1317 struct mbuf *m_head = NULL; 1318 u_int32_t idx; 1319 1320 sc = ifp->if_softc; 1321 1322 if (!sc->lge_link) 1323 return; 1324 1325 idx = sc->lge_cdata.lge_tx_prod; 1326 1327 if (ifp->if_flags & IFF_OACTIVE) 1328 return; 1329 1330 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1331 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1332 break; 1333 1334 IF_DEQUEUE(&ifp->if_snd, m_head); 1335 if (m_head == NULL) 1336 break; 1337 1338 if (lge_encap(sc, m_head, &idx)) { 1339 IF_PREPEND(&ifp->if_snd, m_head); 1340 ifp->if_flags |= IFF_OACTIVE; 1341 break; 1342 } 1343 1344 /* 1345 * If there's a BPF listener, bounce a copy of this frame 1346 * to him. 1347 */ 1348 if (ifp->if_bpf) 1349 bpf_mtap(ifp, m_head); 1350 } 1351 1352 sc->lge_cdata.lge_tx_prod = idx; 1353 1354 /* 1355 * Set a timeout in case the chip goes out to lunch. 1356 */ 1357 ifp->if_timer = 5; 1358 1359 return; 1360 } 1361 1362 static void lge_init(xsc) 1363 void *xsc; 1364 { 1365 struct lge_softc *sc = xsc; 1366 struct ifnet *ifp = &sc->arpcom.ac_if; 1367 struct mii_data *mii; 1368 int s; 1369 1370 if (ifp->if_flags & IFF_RUNNING) 1371 return; 1372 1373 s = splimp(); 1374 1375 /* 1376 * Cancel pending I/O and free all RX/TX buffers. 1377 */ 1378 lge_stop(sc); 1379 lge_reset(sc); 1380 1381 mii = device_get_softc(sc->lge_miibus); 1382 1383 /* Set MAC address */ 1384 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1385 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1386 1387 /* Init circular RX list. */ 1388 if (lge_list_rx_init(sc) == ENOBUFS) { 1389 printf("lge%d: initialization failed: no " 1390 "memory for rx buffers\n", sc->lge_unit); 1391 lge_stop(sc); 1392 (void)splx(s); 1393 return; 1394 } 1395 1396 /* 1397 * Init tx descriptors. 1398 */ 1399 lge_list_tx_init(sc); 1400 1401 /* Set initial value for MODE1 register. */ 1402 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1403 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1404 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1405 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1406 1407 /* If we want promiscuous mode, set the allframes bit. */ 1408 if (ifp->if_flags & IFF_PROMISC) { 1409 CSR_WRITE_4(sc, LGE_MODE1, 1410 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1411 } else { 1412 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1413 } 1414 1415 /* 1416 * Set the capture broadcast bit to capture broadcast frames. 1417 */ 1418 if (ifp->if_flags & IFF_BROADCAST) { 1419 CSR_WRITE_4(sc, LGE_MODE1, 1420 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1421 } else { 1422 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1423 } 1424 1425 /* Packet padding workaround? */ 1426 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1427 1428 /* No error frames */ 1429 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1430 1431 /* Receive large frames */ 1432 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1433 1434 /* Workaround: disable RX/TX flow control */ 1435 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1436 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1437 1438 /* Make sure to strip CRC from received frames */ 1439 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1440 1441 /* Turn off magic packet mode */ 1442 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1443 1444 /* Turn off all VLAN stuff */ 1445 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1446 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1447 1448 /* Workarond: FIFO overflow */ 1449 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1450 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1451 1452 /* 1453 * Load the multicast filter. 1454 */ 1455 lge_setmulti(sc); 1456 1457 /* 1458 * Enable hardware checksum validation for all received IPv4 1459 * packets, do not reject packets with bad checksums. 1460 */ 1461 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1462 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1463 LGE_MODE2_RX_ERRCSUM); 1464 1465 /* 1466 * Enable the delivery of PHY interrupts based on 1467 * link/speed/duplex status chalges. 1468 */ 1469 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1470 1471 /* Enable receiver and transmitter. */ 1472 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1473 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1474 1475 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1476 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1477 1478 /* 1479 * Enable interrupts. 1480 */ 1481 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1482 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1483 1484 lge_ifmedia_upd(ifp); 1485 1486 ifp->if_flags |= IFF_RUNNING; 1487 ifp->if_flags &= ~IFF_OACTIVE; 1488 1489 (void)splx(s); 1490 1491 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1492 1493 return; 1494 } 1495 1496 /* 1497 * Set media options. 1498 */ 1499 static int lge_ifmedia_upd(ifp) 1500 struct ifnet *ifp; 1501 { 1502 struct lge_softc *sc; 1503 struct mii_data *mii; 1504 1505 sc = ifp->if_softc; 1506 1507 mii = device_get_softc(sc->lge_miibus); 1508 sc->lge_link = 0; 1509 if (mii->mii_instance) { 1510 struct mii_softc *miisc; 1511 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1512 miisc = LIST_NEXT(miisc, mii_list)) 1513 mii_phy_reset(miisc); 1514 } 1515 mii_mediachg(mii); 1516 1517 return(0); 1518 } 1519 1520 /* 1521 * Report current media status. 1522 */ 1523 static void lge_ifmedia_sts(ifp, ifmr) 1524 struct ifnet *ifp; 1525 struct ifmediareq *ifmr; 1526 { 1527 struct lge_softc *sc; 1528 struct mii_data *mii; 1529 1530 sc = ifp->if_softc; 1531 1532 mii = device_get_softc(sc->lge_miibus); 1533 mii_pollstat(mii); 1534 ifmr->ifm_active = mii->mii_media_active; 1535 ifmr->ifm_status = mii->mii_media_status; 1536 1537 return; 1538 } 1539 1540 static int lge_ioctl(ifp, command, data) 1541 struct ifnet *ifp; 1542 u_long command; 1543 caddr_t data; 1544 { 1545 struct lge_softc *sc = ifp->if_softc; 1546 struct ifreq *ifr = (struct ifreq *) data; 1547 struct mii_data *mii; 1548 int s, error = 0; 1549 1550 s = splimp(); 1551 1552 switch(command) { 1553 case SIOCSIFADDR: 1554 case SIOCGIFADDR: 1555 error = ether_ioctl(ifp, command, data); 1556 break; 1557 case SIOCSIFMTU: 1558 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1559 error = EINVAL; 1560 else 1561 ifp->if_mtu = ifr->ifr_mtu; 1562 break; 1563 case SIOCSIFFLAGS: 1564 if (ifp->if_flags & IFF_UP) { 1565 if (ifp->if_flags & IFF_RUNNING && 1566 ifp->if_flags & IFF_PROMISC && 1567 !(sc->lge_if_flags & IFF_PROMISC)) { 1568 CSR_WRITE_4(sc, LGE_MODE1, 1569 LGE_MODE1_SETRST_CTL1| 1570 LGE_MODE1_RX_PROMISC); 1571 } else if (ifp->if_flags & IFF_RUNNING && 1572 !(ifp->if_flags & IFF_PROMISC) && 1573 sc->lge_if_flags & IFF_PROMISC) { 1574 CSR_WRITE_4(sc, LGE_MODE1, 1575 LGE_MODE1_RX_PROMISC); 1576 } else { 1577 ifp->if_flags &= ~IFF_RUNNING; 1578 lge_init(sc); 1579 } 1580 } else { 1581 if (ifp->if_flags & IFF_RUNNING) 1582 lge_stop(sc); 1583 } 1584 sc->lge_if_flags = ifp->if_flags; 1585 error = 0; 1586 break; 1587 case SIOCADDMULTI: 1588 case SIOCDELMULTI: 1589 lge_setmulti(sc); 1590 error = 0; 1591 break; 1592 case SIOCGIFMEDIA: 1593 case SIOCSIFMEDIA: 1594 mii = device_get_softc(sc->lge_miibus); 1595 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1596 break; 1597 default: 1598 error = EINVAL; 1599 break; 1600 } 1601 1602 (void)splx(s); 1603 1604 return(error); 1605 } 1606 1607 static void lge_watchdog(ifp) 1608 struct ifnet *ifp; 1609 { 1610 struct lge_softc *sc; 1611 1612 sc = ifp->if_softc; 1613 1614 ifp->if_oerrors++; 1615 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1616 1617 lge_stop(sc); 1618 lge_reset(sc); 1619 ifp->if_flags &= ~IFF_RUNNING; 1620 lge_init(sc); 1621 1622 if (ifp->if_snd.ifq_head != NULL) 1623 lge_start(ifp); 1624 1625 return; 1626 } 1627 1628 /* 1629 * Stop the adapter and free any mbufs allocated to the 1630 * RX and TX lists. 1631 */ 1632 static void lge_stop(sc) 1633 struct lge_softc *sc; 1634 { 1635 int i; 1636 struct ifnet *ifp; 1637 1638 ifp = &sc->arpcom.ac_if; 1639 ifp->if_timer = 0; 1640 untimeout(lge_tick, sc, sc->lge_stat_ch); 1641 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1642 1643 /* Disable receiver and transmitter. */ 1644 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1645 sc->lge_link = 0; 1646 1647 /* 1648 * Free data in the RX lists. 1649 */ 1650 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1651 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1652 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1653 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1654 } 1655 } 1656 bzero((char *)&sc->lge_ldata->lge_rx_list, 1657 sizeof(sc->lge_ldata->lge_rx_list)); 1658 1659 /* 1660 * Free the TX list buffers. 1661 */ 1662 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1663 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1664 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1665 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1666 } 1667 } 1668 1669 bzero((char *)&sc->lge_ldata->lge_tx_list, 1670 sizeof(sc->lge_ldata->lge_tx_list)); 1671 1672 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1673 1674 return; 1675 } 1676 1677 /* 1678 * Stop all chip I/O so that the kernel's probe routines don't 1679 * get confused by errant DMAs when rebooting. 1680 */ 1681 static void lge_shutdown(dev) 1682 device_t dev; 1683 { 1684 struct lge_softc *sc; 1685 1686 sc = device_get_softc(dev); 1687 1688 lge_reset(sc); 1689 lge_stop(sc); 1690 1691 return; 1692 } 1693