1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $ 34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.29 2005/06/14 15:08:16 joerg Exp $ 35 */ 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * Written by Bill Paul <william.paul@windriver.com> 42 * Wind River Systems 43 */ 44 45 /* 46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 47 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 49 * are three supported methods for data transfer between host and 50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 51 * Propulsion Technology (tm) DMA. The latter mechanism is a form 52 * of double buffer DMA where the packet data is copied to a 53 * pre-allocated DMA buffer who's physical address has been loaded 54 * into a table at device initialization time. The rationale is that 55 * the virtual to physical address translation needed for normal 56 * scatter/gather DMA is more expensive than the data copy needed 57 * for double buffering. This may be true in Windows NT and the like, 58 * but it isn't true for us, at least on the x86 arch. This driver 59 * uses the scatter/gather I/O method for both TX and RX. 60 * 61 * The LXT1001 only supports TCP/IP checksum offload on receive. 62 * Also, the VLAN tagging is done using a 16-entry table which allows 63 * the chip to perform hardware filtering based on VLAN tags. Sadly, 64 * our vlan support doesn't currently play well with this kind of 65 * hardware support. 66 * 67 * Special thanks to: 68 * - Jeff James at Intel, for arranging to have the LXT1001 manual 69 * released (at long last) 70 * - Beny Chen at D-Link, for actually sending it to me 71 * - Brad Short and Keith Alexis at SMC, for sending me sample 72 * SMC9462SX and SMC9462TX adapters for testing 73 * - Paul Saab at Y!, for not killing me (though it remains to be seen 74 * if in fact he did me much of a favor) 75 */ 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/sockio.h> 80 #include <sys/mbuf.h> 81 #include <sys/malloc.h> 82 #include <sys/kernel.h> 83 #include <sys/socket.h> 84 #include <sys/thread2.h> 85 86 #include <net/if.h> 87 #include <net/ifq_var.h> 88 #include <net/if_arp.h> 89 #include <net/ethernet.h> 90 #include <net/if_dl.h> 91 #include <net/if_media.h> 92 93 #include <net/bpf.h> 94 95 #include <vm/vm.h> /* for vtophys */ 96 #include <vm/pmap.h> /* for vtophys */ 97 #include <machine/bus.h> 98 #include <machine/resource.h> 99 #include <sys/bus.h> 100 #include <sys/rman.h> 101 102 #include <dev/netif/mii_layer/mii.h> 103 #include <dev/netif/mii_layer/miivar.h> 104 105 #include <bus/pci/pcireg.h> 106 #include <bus/pci/pcivar.h> 107 108 #define LGE_USEIOSPACE 109 110 #include "if_lgereg.h" 111 112 /* "controller miibus0" required. See GENERIC if you get errors here. */ 113 #include "miibus_if.h" 114 115 /* 116 * Various supported device vendors/types and their names. 117 */ 118 static struct lge_type lge_devs[] = { 119 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 120 { 0, 0, NULL } 121 }; 122 123 static int lge_probe(device_t); 124 static int lge_attach(device_t); 125 static int lge_detach(device_t); 126 127 static int lge_alloc_jumbo_mem(struct lge_softc *); 128 static void lge_free_jumbo_mem(struct lge_softc *); 129 static struct lge_jslot 130 *lge_jalloc(struct lge_softc *); 131 static void lge_jfree(void *); 132 static void lge_jref(void *); 133 134 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, 135 struct mbuf *); 136 static int lge_encap(struct lge_softc *, struct mbuf *, uint32_t *); 137 static void lge_rxeof(struct lge_softc *, int); 138 static void lge_rxeoc(struct lge_softc *); 139 static void lge_txeof(struct lge_softc *); 140 static void lge_intr(void *); 141 static void lge_tick(void *); 142 static void lge_start(struct ifnet *); 143 static int lge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 144 static void lge_init(void *); 145 static void lge_stop(struct lge_softc *); 146 static void lge_watchdog(struct ifnet *); 147 static void lge_shutdown(device_t); 148 static int lge_ifmedia_upd(struct ifnet *); 149 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 150 151 static void lge_eeprom_getword(struct lge_softc *, int, uint16_t *); 152 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int); 153 154 static int lge_miibus_readreg(device_t, int, int); 155 static int lge_miibus_writereg(device_t, int, int, int); 156 static void lge_miibus_statchg(device_t); 157 158 static void lge_setmulti(struct lge_softc *); 159 static void lge_reset(struct lge_softc *); 160 static int lge_list_rx_init(struct lge_softc *); 161 static int lge_list_tx_init(struct lge_softc *); 162 163 #ifdef LGE_USEIOSPACE 164 #define LGE_RES SYS_RES_IOPORT 165 #define LGE_RID LGE_PCI_LOIO 166 #else 167 #define LGE_RES SYS_RES_MEMORY 168 #define LGE_RID LGE_PCI_LOMEM 169 #endif 170 171 static device_method_t lge_methods[] = { 172 /* Device interface */ 173 DEVMETHOD(device_probe, lge_probe), 174 DEVMETHOD(device_attach, lge_attach), 175 DEVMETHOD(device_detach, lge_detach), 176 DEVMETHOD(device_shutdown, lge_shutdown), 177 178 /* bus interface */ 179 DEVMETHOD(bus_print_child, bus_generic_print_child), 180 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 181 182 /* MII interface */ 183 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 184 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 185 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 186 187 { 0, 0 } 188 }; 189 190 static DEFINE_CLASS_0(lge, lge_driver, lge_methods, sizeof(struct lge_softc)); 191 static devclass_t lge_devclass; 192 193 DECLARE_DUMMY_MODULE(if_lge); 194 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0); 195 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 196 197 #define LGE_SETBIT(sc, reg, x) \ 198 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 199 200 #define LGE_CLRBIT(sc, reg, x) \ 201 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 202 203 #define SIO_SET(x) \ 204 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x)) 205 206 #define SIO_CLR(x) \ 207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x)) 208 209 /* 210 * Read a word of data stored in the EEPROM at address 'addr.' 211 */ 212 static void 213 lge_eeprom_getword(struct lge_softc *sc, int addr, uint16_t *dest) 214 { 215 int i; 216 uint32_t val; 217 218 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 219 LGE_EECTL_SINGLEACCESS | ((addr >> 1) << 8)); 220 221 for (i = 0; i < LGE_TIMEOUT; i++) { 222 if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0) 223 break; 224 } 225 226 if (i == LGE_TIMEOUT) { 227 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 228 return; 229 } 230 231 val = CSR_READ_4(sc, LGE_EEDATA); 232 233 if (addr & 1) 234 *dest = (val >> 16) & 0xFFFF; 235 else 236 *dest = val & 0xFFFF; 237 } 238 239 /* 240 * Read a sequence of words from the EEPROM. 241 */ 242 static void 243 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt) 244 { 245 int i; 246 uint16_t word = 0, *ptr; 247 248 for (i = 0; i < cnt; i++) { 249 lge_eeprom_getword(sc, off + i, &word); 250 ptr = (uint16_t *)(dest + (i * 2)); 251 *ptr = ntohs(word); 252 } 253 } 254 255 static int 256 lge_miibus_readreg(device_t dev, int phy, int reg) 257 { 258 struct lge_softc *sc = device_get_softc(dev); 259 int i; 260 261 /* 262 * If we have a non-PCS PHY, pretend that the internal 263 * autoneg stuff at PHY address 0 isn't there so that 264 * the miibus code will find only the GMII PHY. 265 */ 266 if (sc->lge_pcs == 0 && phy == 0) 267 return(0); 268 269 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 270 271 for (i = 0; i < LGE_TIMEOUT; i++) { 272 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) 273 break; 274 } 275 276 if (i == LGE_TIMEOUT) { 277 printf("lge%d: PHY read timed out\n", sc->lge_unit); 278 return(0); 279 } 280 281 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 282 } 283 284 static int 285 lge_miibus_writereg(device_t dev, int phy, int reg, int data) 286 { 287 struct lge_softc *sc = device_get_softc(dev); 288 int i; 289 290 CSR_WRITE_4(sc, LGE_GMIICTL, 291 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 292 293 for (i = 0; i < LGE_TIMEOUT; i++) { 294 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) 295 break; 296 } 297 298 if (i == LGE_TIMEOUT) { 299 printf("lge%d: PHY write timed out\n", sc->lge_unit); 300 return(0); 301 } 302 303 return(0); 304 } 305 306 static void 307 lge_miibus_statchg(device_t dev) 308 { 309 struct lge_softc *sc = device_get_softc(dev); 310 struct mii_data *mii = device_get_softc(sc->lge_miibus); 311 312 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 313 switch (IFM_SUBTYPE(mii->mii_media_active)) { 314 case IFM_1000_T: 315 case IFM_1000_SX: 316 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 317 break; 318 case IFM_100_TX: 319 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 320 break; 321 case IFM_10_T: 322 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 323 break; 324 default: 325 /* 326 * Choose something, even if it's wrong. Clearing 327 * all the bits will hose autoneg on the internal 328 * PHY. 329 */ 330 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 331 break; 332 } 333 334 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 335 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 336 else 337 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 338 } 339 340 static void 341 lge_setmulti(struct lge_softc *sc) 342 { 343 struct ifnet *ifp = &sc->arpcom.ac_if; 344 struct ifmultiaddr *ifma; 345 uint32_t h = 0, hashes[2] = { 0, 0 }; 346 347 /* Make sure multicast hash table is enabled. */ 348 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_MCAST); 349 350 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 351 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 352 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 353 return; 354 } 355 356 /* first, zot all the existing hash bits */ 357 CSR_WRITE_4(sc, LGE_MAR0, 0); 358 CSR_WRITE_4(sc, LGE_MAR1, 0); 359 360 /* now program new ones */ 361 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 362 if (ifma->ifma_addr->sa_family != AF_LINK) 363 continue; 364 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 365 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 366 if (h < 32) 367 hashes[0] |= (1 << h); 368 else 369 hashes[1] |= (1 << (h - 32)); 370 } 371 372 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 373 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 374 375 return; 376 } 377 378 static void 379 lge_reset(struct lge_softc *sc) 380 { 381 int i; 382 383 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_SOFTRST); 384 385 for (i = 0; i < LGE_TIMEOUT; i++) { 386 if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0) 387 break; 388 } 389 390 if (i == LGE_TIMEOUT) 391 printf("lge%d: reset never completed\n", sc->lge_unit); 392 393 /* Wait a little while for the chip to get its brains in order. */ 394 DELAY(1000); 395 } 396 397 /* 398 * Probe for a Level 1 chip. Check the PCI vendor and device 399 * IDs against our list and return a device name if we find a match. 400 */ 401 static int 402 lge_probe(device_t dev) 403 { 404 struct lge_type *t; 405 uint16_t vendor, product; 406 407 vendor = pci_get_vendor(dev); 408 product = pci_get_device(dev); 409 410 for (t = lge_devs; t->lge_name != NULL; t++) { 411 if (vendor == t->lge_vid && product == t->lge_did) { 412 device_set_desc(dev, t->lge_name); 413 return(0); 414 } 415 } 416 417 return(ENXIO); 418 } 419 420 /* 421 * Attach the interface. Allocate softc structures, do ifmedia 422 * setup and ethernet/BPF attach. 423 */ 424 static int 425 lge_attach(device_t dev) 426 { 427 uint8_t eaddr[ETHER_ADDR_LEN]; 428 struct lge_softc *sc; 429 struct ifnet *ifp; 430 int unit, error = 0, rid; 431 432 sc = device_get_softc(dev); 433 unit = device_get_unit(dev); 434 callout_init(&sc->lge_stat_timer); 435 436 /* 437 * Handle power management nonsense. 438 */ 439 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 440 uint32_t iobase, membase, irq; 441 442 /* Save important PCI config data. */ 443 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 444 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 445 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 446 447 /* Reset the power state. */ 448 device_printf(dev, "chip is in D%d power mode " 449 "-- setting to D0\n", pci_get_powerstate(dev)); 450 451 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 452 453 /* Restore PCI config data. */ 454 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 455 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 456 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 457 } 458 459 pci_enable_busmaster(dev); 460 461 rid = LGE_RID; 462 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 463 464 if (sc->lge_res == NULL) { 465 printf("lge%d: couldn't map ports/memory\n", unit); 466 error = ENXIO; 467 goto fail; 468 } 469 470 sc->lge_btag = rman_get_bustag(sc->lge_res); 471 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 472 473 /* Allocate interrupt */ 474 rid = 0; 475 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 476 RF_SHAREABLE | RF_ACTIVE); 477 478 if (sc->lge_irq == NULL) { 479 printf("lge%d: couldn't map interrupt\n", unit); 480 error = ENXIO; 481 goto fail; 482 } 483 484 /* Reset the adapter. */ 485 lge_reset(sc); 486 487 /* 488 * Get station address from the EEPROM. 489 */ 490 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1); 491 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1); 492 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1); 493 494 sc->lge_unit = unit; 495 496 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 497 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 498 499 if (sc->lge_ldata == NULL) { 500 printf("lge%d: no memory for list buffers!\n", unit); 501 error = ENXIO; 502 goto fail; 503 } 504 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 505 506 /* Try to allocate memory for jumbo buffers. */ 507 if (lge_alloc_jumbo_mem(sc)) { 508 printf("lge%d: jumbo buffer allocation failed\n", 509 sc->lge_unit); 510 error = ENXIO; 511 goto fail; 512 } 513 514 ifp = &sc->arpcom.ac_if; 515 ifp->if_softc = sc; 516 if_initname(ifp, "lge", unit); 517 ifp->if_mtu = ETHERMTU; 518 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 519 ifp->if_ioctl = lge_ioctl; 520 ifp->if_start = lge_start; 521 ifp->if_watchdog = lge_watchdog; 522 ifp->if_init = lge_init; 523 ifp->if_baudrate = 1000000000; 524 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1); 525 ifq_set_ready(&ifp->if_snd); 526 ifp->if_capabilities = IFCAP_RXCSUM; 527 ifp->if_capenable = ifp->if_capabilities; 528 529 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 530 sc->lge_pcs = 1; 531 else 532 sc->lge_pcs = 0; 533 534 /* 535 * Do MII setup. 536 */ 537 if (mii_phy_probe(dev, &sc->lge_miibus, 538 lge_ifmedia_upd, lge_ifmedia_sts)) { 539 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 540 error = ENXIO; 541 goto fail; 542 } 543 544 /* 545 * Call MI attach routine. 546 */ 547 ether_ifattach(ifp, eaddr); 548 549 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 550 lge_intr, sc, &sc->lge_intrhand, NULL); 551 if (error) { 552 ether_ifdetach(ifp); 553 printf("lge%d: couldn't set up irq\n", unit); 554 goto fail; 555 } 556 557 return(0); 558 559 fail: 560 lge_detach(dev); 561 return(error); 562 } 563 564 static int 565 lge_detach(device_t dev) 566 { 567 struct lge_softc *sc= device_get_softc(dev); 568 struct ifnet *ifp = &sc->arpcom.ac_if; 569 570 crit_enter(); 571 572 if (device_is_attached(dev)) { 573 lge_reset(sc); 574 lge_stop(sc); 575 ether_ifdetach(ifp); 576 } 577 578 if (sc->lge_miibus) 579 device_delete_child(dev, sc->lge_miibus); 580 bus_generic_detach(dev); 581 582 if (sc->lge_intrhand) 583 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 584 585 crit_exit(); 586 587 if (sc->lge_irq) 588 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 589 if (sc->lge_res) 590 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 591 592 if (sc->lge_ldata) 593 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), 594 M_DEVBUF); 595 lge_free_jumbo_mem(sc); 596 597 return(0); 598 } 599 600 /* 601 * Initialize the transmit descriptors. 602 */ 603 static int 604 lge_list_tx_init(struct lge_softc *sc) 605 { 606 struct lge_list_data *ld; 607 struct lge_ring_data *cd; 608 int i; 609 610 cd = &sc->lge_cdata; 611 ld = sc->lge_ldata; 612 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 613 ld->lge_tx_list[i].lge_mbuf = NULL; 614 ld->lge_tx_list[i].lge_ctl = 0; 615 } 616 617 cd->lge_tx_prod = cd->lge_tx_cons = 0; 618 619 return(0); 620 } 621 622 623 /* 624 * Initialize the RX descriptors and allocate mbufs for them. Note that 625 * we arralge the descriptors in a closed ring, so that the last descriptor 626 * points back to the first. 627 */ 628 static int 629 lge_list_rx_init(struct lge_softc *sc) 630 { 631 struct lge_list_data *ld; 632 struct lge_ring_data *cd; 633 int i; 634 635 ld = sc->lge_ldata; 636 cd = &sc->lge_cdata; 637 638 cd->lge_rx_prod = cd->lge_rx_cons = 0; 639 640 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 641 642 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 643 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 644 break; 645 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 646 return(ENOBUFS); 647 } 648 649 /* Clear possible 'rx command queue empty' interrupt. */ 650 CSR_READ_4(sc, LGE_ISR); 651 652 return(0); 653 } 654 655 /* 656 * Initialize an RX descriptor and attach an MBUF cluster. 657 */ 658 static int 659 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m) 660 { 661 struct mbuf *m_new = NULL; 662 struct lge_jslot *buf; 663 664 if (m == NULL) { 665 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 666 if (m_new == NULL) { 667 printf("lge%d: no memory for rx list " 668 "-- packet dropped!\n", sc->lge_unit); 669 return(ENOBUFS); 670 } 671 672 /* Allocate the jumbo buffer */ 673 buf = lge_jalloc(sc); 674 if (buf == NULL) { 675 #ifdef LGE_VERBOSE 676 printf("lge%d: jumbo allocation failed " 677 "-- packet dropped!\n", sc->lge_unit); 678 #endif 679 m_freem(m_new); 680 return(ENOBUFS); 681 } 682 /* Attach the buffer to the mbuf */ 683 m_new->m_ext.ext_arg = buf; 684 m_new->m_ext.ext_buf = buf->lge_buf; 685 m_new->m_ext.ext_free = lge_jfree; 686 m_new->m_ext.ext_ref = lge_jref; 687 m_new->m_ext.ext_size = LGE_JUMBO_FRAMELEN; 688 689 m_new->m_data = m_new->m_ext.ext_buf; 690 m_new->m_flags |= M_EXT; 691 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 692 } else { 693 m_new = m; 694 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN; 695 m_new->m_data = m_new->m_ext.ext_buf; 696 } 697 698 /* 699 * Adjust alignment so packet payload begins on a 700 * longword boundary. Mandatory for Alpha, useful on 701 * x86 too. 702 */ 703 m_adj(m_new, ETHER_ALIGN); 704 705 c->lge_mbuf = m_new; 706 c->lge_fragptr_hi = 0; 707 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 708 c->lge_fraglen = m_new->m_len; 709 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 710 c->lge_sts = 0; 711 712 /* 713 * Put this buffer in the RX command FIFO. To do this, 714 * we just write the physical address of the descriptor 715 * into the RX descriptor address registers. Note that 716 * there are two registers, one high DWORD and one low 717 * DWORD, which lets us specify a 64-bit address if 718 * desired. We only use a 32-bit address for now. 719 * Writing to the low DWORD register is what actually 720 * causes the command to be issued, so we do that 721 * last. 722 */ 723 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 724 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 725 726 return(0); 727 } 728 729 static int 730 lge_alloc_jumbo_mem(struct lge_softc *sc) 731 { 732 struct lge_jslot *entry; 733 caddr_t ptr; 734 int i; 735 736 /* Grab a big chunk o' storage. */ 737 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 738 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 739 740 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 741 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 742 return(ENOBUFS); 743 } 744 745 SLIST_INIT(&sc->lge_jfree_listhead); 746 747 /* 748 * Now divide it up into 9K pieces and save the addresses 749 * in an array. 750 */ 751 ptr = sc->lge_cdata.lge_jumbo_buf; 752 for (i = 0; i < LGE_JSLOTS; i++) { 753 entry = &sc->lge_cdata.lge_jslots[i]; 754 entry->lge_sc = sc; 755 entry->lge_buf = ptr; 756 entry->lge_inuse = 0; 757 entry->lge_slot = i; 758 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jslot_link); 759 ptr += LGE_JLEN; 760 } 761 762 return(0); 763 } 764 765 static void 766 lge_free_jumbo_mem(struct lge_softc *sc) 767 { 768 if (sc->lge_cdata.lge_jumbo_buf) 769 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 770 } 771 772 /* 773 * Allocate a jumbo buffer. 774 */ 775 static struct lge_jslot * 776 lge_jalloc(struct lge_softc *sc) 777 { 778 struct lge_jslot *entry; 779 780 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 781 782 if (entry == NULL) { 783 #ifdef LGE_VERBOSE 784 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 785 #endif 786 return(NULL); 787 } 788 789 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jslot_link); 790 entry->lge_inuse = 1; 791 792 return(entry); 793 } 794 795 /* 796 * Adjust usage count on a jumbo buffer. In general this doesn't 797 * get used much because our jumbo buffers don't get passed around 798 * a lot, but it's implemented for correctness. 799 */ 800 static void 801 lge_jref(void *arg) 802 { 803 struct lge_jslot *entry = (struct lge_jslot *)arg; 804 struct lge_softc *sc = entry->lge_sc; 805 806 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) 807 panic("lge_jref: asked to reference buffer " 808 "that we don't manage!"); 809 else if (entry->lge_inuse == 0) 810 panic("lge_jref: buffer already free!"); 811 else 812 entry->lge_inuse++; 813 } 814 815 /* 816 * Release a jumbo buffer. 817 */ 818 static void 819 lge_jfree(void *arg) 820 { 821 struct lge_jslot *entry = (struct lge_jslot *)arg; 822 struct lge_softc *sc = entry->lge_sc; 823 824 if (sc == NULL) 825 panic("lge_jfree: can't find softc pointer!"); 826 827 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) 828 panic("lge_jfree: asked to free buffer that we don't manage!"); 829 else if (entry->lge_inuse == 0) 830 panic("lge_jfree: buffer already free!"); 831 else if (--entry->lge_inuse == 0) 832 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jslot_link); 833 } 834 835 /* 836 * A frame has been uploaded: pass the resulting mbuf chain up to 837 * the higher level protocols. 838 */ 839 static void 840 lge_rxeof(struct lge_softc *sc, int cnt) 841 { 842 struct ifnet *ifp = &sc->arpcom.ac_if; 843 struct mbuf *m; 844 struct lge_rx_desc *cur_rx; 845 int c, i, total_len = 0; 846 uint32_t rxsts, rxctl; 847 848 849 /* Find out how many frames were processed. */ 850 c = cnt; 851 i = sc->lge_cdata.lge_rx_cons; 852 853 /* Suck them in. */ 854 while(c) { 855 struct mbuf *m0 = NULL; 856 857 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 858 rxctl = cur_rx->lge_ctl; 859 rxsts = cur_rx->lge_sts; 860 m = cur_rx->lge_mbuf; 861 cur_rx->lge_mbuf = NULL; 862 total_len = LGE_RXBYTES(cur_rx); 863 LGE_INC(i, LGE_RX_LIST_CNT); 864 c--; 865 866 /* 867 * If an error occurs, update stats, clear the 868 * status word and leave the mbuf cluster in place: 869 * it should simply get re-used next time this descriptor 870 * comes up in the ring. 871 */ 872 if (rxctl & LGE_RXCTL_ERRMASK) { 873 ifp->if_ierrors++; 874 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 875 continue; 876 } 877 878 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 879 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 880 total_len + ETHER_ALIGN, 0, ifp, NULL); 881 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 882 if (m0 == NULL) { 883 printf("lge%d: no receive buffers " 884 "available -- packet dropped!\n", 885 sc->lge_unit); 886 ifp->if_ierrors++; 887 continue; 888 } 889 m_adj(m0, ETHER_ALIGN); 890 m = m0; 891 } else { 892 m->m_pkthdr.rcvif = ifp; 893 m->m_pkthdr.len = m->m_len = total_len; 894 } 895 896 ifp->if_ipackets++; 897 898 /* Do IP checksum checking. */ 899 if (rxsts & LGE_RXSTS_ISIP) 900 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 901 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 902 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 903 if ((rxsts & LGE_RXSTS_ISTCP && 904 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 905 (rxsts & LGE_RXSTS_ISUDP && 906 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 907 m->m_pkthdr.csum_flags |= 908 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 909 m->m_pkthdr.csum_data = 0xffff; 910 } 911 912 (*ifp->if_input)(ifp, m); 913 } 914 915 sc->lge_cdata.lge_rx_cons = i; 916 } 917 918 static void 919 lge_rxeoc(struct lge_softc *sc) 920 { 921 struct ifnet *ifp = &sc->arpcom.ac_if; 922 923 ifp->if_flags &= ~IFF_RUNNING; 924 lge_init(sc); 925 } 926 927 /* 928 * A frame was downloaded to the chip. It's safe for us to clean up 929 * the list buffers. 930 */ 931 static void 932 lge_txeof(struct lge_softc *sc) 933 { 934 struct ifnet *ifp = &sc->arpcom.ac_if; 935 struct lge_tx_desc *cur_tx = NULL; 936 uint32_t idx, txdone; 937 938 /* Clear the timeout timer. */ 939 ifp->if_timer = 0; 940 941 /* 942 * Go through our tx list and free mbufs for those 943 * frames that have been transmitted. 944 */ 945 idx = sc->lge_cdata.lge_tx_cons; 946 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 947 948 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 949 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 950 951 ifp->if_opackets++; 952 if (cur_tx->lge_mbuf != NULL) { 953 m_freem(cur_tx->lge_mbuf); 954 cur_tx->lge_mbuf = NULL; 955 } 956 cur_tx->lge_ctl = 0; 957 958 txdone--; 959 LGE_INC(idx, LGE_TX_LIST_CNT); 960 ifp->if_timer = 0; 961 } 962 963 sc->lge_cdata.lge_tx_cons = idx; 964 965 if (cur_tx != NULL) 966 ifp->if_flags &= ~IFF_OACTIVE; 967 } 968 969 static void 970 lge_tick(void *xsc) 971 { 972 struct lge_softc *sc = xsc; 973 struct mii_data *mii; 974 struct ifnet *ifp = &sc->arpcom.ac_if; 975 976 crit_enter(); 977 978 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 979 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 980 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 981 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 982 983 if (!sc->lge_link) { 984 mii = device_get_softc(sc->lge_miibus); 985 mii_tick(mii); 986 mii_pollstat(mii); 987 if (mii->mii_media_status & IFM_ACTIVE && 988 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 989 sc->lge_link++; 990 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 991 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 992 printf("lge%d: gigabit link up\n", 993 sc->lge_unit); 994 if (!ifq_is_empty(&ifp->if_snd)) 995 (*ifp->if_start)(ifp); 996 } 997 } 998 999 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1000 1001 crit_exit(); 1002 } 1003 1004 static void 1005 lge_intr(void *arg) 1006 { 1007 struct lge_softc *sc = arg; 1008 struct ifnet *ifp = &sc->arpcom.ac_if; 1009 uint32_t status; 1010 1011 /* Supress unwanted interrupts */ 1012 if ((ifp->if_flags & IFF_UP) == 0) { 1013 lge_stop(sc); 1014 return; 1015 } 1016 1017 for (;;) { 1018 /* 1019 * Reading the ISR register clears all interrupts, and 1020 * clears the 'interrupts enabled' bit in the IMR 1021 * register. 1022 */ 1023 status = CSR_READ_4(sc, LGE_ISR); 1024 1025 if ((status & LGE_INTRS) == 0) 1026 break; 1027 1028 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1029 lge_txeof(sc); 1030 1031 if (status & LGE_ISR_RXDMA_DONE) 1032 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1033 1034 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1035 lge_rxeoc(sc); 1036 1037 if (status & LGE_ISR_PHY_INTR) { 1038 sc->lge_link = 0; 1039 callout_stop(&sc->lge_stat_timer); 1040 lge_tick(sc); 1041 } 1042 } 1043 1044 /* Re-enable interrupts. */ 1045 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1046 1047 if (!ifq_is_empty(&ifp->if_snd)) 1048 (*ifp->if_start)(ifp); 1049 } 1050 1051 /* 1052 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1053 * pointers to the fragment pointers. 1054 */ 1055 static int 1056 lge_encap(struct lge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1057 { 1058 struct lge_frag *f = NULL; 1059 struct lge_tx_desc *cur_tx; 1060 struct mbuf *m; 1061 int frag = 0, tot_len = 0; 1062 1063 /* 1064 * Start packing the mbufs in this chain into 1065 * the fragment pointers. Stop when we run out 1066 * of fragments or hit the end of the mbuf chain. 1067 */ 1068 m = m_head; 1069 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1070 frag = 0; 1071 1072 for (m = m_head; m != NULL; m = m->m_next) { 1073 if (m->m_len != 0) { 1074 tot_len += m->m_len; 1075 f = &cur_tx->lge_frags[frag]; 1076 f->lge_fraglen = m->m_len; 1077 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1078 f->lge_fragptr_hi = 0; 1079 frag++; 1080 } 1081 } 1082 1083 if (m != NULL) 1084 return(ENOBUFS); 1085 1086 cur_tx->lge_mbuf = m_head; 1087 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1088 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1089 1090 /* Queue for transmit */ 1091 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1092 1093 return(0); 1094 } 1095 1096 /* 1097 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1098 * to the mbuf data regions directly in the transmit lists. We also save a 1099 * copy of the pointers since the transmit list fragment pointers are 1100 * physical addresses. 1101 */ 1102 1103 static void 1104 lge_start(struct ifnet *ifp) 1105 { 1106 struct lge_softc *sc = ifp->if_softc; 1107 struct mbuf *m_head = NULL; 1108 uint32_t idx; 1109 1110 if (!sc->lge_link) 1111 return; 1112 1113 idx = sc->lge_cdata.lge_tx_prod; 1114 1115 if (ifp->if_flags & IFF_OACTIVE) 1116 return; 1117 1118 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1119 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1120 break; 1121 1122 m_head = ifq_poll(&ifp->if_snd); 1123 if (m_head == NULL) 1124 break; 1125 1126 if (lge_encap(sc, m_head, &idx)) { 1127 ifp->if_flags |= IFF_OACTIVE; 1128 break; 1129 } 1130 m_head = ifq_dequeue(&ifp->if_snd); 1131 1132 BPF_MTAP(ifp, m_head); 1133 } 1134 1135 sc->lge_cdata.lge_tx_prod = idx; 1136 1137 /* 1138 * Set a timeout in case the chip goes out to lunch. 1139 */ 1140 ifp->if_timer = 5; 1141 } 1142 1143 static void 1144 lge_init(void *xsc) 1145 { 1146 struct lge_softc *sc = xsc; 1147 struct ifnet *ifp = &sc->arpcom.ac_if; 1148 struct mii_data *mii; 1149 1150 crit_enter(); 1151 1152 if (ifp->if_flags & IFF_RUNNING) { 1153 crit_exit(); 1154 return; 1155 } 1156 1157 /* 1158 * Cancel pending I/O and free all RX/TX buffers. 1159 */ 1160 lge_stop(sc); 1161 lge_reset(sc); 1162 1163 mii = device_get_softc(sc->lge_miibus); 1164 1165 /* Set MAC address */ 1166 CSR_WRITE_4(sc, LGE_PAR0, *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1167 CSR_WRITE_4(sc, LGE_PAR1, *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1168 1169 /* Init circular RX list. */ 1170 if (lge_list_rx_init(sc) == ENOBUFS) { 1171 printf("lge%d: initialization failed: no " 1172 "memory for rx buffers\n", sc->lge_unit); 1173 lge_stop(sc); 1174 crit_exit(); 1175 return; 1176 } 1177 1178 /* 1179 * Init tx descriptors. 1180 */ 1181 lge_list_tx_init(sc); 1182 1183 /* Set initial value for MODE1 register. */ 1184 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST | 1185 LGE_MODE1_TX_CRC | LGE_MODE1_TXPAD | 1186 LGE_MODE1_RX_FLOWCTL | LGE_MODE1_SETRST_CTL0 | 1187 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_SETRST_CTL2); 1188 1189 /* If we want promiscuous mode, set the allframes bit. */ 1190 if (ifp->if_flags & IFF_PROMISC) { 1191 CSR_WRITE_4(sc, LGE_MODE1, 1192 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_PROMISC); 1193 } else { 1194 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1195 } 1196 1197 /* 1198 * Set the capture broadcast bit to capture broadcast frames. 1199 */ 1200 if (ifp->if_flags & IFF_BROADCAST) { 1201 CSR_WRITE_4(sc, LGE_MODE1, 1202 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_BCAST); 1203 } else { 1204 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1205 } 1206 1207 /* Packet padding workaround? */ 1208 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1209 1210 /* No error frames */ 1211 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1212 1213 /* Receive large frames */ 1214 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_GIANTS); 1215 1216 /* Workaround: disable RX/TX flow control */ 1217 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1218 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1219 1220 /* Make sure to strip CRC from received frames */ 1221 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1222 1223 /* Turn off magic packet mode */ 1224 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1225 1226 /* Turn off all VLAN stuff */ 1227 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX | LGE_MODE1_VLAN_TX | 1228 LGE_MODE1_VLAN_STRIP | LGE_MODE1_VLAN_INSERT); 1229 1230 /* Workarond: FIFO overflow */ 1231 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1232 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1233 1234 /* 1235 * Load the multicast filter. 1236 */ 1237 lge_setmulti(sc); 1238 1239 /* 1240 * Enable hardware checksum validation for all received IPv4 1241 * packets, do not reject packets with bad checksums. 1242 */ 1243 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM | 1244 LGE_MODE2_RX_TCPCSUM | LGE_MODE2_RX_UDPCSUM | 1245 LGE_MODE2_RX_ERRCSUM); 1246 1247 /* 1248 * Enable the delivery of PHY interrupts based on 1249 * link/speed/duplex status chalges. 1250 */ 1251 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_GMIIPOLL); 1252 1253 /* Enable receiver and transmitter. */ 1254 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1255 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_ENB); 1256 1257 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1258 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_TX_ENB); 1259 1260 /* 1261 * Enable interrupts. 1262 */ 1263 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0 | 1264 LGE_IMR_SETRST_CTL1 | LGE_IMR_INTR_ENB|LGE_INTRS); 1265 1266 lge_ifmedia_upd(ifp); 1267 1268 ifp->if_flags |= IFF_RUNNING; 1269 ifp->if_flags &= ~IFF_OACTIVE; 1270 1271 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1272 1273 crit_exit(); 1274 } 1275 1276 /* 1277 * Set media options. 1278 */ 1279 static int 1280 lge_ifmedia_upd(struct ifnet *ifp) 1281 { 1282 struct lge_softc *sc = ifp->if_softc; 1283 struct mii_data *mii = device_get_softc(sc->lge_miibus); 1284 1285 sc->lge_link = 0; 1286 if (mii->mii_instance) { 1287 struct mii_softc *miisc; 1288 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1289 mii_phy_reset(miisc); 1290 } 1291 mii_mediachg(mii); 1292 1293 return(0); 1294 } 1295 1296 /* 1297 * Report current media status. 1298 */ 1299 static void 1300 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1301 { 1302 struct lge_softc *sc = ifp->if_softc; 1303 struct mii_data *mii; 1304 1305 mii = device_get_softc(sc->lge_miibus); 1306 mii_pollstat(mii); 1307 ifmr->ifm_active = mii->mii_media_active; 1308 ifmr->ifm_status = mii->mii_media_status; 1309 } 1310 1311 static int 1312 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1313 { 1314 struct lge_softc *sc = ifp->if_softc; 1315 struct ifreq *ifr = (struct ifreq *) data; 1316 struct mii_data *mii; 1317 int error = 0; 1318 1319 crit_enter(); 1320 1321 switch(command) { 1322 case SIOCSIFMTU: 1323 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1324 error = EINVAL; 1325 else 1326 ifp->if_mtu = ifr->ifr_mtu; 1327 break; 1328 case SIOCSIFFLAGS: 1329 if (ifp->if_flags & IFF_UP) { 1330 if (ifp->if_flags & IFF_RUNNING && 1331 ifp->if_flags & IFF_PROMISC && 1332 !(sc->lge_if_flags & IFF_PROMISC)) { 1333 CSR_WRITE_4(sc, LGE_MODE1, 1334 LGE_MODE1_SETRST_CTL1| 1335 LGE_MODE1_RX_PROMISC); 1336 } else if (ifp->if_flags & IFF_RUNNING && 1337 !(ifp->if_flags & IFF_PROMISC) && 1338 sc->lge_if_flags & IFF_PROMISC) { 1339 CSR_WRITE_4(sc, LGE_MODE1, 1340 LGE_MODE1_RX_PROMISC); 1341 } else { 1342 ifp->if_flags &= ~IFF_RUNNING; 1343 lge_init(sc); 1344 } 1345 } else { 1346 if (ifp->if_flags & IFF_RUNNING) 1347 lge_stop(sc); 1348 } 1349 sc->lge_if_flags = ifp->if_flags; 1350 error = 0; 1351 break; 1352 case SIOCADDMULTI: 1353 case SIOCDELMULTI: 1354 lge_setmulti(sc); 1355 error = 0; 1356 break; 1357 case SIOCGIFMEDIA: 1358 case SIOCSIFMEDIA: 1359 mii = device_get_softc(sc->lge_miibus); 1360 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1361 break; 1362 default: 1363 error = ether_ioctl(ifp, command, data); 1364 break; 1365 } 1366 1367 crit_exit(); 1368 1369 return(error); 1370 } 1371 1372 static void 1373 lge_watchdog(struct ifnet *ifp) 1374 { 1375 struct lge_softc *sc = ifp->if_softc; 1376 1377 ifp->if_oerrors++; 1378 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1379 1380 lge_stop(sc); 1381 lge_reset(sc); 1382 ifp->if_flags &= ~IFF_RUNNING; 1383 lge_init(sc); 1384 1385 if (!ifq_is_empty(&ifp->if_snd)) 1386 (*ifp->if_start)(ifp); 1387 } 1388 1389 /* 1390 * Stop the adapter and free any mbufs allocated to the 1391 * RX and TX lists. 1392 */ 1393 static void 1394 lge_stop(struct lge_softc *sc) 1395 { 1396 struct ifnet *ifp = &sc->arpcom.ac_if; 1397 int i; 1398 1399 ifp->if_timer = 0; 1400 callout_stop(&sc->lge_stat_timer); 1401 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1402 1403 /* Disable receiver and transmitter. */ 1404 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1405 sc->lge_link = 0; 1406 1407 /* 1408 * Free data in the RX lists. 1409 */ 1410 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1411 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1412 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1413 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1414 } 1415 } 1416 bzero(&sc->lge_ldata->lge_rx_list, sizeof(sc->lge_ldata->lge_rx_list)); 1417 1418 /* 1419 * Free the TX list buffers. 1420 */ 1421 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1422 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1423 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1424 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1425 } 1426 } 1427 1428 bzero(&sc->lge_ldata->lge_tx_list, sizeof(sc->lge_ldata->lge_tx_list)); 1429 1430 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1431 } 1432 1433 /* 1434 * Stop all chip I/O so that the kernel's probe routines don't 1435 * get confused by errant DMAs when rebooting. 1436 */ 1437 static void 1438 lge_shutdown(device_t dev) 1439 { 1440 struct lge_softc *sc = device_get_softc(dev); 1441 1442 lge_reset(sc); 1443 lge_stop(sc); 1444 } 1445