xref: /dragonfly/sys/dev/netif/mii_layer/e1000phy.c (revision 25a2db75)
1 /* $FreeBSD: src/sys/dev/mii/e1000phy.c,v 1.18 2006/12/11 11:09:48 yongari Exp $ */
2 /*	$OpenBSD: eephy.c,v 1.26 2006/06/08 00:27:12 brad Exp $	*/
3 /*
4  * Principal Author: Parag Patel
5  * Copyright (c) 2001
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice unmodified, this list of conditions, and the following
13  *    disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  * Additonal Copyright (c) 2001 by Traakan Software under same licence.
31  * Secondary Author: Matthew Jacob
32  */
33 
34 /*
35  * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
36  */
37 
38 /*
39  * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseT and
40  * 1000baseSX PHY.
41  * Nathan Binkert <nate@openbsd.org>
42  * Jung-uk Kim <jkim@niksun.com>
43  */
44 
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/bus.h>
50 
51 #include <net/if.h>
52 #include <net/if_media.h>
53 
54 #include "mii.h"
55 #include "miivar.h"
56 #include "miidevs.h"
57 
58 #include "e1000phyreg.h"
59 
60 #include "miibus_if.h"
61 
62 static int	e1000phy_probe(device_t);
63 static int	e1000phy_attach(device_t);
64 static int	e1000phy_service(struct mii_softc *, struct mii_data *, int);
65 static void	e1000phy_status(struct mii_softc *);
66 static void	e1000phy_mii_phy_auto(struct mii_softc *);
67 static void	e1000phy_reset(struct mii_softc *);
68 
69 static device_method_t e1000phy_methods[] = {
70 	/* device interface */
71 	DEVMETHOD(device_probe,		e1000phy_probe),
72 	DEVMETHOD(device_attach,	e1000phy_attach),
73 	DEVMETHOD(device_detach,	ukphy_detach),
74 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
75 	DEVMETHOD_END
76 };
77 
78 static const struct mii_phydesc e1000phys[] = {
79 	MII_PHYDESC(xxMARVELL,	E1011),
80 	MII_PHYDESC(xxMARVELL,	E1000_3),
81 	MII_PHYDESC(xxMARVELL,	E1000_5),
82 	MII_PHYDESC(xxMARVELL,	E1111),
83 	MII_PHYDESC(MARVELL,	E1000),
84 	MII_PHYDESC(MARVELL,	E1011),
85 	MII_PHYDESC(MARVELL,	E1000_3),
86 	MII_PHYDESC(MARVELL,	E1000S),
87 	MII_PHYDESC(MARVELL,	E1000_5),
88 	MII_PHYDESC(MARVELL,	E1101),
89 	MII_PHYDESC(MARVELL,	E3082),
90 	MII_PHYDESC(MARVELL,	E1112),
91 	MII_PHYDESC(MARVELL,	E1149),
92 	MII_PHYDESC(MARVELL,	E1111),
93 	MII_PHYDESC(MARVELL,	E1116),
94 	MII_PHYDESC(MARVELL,	E1116R),
95 	MII_PHYDESC(MARVELL,	E1118),
96 	MII_PHYDESC(MARVELL,	E3016),
97 	MII_PHYDESC(MARVELL,	PHYG65G),
98 	MII_PHYDESC(MARVELL,	E1149R),
99 	MII_PHYDESC_NULL
100 };
101 
102 static devclass_t e1000phy_devclass;
103 
104 static driver_t e1000phy_driver = {
105 	"e1000phy",
106 	e1000phy_methods,
107 	sizeof(struct mii_softc)
108 };
109 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, NULL, NULL);
110 
111 static int
112 e1000phy_probe(device_t	dev)
113 {
114 	struct mii_attach_args *ma = device_get_ivars(dev);
115 	const struct mii_phydesc *mpd;
116 
117 	mpd = mii_phy_match(ma, e1000phys);
118 	if (mpd != NULL) {
119 		device_set_desc(dev, mpd->mpd_name);
120 		return 0;
121 	}
122 	return (ENXIO);
123 }
124 
125 static int
126 e1000phy_attach(device_t dev)
127 {
128 	struct mii_softc *sc;
129 	struct mii_attach_args *ma;
130 	struct mii_data *mii;
131 
132 	sc = device_get_softc(dev);
133 	ma = device_get_ivars(dev);
134 	mii_softc_init(sc, ma);
135 	sc->mii_dev = device_get_parent(dev);
136 	mii = device_get_softc(sc->mii_dev);
137 	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
138 
139 	sc->mii_inst = mii->mii_instance;
140 	sc->mii_service = e1000phy_service;
141 	sc->mii_reset = e1000phy_reset;
142 	sc->mii_anegticks = MII_ANEGTICKS_GIGE;
143 	sc->mii_pdata = mii;
144 
145 	sc->mii_flags |= MIIF_NOISOLATE;
146 
147 	switch (sc->mii_model) {
148 	case MII_MODEL_MARVELL_E1011:
149 	case MII_MODEL_MARVELL_E1112:
150 		if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK)
151 			sc->mii_flags |= MIIF_HAVEFIBER;
152 		break;
153 	case MII_MODEL_MARVELL_E1149:
154 	case MII_MODEL_MARVELL_E1149R:
155 		/*
156 		 * Some 88E1149 PHY's page select is initialized to
157 		 * point to other bank instead of copper/fiber bank
158 		 * which in turn resulted in wrong registers were
159 		 * accessed during PHY operation. It is believed that
160 		 * page 0 should be used for copper PHY so reinitialize
161 		 * E1000_EADR to select default copper PHY. If parent
162 		 * device know the type of PHY(either copper or fiber),
163 		 * that information should be used to select default
164 		 * type of PHY.
165 		 */
166 		PHY_WRITE(sc, E1000_EADR, 0);
167 		break;
168 	}
169 
170 	mii->mii_instance++;
171 
172 	e1000phy_reset(sc);
173 
174 	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
175 	if (sc->mii_capabilities & BMSR_EXTSTAT)
176 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
177 
178 	if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0)
179 		sc->mii_anegticks = MII_ANEGTICKS;
180 
181 	device_printf(dev, " ");
182 	if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
183 	    (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
184 		kprintf("no media present");
185 	else
186 		mii_phy_add_media(sc);
187 	kprintf("\n");
188 
189 	MIIBUS_MEDIAINIT(sc->mii_dev);
190 	return 0;
191 }
192 
193 static void
194 e1000phy_reset(struct mii_softc *sc)
195 {
196 	uint16_t reg, page;
197 
198 	reg = PHY_READ(sc, E1000_SCR);
199 	if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) {
200 		reg &= ~E1000_SCR_AUTO_X_MODE;
201 		PHY_WRITE(sc, E1000_SCR, reg);
202 		if (sc->mii_model == MII_MODEL_MARVELL_E1112) {
203 			/* Select 1000BASE-X only mode. */
204 			page = PHY_READ(sc, E1000_EADR);
205 			PHY_WRITE(sc, E1000_EADR, 2);
206 			reg = PHY_READ(sc, E1000_SCR);
207 			reg &= ~E1000_SCR_MODE_MASK;
208 			reg |= E1000_SCR_MODE_1000BX;
209 			PHY_WRITE(sc, E1000_SCR, reg);
210 			/* TODO */
211 			PHY_WRITE(sc, E1000_EADR, page);
212 		}
213 	} else {
214 		switch (sc->mii_model) {
215 		case MII_MODEL_MARVELL_E1111:
216 		case MII_MODEL_MARVELL_E1112:
217 		case MII_MODEL_MARVELL_E1116:
218 		case MII_MODEL_MARVELL_E1118:
219 		case MII_MODEL_MARVELL_E1149:
220 		case MII_MODEL_MARVELL_E1149R:
221 		case MII_MODEL_MARVELL_PHYG65G:
222 			/* Disable energy detect mode. */
223 			reg &= ~E1000_SCR_EN_DETECT_MASK;
224 			reg |= E1000_SCR_AUTO_X_MODE;
225 			if (sc->mii_model == MII_MODEL_MARVELL_E1116)
226 				reg &= ~E1000_SCR_POWER_DOWN;
227 			reg |= E1000_SCR_ASSERT_CRS_ON_TX;
228 			break;
229 		case MII_MODEL_MARVELL_E3082:
230 			reg |= (E1000_SCR_AUTO_X_MODE >> 1);
231 			reg |= E1000_SCR_ASSERT_CRS_ON_TX;
232 			break;
233 		case MII_MODEL_MARVELL_E3016:
234 			reg |= E1000_SCR_AUTO_MDIX;
235 			reg &= ~(E1000_SCR_EN_DETECT |
236 			    E1000_SCR_SCRAMBLER_DISABLE);
237 			reg |= E1000_SCR_LPNP;
238 			/* XXX Enable class A driver for Yukon FE+ A0. */
239 			PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001);
240 			break;
241 		default:
242 			reg &= ~E1000_SCR_AUTO_X_MODE;
243 			reg |= E1000_SCR_ASSERT_CRS_ON_TX;
244 			break;
245 		}
246 		if (sc->mii_model != MII_MODEL_MARVELL_E3016) {
247 			/* Auto correction for reversed cable polarity. */
248 			reg &= ~E1000_SCR_POLARITY_REVERSAL;
249 		}
250 		PHY_WRITE(sc, E1000_SCR, reg);
251 
252 		if (sc->mii_model == MII_MODEL_MARVELL_E1116 ||
253 		    sc->mii_model == MII_MODEL_MARVELL_E1149 ||
254 		    sc->mii_model == MII_MODEL_MARVELL_E1149R) {
255 			PHY_WRITE(sc, E1000_EADR, 2);
256 			reg = PHY_READ(sc, E1000_SCR);
257 			reg |= E1000_SCR_RGMII_POWER_UP;
258 			PHY_WRITE(sc, E1000_SCR, reg);
259 			PHY_WRITE(sc, E1000_EADR, 0);
260 		}
261 	}
262 
263 	switch (MII_MODEL(sc->mii_model)) {
264 	case MII_MODEL_MARVELL_E3082:
265 	case MII_MODEL_MARVELL_E1112:
266 	case MII_MODEL_MARVELL_E1118:
267 		break;
268 	case MII_MODEL_MARVELL_E1116:
269 		page = PHY_READ(sc, E1000_EADR);
270 		/* Select page 3, LED control register. */
271 		PHY_WRITE(sc, E1000_EADR, 3);
272 		PHY_WRITE(sc, E1000_SCR,
273 		    E1000_SCR_LED_LOS(1) |	/* Link/Act */
274 		    E1000_SCR_LED_INIT(8) |	/* 10Mbps */
275 		    E1000_SCR_LED_STAT1(7) |	/* 100Mbps */
276 		    E1000_SCR_LED_STAT0(7));	/* 1000Mbps */
277 		/* Set blink rate. */
278 		PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) |
279 		    E1000_BLINK_RATE(E1000_BLINK_84MS));
280 		PHY_WRITE(sc, E1000_EADR, page);
281 		break;
282 	case MII_MODEL_MARVELL_E3016:
283 		/* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */
284 		PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);
285 		/* Integrated register calibration workaround. */
286 		PHY_WRITE(sc, 0x1D, 17);
287 		PHY_WRITE(sc, 0x1E, 0x3F60);
288  		break;
289 	default:
290 		/* Force TX_CLK to 25MHz clock. */
291 		reg = PHY_READ(sc, E1000_ESCR);
292 		reg |= E1000_ESCR_TX_CLK_25;
293 		PHY_WRITE(sc, E1000_ESCR, reg);
294 		break;
295 	}
296 
297 	/* Reset the PHY so all changes take effect. */
298 	reg = PHY_READ(sc, E1000_CR);
299 	reg |= E1000_CR_RESET;
300 	PHY_WRITE(sc, E1000_CR, reg);
301 }
302 
303 static int
304 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
305 {
306 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
307 	uint16_t speed, gig;
308 	int reg;
309 
310 	switch (cmd) {
311 	case MII_POLLSTAT:
312 		/*
313 		 * If we're not polling our PHY instance, just return.
314 		 */
315 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
316 			return (0);
317 		break;
318 
319 	case MII_MEDIACHG:
320 		/*
321 		 * If the media indicates a different PHY instance,
322 		 * isolate ourselves.
323 		 */
324 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
325 			reg = PHY_READ(sc, E1000_CR);
326 			PHY_WRITE(sc, E1000_CR, reg | E1000_CR_ISOLATE);
327 			return (0);
328 		}
329 
330 		/*
331 		 * If the interface is not up, don't do anything.
332 		 */
333 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
334 			break;
335 
336 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
337 			e1000phy_mii_phy_auto(sc);
338 			break;
339 		}
340 
341 		speed = 0;
342 		switch (IFM_SUBTYPE(ife->ifm_media)) {
343 		case IFM_1000_T:
344 			if ((sc->mii_extcapabilities &
345 			    (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0)
346 				return EINVAL;
347 			speed = E1000_CR_SPEED_1000;
348 			break;
349 		case IFM_1000_SX:
350 			if ((sc->mii_extcapabilities &
351 			    (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0)
352 				return EINVAL;
353 			speed = E1000_CR_SPEED_1000;
354 			break;
355 		case IFM_100_TX:
356 			speed = E1000_CR_SPEED_100;
357 			break;
358 		case IFM_10_T:
359 			speed = E1000_CR_SPEED_10;
360 			break;
361 		case IFM_NONE:
362 			reg = PHY_READ(sc, E1000_CR);
363 			PHY_WRITE(sc, E1000_CR,
364 			    reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);
365 			goto done;
366 		default:
367 			return (EINVAL);
368 		}
369 
370 		if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
371 			speed |= E1000_CR_FULL_DUPLEX;
372 			gig = E1000_1GCR_1000T_FD;
373 		} else {
374 			gig = E1000_1GCR_1000T;
375 		}
376 
377 		reg = PHY_READ(sc, E1000_CR);
378 		reg &= ~E1000_CR_AUTO_NEG_ENABLE;
379 		PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
380 
381 		/*
382 		 * When setting the link manually, one side must
383 		 * be the master and the other the slave. However
384 		 * ifmedia doesn't give us a good way to specify
385 		 * this, so we fake it by using one of the LINK
386 		 * flags. If LINK0 is set, we program the PHY to
387 		 * be a master, otherwise it's a slave.
388 		 */
389 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T ||
390 		    IFM_SUBTYPE(ife->ifm_media) == IFM_1000_SX) {
391 			if (mii->mii_ifp->if_flags & IFF_LINK0) {
392 				PHY_WRITE(sc, E1000_1GCR, gig |
393 				    E1000_1GCR_MS_ENABLE | E1000_1GCR_MS_VALUE);
394 			} else {
395 				PHY_WRITE(sc, E1000_1GCR, gig |
396 				    E1000_1GCR_MS_ENABLE);
397 			}
398 		} else {
399 			if ((sc->mii_extcapabilities &
400 			    (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
401 				PHY_WRITE(sc, E1000_1GCR, 0);
402 		}
403 		PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
404 		PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET);
405 done:
406 		break;
407 
408 	case MII_TICK:
409 		/*
410 		 * If we're not currently selected, just return.
411 		 */
412 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
413 			return (0);
414 
415 		/*
416 		 * Is the interface even up?
417 		 */
418 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
419 			return (0);
420 
421 		/*
422 		 * Only used for autonegotiation.
423 		 */
424 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
425 			break;
426 
427 		/*
428 		 * Check to see if we have link.  If we do, we don't
429 		 * need to restart the autonegotiation process.  Read
430 		 * the BMSR twice in case it's latched.
431 		 */
432 		reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
433 		if (reg & BMSR_LINK) {
434 			sc->mii_ticks = 0;
435 			break;
436 		}
437 
438 		/*
439 		 * Only retry autonegotiation every mii_anegticks seconds.
440 		 */
441 		if (++sc->mii_ticks <= sc->mii_anegticks)
442 			return (0);
443 		sc->mii_ticks = 0;
444 
445 		e1000phy_reset(sc);
446 		e1000phy_mii_phy_auto(sc);
447 		break;
448 	}
449 
450 	/* Update the media status. */
451 	e1000phy_status(sc);
452 
453 	/* Callback if something changed. */
454 	mii_phy_update(sc, cmd);
455 	return (0);
456 }
457 
458 static void
459 e1000phy_status(struct mii_softc *sc)
460 {
461 	struct mii_data *mii = sc->mii_pdata;
462 	int bmsr, bmcr, gsr, ssr, ar, lpar;
463 
464 	mii->mii_media_status = IFM_AVALID;
465 	mii->mii_media_active = IFM_ETHER;
466 
467 	bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
468 	bmcr = PHY_READ(sc, E1000_CR);
469 	ssr = PHY_READ(sc, E1000_SSR);
470 
471 	if (bmsr & E1000_SR_LINK_STATUS)
472 		mii->mii_media_status |= IFM_ACTIVE;
473 
474 	if (bmcr & E1000_CR_LOOPBACK)
475 		mii->mii_media_active |= IFM_LOOP;
476 
477 	if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 &&
478 	    (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) {
479 		/* Erg, still trying, I guess... */
480 		mii->mii_media_active |= IFM_NONE;
481 		return;
482 	}
483 
484 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
485 		switch (ssr & E1000_SSR_SPEED) {
486 		case E1000_SSR_1000MBS:
487 			mii->mii_media_active |= IFM_1000_T;
488 			break;
489 		case E1000_SSR_100MBS:
490 			mii->mii_media_active |= IFM_100_TX;
491 			break;
492 		case E1000_SSR_10MBS:
493 			mii->mii_media_active |= IFM_10_T;
494 			break;
495 		default:
496 			mii->mii_media_active |= IFM_NONE;
497 			return;
498 		}
499 	} else {
500 		/*
501 		 * Some fiber PHY(88E1112) does not seem to set resolved
502 		 * speed so always assume we've got IFM_1000_SX.
503 		 */
504 		mii->mii_media_active |= IFM_1000_SX;
505 	}
506 
507 	if (ssr & E1000_SSR_DUPLEX)
508 		mii->mii_media_active |= IFM_FDX;
509 	else
510 		mii->mii_media_active |= IFM_HDX;
511 
512 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
513 		ar = PHY_READ(sc, E1000_AR);
514 		lpar = PHY_READ(sc, E1000_LPAR);
515 		/* FLAG0==rx-flow-control FLAG1==tx-flow-control */
516 		if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) {
517 			mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
518 		} else if (!(ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
519 		    (lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
520 			mii->mii_media_active |= IFM_FLAG1;
521 		} else if ((ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
522 		    !(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
523 			mii->mii_media_active |= IFM_FLAG0;
524 		}
525 	}
526 
527 	/* FLAG2 : local PHY resolved to MASTER */
528 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
529 	    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
530 		PHY_READ(sc, E1000_1GSR);
531 		gsr = PHY_READ(sc, E1000_1GSR);
532 		if ((gsr & E1000_1GSR_MS_CONFIG_RES) != 0)
533 			mii->mii_media_active |= IFM_FLAG2;
534 	}
535 }
536 
537 static void
538 e1000phy_mii_phy_auto(struct mii_softc *sc)
539 {
540 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
541 		uint16_t reg;
542 
543 		reg = PHY_READ(sc, E1000_AR);
544 		reg |= E1000_AR_10T | E1000_AR_10T_FD |
545  		    E1000_AR_100TX | E1000_AR_100TX_FD |
546 		    E1000_AR_PAUSE | E1000_AR_ASM_DIR;
547 		PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);
548 	} else {
549 		PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X |
550 		    E1000_FA_SYM_PAUSE | E1000_FA_ASYM_PAUSE);
551 	}
552 	if ((sc->mii_extcapabilities &
553 	    (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) {
554 		PHY_WRITE(sc, E1000_1GCR,
555 		    E1000_1GCR_1000T_FD | E1000_1GCR_1000T);
556 	}
557 	PHY_WRITE(sc, E1000_CR,
558 	    E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);
559 }
560